abc9_ops: Add a check ensuring that connected port actually exists.

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 00af36615e15463635f4af9c560642da5c74ec8f..8ae1b51ffea328f7e1479e8a6f0d3a83119d7189 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -434,6 +434,9 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
                auto &t = timing.at(derived_type).required;
                for (auto &conn : cell->connections_) {
                        auto port_wire = inst_module->wire(conn.first);
+                       if (!port_wire)
+                               log_error("Port %s in cell %s (type %s) of module %s does not actually exist",
+                                               log_id(conn.first), log_id(cell->name), log_id(cell->type), log_id(module->name));
                        if (!port_wire->port_input)
                                continue;