whoops consistent inversion of inv,CRbit was CRbit,inv

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index c4152057574c519cbd59588352933bc929f0acf1..75879f86b126db3298809cab051b070ad9895134 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1305,7 +1305,7 @@ class FFPRRc1BaseRM(BaseRM):
     def specifiers(self, record, mode):
         inv = _SelectableInt(value=int(self.inv), bits=1)
         CR = _SelectableInt(value=int(self.CR), bits=2)
-        mask = int(_selectconcat(inv, CR))
+        mask = int(_selectconcat(CR, inv))
         predicate = PredicateBaseRM.predicate(True, mask)
         yield f"{mode}={predicate}"
 

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index a3e6f44b6eba9cde73a95220d6cac3ccd8538262..eb1f811540c2ab864b7e7bd5e2307238faad1e43 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -669,8 +669,8 @@ def decode_bo(encoding):
     # barse-ackwards MSB0/LSB0. sigh
     mapped = pmap[encoding]
     si =  SelectableInt(0, 3)
-    si[0] = mapped>>2 # inv
-    si[1:3] = mapped & 3 # CR
+    si[0] = mapped & 1 # inv
+    si[1:3] = mapped >> 1 # CR
     return int(si)