xaiger: always sort input/output bits by port id

redundant for normal design, but necessary for holes

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 17a2748dcc12c7667827142bedfa6b2a6f65e8e7..6f0ed6e89f01743851f6bb7db0068fadcc70f93c 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -138,7 +138,7 @@ struct XAigerWriter
                return a;
        }
 
-       XAigerWriter(Module *module, bool dff_mode, bool holes_mode=false) : module(module), sigmap(module)
+       XAigerWriter(Module *module, bool dff_mode) : module(module), sigmap(module)
        {
                pool<SigBit> undriven_bits;
                pool<SigBit> unused_bits;
@@ -411,16 +411,14 @@ struct XAigerWriter
                        undriven_bits.erase(bit);
                }
 
-               if (holes_mode) {
-                       struct sort_by_port_id {
-                               bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
-                                       return a.wire->port_id < b.wire->port_id ||
-                                           (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
-                               }
-                       };
-                       input_bits.sort(sort_by_port_id());
-                       output_bits.sort(sort_by_port_id());
-               }
+               struct sort_by_port_id {
+                       bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
+                               return a.wire->port_id < b.wire->port_id ||
+                                   (a.wire->port_id == b.wire->port_id && a.offset < b.offset);
+                       }
+               };
+               input_bits.sort(sort_by_port_id());
+               output_bits.sort(sort_by_port_id());
 
                aig_map[State::S0] = 0;
                aig_map[State::S1] = 1;
@@ -685,7 +683,7 @@ struct XAigerWriter
                        RTLIL::Module *holes_module = holes_design ? holes_design->module(module->name) : nullptr;
                        if (holes_module) {
                                std::stringstream a_buffer;
-                               XAigerWriter writer(holes_module, false /* dff_mode */, true /* holes_mode */);
+                               XAigerWriter writer(holes_module, false /* dff_mode */);
                                writer.write_aiger(a_buffer, false /*ascii_mode*/);
 
                                f << "a";