(peepholes for two DF load/store): New peepholes.

From-SVN: r8517

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index a11f75678a99cfe5f6e3ff8f01b131b44b842015..e6c2e711856c1b14b78e3747b10614e8865bf880 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4436,6 +4436,30 @@
   "@
    stfdux %3,%0,%2
    stfdu %3,%2(%0)")
+
+;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
+
+(define_peephole
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+       (match_operand:DF 1 "memory_operand" ""))
+   (set (match_operand:DF 2 "gpc_reg_operand" "=f")
+       (match_operand:DF 3 "memory_operand" ""))]
+  "TARGET_POWER2
+   && registers_ok_for_quad_peep (operands[0], operands[2])
+   && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
+   && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
+  "lfq%U1%X1 %0,%1")
+
+(define_peephole
+  [(set (match_operand:DF 0 "memory_operand" "")
+       (match_operand:DF 1 "gpc_reg_operand" "f"))
+   (set (match_operand:DF 2 "memory_operand" "")
+       (match_operand:DF 3 "gpc_reg_operand" "f"))]
+  "TARGET_POWER2
+   && registers_ok_for_quad_peep (operands[1], operands[3])
+   && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
+   && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
+  "stfq%U0%X0 %1,%0")
 \f
 ;; Next come insns related to the calling sequence.
 ;;