riscv: remove dependency on num_cores

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 60ee674822724800fdf702be2f4f76e65e03de62..ef68c2ffe20d37760d1d1da89dd4cbcfdc52db04 100644 (file)
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -137,9 +137,6 @@
 #define IRQ_HOST     13
 
 #define DEFAULT_RSTVEC     0x00001000
-#define DEFAULT_NMIVEC     0x00001004
-#define DEFAULT_MTVEC      0x00001010
-#define CONFIG_STRING_ADDR 0x0000100C
 #define EXT_IO_BASE        0x40000000
 #define DRAM_BASE          0x80000000
 

diff --git a/riscv/interactive.cc b/riscv/interactive.cc
index 623c425c7f7f85b63f5a6eeb29506ae2f58de6ef..ee8837522e163649268e3f74e4fb80c941420fd5 100644 (file)
--- a/riscv/interactive.cc
+++ b/riscv/interactive.cc
@@ -24,7 +24,7 @@ processor_t *sim_t::get_core(const std::string& i)
 {
   char *ptr;
   unsigned long p = strtoul(i.c_str(), &ptr, 10);
-  if (*ptr || p >= num_cores())
+  if (*ptr || p >= procs.size())
     throw trap_interactive();
   return get_core(p);
 }

diff --git a/riscv/processor.cc b/riscv/processor.cc
index aa69bdc1adb5585dd6daaa9184b4da5da969277e..f6b4cb649f0c357c98b2444842a2536031145ba3 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -118,7 +118,6 @@ void state_t::reset()
   memset(this, 0, sizeof(*this));
   prv = PRV_M;
   pc = DEFAULT_RSTVEC;
-  mtvec = DEFAULT_MTVEC;
   load_reservation = -1;
   tselect = 0;
   for (unsigned int i = 0; i < num_triggers; i++)