(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 6189eef0700d6e34ba4334d05d9cb66436412797..a6c56cf59204fb9234743823feb608e19890457b 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -496,7 +496,7 @@ to 4-bit CR fields.  Vectorised Integer results, when Rc=1, will begin
 writing to CR8 (TBD evaluate) and increase sequentially from there.  Vectorised FP
 results, when Rc=1, start from CR32 (TBD evaluate).  This is so that:
 
-* implementations may rely on the Vector CRs being aligned to 8. This means that CRs may be read or written in aligned batches of 32 bits, for high performance implementations.
+* implementations may rely on the Vector CRs being aligned to 8. This means that CRs may be read or written in aligned batches of 32 bits (8 CRs per batch), for high performance implementations.
 * scalar Rc=1 operation (CR0, CR1) and callee-saved CRs (CR2-4) are not overwritten by vector Rc=1 operations except for very large VL
 * Vector FP and Integer Rc=1 operations do not overwrite each other except for large VL.