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diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index b04d05a3d0856ec3ff20585596f481c8d89a9042..44bba6d23cc69621cfe3fb511433230bc7ee7f3f 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -153,6 +153,26 @@ for the type of operation (Branch, CRs, Memory, Arithmetic),
 and each Category has its own relevant but
 ultimately rational quirks.
 
+# Twin Predication
+
+Twin Predication is an entirely new concept not present in any commercial
+Vector ISA of the past forty years.  To explain:
+
+* Predication on the destination of a LOAD instruction creates something
+  called "Vector Compressed Load" (VCOMPRESS).
+* Predication on the *source* of a STORE instruction creates something
+  called "Vector Expanded Store" (VEXPAND).
+* SVP64 allows the two to be put back-to-back.
+
+The above allows a reader familiar with VCOMPRESS and VEXPAND to
+conceptualise what the effect of Twin Predication is, but it actually
+goes much further: in *any* twin-predicated instruction (extsw, fmv)
+it is possible to apply one predicate to the source register (compressing
+the source element array) and another *completely separate* predicate
+to the destination register, *in one instruction* and not just on Load/Stores.
+
+
+
 # CR weird instructions
 
 [[sv/int_cr_predication]] is by far the biggest violator of the SVP64