arm: Auto-vectorization for MVE: vneg

This patch enables MVE vneg instructions for auto-vectorization.  MVE
vnegq insns in mve.md are modified to use 'neg' instead of unspec
expression.  The neg<mode>2 expander is added to vec-common.md.

Existing patterns in neon.md are prefixed with neon_.
It's not clear why we have different patterns for VDQW
and VH in neon.md, when WDQWH handles both, and patterns
with VDQ have provision for attributes for FP modes.

Another question is why <absneg_str><mode>2 always sets
neon_abs<q> type when it also handles neon_neq<q> cases.

2020-12-11  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/mve.md (mve_vnegq_f): Use 'neg' instead of unspec.
	(mve_vnegq_s): Likewise.
	* config/arm/neon.md (neg<mode>2): Rename into neon_neg<mode>2.
	(<absneg_str><mode>2): Rename into neon_<absneg_str><mode>2.
	(neon_v<absneg_str><mode>): Call gen_neon_<absneg_str><mode>2.
	(vashr<mode>3): Call gen_neon_neg<mode>2.
	(vlshr<mode>3): Call gen_neon_neg<mode>2.
	(neon_vneg<mode>): Call gen_neon_neg<mode>2.
	* config/arm/unspecs.md (VNEGQ_F, VNEGQ_S): Remove.
	* config/arm/vec-common.md (neg<mode>2): New expander.

	gcc/testsuite/
	* gcc.target/arm/simd/mve-vneg.c: Add tests for vneg.

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 86d7fc64763a6089e8ccdcc7afdd7a5801b588f8..b4c5a1e27c41e2270e05f9f4da1c055457a20ad3 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -271,8 +271,7 @@
 (define_insn "mve_vnegq_f<mode>"
   [
    (set (match_operand:MVE_0 0 "s_register_operand" "=w")
-       (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")]
-        VNEGQ_F))
+       (neg:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
   "vneg.f%#<V_sz_elem>  %q0, %q1"
@@ -422,8 +421,7 @@
 (define_insn "mve_vnegq_s<mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-       (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")]
-        VNEGQ_S))
+       (neg:MVE_2 (match_operand:MVE_2 1 "s_register_operand" "w")))
   ]
   "TARGET_HAVE_MVE"
   "vneg.s%#<V_sz_elem>  %q0, %q1"

diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index f58d4f5479c3472a33c86962a21a8e1ad0f42df5..d2e92baeb495de6b8887056b04220d200c29f5f8 100644 (file)
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -775,7 +775,7 @@
                     (const_string "neon_abs<q>")))]
 )
 
-(define_insn "neg<mode>2"
+(define_insn "neon_neg<mode>2"
   [(set (match_operand:VDQW 0 "s_register_operand" "=w")
        (neg:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))]
   "TARGET_NEON"
@@ -786,7 +786,7 @@
                     (const_string "neon_neg<q>")))]
 )
 
-(define_insn "<absneg_str><mode>2"
+(define_insn "neon_<absneg_str><mode>2"
   [(set (match_operand:VH 0 "s_register_operand" "=w")
     (ABSNEG:VH (match_operand:VH 1 "s_register_operand" "w")))]
  "TARGET_NEON_FP16INST"
@@ -800,7 +800,7 @@
    (ABSNEG:VH (match_operand:VH 1 "s_register_operand")))]
  "TARGET_NEON_FP16INST"
 {
-  emit_insn (gen_<absneg_str><mode>2 (operands[0], operands[1]));
+  emit_insn (gen_neon_<absneg_str><mode>2 (operands[0], operands[1]));
   DONE;
 })
 
@@ -952,7 +952,7 @@
   if (s_register_operand (operands[2], <MODE>mode))
     {
       rtx neg = gen_reg_rtx (<MODE>mode);
-      emit_insn (gen_neg<mode>2 (neg, operands[2]));
+      emit_insn (gen_neon_neg<mode>2 (neg, operands[2]));
       emit_insn (gen_ashl<mode>3_signed (operands[0], operands[1], neg));
     }
   else
@@ -969,7 +969,7 @@
   if (s_register_operand (operands[2], <MODE>mode))
     {
       rtx neg = gen_reg_rtx (<MODE>mode);
-      emit_insn (gen_neg<mode>2 (neg, operands[2]));
+      emit_insn (gen_neon_neg<mode>2 (neg, operands[2]));
       emit_insn (gen_ashl<mode>3_unsigned (operands[0], operands[1], neg));
     }
   else
@@ -2953,7 +2953,7 @@
    (match_operand:VDQW 1 "s_register_operand")]
   "TARGET_NEON"
 {
-  emit_insn (gen_neg<mode>2 (operands[0], operands[1]));
+  emit_insn (gen_neon_neg<mode>2 (operands[0], operands[1]));
   DONE;
 })
 

diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index e5816459f12e82123a59b8a571c290e2c750c2ec..ef64989600dcad642af54d7bf0250728a9fb7502 100644 (file)
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -530,7 +530,6 @@
   VRNDMQ_F
   VRNDAQ_F
   VREV64Q_F
-  VNEGQ_F
   VDUPQ_N_F
   VABSQ_F
   VREV32Q_F
@@ -549,7 +548,6 @@
   VREV64Q_S
   VREV64Q_U
   VQABSQ_S
-  VNEGQ_S
   VDUPQ_N_U
   VDUPQ_N_S
   VCLZQ_U

diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 37ff518fc4e72379415d11f8741303da91b0aedb..2d0932b95a1615e94aa6572a593fc9849c9b36db 100644 (file)
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -199,3 +199,9 @@
        (not:VDQ (match_operand:VDQ 1 "s_register_operand")))]
   "ARM_HAVE_<MODE>_ARITH"
 )
+
+(define_expand "neg<mode>2"
+  [(set (match_operand:VDQWH 0 "s_register_operand" "")
+       (neg:VDQWH (match_operand:VDQWH 1 "s_register_operand" "")))]
+  "ARM_HAVE_<MODE>_ARITH"
+)

diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c
new file mode 100644 (file)
index 0000000..afd0d60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vneg.c
@@ -0,0 +1,49 @@
+/* { dg-do assemble } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+/* { dg-additional-options "-O3" } */
+
+#include <stdint.h>
+#include <arm_mve.h>
+
+#define FUNC(SIGN, TYPE, BITS, NB, OP, NAME)                           \
+  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a) { \
+    int i;                                                             \
+    for (i=0; i<NB; i++) {                                             \
+      dest[i] = OP a[i];                                               \
+    }                                                                  \
+}
+
+#define FUNC_FLOAT(SIGN, TYPE, BITS, NB, OP, NAME)                             \
+  void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE * __restrict__ dest, TYPE *a) { \
+    int i;                                                             \
+    for (i=0; i<NB; i++) {                                             \
+      dest[i] = OP a[i];                                               \
+    }                                                                  \
+}
+
+/* vmnvq supports only 16-bit and 32-bit elements.  */
+/* 64-bit vectors.  */
+FUNC(s, int, 32, 2, -, vneg)
+FUNC(u, uint, 32, 2, -, vneg)
+FUNC(s, int, 16, 4, -, vneg)
+FUNC(u, uint, 16, 4, -, vneg)
+FUNC(s, int, 8, 8, -, vneg)
+FUNC(u, uint, 8, 8, -, vneg)
+FUNC_FLOAT(f, float, 32, 2, -, vneg)
+FUNC(f, float, 16, 4, -, vneg)
+
+/* 128-bit vectors.  */
+FUNC(s, int, 32, 4, -, vneg)
+FUNC(u, uint, 32, 4, -, vneg)
+FUNC(s, int, 16, 8, -, vneg)
+FUNC(u, uint, 16, 8, -, vneg)
+FUNC(s, int, 8, 16, -, vneg)
+FUNC(u, uint, 8, 16, -, vneg)
+FUNC_FLOAT(f, float, 32, 4, -, vneg)
+FUNC(f, float, 16, 8, -, vneg)
+
+/* MVE has only 128-bit vectors, so we can vectorize only half of the
+   functions above.  */
+/* { dg-final { scan-assembler-times {vneg.s[0-9]+  q[0-9]+, q[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {vneg.f[0-9]+  q[0-9]+, q[0-9]+} 2 } } */