Fix compile error

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index a1a397b83f0e48156d07a514aadb92d82396fe43..31e11c7426c46ce73f614473b91868fef962b0f4 100644 (file)
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -23,10 +23,6 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-template<class T> inline bool includes(const T &lhs, const T &rhs) {
-       return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end());
-}
-#include <set>
 #include "passes/pmgen/ice40_dsp_pm.h"
 
 void create_ice40_dsp(ice40_dsp_pm &pm)

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index cf7957ff31f890c4e2da2ab1c770221e63439728..24bdfd3f2e4d83d9ed6964d05d6c46103645ae69 100644 (file)
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -34,7 +34,6 @@ match ffA
        if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
        if !sigAset.empty()
        select ffA->type.in($dff)
-       filter includes(port(ffA, \Q).to_sigbit_set(), sigAset)
        optional
 endmatch
 
@@ -42,6 +41,10 @@ code sigA clock clock_pol
        sigA = port(mul, \A);
 
        if (ffA) {
+               auto ffAset = port(ffA, \Q).to_sigbit_set();
+               if (!std::includes(ffAset.begin(), ffAset.end(), sigAset.begin(), sigAset.end()))
+                       reject;
+
                for (auto b : port(ffA, \Q))
                        if (b.wire->get_bool_attribute(\keep))
                                reject;
@@ -57,7 +60,6 @@ match ffB
        if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
        if !sigBset.empty()
        select ffB->type.in($dff)
-       filter includes(port(ffB, \Q).to_sigbit_set(), sigBset)
        optional
 endmatch
 
@@ -65,6 +67,10 @@ code sigB clock clock_pol
        sigB = port(mul, \B);
 
        if (ffB) {
+               auto ffBset = port(ffB, \Q).to_sigbit_set();
+               if (!std::includes(ffBset.begin(), ffBset.end(), sigBset.begin(), sigBset.end()))
+                       reject;
+
                for (auto b : port(ffB, \Q))
                        if (b.wire->get_bool_attribute(\keep))
                                reject;
@@ -207,7 +213,9 @@ code
        if (ffO_lo) {
                SigSpec O = sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()));
                O.remove_const();
-               if (!includes(port(ffO_lo, \D).to_sigbit_set(), O.to_sigbit_set()))
+               auto ffO_loSet = port(ffO_lo, \D).to_sigbit_set();
+               auto Oset = O.to_sigbit_set();
+               if (!std::includes(ffO_loSet.begin(), ffO_loSet.end(), Oset.begin(), Oset.end()))
                        reject;
        }
 endcode
@@ -223,7 +231,9 @@ code
        if (ffO_hi) {
                SigSpec O = sigOused.extract_end(16);
                O.remove_const();
-               if (!includes(port(ffO_hi, \D).to_sigbit_set(), O.to_sigbit_set()))
+               auto ffO_hiSet = port(ffO_hi, \D).to_sigbit_set();
+               auto Oset = O.to_sigbit_set();
+               if (!std::includes(ffO_hiSet.begin(), ffO_hiSet.end(), Oset.begin(), Oset.end()))
                        reject;
        }
 endcode