Add (* abc_arrival=<int> *) doc

diff --git a/README.md b/README.md
index fe30348eb77fa621317083e2d0063393dcb2cff1..63cefaf26301f6c370c7da24fff8b2485b638cd7 100644 (file)
--- a/README.md
+++ b/README.md
@@ -414,6 +414,11 @@ Verilog Attributes and non-standard features
   `abc9` to preserve the integrity of carry-chains. Specifying this attribute
   onto a bus port will affect only its most significant bit.
 
+- The port attribute ``abc_arrival`` specifies an integer (for output ports
+  only) to be used as the arrival time of this sequential port. It can be used,
+  for example, to specify the clk-to-Q delay of a flip-flop for consideration
+  during techmapping.
+
 
 Non-standard or SystemVerilog features for formal verification
 ==============================================================