self.shared_pads = UARTPads()
self.bridge_pads = UARTPads()
- ###
+ # # #
+
# Route rx pad:
# when sel==0, route it to shared rx and bridge rx
# when sel==1, route it only to bridge rx
self.wishbone = wishbone.Interface()
if share_uart:
self._sel = CSRStorage()
- ###
+
+ # # #
+
if share_uart:
mux = UARTMux(pads)
uart = UARTPHYSerial(mux.bridge_pads, clk_freq, baudrate)
)
]
- ###
fsm = InsertReset(FSM(reset_state="IDLE"))
timeout = Timeout(clk_freq//10)
self.submodules += fsm, timeout
self.trig = Signal(dw)
self.mask = Signal(dw)
- ###
+
+ # # #
+
self.comb += [
source.stb.eq(sink.stb),
source.hit.eq((sink.data & self.mask) == self.trig),
LiteScopeTermUnit.__init__(self, dw)
self._trig = CSRStorage(dw)
self._mask = CSRStorage(dw)
- ###
+
+ # # #
+
self.comb += [
self.trig.eq(self._trig.storage),
self.mask.eq(self._mask.storage)
self.low = Signal(dw)
self.high = Signal(dw)
- ###
+
+ # # #
+
self.comb += [
source.stb.eq(sink.stb),
source.hit.eq((sink.data >= self.low) & (sink.data <= self.high)),
LiteScopeRangeDetectorUnit.__init__(self, dw)
self._low = CSRStorage(dw)
self._high = CSRStorage(dw)
- ###
+
+ # # #
+
self.comb += [
self.low.eq(self._low.storage),
self.high.eq(self._high.storage)
self.rising_mask = Signal(dw)
self.falling_mask = Signal(dw)
self.both_mask = Signal(dw)
- ###
+
+ # # #
+
self.buffer = Buffer(self.sink.description)
self.comb += Record.connect(self.sink, self.buffer.sink)
self._rising = CSRStorage(dw)
self._falling = CSRStorage(dw)
self._both = CSRStorage(dw)
- ###
+
+ # # #
+
self.comb += [
self.rising.eq(self._rising.storage),
self.falling.eq(self._falling.storage),
self.sink = sink = Sink(data_layout(dw))
self.source = source = Source(data_layout(dw))
self.value = Signal(32)
- ###
+
+ # # #
+
self.submodules.counter = Counter(32)
done = Signal()
self.comb += [
def __init__(self, dw):
LiteScopeSubSamplerUnit.__init__(self, dw)
self._value = CSRStorage(32)
- ###
+
+ # # #
+
self.comb += self.value.eq(self._value.storage)
self.source = source = Source(data_layout(dw))
self.enable = Signal()
- ###
+
+ # # #
+
self.submodules.buf = buf = Buffer(sink.description)
self.comb += Record.connect(sink, buf.d)
LiteScopeRunLengthEncoderUnit.__init__(self, dw, length)
self._enable = CSRStorage()
self.external_enable = Signal(reset=1)
- ###
+
+ # # #
+
self.comb += self.enable.eq(self._enable.storage & self.external_enable)
self.source = Source(data_layout(dw))
- ###
+ # # #
fifo = InsertReset(SyncFIFO(data_layout(dw), depth, buffered=True))
self.submodules += fifo
self._source_ack = CSR()
self._source_data = CSRStatus(dw)
- ###
+ # # #
self.comb += [
self.trigger.eq(self._trigger.re),
prog = mem.get_port(write_capable=True)
self.specials += mem, lut, prog
- ###
+ # # #
# program port
self.comb += [
self._prog_we = CSR()
self._prog_adr = CSRStorage(ports)
self._prog_dat = CSRStorage()
- ###
+
+ # # #
+
self.comb += [
self.prog_we.eq(self._prog_we.re & self._prog_we.r),
self.prog_adr.eq(self._prog_adr.storage),
def do_finalize(self):
self.submodules.sum = LiteScopeSum(len(self.ports))
- ###
for i, port in enumerate(self.ports):
# Note: port's ack is not used and supposed to be always 1
self.comb += [
def led_anim1(io):
for j in range(4):
- #Led <<
+ # Led <<
led_data = 1
for i in range(8):
io.write(led_data)
time.sleep(i*i*0.0020)
led_data = (led_data<<1)
- #Led >>
+ # Led >>
ledData = 128
for i in range(8):
io.write(led_data)
def main(wb):
io = LiteScopeIODriver(wb.regs, "io")
wb.open()
- ###
+ # # #
led_anim0(io)
led_anim1(io)
print("{:02X}".format(io.read()))
- ###
+ # # #
wb.close()
def main(wb):
wb.open()
- ###
+ # # #
la = LiteScopeLADriver(wb.regs, "la", debug=True)
- #cond = {"cnt0" : 128} # trigger on cnt0 = 128
+ # cond = {"cnt0" : 128} # trigger on cnt0 = 128
cond = {} # trigger on cnt0 = 128
la.configure_term(port=0, cond=cond)
la.configure_sum("term")
la.configure_subsampler(1)
- #la.configure_qualifier(1)
+ # la.configure_qualifier(1)
la.configure_rle(1)
la.run(offset=128, length=256)
la.save("dump.csv")
la.save("dump.py")
la.save("dump.sr")
- ###
+ # # #
wb.close()
def main(wb):
wb.open()
regs = wb.regs
- ###
+ # # #
print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
- ###
+ # # #
wb.close()
projects / litex.git / commitdiff