(no commit message)

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 80c6e7eac60609f93354fd9d41dcb994c1d2eed8..1b5953d9c817a4aeca2e3aeee54161a149d22c83 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -193,7 +193,7 @@ of LDs, which may be valuable in Embedded scenarios.
 
 # Vectorisation of Scalar Power ISA v3.0B
 
-OpenPOWER Load/Store operations may be seen from [[isa/fixedload]] and
+Scalar Power ISA Load/Store operations may be seen from [[isa/fixedload]] and
 [[isa/fixedstore]] pseudocode to be of the form:
 
     lbux RT, RA, RB
@@ -212,7 +212,7 @@ example only the one source and one dest may be marked as scalar or
 vector.
 
 Thus we can see that Vector Indexed may be covered, and, as demonstrated
-with the pseudocode below, the immediate can be used to give unit stride or element stride.  With there being no way to tell which from the OpenPOWER v3.0B Scalar opcode alone, the choice is provided instead by the SV Context.
+with the pseudocode below, the immediate can be used to give unit stride or element stride.  With there being no way to tell which from the Power v3.0B Scalar opcode alone, the choice is provided instead by the SV Context.
 
     # LD not VLD!  format - ldop RT, immed(RA)
     # op_width: lb=1, lh=2, lw=4, ld=8
@@ -383,7 +383,7 @@ is implemented.
 
 # LOAD/STORE Elwidths <a name="elwidth"></a>
 
-Loads and Stores are almost unique in that the OpenPOWER Scalar ISA
+Loads and Stores are almost unique in that the Power Scalar ISA
 provides a width for the operation (lb, lh, lw, ld).  Only `extsb` and
 others like it provide an explicit operation width.  There are therefore
 *three* widths involved:
@@ -406,10 +406,10 @@ which are expressly in this order:
    - Sign-extension or truncation from operation width to dest width
    - signed/unsigned saturation down to dest elwidth
 
-In order to respect OpenPOWER v3.0B Scalar behaviour the memory side
+In order to respect Power v3.0B Scalar behaviour the memory side
 is treated effectively as completely separate and distinct from SV
 augmentation.  This is primarily down to quirks surrounding LE/BE and
-byte-reversal in OpenPOWER.
+byte-reversal.
 
 It is rather unfortunately possible to request an elwidth override
 on the memory side which