abc9_ops: -prep_dff_map to error if async flop found

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index ee25866c377ce0344aa98f05419370a8a4fc219b..62007c61e7be624abf834f0d862191920da7fa63 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -181,7 +181,7 @@ void prep_dff_map(RTLIL::Design *design)
                for (auto cell : module->cells())
                        if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
                                if (dff_cell)
-                                       log_error("More than one $_DFF_[NP]_ cell found in module '%s' marked (* abc9_flop *)\n", log_id(module));
+                                       log_error("Module '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", log_id(module));
                                dff_cell = cell;
 
                                // Block sequential synthesis on cells with (* init *) != 1'b0
@@ -207,10 +207,15 @@ void prep_dff_map(RTLIL::Design *design)
                                        goto continue_outer_loop;
                                }
                        }
+                       else if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+                                               ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
+                                               ID($__DFFE_NN0), ID($__DFFE_NN1), ID($__DFFE_NP0), ID($__DFFE_NP1),
+                                               ID($__DFFE_PN0), ID($__DFFE_PN1), ID($__DFFE_PP0), ID($__DFFE_PP1)))
+                               log_error("Module '%s' with (* abc9_flop *) contains an asynchronous $_DFFE?_[NP][NP][01]_? cell, which is not supported for sequential synthesis.\n", log_id(module));
                        else if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
                                specify_cells.emplace_back(cell);
                if (!dff_cell)
-                       log_error("$_DFF_[NP]_ cell not found in module '%s' marked (* abc9_flop *)\n", log_id(module));
+                       log_error("Module '%s' with (* abc9_flop *) does not any contain $_DFF_[NP]_ cells.\n", log_id(module));
 
                D = dff_cell->getPort(ID::D);
 
@@ -229,9 +234,6 @@ void prep_dff_map(RTLIL::Design *design)
                        D = w;
                }
 
-               if (GetSize(specify_cells) == 0)
-                       log_error("Module '%s' marked (* abc9_flop *) contains no specify timing information.\n", log_id(module));
-
                // Rewrite $specify cells that end with $_DFF_[NP]_.Q
                //   to $_DFF_[NP]_.D since it will be moved into
                //   the submodule

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 5143f87da403e86a51ca74230a37b5edaa013924..25df3a8652325b120319ac05c378312edf0c122d 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -656,7 +656,6 @@ module FDRSE (
       Q <= d;
 endmodule
 
-(* lib_whitebox *)
 module FDCE (
   output reg Q,
   (* clkbuf_sink *)
@@ -699,7 +698,6 @@ module FDCE (
   endspecify
 endmodule
 
-(* lib_whitebox *)
 module FDCE_1 (
   output reg Q,
   (* clkbuf_sink *)
@@ -724,7 +722,6 @@ module FDCE_1 (
   endspecify
 endmodule
 
-(* lib_whitebox *)
 module FDPE (
   output reg Q,
   (* clkbuf_sink *)
@@ -766,7 +763,6 @@ module FDPE (
   endspecify
 endmodule
 
-(* lib_whitebox *)
 module FDPE_1 (
   output reg Q,
   (* clkbuf_sink *)