soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1

diff --git a/litex/soc/cores/icap.py b/litex/soc/cores/icap.py
index 6c312dda4a8f11f2c9f626f565114f9d2ce1a3f4..5d7626b1afcb271b16efdd12959e46fa30a14658 100644 (file)
--- a/litex/soc/cores/icap.py
+++ b/litex/soc/cores/icap.py
@@ -112,9 +112,9 @@ class ICAPBitstream(Module, AutoCSR):
         self._csib = _csib = Signal(reset=1)
         self._i    =    _i = Signal(32, reset=0xffffffff)
         self.comb += [
+            fifo.source.ready.eq(1),
             If(fifo.source.valid,
                 _csib.eq(0),
-                fifo.source.ready.eq(1),
                 _i.eq(fifo.source.data)
             )
         ]