bus/csr: add configurable address_width (needed more than 32 modules with CSR)

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 80ce0fcb709f1fee7577fcaaf21d87f6612bc404..49dc55330886612099efeee7c247143bd7034755 100644 (file)
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -5,16 +5,16 @@ from migen.genlib.record import *
 from migen.genlib.misc import chooser
 
 _layout = [
-       ("adr",         14,                             DIR_M_TO_S),
-       ("we",          1,                              DIR_M_TO_S),
-       ("dat_w",       "data_width",   DIR_M_TO_S),
-       ("dat_r",       "data_width",   DIR_S_TO_M)
+       ("adr",         "address_width",        DIR_M_TO_S),
+       ("we",          1,                                      DIR_M_TO_S),
+       ("dat_w",       "data_width",           DIR_M_TO_S),
+       ("dat_r",       "data_width",           DIR_S_TO_M)
 ]
 
 class Interface(Record):
-       def __init__(self, data_width=8):
+       def __init__(self, data_width=8, address_width=14):
                Record.__init__(self, set_layout_parameters(_layout,
-                       data_width=data_width))
+                       data_width=data_width, address_width=address_width))
 
 class Interconnect(Module):
        def __init__(self, master, slaves):