mibuild/xilinx: share more code between ISE and Vivado, use special overrides with...

diff --git a/mibuild/xilinx_common.py b/mibuild/xilinx_common.py
index b9452b72d8d6e77acebe0191fea7c6356074c1a4..94ac17b7b07108d74ff1c25aaf8e8979d2cceb13 100644 (file)
--- a/mibuild/xilinx_common.py
+++ b/mibuild/xilinx_common.py
@@ -1,4 +1,34 @@
+import os
+from distutils.version import StrictVersion
+
 from migen.fhdl.std import *
+from migen.fhdl.specials import SynthesisDirective
+from migen.genlib.cdc import *
+from mibuild.generic_platform import GenericPlatform
+from mibuild import tools
+
+def settings(path, ver=None, sub=None):
+       vers = list(tools.versions(path))
+       if ver is None:
+               ver = max(vers)
+       else:
+               ver = StrictVersion(ver)
+               assert ver in vers
+
+       full = os.path.join(path, str(ver))
+       if sub:
+               full = os.path.join(full, sub)
+
+       search = [64, 32]
+       if tools.arch_bits() == 32:
+               search.reverse()
+
+       for b in search:
+               settings = os.path.join(full, "settings{0}.sh".format(b))
+               if os.path.exists(settings):
+                       return settings
+
+       raise ValueError("no settings file found")
 
 class CRG_DS(Module):
        def __init__(self, platform, clk_name, rst_name, rst_invert=False):
@@ -16,3 +46,36 @@ class CRG_DS(Module):
                        else:
                                self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
 
+class XilinxNoRetimingImpl(Module):
+       def __init__(self, reg):
+               self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg)
+
+class XilinxNoRetiming:
+       @staticmethod
+       def lower(dr):
+               return XilinxNoRetimingImpl(dr.reg)
+
+class XilinxMultiRegImpl(MultiRegImpl):
+       def __init__(self, *args, **kwargs):
+               MultiRegImpl.__init__(self, *args, **kwargs)
+               self.specials += [SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
+                       for r in self.regs]
+
+class XilinxMultiReg:
+       @staticmethod
+       def lower(dr):
+               return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
+
+class XilinxGenericPlatform(GenericPlatform):
+       bitstream_ext = ".bit"
+
+       def get_verilog(self, *args, special_overrides=dict(), **kwargs):
+               so = {
+                       NoRetiming: XilinxNoRetiming,
+                       MultiReg:   XilinxMultiReg
+               }
+               so.update(special_overrides)
+               return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
+
+       def get_edif(self, fragment, **kwargs):
+               return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs)

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 12a5862dba48989df97bbcaa6707996d8148c7e9..b34a9627503553508fb9a6750c903d56471b17c4 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -1,12 +1,10 @@
 import os, subprocess, sys
 
 from migen.fhdl.std import *
-from migen.fhdl.specials import SynthesisDirective
-from migen.genlib.cdc import *
 from migen.fhdl.structure import _Fragment
 
 from mibuild.generic_platform import *
-from mibuild import tools, xilinx_tools
+from mibuild import tools, xilinx_common
 
 def _format_constraint(c):
        if isinstance(c, Pins):
@@ -94,7 +92,7 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
                source = False
        build_script_contents = "# Autogenerated by mibuild\nset -e\n"
        if source:
-               settings = xilinx_tools.settings(ise_path, ver, "ISE_DS")
+               settings = xilinx_common.settings(ise_path, ver, "ISE_DS")
                build_script_contents += "source " + settings + "\n"
        if mode == "edif":
                ext = "edif"
@@ -121,28 +119,7 @@ bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit
        if r != 0:
                raise OSError("Subprocess failed")
 
-class XilinxNoRetimingImpl(Module):
-       def __init__(self, reg):
-               self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg)
-
-class XilinxNoRetiming:
-       @staticmethod
-       def lower(dr):
-               return XilinxNoRetimingImpl(dr.reg)
-
-class XilinxMultiRegImpl(MultiRegImpl):
-       def __init__(self, *args, **kwargs):
-               MultiRegImpl.__init__(self, *args, **kwargs)
-               self.specials += [SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
-                       for r in self.regs]
-
-class XilinxMultiReg:
-       @staticmethod
-       def lower(dr):
-               return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
-
-class XilinxISEPlatform(GenericPlatform):
-       bitstream_ext = ".bit"
+class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform):
        xst_opt = """-ifmt MIXED
 -opt_mode SPEED
 -register_balancing yes"""
@@ -151,16 +128,6 @@ class XilinxISEPlatform(GenericPlatform):
        ngdbuild_opt = ""
        bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w"
        ise_commands = ""
-       def get_verilog(self, *args, special_overrides=dict(), **kwargs):
-               so = {
-                       NoRetiming: XilinxNoRetiming,
-                       MultiReg:   XilinxMultiReg
-               }
-               so.update(special_overrides)
-               return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
-
-       def get_edif(self, fragment, **kwargs):
-               return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs)
 
        def build(self, fragment, build_dir="build", build_name="top",
                        ise_path="/opt/Xilinx", source=True, run=True, mode="xst"):

diff --git a/mibuild/xilinx_tools.py b/mibuild/xilinx_tools.py
deleted file mode 100644 (file)
index 98c2e21..0000000
--- a/mibuild/xilinx_tools.py
+++ /dev/null
@@ -1,27 +0,0 @@
-import os
-from distutils.version import StrictVersion
-
-from mibuild import tools
-
-def settings(path, ver=None, sub=None):
-       vers = list(tools.versions(path))
-       if ver is None:
-               ver = max(vers)
-       else:
-               ver = StrictVersion(ver)
-               assert ver in vers
-
-       full = os.path.join(path, str(ver))
-       if sub:
-               full = os.path.join(full, sub)
-
-       search = [64, 32]
-       if tools.arch_bits() == 32:
-               search.reverse()
-
-       for b in search:
-               settings = os.path.join(full, "settings{0}.sh".format(b))
-               if os.path.exists(settings):
-                       return settings
-
-       raise ValueError("no settings file found")

diff --git a/mibuild/xilinx_vivado.py b/mibuild/xilinx_vivado.py
index cba54ac0cc62c4c4026936e380a434b6927c4501..83dd4edf81971001e7205954b80f2c58faa98c9c 100644 (file)
--- a/mibuild/xilinx_vivado.py
+++ b/mibuild/xilinx_vivado.py
@@ -5,9 +5,9 @@ import os, subprocess, sys
 
 from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
-
 from mibuild.generic_platform import *
-from mibuild import tools, xilinx_tools
+
+from mibuild import tools, xilinx_common
 
 def _format_constraint(c):
        if isinstance(c, Pins):
@@ -61,7 +61,7 @@ def _run_vivado(build_name, vivado_path, source, ver=None):
                source = False
        build_script_contents = "# Autogenerated by mibuild\nset -e\n"
        if source:
-               settings = xilinx_tools.settings(vivado_path, ver)
+               settings = xilinx_common.settings(vivado_path, ver)
                build_script_contents += "source " + settings + "\n"
        build_script_contents += "vivado -mode tcl -source " + build_name + ".tcl\n"
        build_script_file = "build_" + build_name + ".sh"
@@ -71,13 +71,7 @@ def _run_vivado(build_name, vivado_path, source, ver=None):
        if r != 0:
                raise OSError("Subprocess failed")
 
-class XilinxVivadoPlatform(GenericPlatform):
-       bitstream_ext = ".bit"
-       def get_verilog(self, *args, special_overrides=dict(), **kwargs):
-               so = {}
-               so.update(special_overrides)
-               return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
-
+class XilinxVivadoPlatform(xilinx_common.XilinxGenericPlatform):
        def build(self, fragment, build_dir="build", build_name="top",
                        vivado_path="/opt/Xilinx/Vivado", source=True, run=True):
                tools.mkdir_noerror(build_dir)