(no commit message)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 221b2881dc8c71d556eabbacb093e46df68557a6..bb13521aab65e018e945e28175f41d933adf216d 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -117,7 +117,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
 * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO)
 * Another 24-bit (a second 2-bit XO) is needed for a planned future encoding,
   currently named "SVP64-Single" [^likeext001]
-* A third 24-bits (third 2-bit XO) is strongly recommended to be **reserved**
+* A third 24-bits (third 2-bit XO) is strongly recommended to be `RESERVED`
   such that future unforeseen capability is needed.
 * To hold all Vector Context, five SPRs are needed for userspace.
   If Supervisor and Hypervisor mode are to