intel: genxml: decode variable length MI_LRI

MI_LOAD_REGISTER_IMM can load multiple (register, value) tuples in one
command. In our drivers we only use one tuple at a time, but the
kernel might load more than one at a time.

Instead of making all the tuple part of a group, we leave out the
first tuple (the one we use in the generated packing structures).

This is particularly useful for looking at error stats generated by
the kernel.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index bd914ad10ee5bc8fda7424741c697bce2b5c2d8b..8c35d70e9d293c975ff48dcdca57a95d9985194a 100644 (file)
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -2969,6 +2969,10 @@
     <field name="DWord Length" start="0" end="7" type="uint" default="1"/>
     <field name="Register Offset" start="34" end="54" type="offset"/>
     <field name="Data DWord" start="64" end="95" type="uint"/>
+    <group count="0" start="96" size="64">
+      <field name="Register Offset" start="2" end="22" type="offset"/>
+      <field name="Data DWord" start="32" end="63" type="uint"/>
+    </group>
   </instruction>
 
   <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4">

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index cb3212620f521c68aa3fc1b3fd08ef5e38d42622..517f0beb93b0030e179b3fd8894b79311da1ea2a 100644 (file)
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -2956,6 +2956,10 @@
     <field name="DWord Length" start="0" end="7" type="uint" default="1"/>
     <field name="Register Offset" start="34" end="54" type="offset"/>
     <field name="Data DWord" start="64" end="95" type="uint"/>
+    <group count="0" start="96" size="64">
+      <field name="Register Offset" start="2" end="22" type="offset"/>
+      <field name="Data DWord" start="32" end="63" type="uint"/>
+    </group>
   </instruction>
 
   <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4">

diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
index e1ca810f236096818b45b5bd77dbe5f2aac942d1..6f513c5833bf2afe77e4ba407f346a22eee64201 100644 (file)
--- a/src/intel/genxml/gen4.xml
+++ b/src/intel/genxml/gen4.xml
@@ -860,6 +860,10 @@
     <field name="DWord Length" start="0" end="5" type="uint" default="1"/>
     <field name="Register Offset" start="34" end="63" type="offset"/>
     <field name="Data DWord" start="64" end="95" type="uint"/>
+    <group count="0" start="96" size="64">
+      <field name="Register Offset" start="2" end="31" type="offset"/>
+      <field name="Data DWord" start="32" end="63" type="uint"/>
+    </group>
   </instruction>
 
   <instruction name="MI_STORE_DATA_IMM" bias="2" length="5">

diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index 91dc3634801a421f57d4c4c51c78d53fe8d8d218..fbd57a00c505df8652da06349f804498b0b29823 100644 (file)
--- a/src/intel/genxml/gen45.xml
+++ b/src/intel/genxml/gen45.xml
@@ -890,6 +890,10 @@
     <field name="DWord Length" start="0" end="5" type="uint" default="1"/>
     <field name="Register Offset" start="34" end="63" type="offset"/>
     <field name="Data DWord" start="64" end="95" type="uint"/>
+    <group count="0" start="96" size="64">
+      <field name="Register Offset" start="2" end="31" type="offset"/>
+      <field name="Data DWord" start="32" end="63" type="uint"/>
+    </group>
   </instruction>
 
   <instruction name="MI_STORE_DATA_IMM" bias="2" length="5">

diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index 650692f6bda5d448fa775cb917d7b0a531c0baf5..5c93ecdda30fac0c1d3321deba8cc8efd902f6bf 100644 (file)
--- a/src/intel/genxml/gen5.xml
+++ b/src/intel/genxml/gen5.xml
@@ -974,6 +974,10 @@
     <field name="DWord Length" start="0" end="5" type="uint" default="1"/>
     <field name="Register Offset" start="34" end="63" type="offset"/>
     <field name="Data DWord" start="64" end="95" type="uint"/>
+    <group count="0" start="96" size="64">
+      <field name="Register Offset" start="2" end="31" type="offset"/>
+      <field name="Data DWord" start="32" end="63" type="uint"/>
+    </group>
   </instruction>
 
   <instruction name="MI_STORE_DATA_IMM" bias="2" length="5">

diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml
index 08779733dbd5e30508706d4202f07569ead70584..0493221bd7273fe665118bb91fcdfacf9ec4b1c1 100644 (file)
--- a/src/intel/genxml/gen6.xml
+++ b/src/intel/genxml/gen6.xml
@@ -1531,6 +1531,10 @@
     <field name="DWord Length" start="0" end="7" type="uint" default="1"/>
     <field name="Register Offset" start="34" end="54" type="offset"/>
     <field name="Data DWord" start="64" end="95" type="uint"/>
+    <group count="0" start="96" size="64">
+      <field name="Register Offset" start="2" end="22" type="offset"/>
+      <field name="Data DWord" start="32" end="63" type="uint"/>
+    </group>
   </instruction>
 
   <instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2">

diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 4865843fcbbad6f3fe54b551e8589fe344c8eeac..baf42a7d32d32602632fc20d666524fde26632e1 100644 (file)
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2020,6 +2020,10 @@
     <field name="DWord Length" start="0" end="7" type="uint" default="1"/>
     <field name="Register Offset" start="34" end="54" type="offset"/>
     <field name="Data DWord" start="64" end="95" type="uint"/>
+    <group count="0" start="96" size="64">
+      <field name="Register Offset" start="2" end="22" type="offset"/>
+      <field name="Data DWord" start="32" end="63" type="uint"/>
+    </group>
   </instruction>
 
   <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="3">

diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index da06e84ee918ffdb069c43d79294ac6272e8925f..7b635b22dacaddca58ae190ef1373cd8fd911c97 100644 (file)
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2380,6 +2380,10 @@
     <field name="DWord Length" start="0" end="7" type="uint" default="1"/>
     <field name="Register Offset" start="34" end="54" type="offset"/>
     <field name="Data DWord" start="64" end="95" type="uint"/>
+    <group count="0" start="96" size="64">
+      <field name="Register Offset" start="2" end="22" type="offset"/>
+      <field name="Data DWord" start="32" end="63" type="uint"/>
+    </group>
   </instruction>
 
   <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="3">

diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 28fbdfdf09a04cb86bfb67a8af10343c26b1252d..0f3757034f3a5d09be1b09380fc50deb850ed95e 100644 (file)
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2607,6 +2607,10 @@
     <field name="DWord Length" start="0" end="7" type="uint" default="1"/>
     <field name="Register Offset" start="34" end="54" type="offset"/>
     <field name="Data DWord" start="64" end="95" type="uint"/>
+    <group count="0" start="64" size="64">
+      <field name="Register Offset" start="2" end="22" type="offset"/>
+      <field name="Data DWord" start="32" end="63" type="uint"/>
+    </group>
   </instruction>
 
   <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4">

diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 0912b6f7fe42689946580bab4d2bd6e38f7995aa..7d3c74de74cd3822336e62af73d49feaeb422a7d 100644 (file)
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2894,6 +2894,10 @@
     <field name="DWord Length" start="0" end="7" type="uint" default="1"/>
     <field name="Register Offset" start="34" end="54" type="offset"/>
     <field name="Data DWord" start="64" end="95" type="uint"/>
+    <group count="0" start="96" size="64">
+      <field name="Register Offset" start="2" end="22" type="offset"/>
+      <field name="Data DWord" start="32" end="63" type="uint"/>
+    </group>
   </instruction>
 
   <instruction name="MI_LOAD_REGISTER_MEM" bias="2" length="4">