arch,cpu: Get rid of unused/unimplemented vtophys variants.

The version of vtophys which didn't take a ThreadContext had only been
implemented on Alpha which has since been removed, so this version of
the function was completely unimplemented and never used.

This change also gets rid of the dbg_vtophys which was sometimes
implemented but also never used, and takes the opportunity to fix up
some style problems in some of the vtophys arch files.

Change-Id: Ie10f881f8ce08c7188e71805357cf3264be4c81a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26224
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/vtophys.cc b/src/arch/arm/vtophys.cc
index c915fa7f6244d145d291805d2971da870e005a99..62f4d78f4cdabe68f20593df8f8f7adf0687a6a7 100644 (file)
--- a/src/arch/arm/vtophys.cc
+++ b/src/arch/arm/vtophys.cc
@@ -54,12 +54,6 @@
 using namespace std;
 using namespace ArmISA;
 
-Addr
-ArmISA::vtophys(Addr vaddr)
-{
-    fatal("VTOPHYS: Can't convert vaddr to paddr on ARM without a thread context");
-}
-
 static std::pair<bool, Addr>
 try_translate(ThreadContext *tc, Addr addr)
 {
@@ -97,7 +91,8 @@ ArmISA::vtophys(ThreadContext *tc, Addr addr)
     if (translation.first)
         return translation.second;
     else
-        panic("Table walkers support functional accesses. We should never get here\n");
+        panic("Table walkers support functional accesses. "
+                "We should never get here.");
 }
 
 bool

diff --git a/src/arch/arm/vtophys.hh b/src/arch/arm/vtophys.hh
index a72a24b7b9556e02b842b50209d7ed66ebf9a2e3..7810b9885bd2a29286fc7d309aa2e43a0aba5358 100644 (file)
--- a/src/arch/arm/vtophys.hh
+++ b/src/arch/arm/vtophys.hh
@@ -27,21 +27,23 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_ARM_VTOPHYS_H__
-#define __ARCH_ARM_VTOPHYS_H__
+#ifndef __ARCH_ARM_VTOPHYS_HH__
+#define __ARCH_ARM_VTOPHYS_HH__
 
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/utility.hh"
 
 class ThreadContext;
 
-namespace ArmISA {
-    inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
+namespace ArmISA
+{
 
-    Addr vtophys(Addr vaddr);
-    Addr vtophys(ThreadContext *tc, Addr vaddr);
-    bool virtvalid(ThreadContext *tc, Addr vaddr);
-}
+inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
 
-#endif // __ARCH_ARM_VTOPHYS_H__
+Addr vtophys(ThreadContext *tc, Addr vaddr);
+bool virtvalid(ThreadContext *tc, Addr vaddr);
+
+} // namespace ArmISA
+
+#endif // __ARCH_ARM_VTOPHYS_HH__
 

diff --git a/src/arch/mips/vtophys.cc b/src/arch/mips/vtophys.cc
index d37f5a1ea1a8ca24506e9c8473805ba92357b721..b4711fa3399e002bef03da2829658507f3442d03 100644 (file)
--- a/src/arch/mips/vtophys.cc
+++ b/src/arch/mips/vtophys.cc
@@ -29,22 +29,7 @@
 
 #include "arch/mips/vtophys.hh"
 
-#include <string>
-
-#include "base/chunk_generator.hh"
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-#include "debug/VtoPhys.hh"
-
-using namespace std;
-using namespace MipsISA;
-
-Addr
-MipsISA::vtophys(Addr vaddr)
-{
-    fatal("VTOPHYS: Unimplemented on MIPS\n");
-    return 0;
-}
+#include "base/logging.hh"
 
 Addr
 MipsISA::vtophys(ThreadContext *tc, Addr addr)

diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh
index 0f70c7701ee58ac538ec87ce4a505987ce87a4c7..045d5baa7689dde720d2ea168b9b05de9681f94c 100644 (file)
--- a/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@ -27,18 +27,20 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_MIPS_VTOPHYS_H__
-#define __ARCH_MIPS_VTOPHYS_H__
+#ifndef __ARCH_MIPS_VTOPHYS_HH__
+#define __ARCH_MIPS_VTOPHYS_HH__
 
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/utility.hh"
 
 class ThreadContext;
 
-namespace MipsISA {
-    Addr vtophys(Addr vaddr);
-    Addr vtophys(ThreadContext *tc, Addr vaddr);
+namespace MipsISA
+{
 
-};
-#endif // __ARCH_MIPS_VTOPHYS_H__
+Addr vtophys(ThreadContext *tc, Addr vaddr);
+
+} // namespace MipsISA
+
+#endif // __ARCH_MIPS_VTOPHYS_HH__
 

diff --git a/src/arch/power/vtophys.cc b/src/arch/power/vtophys.cc
index 9c57e41317c6d0333d1f5c42134ee11bdbaa469a..973facc3180da002641b3850bd25a13483b29ad0 100644 (file)
--- a/src/arch/power/vtophys.cc
+++ b/src/arch/power/vtophys.cc
@@ -30,12 +30,6 @@
 
 using namespace std;
 
-Addr
-PowerISA::vtophys(Addr vaddr)
-{
-    fatal("vtophys: Unimplemented on POWER\n");
-}
-
 Addr
 PowerISA::vtophys(ThreadContext *tc, Addr addr)
 {

diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh
index 2163494047912afbf02577bb58886eea0aaa22a3..650fb5f1f09da7569bc011fd2abf44c3992ef9a2 100644 (file)
--- a/src/arch/power/vtophys.hh
+++ b/src/arch/power/vtophys.hh
@@ -36,9 +36,9 @@
 
 class ThreadContext;
 
-namespace PowerISA {
+namespace PowerISA
+{
 
-Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);
 
 inline Addr

diff --git a/src/arch/riscv/vtophys.hh b/src/arch/riscv/vtophys.hh
index 29d9f4fd909fc88f184cd83e3a18002ffa26b964..7dcc7af2d099fa1b0c7cc479b718adc22353579b 100644 (file)
--- a/src/arch/riscv/vtophys.hh
+++ b/src/arch/riscv/vtophys.hh
@@ -37,20 +37,13 @@
 
 class ThreadContext;
 
-namespace RiscvISA {
-
-inline Addr
-vtophys(Addr vaddr)
+namespace RiscvISA
 {
-    fatal("VTOPHYS: Unimplemented on RISC-V\n");
-    return vaddr;
-}
 
-inline Addr
+static inline Addr
 vtophys(ThreadContext *tc, Addr vaddr)
 {
     fatal("VTOPHYS: Unimplemented on RISC-V\n");
-    return vtophys(vaddr);
 }
 
 } // namespace RiscvISA

diff --git a/src/arch/sparc/vtophys.cc b/src/arch/sparc/vtophys.cc
index 80727e68f2b094fb9c3e041778f85d39ed95533c..906d082d031b42d33620fa4a3cfd6330dd4a293c 100644 (file)
--- a/src/arch/sparc/vtophys.cc
+++ b/src/arch/sparc/vtophys.cc
@@ -30,6 +30,7 @@
 
 #include <string>
 
+#include "arch/sparc/pagetable.hh"
 #include "arch/sparc/tlb.hh"
 #include "base/chunk_generator.hh"
 #include "base/compiler.hh"
@@ -40,20 +41,8 @@
 
 using namespace std;
 
-namespace SparcISA {
-
-Addr
-vtophys(Addr vaddr)
+namespace SparcISA
 {
-    // In SPARC it's almost always impossible to turn a VA->PA w/o a
-    // context The only times we can kinda do it are if we have a
-    // SegKPM mapping and can find the real address in the tlb or we
-    // have a physical adddress already (beacuse we are looking at the
-    // hypervisor) Either case is rare, so we'll just panic.
-
-    panic("vtophys() without context on SPARC largly worthless\n");
-    M5_DUMMY_RETURN;
-}
 
 Addr
 vtophys(ThreadContext *tc, Addr addr)

diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh
index c0d820fc52f31c4190f33b1d903cf8b50d589e9b..33cefff2a8e2233887fdbd8da477a296498c8ced 100644 (file)
--- a/src/arch/sparc/vtophys.hh
+++ b/src/arch/sparc/vtophys.hh
@@ -26,19 +26,19 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __ARCH_SPARC_VTOPHYS_H__
-#define __ARCH_SPARC_VTOPHYS_H__
+#ifndef __ARCH_SPARC_VTOPHYS_HH__
+#define __ARCH_SPARC_VTOPHYS_HH__
 
 #include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/pagetable.hh"
 
 class ThreadContext;
 
-namespace SparcISA {
+namespace SparcISA
+{
 
-Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);
 
-};
-#endif // __ARCH_SPARC_VTOPHYS_H__
+}; // namespace SparcISA
+
+#endif // __ARCH_SPARC_VTOPHYS_HH__
 

diff --git a/src/arch/x86/vtophys.cc b/src/arch/x86/vtophys.cc
index ed025f82f50bb2784e1306771e924feefeec63c3..5e07ddb3fbba62c99c48510e5fb6e02921fbe3d2 100644 (file)
--- a/src/arch/x86/vtophys.cc
+++ b/src/arch/x86/vtophys.cc
@@ -47,27 +47,18 @@
 
 using namespace std;
 
-namespace X86ISA
+Addr
+X86ISA::vtophys(ThreadContext *tc, Addr vaddr)
 {
-    Addr
-    vtophys(Addr vaddr)
-    {
-        panic("Need access to page tables\n");
-    }
-
-    Addr
-    vtophys(ThreadContext *tc, Addr vaddr)
-    {
-        Walker *walker = dynamic_cast<TLB *>(tc->getDTBPtr())->getWalker();
-        unsigned logBytes;
-        Addr addr = vaddr;
-        Fault fault = walker->startFunctional(
-                tc, addr, logBytes, BaseTLB::Read);
-        if (fault != NoFault)
-            panic("vtophys page walk returned fault\n");
-        Addr masked_addr = vaddr & mask(logBytes);
-        Addr paddr = addr | masked_addr;
-        DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
-        return paddr;
-    }
+    Walker *walker = dynamic_cast<TLB *>(tc->getDTBPtr())->getWalker();
+    unsigned logBytes;
+    Addr addr = vaddr;
+    Fault fault = walker->startFunctional(
+            tc, addr, logBytes, BaseTLB::Read);
+    if (fault != NoFault)
+        panic("vtophys page walk returned fault\n");
+    Addr masked_addr = vaddr & mask(logBytes);
+    Addr paddr = addr | masked_addr;
+    DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
+    return paddr;
 }

diff --git a/src/arch/x86/vtophys.hh b/src/arch/x86/vtophys.hh
index 93b423e19a6a65f0d5eb92a176e176c4f8abd36f..51ce8eb2e991b95c630c22294b6b7dc9878e60fc 100644 (file)
--- a/src/arch/x86/vtophys.hh
+++ b/src/arch/x86/vtophys.hh
@@ -45,7 +45,6 @@ class ThreadContext;
 namespace X86ISA
 {
 
-Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);
 
 }

diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 736911a7e39cb766ba8739065d957a1fd9b06985..16fcc14decf69c8bd72854316efdd7c152fc5fbd 100644 (file)
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -356,12 +356,6 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size,
    return fault;
 }
 
-Addr
-CheckerCPU::dbg_vtophys(Addr addr)
-{
-    return vtophys(tc, addr);
-}
-
 /**
  * Checks if the flags set by the Checker and Checkee match.
  */

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 763e3e9dfed770d79dab72647716b1d3e9204766..6bd702276f92d1132c30779b70bcdfff4f8b53c6 100644 (file)
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -135,8 +135,6 @@ class CheckerCPU : public BaseCPU, public ExecContext
     BaseTLB *itb;
     BaseTLB *dtb;
 
-    Addr dbg_vtophys(Addr addr);
-
     // ISAs like ARM can have multiple destination registers to check,
     // keep them all in a std::queue
     std::queue<InstResult> result;

diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
index 6fd21f587ac84925d795b9351958f9a1de8dd298..e0ebef61f35a22d99a98b7907eaf75717f96e3b6 100644 (file)
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -143,15 +143,6 @@ MinorCPU::unserialize(CheckpointIn &cp)
     BaseCPU::unserialize(cp);
 }
 
-Addr
-MinorCPU::dbg_vtophys(Addr addr)
-{
-    /* Note that this gives you the translation for thread 0 */
-    panic("No implementation for vtophy\n");
-
-    return 0;
-}
-
 void
 MinorCPU::wakeup(ThreadID tid)
 {

diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index c9dbb8fd998f3ad4e5cdfdafff31cf9c660a6499..b8ca087f5f85c2f799236a0519a7e9b41a9a52a7 100644 (file)
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -128,8 +128,6 @@ class MinorCPU : public BaseCPU
     void startup() override;
     void wakeup(ThreadID tid) override;
 
-    Addr dbg_vtophys(Addr addr);
-
     /** Processor-specific statistics */
     Minor::MinorStats stats;
 

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 6be7cc06d4bfc1d7eb299d44dc4e6ca247067ba7..2f616f1ec1e7541d494d0f4d999e4099b637d31b 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -422,12 +422,6 @@ change_thread_state(ThreadID tid, int activate, int priority)
 {
 }
 
-Addr
-BaseSimpleCPU::dbg_vtophys(Addr addr)
-{
-    return vtophys(threadContexts[curThread], addr);
-}
-
 void
 BaseSimpleCPU::wakeup(ThreadID tid)
 {

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index b270ff431d4b3c3cd9089f612fc52e1e4c209ffc..df17c26725516a9cfc170fef85fdcfeebca60702 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -121,9 +121,6 @@ class BaseSimpleCPU : public BaseCPU
     Status _status;
 
   public:
-    Addr dbg_vtophys(Addr addr);
-
-
     void checkForInterrupts();
     void setupFetchRequest(const RequestPtr &req);
     void preExecute();