Fix verific handling of anyconst/anyseq attributes

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 624c04be925a2c1c710bbeb1178fe20c4703db7e..7ebcbca0481711002e869cc674e6b89397371f29 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -189,12 +189,12 @@ RTLIL::SigSpec VerificImporter::operatorInport(Instance *inst, const char *portn
        }
 }
 
-RTLIL::SigSpec VerificImporter::operatorOutput(Instance *inst)
+RTLIL::SigSpec VerificImporter::operatorOutput(Instance *inst, const pool<Net*, hash_ptr_ops> *any_all_nets)
 {
        RTLIL::SigSpec sig;
        RTLIL::Wire *dummy_wire = NULL;
        for (int i = int(inst->OutputSize())-1; i >= 0; i--)
-               if (inst->GetOutputBit(i)) {
+               if (inst->GetOutputBit(i) && (!any_all_nets || !any_all_nets->count(inst->GetOutputBit(i)))) {
                        sig.append(net_map_at(inst->GetOutputBit(i)));
                        dummy_wire = NULL;
                } else {
@@ -394,6 +394,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
        #define IN1 operatorInput1(inst)
        #define IN2 operatorInput2(inst)
        #define OUT operatorOutput(inst)
+       #define FILTERED_OUT operatorOutput(inst, &any_all_nets)
        #define SIGNED inst->View()->IsSigned()
 
        if (inst->Type() == OPER_ADDER) {
@@ -525,7 +526,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
        }
 
        if (inst->Type() == OPER_WIDE_BUF) {
-               module->addPos(inst_name, IN, OUT, SIGNED);
+               module->addPos(inst_name, IN, FILTERED_OUT, SIGNED);
                return true;
        }
 
@@ -791,6 +792,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
        dict<Net*, char, hash_ptr_ops> init_nets;
        pool<Net*, hash_ptr_ops> anyconst_nets, anyseq_nets;
        pool<Net*, hash_ptr_ops> allconst_nets, allseq_nets;
+       any_all_nets.clear();
 
        FOREACH_NET_OF_NETLIST(nl, mi, net)
        {
@@ -871,23 +873,30 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
                const char *allconst_attr = net->GetAttValue("allconst");
                const char *allseq_attr = net->GetAttValue("allseq");
 
-               if (rand_const_attr != nullptr && (!strcmp(rand_const_attr, "1") || !strcmp(rand_const_attr, "'1'")))
+               if (rand_const_attr != nullptr && (!strcmp(rand_const_attr, "1") || !strcmp(rand_const_attr, "'1'"))) {
                        anyconst_nets.insert(net);
-
-               else if (rand_attr != nullptr && (!strcmp(rand_attr, "1") || !strcmp(rand_attr, "'1'")))
+                       any_all_nets.insert(net);
+               }
+               else if (rand_attr != nullptr && (!strcmp(rand_attr, "1") || !strcmp(rand_attr, "'1'"))) {
                        anyseq_nets.insert(net);
-
-               else if (anyconst_attr != nullptr && (!strcmp(anyconst_attr, "1") || !strcmp(anyconst_attr, "'1'")))
+                       any_all_nets.insert(net);
+               }
+               else if (anyconst_attr != nullptr && (!strcmp(anyconst_attr, "1") || !strcmp(anyconst_attr, "'1'"))) {
                        anyconst_nets.insert(net);
-
-               else if (anyseq_attr != nullptr && (!strcmp(anyseq_attr, "1") || !strcmp(anyseq_attr, "'1'")))
+                       any_all_nets.insert(net);
+               }
+               else if (anyseq_attr != nullptr && (!strcmp(anyseq_attr, "1") || !strcmp(anyseq_attr, "'1'"))) {
                        anyseq_nets.insert(net);
-
-               else if (allconst_attr != nullptr && (!strcmp(allconst_attr, "1") || !strcmp(allconst_attr, "'1'")))
+                       any_all_nets.insert(net);
+               }
+               else if (allconst_attr != nullptr && (!strcmp(allconst_attr, "1") || !strcmp(allconst_attr, "'1'"))) {
                        allconst_nets.insert(net);
-
-               else if (allseq_attr != nullptr && (!strcmp(allseq_attr, "1") || !strcmp(allseq_attr, "'1'")))
+                       any_all_nets.insert(net);
+               }
+               else if (allseq_attr != nullptr && (!strcmp(allseq_attr, "1") || !strcmp(allseq_attr, "'1'"))) {
                        allseq_nets.insert(net);
+                       any_all_nets.insert(net);
+               }
 
                if (net_map.count(net)) {
                        if (verific_verbose)
@@ -1064,7 +1073,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
                }
 
                if (inst->Type() == PRIM_BUF) {
-                       module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+                       auto outnet = inst->GetOutput();
+                       if (!anyconst_nets.count(outnet) && !anyseq_nets.count(outnet) && !allconst_nets.count(outnet) && !allseq_nets.count(outnet))
+                               module->addBufGate(inst_name, net_map_at(inst->GetInput()), net_map_at(outnet));
                        continue;
                }
 

diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h
index 2dd688e0d20af582d63774e1e9e565ccc7256c22..714b7c82abf5602b38acd8b11b081a6b315d65d0 100644 (file)
--- a/frontends/verific/verific.h
+++ b/frontends/verific/verific.h
@@ -65,6 +65,7 @@ struct VerificImporter
 
        std::map<Verific::Net*, RTLIL::SigBit> net_map;
        std::map<Verific::Net*, Verific::Net*> sva_posedge_map;
+       pool<Verific::Net*, hash_ptr_ops> any_all_nets;
 
        bool mode_gates, mode_keep, mode_nosva, mode_names, mode_verific;
        bool mode_autocover;
@@ -79,7 +80,7 @@ struct VerificImporter
        RTLIL::SigSpec operatorInput1(Verific::Instance *inst);
        RTLIL::SigSpec operatorInput2(Verific::Instance *inst);
        RTLIL::SigSpec operatorInport(Verific::Instance *inst, const char *portname);
-       RTLIL::SigSpec operatorOutput(Verific::Instance *inst);
+       RTLIL::SigSpec operatorOutput(Verific::Instance *inst, const pool<Verific::Net*, hash_ptr_ops> *any_all_nets = nullptr);
 
        bool import_netlist_instance_gates(Verific::Instance *inst, RTLIL::IdString inst_name);
        bool import_netlist_instance_cells(Verific::Instance *inst, RTLIL::IdString inst_name);