Rename according to vendor doc TN1295

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 5f6a20dfcc71da624639aac4f7c0e526c3350f90..d4e2914d92beb86781e5c6447498b25595b905c2 100644 (file)
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -37,10 +37,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
        log("ffA:   %s\n", log_id(st.ffA, "--"));
        log("ffB:   %s\n", log_id(st.ffB, "--"));
        log("mul:   %s\n", log_id(st.mul, "--"));
-       log("ffY:   %s\n", log_id(st.ffY, "--"));
+       log("ffH:   %s\n", log_id(st.ffH, "--"));
        log("addAB: %s\n", log_id(st.addAB, "--"));
        log("muxAB: %s\n", log_id(st.muxAB, "--"));
-       log("ffS:   %s\n", log_id(st.ffS, "--"));
+       log("ffO:   %s\n", log_id(st.ffO, "--"));
 #endif
 
        log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
@@ -55,13 +55,13 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
                return;
        }
 
-       if (GetSize(st.sigS) > 32) {
-               log("  accumulator (%s) is too large (%d > 32).\n", log_signal(st.sigS), GetSize(st.sigS));
+       if (GetSize(st.sigO) > 32) {
+               log("  accumulator (%s) is too large (%d > 32).\n", log_signal(st.sigO), GetSize(st.sigO));
                return;
        }
 
-       if (GetSize(st.sigY) > 32) {
-               log("  output (%s) is too large (%d > 32).\n", log_signal(st.sigY), GetSize(st.sigY));
+       if (GetSize(st.sigH) > 32) {
+               log("  output (%s) is too large (%d > 32).\n", log_signal(st.sigH), GetSize(st.sigH));
                return;
        }
 
@@ -96,7 +96,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
                else if (st.addB)
                        CD = st.addAB->getPort("\\A");
                else log_abort();
-               CD_signed = st.sigS_signed;
+               CD_signed = st.sigO_signed;
        }
        CD.extend_u0(32, CD_signed);
 
@@ -130,11 +130,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
                if (st.ffB)
                        log(" ffB:%s", log_id(st.ffB));
 
-               if (st.ffY)
-                       log(" ffY:%s", log_id(st.ffY));
+               if (st.ffH)
+                       log(" ffH:%s", log_id(st.ffH));
 
-               if (st.ffS)
-                       log(" ffS:%s", log_id(st.ffS));
+               if (st.ffO)
+                       log(" ffO:%s", log_id(st.ffO));
 
                log("\n");
        }
@@ -158,20 +158,20 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
        // SB_MAC16 Output Interface
 
-       SigSpec O = st.ffS ? st.sigS : (st.addAB ? st.addAB->getPort("\\Y") : st.sigY);
+       SigSpec O = st.ffO ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH);
        if (GetSize(O) < 32)
                O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
 
        cell->setPort("\\O", O);
 
-       // MAC only if ffS exists and adder's other input (sigS)
-       //   is output of ffS
+       // MAC only if ffO exists and adder's other input (sigO)
+       //   is output of ffO
        bool accum = false;
        if (st.addAB) {
                 if (st.addA)
-                      accum = (st.ffS && st.addAB->getPort("\\B") == st.ffS->getPort("\\Q"));
+                      accum = (st.ffO && st.addAB->getPort("\\B") == st.ffO->getPort("\\Q"));
                 else if (st.addB)
-                      accum = (st.ffS && st.addAB->getPort("\\A") == st.ffS->getPort("\\Q"));
+                      accum = (st.ffO && st.addAB->getPort("\\A") == st.ffO->getPort("\\Q"));
                 else log_abort();
                 if (accum)
                         log("  accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
@@ -204,17 +204,17 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
        cell->setParam("\\C_REG", State::S0);
        cell->setParam("\\D_REG", State::S0);
 
-       cell->setParam("\\TOP_8x8_MULT_REG", st.ffY ? State::S1 : State::S0);
-       cell->setParam("\\BOT_8x8_MULT_REG", st.ffY ? State::S1 : State::S0);
-       cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffY ? State::S1 : State::S0);
+       cell->setParam("\\TOP_8x8_MULT_REG", st.ffH ? State::S1 : State::S0);
+       cell->setParam("\\BOT_8x8_MULT_REG", st.ffH ? State::S1 : State::S0);
+       cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffH ? State::S1 : State::S0);
        cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
 
-       cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2));
+       cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffO ? 1 : (st.addAB ? 0 : 3), 2));
        cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
        cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
        cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
 
-       cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2));
+       cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffO ? 1 : (st.addAB ? 0 : 3), 2));
        cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
        cell->setParam("\\BOTADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
        cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
@@ -224,10 +224,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
        cell->setParam("\\B_SIGNED", b_signed);
 
        pm.autoremove(st.mul);
-       pm.autoremove(st.ffY);
+       pm.autoremove(st.ffH);
        pm.autoremove(st.addAB);
-        if (st.ffS)
-                st.ffS->connections_.at("\\Q").replace(st.sigS, pm.module->addWire(NEW_ID, GetSize(st.sigS)));
+        if (st.ffO)
+                st.ffO->connections_.at("\\Q").replace(st.sigO, pm.module->addWire(NEW_ID, GetSize(st.sigO)));
 }
 
 struct Ice40DspPass : public Pass {

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 223f9b2e43efbb9debf3bbab92bcbf69f221349e..a74bd79028eee9b6d1c9c3e230843708f5d8e13e 100644 (file)
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -1,8 +1,8 @@
 pattern ice40_dsp
 
 state <SigBit> clock
-state <bool> clock_pol sigS_signed
-state <SigSpec> sigA sigB sigY sigS
+state <bool> clock_pol sigO_signed
+state <SigSpec> sigA sigB sigH sigO
 state <Cell*> addAB muxAB
 
 match mul
@@ -53,21 +53,21 @@ code sigB clock clock_pol
        }
 endcode
 
-match ffY
-       select ffY->type.in($dff)
-       select nusers(port(ffY, \D)) == 2
-       index <SigSpec> port(ffY, \D) === port(mul, \Y)
+match ffH
+       select ffH->type.in($dff)
+       select nusers(port(ffH, \D)) == 2
+       index <SigSpec> port(ffH, \D) === port(mul, \Y)
        optional
 endmatch
 
-code sigY clock clock_pol
-       sigY = port(mul, \Y);
+code sigH clock clock_pol
+       sigH = port(mul, \Y);
 
-       if (ffY) {
-               sigY = port(ffY, \Q);
+       if (ffH) {
+               sigH = port(ffH, \Q);
 
-               SigBit c = port(ffY, \CLK).as_bit();
-               bool cp = param(ffY, \CLK_POLARITY).as_bool();
+               SigBit c = port(ffH, \CLK).as_bit();
+               bool cp = param(ffH, \CLK_POLARITY).as_bool();
 
                if (clock != SigBit() && (c != clock || cp != clock_pol))
                        reject;
@@ -80,7 +80,7 @@ endcode
 match addA
        select addA->type.in($add)
        select nusers(port(addA, \A)) == 2
-       index <SigSpec> port(addA, \A) === sigY
+       index <SigSpec> port(addA, \A) === sigH
        optional
 endmatch
 
@@ -88,25 +88,25 @@ match addB
        if !addA
        select addB->type.in($add, $sub)
        select nusers(port(addB, \B)) == 2
-       index <SigSpec> port(addB, \B) === sigY
+       index <SigSpec> port(addB, \B) === sigH
        optional
 endmatch
 
-code addAB sigS sigS_signed
+code addAB sigO sigO_signed
        if (addA) {
                addAB = addA;
-               sigS = port(addAB, \B);
-               sigS_signed = param(addAB, \B_SIGNED).as_bool();
+               sigO = port(addAB, \B);
+               sigO_signed = param(addAB, \B_SIGNED).as_bool();
        }
        if (addB) {
                addAB = addB;
-               sigS = port(addAB, \A);
-               sigS_signed = param(addAB, \A_SIGNED).as_bool();
+               sigO = port(addAB, \A);
+               sigO_signed = param(addAB, \A_SIGNED).as_bool();
        }
        if (addAB) {
                int natural_mul_width = GetSize(sigA) + GetSize(sigB);
-               int actual_mul_width = GetSize(sigY);
-               int actual_acc_width = GetSize(sigS);
+               int actual_mul_width = GetSize(sigH);
+               int actual_acc_width = GetSize(sigO);
 
                if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
                        reject;
@@ -140,22 +140,22 @@ code muxAB
                muxAB = muxB;
 endcode
 
-match ffS
+match ffO
        if muxAB
-       select ffS->type.in($dff)
+       select ffO->type.in($dff)
        filter nusers(port(muxAB, \Y)) == 2
-       filter includes(port(ffS, \D).to_sigbit_set(), port(muxAB, \Y).to_sigbit_set())
+       filter includes(port(ffO, \D).to_sigbit_set(), port(muxAB, \Y).to_sigbit_set())
        optional
 endmatch
 
-code clock clock_pol sigS
-       if (ffS) {
-               SigBit c = port(ffS, \CLK).as_bit();
-               bool cp = param(ffS, \CLK_POLARITY).as_bool();
+code clock clock_pol sigO
+       if (ffO) {
+               SigBit c = port(ffO, \CLK).as_bit();
+               bool cp = param(ffO, \CLK_POLARITY).as_bool();
 
-               if (port(ffS, \Q) != sigS) {
-                       sigS = port(muxAB, \Y);
-                       sigS.replace(port(ffS, \D), port(ffS, \Q));
+               if (port(ffO, \Q) != sigO) {
+                       sigO = port(muxAB, \Y);
+                       sigO.replace(port(ffO, \D), port(ffO, \Q));
                }
 
                if (clock != SigBit() && (c != clock || cp != clock_pol))

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index ce88a0542e6afdd0d959fd2b70677fb107489fb5..50e071a1a46446d0d4109bca69b875e6a6572222 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -271,6 +271,7 @@ struct SynthIce40Pass : public ScriptPass
                                run("wreduce", "                      (if -dsp)");
                                run("ice40_dsp", "                    (if -dsp)");
                                run("chtype -set $mul t:$__soft_mul","(if -dsp)");
+                               run("dump A:top");
                        }
                        run("alumacc");
                        run("opt");