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authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 10 Jan 2024 15:48:38 +0000 (15:48 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 10 Jan 2024 15:48:38 +0000 (15:48 +0000)
src/openpower/decoder/isa/caller.py patch | blob | history

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index b07f785a4d183d4f03369bdcf3c5a8a8bc6d357b..0488f416f5a5f45e315c027c1e89fc69fa7a903f 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -2218,8 +2218,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
         asmop = yield from self.get_assembly_name()
-        log("call", ins_name, asmop,
-            kind=LogType.InstrInOuts)
+        log("call", ins_name, asmop, kind=LogType.InstrInOuts)
 
         # sv.setvl is *not* a loop-function. sigh
         log("is_svp64_mode", self.is_svp64_mode, asmop)