arch-arm: Fix MCR/MRC disassemble

This patch is fixing the Aarch32 MCR/MRC disassemble, which was
previously printing unexisting integer registers as source/destination
operands rather than the coprocessor register name

Change-Id: I1937938c43680200cf6c5c9558e835ce2b209adc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5862
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 059f86f63a5a92bb89ffe7aea40abb826821f668..ec1b9358c3cbb554dcb5ec6a4211ed7ef6e2931f 100644 (file)
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -259,10 +259,9 @@ MiscRegRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printIntReg(ss, dest);
+    printMiscReg(ss, dest);
     ss << ", ";
     printIntReg(ss, op1);
-    ccprintf(ss, ", #%d", imm);
     return ss.str();
 }
 
@@ -273,8 +272,7 @@ RegMiscRegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     printMnemonic(ss);
     printIntReg(ss, dest);
     ss << ", ";
-    printIntReg(ss, op1);
-    ccprintf(ss, ", #%d", imm);
+    printMiscReg(ss, op1);
     return ss.str();
 }