(no commit message)

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 5e55c83419fda971820938e91ce33eaefb5bd9a2..4c1aa1159c5be852a3477655404e74ed7f0734dd 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -95,12 +95,39 @@ Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise
 
 Additional pseudo-op for obtaining VL without modifying it:
 
-    getvl r5       : setvl r5, r0, vs=0, ms=0
+    getvl r5       : setvl r5, r0, vf=0, vs=0, ms=0
+
+For Vertical-First mode, a pseudo-op for explicit incrementing
+of srcstep and dststep:
+
+    svstep.        : setvl. 0, 0, vf=1, vs=0, ms=0
 
 Note that whilst it is possible to set both MVL and VL from the same
 immediate, it is not possible to set them to different immediates in
 the same instruction.  That would require two instructions.
 
+# Vertical First Mode
+
+Vertical First is effectively like an implicit single bit predicate
+applied to every SVP64 instruction.  **ONLY** one element in each
+SVP64 Vector instruction is executed; srcstep and dststep do **not**
+increment, and the Program Counter progresses **immediately* to
+the next instruction just as it would for any standard scalar v3.0B
+instruction.
+
+An explicit instruction is called which can move srcstep and
+dststep on to the next element, still respecting predicate
+masks.
+
+In other words, where normal SVP64 Vectorisation acts "horizontally"
+by looping first through 0 to VL-1 and only then moving the PC
+to the next instruction, Vertical-First moves the PC onwards
+(vertically) through multiple instructions **with the same
+srcstep and dststep**, then an explict instruction used to
+advance srcstep/dststep, and an outer loop is expected to be
+used (branch instruction) which completes a series of
+Vector operations.
+
 # Pseudocode
 
     // instruction fields: