Add testcase for generation of 32/64_PCREL.
authorcailulu <cailulu@loongson.cn>
Fri, 1 Sep 2023 03:09:01 +0000 (11:09 +0800)
committerliuzhensong <liuzhensong@loongson.cn>
Thu, 7 Sep 2023 11:45:52 +0000 (19:45 +0800)
gas/testsuite/gas/loongarch/pcrel_norelax.d [new file with mode: 0644]
gas/testsuite/gas/loongarch/pcrel_norelax.s [new file with mode: 0644]
gas/testsuite/gas/loongarch/pcrel_relax.d [new file with mode: 0644]
gas/testsuite/gas/loongarch/pcrel_relax.s [new file with mode: 0644]

diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.d b/gas/testsuite/gas/loongarch/pcrel_norelax.d
new file mode 100644 (file)
index 0000000..842c8d4
--- /dev/null
@@ -0,0 +1,56 @@
+#as: -mno-relax
+#objdump: -Dr
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+00000000.* <.L1>:
+[      ]+...
+[      ]+0:[   ]+R_LARCH_32_PCREL[     ]+.L3
+[      ]+4:[   ]+R_LARCH_32_PCREL[     ]+.L3\+0x4
+
+0*00000008[ ]+<.L2>:
+[      ]+...
+[      ]+8:[   ]+R_LARCH_64_PCREL[     ]+.L3
+[      ]+10:[  ]+R_LARCH_64_PCREL[     ]+.L3\+0x8
+
+Disassembly[   ]+of[   ]+section[      ]+sx:
+
+0*00000000[ ]+<.L3>:
+[      ]+0:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
+[      ]+4:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
+[      ]+8:[   ]+ffffffff[     ]+.word[        ]+0xffffffff
+
+0*0000000c[ ]+<.L4>:
+[      ]+...
+[      ]+c:[   ]+R_LARCH_ADD32[        ]+.L4
+[      ]+c:[   ]+R_LARCH_SUB32[        ]+.L5
+[      ]+10:[  ]+R_LARCH_ADD64[        ]+.L4
+[      ]+10:[  ]+R_LARCH_SUB64[        ]+.L5
+
+Disassembly[   ]+of[   ]+section[      ]+sy:
+
+0*00000000[ ]+<.L5>:
+[      ]+...
+[      ]+0:[   ]+R_LARCH_32_PCREL[     ]+.L1
+[      ]+4:[   ]+R_LARCH_32_PCREL[     ]+.L2\+0x4
+[      ]+8:[   ]+R_LARCH_64_PCREL[     ]+.L1\+0x8
+[      ]+10:[  ]+R_LARCH_64_PCREL[     ]+.L2\+0x10
+
+Disassembly[   ]+of[   ]+section[      ]+sz:
+
+0*00000000[ ]+<sz>:
+[      ]+0:[   ]+fffffff8[     ]+.word[        ]+0xfffffff8
+[      ]+4:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
+[      ]+8:[   ]+00000000[     ]+.word[        ]+0x00000000
+[      ]+8:[   ]+R_LARCH_ADD32[        ]+.L2
+[      ]+8:[   ]+R_LARCH_SUB32[        ]+.L3
+[      ]+c:[   ]+fffffff8[     ]+.word[        ]+0xfffffff8
+[      ]+10:[  ]+ffffffff[     ]+.word[        ]+0xffffffff
+[      ]+14:[  ]+fffffff4[     ]+.word[        ]+0xfffffff4
+[      ]+18:[  ]+ffffffff[     ]+.word[        ]+0xffffffff
+[      ]+...
+[      ]+1c:[  ]+R_LARCH_ADD64[        ]+.L2
+[      ]+1c:[  ]+R_LARCH_SUB64[        ]+.L3
diff --git a/gas/testsuite/gas/loongarch/pcrel_norelax.s b/gas/testsuite/gas/loongarch/pcrel_norelax.s
new file mode 100644 (file)
index 0000000..09527f1
--- /dev/null
@@ -0,0 +1,42 @@
+  .section .text
+.L1:
+  # 32_pcrel
+  .4byte .L3-.L1
+  .4byte .L3-.L1
+.L2:
+  # 64_pcrel
+  .8byte .L3-.L2
+  .8byte .L3-.L2
+
+  .section sx
+.L3:
+  # no relocation
+  .4byte .L3-.L4
+  .8byte .L3-.L4
+.L4:
+  # add32+sub32
+  .4byte .L4-.L5
+  # add64+sub64
+  .8byte .L4-.L5
+
+  .section sy
+.L5:
+  # 32_pcrel
+  .4byte .L1-.L5
+  .4byte .L2-.L5
+  # 64_pcrel
+  .8byte .L1-.L5
+  .8byte .L2-.L5
+
+  .section sz
+  # no relocation
+  .4byte .L1-.L2
+  .4byte .L3-.L4
+  # add32+sub32
+  .4byte .L2-.L3
+
+  # no relocation
+  .8byte .L1-.L2
+  .8byte .L3-.L4
+  # add64+sub64
+  .8byte .L2-.L3
diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.d b/gas/testsuite/gas/loongarch/pcrel_relax.d
new file mode 100644 (file)
index 0000000..d6f8752
--- /dev/null
@@ -0,0 +1,60 @@
+#as:
+#objdump: -Dr
+
+.*:[    ]+file format .*
+
+
+Disassembly of section .text:
+
+00000000.* <.L1>:
+[      ]+...
+[      ]+0:[   ]+R_LARCH_32_PCREL[     ]+.L3
+[      ]+4:[   ]+R_LARCH_ADD32[        ]+.L3
+[      ]+4:[   ]+R_LARCH_SUB32[        ]+.L1
+
+0*00000008[ ]+<.L2>:
+[      ]+...
+[      ]+8:[   ]+R_LARCH_64_PCREL[     ]+.L3
+[      ]+10:[  ]+R_LARCH_ADD64[        ]+.L3
+[      ]+10:[  ]+R_LARCH_SUB64[        ]+.L2
+
+Disassembly[   ]+of[   ]+section[      ]+sx:
+
+0*00000000[ ]+<.L3>:
+[      ]+0:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
+[      ]+4:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
+[      ]+8:[   ]+ffffffff[     ]+.word[        ]+0xffffffff
+
+0*0000000c[ ]+<.L4>:
+[      ]+...
+[      ]+c:[   ]+R_LARCH_ADD32[        ]+.L4
+[      ]+c:[   ]+R_LARCH_SUB32[        ]+.L5
+[      ]+10:[  ]+R_LARCH_ADD64[        ]+.L4
+[      ]+10:[  ]+R_LARCH_SUB64[        ]+.L5
+
+Disassembly[   ]+of[   ]+section[      ]+sy:
+
+0*00000000[ ]+<.L5>:
+[      ]+...
+[      ]+0:[   ]+R_LARCH_32_PCREL[     ]+.L1
+[      ]+4:[   ]+R_LARCH_32_PCREL[     ]+.L3\+0x4
+[      ]+8:[   ]+R_LARCH_64_PCREL[     ]+.L1\+0x8
+[      ]+10:[  ]+R_LARCH_64_PCREL[     ]+.L3\+0x10
+
+Disassembly[   ]+of[   ]+section[      ]+sz:
+
+0*00000000[ ]+<sz>:
+[      ]+0:[   ]+00000000[     ]+.word[        ]+0x00000000
+[      ]+0:[   ]+R_LARCH_ADD32[        ]+.L1
+[      ]+0:[   ]+R_LARCH_SUB32[        ]+.L2
+[      ]+4:[   ]+fffffff4[     ]+.word[        ]+0xfffffff4
+[      ]+...
+[      ]+8:[   ]+R_LARCH_ADD32[        ]+.L3
+[      ]+8:[   ]+R_LARCH_SUB32[        ]+.L5
+[      ]+c:[   ]+R_LARCH_ADD64[        ]+.L1
+[      ]+c:[   ]+R_LARCH_SUB64[        ]+.L2
+[      ]+14:[  ]+fffffff4[     ]+.word[        ]+0xfffffff4
+[      ]+18:[  ]+ffffffff[     ]+.word[        ]+0xffffffff
+[      ]+...
+[      ]+1c:[  ]+R_LARCH_ADD64[        ]+.L3
+[      ]+1c:[  ]+R_LARCH_SUB64[        ]+.L5
diff --git a/gas/testsuite/gas/loongarch/pcrel_relax.s b/gas/testsuite/gas/loongarch/pcrel_relax.s
new file mode 100644 (file)
index 0000000..ded275f
--- /dev/null
@@ -0,0 +1,46 @@
+  .section .text
+.L1:
+  # 32_pcrel
+  .4byte .L3-.L1
+  # add32+sub32
+  .4byte .L3-.L1
+.L2:
+  # 64_pcrel
+  .8byte .L3-.L2
+  # add64+sub64
+  .8byte .L3-.L2
+
+  .section sx
+.L3:
+  # no relocation
+  .4byte .L3-.L4
+  .8byte .L3-.L4
+.L4:
+  # add32+sub32
+  .4byte .L4-.L5
+  # add64+sub64
+  .8byte .L4-.L5
+
+  .section sy
+.L5:
+  # 32_pcrel
+  .4byte .L1-.L5
+  .4byte .L3-.L5
+  # 64_pcrel
+  .8byte .L1-.L5
+  .8byte .L3-.L5
+
+  .section sz
+  # add32+sub32
+  .4byte .L1-.L2
+  # no relocation
+  .4byte .L3-.L4
+  # add32+sub32
+  .4byte .L3-.L5
+
+  #add64+sub64
+  .8byte .L1-.L2
+  # no relocation
+  .8byte .L3-.L4
+  #add64+sub64
+  .8byte .L3-.L5