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diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index ee08e28542b1e734d5c08443a9f61e6d379fd878..985e13d24dcc52b02da9be22a0a37c9160102088 100644 (file)
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -32,6 +32,11 @@ further pressure on Major Opcode space which was never designed with
 Scalable Vectors in mind in the first place.  Contrast with RISC-V which was
 designed over a 7 year period with Cray-style Vectors right from the start.*
 
+Even with this amount of time spent, SVP64 exceeds the capability of RVV.
+RISC-V could have been significanyly enhanced if Simple V had been applied
+to it: this possibility was investigated very early but the decision was
+Made to go with Power ISA instead.
+Therefore it is crucial to note that
 Simple-V is **not RISC-V and is not RISC-V Vectors**.
 [NEC SX Aurora](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf),
 [RVV](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc),