soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is...

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 75163cbcfb3d81cca16e30372b290efa58fe6cf9..324f28743c0e981eb20d88d73d43dbd027b34dfd 100644 (file)
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -122,10 +122,12 @@ class AXI2Wishbone(Module):
         assert axi.data_width    == len(wishbone.dat_r)
         assert axi.address_width == len(wishbone.adr) + 2
 
+        ax_buffer = stream.Buffer(ax_description(axi.address_width, axi.id_width))
         ax_burst = stream.Endpoint(ax_description(axi.address_width, axi.id_width))
         ax_beat = stream.Endpoint(ax_description(axi.address_width, axi.id_width))
-        ax_burst2beat = AXIBurst2Beat(ax_burst, ax_beat)
-        self.submodules += ax_burst2beat
+        self.comb += ax_burst.connect(ax_buffer.sink)
+        ax_burst2beat = AXIBurst2Beat(ax_buffer.source, ax_beat)
+        self.submodules += ax_buffer, ax_burst2beat
 
         _data       = Signal(axi.data_width)
         _addr  = Signal(axi.address_width)