CR0 (if Rc=1)
SO OV OV32 (if OE=1)
FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV
-
-# [DRAFT] Floating Convert To Integer In GPR Single
-
-XO-Form
-
-* fcvttgs RT,FRB,CVM,IT (OE=0 Rc=0)
-* fcvttgs. RT,FRB,CVM,IT (OE=0 Rc=1)
-* fcvttgso RT,FRB,CVM,IT (OE=1 Rc=0)
-* fcvttgso. RT,FRB,CVM,IT (OE=1 Rc=1)
-
-Pseudo-code:
-
-<!-- EXTRA_UNINIT_REGS: RT -->
- # based on xscvdpuxws
- reset_xflags()
- src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB)))
- switch(IT)
- case(0): # Signed 32-bit
- range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000)
- range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF)
- js_mask <- 0x0000_0000_FFFF_FFFF
- case(1): # Unsigned 32-bit
- range_min <- bfp_CONVERT_FROM_UI32(0)
- range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF)
- js_mask <- 0x0000_0000_FFFF_FFFF
- case(2): # Signed 64-bit
- range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000)
- range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF)
- js_mask <- 0xFFFF_FFFF_FFFF_FFFF
- default: # Unsigned 64-bit
- range_min <- bfp_CONVERT_FROM_UI64(0)
- range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF)
- js_mask <- 0xFFFF_FFFF_FFFF_FFFF
- if (CVM[2] = 1) | (FPSCR.RN = 0b01) then
- rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src)
- else if FPSCR.RN = 0b00 then
- rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src)
- else if FPSCR.RN = 0b10 then
- rnd <- bfp_ROUND_TO_INTEGER_CEIL(src)
- else if FPSCR.RN = 0b11 then
- rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src)
- switch(CVM)
- case(0, 1): # OpenPower semantics
- if IsNaN(rnd) then
- result <- si64_CONVERT_FROM_BFP(range_min)
- else if bfp_COMPARE_GT(rnd, range_max) then
- result <- ui64_CONVERT_FROM_BFP(range_max)
- else if bfp_COMPARE_LT(rnd, range_min) then
- result <- si64_CONVERT_FROM_BFP(range_min)
- else if IT[1] = 1 then # Unsigned 32/64-bit
- result <- ui64_CONVERT_FROM_BFP(rnd)
- else # Signed 32/64-bit
- result <- si64_CONVERT_FROM_BFP(rnd)
- case(2, 3): # Java/Saturating semantics
- if IsNaN(rnd) then
- result <- [0] * 64
- else if bfp_COMPARE_GT(rnd, range_max) then
- result <- ui64_CONVERT_FROM_BFP(range_max)
- else if bfp_COMPARE_LT(rnd, range_min) then
- result <- si64_CONVERT_FROM_BFP(range_min)
- else if IT[1] = 1 then # Unsigned 32/64-bit
- result <- ui64_CONVERT_FROM_BFP(rnd)
- else # Signed 32/64-bit
- result <- si64_CONVERT_FROM_BFP(rnd)
- default: # JavaScript semantics
- # CVM = 6, 7 are illegal instructions
- # using a 128-bit intermediate works here because the largest type
- # this instruction can convert from has 53 significand bits, and
- # the largest type this instruction can convert to has 64 bits,
- # and the sum of those is strictly less than the 128 bits of the
- # intermediate result.
- limit <- bfp_CONVERT_FROM_UI128([1] * 128)
- if IsInf(rnd) | IsNaN(rnd) then
- result <- [0] * 64
- else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then
- result <- [0] * 64
- else
- result128 <- si128_CONVERT_FROM_BFP(rnd)
- result <- result128[64:127] & js_mask
- switch(IT)
- case(0): # Signed 32-bit
- result <- EXTS64(result[32:63])
- result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63])
- case(1): # Unsigned 32-bit
- result <- EXTZ64(result[32:63])
- result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63])
- case(2): # Signed 64-bit
- result_bfp <- bfp_CONVERT_FROM_SI64(result)
- default: # Unsigned 64-bit
- result_bfp <- bfp_CONVERT_FROM_UI64(result)
- overflow <- 0 # signals SO only when OE = 1
- if IsNaN(src) | ¬bfp_COMPARE_EQ(rnd, result_bfp) then
- overflow <- 1 # signals SO only when OE = 1
- vxcvi_flag <- 1
- xx_flag <- 0
- inc_flag <- 0
- else
- xx_flag <- ¬bfp_COMPARE_EQ(src, result_bfp)
- inc_flag <- bfp_COMPARE_GT(bfp_ABSOLUTE(result_bfp), bfp_ABSOLUTE(src))
- if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
- if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
- if xx_flag = 1 then SetFX(FPSCR.XX)
- vx_flag <- vxsnan_flag | vxcvi_flag
- vex_flag <- FPSCR.VE & vx_flag
- if vex_flag = 0 then
- RT <- result
- FPSCR.FPRF <- undefined(0b00000)
- FPSCR.FR <- inc_flag
- FPSCR.FI <- xx_flag
- else
- FPSCR.FR <- 0
- FPSCR.FI <- 0
-
-Special Registers Altered:
-
- CR0 (if Rc=1)
- SO OV OV32 (if OE=1)
- FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV
fsqrts,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
fres,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
frsqrtes,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-fcvttgs,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:FRB,0,0,0,FRB,0,RT,0,CR0,0
fcbrts,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
fsinpis,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
fasinpis,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
fatanhs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
fexp2m1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
flog2p1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
-fcvttgso,NORMAL,,2P,EXTRA3,EN,d:RT;d:CR0,s:FRB,0,0,0,FRB,0,RT,0,CR0,0
fcvtfgs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:RB,0,0,0,RB,0,FRT,0,CR1,0
fexpm1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
flogp1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0
# 1111101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagcs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
1101001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmods,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
1111001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fremainders,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-0100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fcvttgs,XO,,1,unofficial until submitted and approved/renumbered by the opf isa wg
-1100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fcvttgso,XO,,1,unofficial until submitted and approved/renumbered by the opf isa wg
1110001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmvtgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
1100001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fcvtfgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
1110001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmvfgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
"dsld", "dsrd", "maddedus",
"sadd", "saddw", "sadduw",
- "fcvttg", "fcvttgo", "fcvttgs", "fcvttgso",
+ "fcvttg", "fcvttgo",
"fmvtg", "fmvtgs",
"fcvtfg", "fcvtfgs",
"fmvfg", "fmvfgs",
"fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg
"fmvis", # FP load immediate
"fishmv", # Float Replace Lower-Half Single, Immediate
- "fcvttg", "fcvttgo", "fcvttgs", "fcvttgso",
+ "fcvttg", "fcvttgo",
"fmvtg", "fmvtgs",
"fcvtfg", "fcvtfgs",
"fmvfg", "fmvfgs",
projects / openpower-isa.git / commitdiff