config: Add a BaseSESystem builder for re-use in regressions

This patch extends the existing system builders to also include a
syscall-emulation builder. This builder is deployed in all
syscall-emulation regressions that do not involve Ruby,
i.e. o3-timing, simple-timing and simple-atomic, as well as the
multi-processor regressions o3-timing-mp, simple-timing-mp and
simple-atomic-mp (the latter are only used by SPARC at this point).

The values chosen for the cache sizes match those that were used in
the existing config scripts (despite being on the large
side). Similarly, a mem_class parameter is added to the builder base
class to enable simple-atomic to use SimpleMemory and o3-timing to use
the default DDR3 configuration.

Due to the different order the ports are connected, the bus stats get
shuffled around for the multi-processor regressions. A separate patch
bumps the port indices. Besides this, all behaviour is exactly the
same.

diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index a4b3969ef05c6a3cb30ac10dc7a135b8d9a7f073..0cafacddaba2ecec0f3e17932b3572e6ffef42d5 100644 (file)
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -34,6 +34,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Andreas Sandberg
+#          Andreas Hansson
 
 from abc import ABCMeta, abstractmethod
 import m5
@@ -56,17 +57,19 @@ class BaseSystem(object):
 
     __metaclass__ = ABCMeta
 
-    def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU,
-                 num_cpus=1, checker=False):
-        """Initialize a simple ARM system.
+    def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
+                 cpu_class=TimingSimpleCPU, num_cpus=1, checker=False):
+        """Initialize a simple base system.
 
         Keyword Arguments:
           mem_mode -- String describing the memory mode (timing or atomic)
+          mem_class -- Memory controller class to use
           cpu_class -- CPU class to use
           num_cpus -- Number of CPUs to instantiate
           checker -- Set to True to add checker CPUs
         """
         self.mem_mode = mem_mode
+        self.mem_class = mem_class
         self.cpu_class = cpu_class
         self.num_cpus = num_cpus
         self.checker = checker
@@ -153,6 +156,50 @@ class BaseSystem(object):
         defined by this class."""
         pass
 
+class BaseSESystem(BaseSystem):
+    """Basic syscall-emulation builder."""
+
+    def __init__(self, **kwargs):
+        BaseSystem.__init__(self, **kwargs)
+
+    def init_system(self, system):
+        BaseSystem.init_system(self, system)
+
+    def create_system(self):
+        system = System(physmem = self.mem_class(),
+                        membus = CoherentBus(),
+                        mem_mode = self.mem_mode)
+        system.system_port = system.membus.slave
+        system.physmem.port = system.membus.master
+        self.init_system(system)
+        return system
+
+    def create_root(self):
+        system = self.create_system()
+        m5.ticks.setGlobalFrequency('1THz')
+        return Root(full_system=False, system=system)
+
+class BaseSESystemUniprocessor(BaseSESystem):
+    """Basic syscall-emulation builder for uniprocessor systems.
+
+    Note: This class is only really needed to provide backwards
+    compatibility in existing test cases.
+    """
+
+    def __init__(self, **kwargs):
+        BaseSESystem.__init__(self, **kwargs)
+
+    def create_caches_private(self, cpu):
+        # The atomic SE configurations do not use caches
+        if self.mem_mode == "timing":
+            # @todo We might want to revisit these rather enthusiastic L1 sizes
+            cpu.addTwoLevelCacheHierarchy(L1Cache(size='128kB'),
+                                          L1Cache(size='256kB'),
+                                          L2Cache(size='2MB'))
+
+    def create_caches_shared(self, system):
+        return None
+
 class BaseFSSystem(BaseSystem):
     """Basic full system builder."""
 

diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index 30e12f7774c6cf9681efedc4f35a431379245308..a5fbd77631f0aa98c8cb8ea15560e2e133de7b92 100644 (file)
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,29 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
-
-cpu = InOrderCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
-                              L1Cache(size = '256kB'),
-                              L2Cache(size = '2MB'))
-
-cpu.clock = '2GHz'
-
-system = System(cpu = cpu,
-                physmem = DDR3_1600_x64(),
-                membus = CoherentBus(),
-                mem_mode = "timing")
-system.clock = '1GHz'
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-# create the interrupt controller
-cpu.createInterruptController()
-cpu.connectAllPorts(system.membus)
+from base_config import *
 
-root = Root(full_system = False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+                                cpu_class=InOrderCPU).create_root()

diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py
index 14948fc87f4347b73524da6e965e462980c5d87d..94131d7456eddcbbc49e271fc95a56a56144e679 100644 (file)
--- a/tests/configs/o3-timing-checker.py
+++ b/tests/configs/o3-timing-checker.py
@@ -1,5 +1,5 @@
-# Copyright (c) 2011 ARM Limited
-# All rights reserved
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
 # not be construed as granting a license to any other intellectual
@@ -33,31 +33,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Geoffrey Blake
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
+from base_config import *
 
-cpu = DerivO3CPU(cpu_id=0)
-cpu.createInterruptController()
-cpu.addCheckerCpu()
-cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
-                              L1Cache(size = '256kB'),
-                              L2Cache(size = '2MB'))
-# @todo Note that the L2 latency here is unmodified and 2 cycles,
-# should set hit latency and response latency to 20 cycles as for
-# other scripts
-cpu.clock = '2GHz'
-
-system = System(cpu = cpu,
-                physmem = DDR3_1600_x64(),
-                membus = CoherentBus(),
-                mem_mode = "timing")
-system.clock = '1GHz'
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-cpu.connectAllPorts(system.membus)
-
-root = Root(full_system = False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+                                cpu_class=DerivO3CPU,
+                                checker=True).create_root()

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 9b4f362e76298db8776853c71cbf1ccee27df440..1ec4182bd684bed8bfbe3281927fd594ffdc985f 100644 (file)
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,52 +36,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Ron Dreslinski
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
+from base_config import *
 
 nb_cores = 4
-cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
-
-# system simulated
-system = System(cpu = cpus,
-                physmem = DDR3_1600_x64(),
-                membus = CoherentBus(),
-                mem_mode = "timing")
-system.clock = '1GHz'
-
-# l2cache & bus
-system.toL2Bus = CoherentBus(clock = '2GHz')
-system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-
-# connect l2c to membus
-system.l2c.mem_side = system.membus.slave
-
-# add L1 caches
-for cpu in cpus:
-    cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
-                                L1Cache(size = '32kB', assoc = 4))
-    # create the interrupt controller
-    cpu.createInterruptController()
-    # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectAllPorts(system.toL2Bus, system.membus)
-    cpu.clock = '2GHz'
-
-# connect memory to membus
-system.physmem.port = system.membus.master
-
-# connect system port to membus
-system.system_port = system.membus.slave
-
-# -----------------------
-# run simulation
-# -----------------------
-
-root = Root( full_system = False, system = system )
-root.system.mem_mode = 'timing'
-#root.trace.flags="Bus Cache"
-#root.trace.flags = "BusAddrRanges"
+root = BaseSESystem(mem_mode='timing', mem_class=DDR3_1600_x64,
+                    cpu_class=DerivO3CPU, num_cpus=nb_cores).create_root()

diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 2be0556a69ef97ccced0a0dbafb2b8f78be4bd35..2f9ea52c2e6af34e7b257c3e4b1695bf9015ab88 100644 (file)
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,31 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
-
-cpu = DerivO3CPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
-                              L1Cache(size = '256kB'),
-                              L2Cache(size = '2MB'))
-# @todo Note that the L2 latency here is unmodified and 2 cycles,
-# should set hit latency and response latency to 20 cycles as for
-# other scripts
-cpu.clock = '2GHz'
-
-system = System(cpu = cpu,
-                physmem = DDR3_1600_x64(),
-                membus = CoherentBus(),
-                mem_mode = "timing")
-system.clock = '1GHz'
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-# create the interrupt controller
-cpu.createInterruptController()
-cpu.connectAllPorts(system.membus)
+from base_config import *
 
-root = Root(full_system = False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+                                cpu_class=DerivO3CPU).create_root()

diff --git a/tests/configs/simple-atomic-dummychecker.py b/tests/configs/simple-atomic-dummychecker.py
index d285014037a4331b680b7cc7f7ce516db57d790f..f3b322f60ce0e8cce9d3950af6585285203c0d87 100644 (file)
--- a/tests/configs/simple-atomic-dummychecker.py
+++ b/tests/configs/simple-atomic-dummychecker.py
@@ -1,5 +1,5 @@
-# Copyright (c) 2011 ARM Limited
-# All rights reserved
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
 # not be construed as granting a license to any other intellectual
@@ -33,20 +33,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Geoffrey Blake
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
+from base_config import *
 
-system = System(cpu = AtomicSimpleCPU(cpu_id=0),
-                physmem = SimpleMemory(),
-                membus = CoherentBus())
-system.clock = '1GHz'
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-system.cpu.addCheckerCpu()
-system.cpu.createInterruptController()
-system.cpu.connectAllPorts(system.membus)
-system.cpu.clock = '2GHz'
-
-root = Root(full_system = False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='atomic',
+                                cpu_class=AtomicSimpleCPU,
+                                checker=True).create_root()

diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index d43371eb557d26f34187c947f3fe4496dd8766f1..308caade06c6eaa4436806116d8e422c59475ae0 100644 (file)
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,48 +36,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Ron Dreslinski
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
+from base_config import *
 
 nb_cores = 4
-cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
-
-# system simulated
-system = System(cpu = cpus,
-                physmem = SimpleMemory(range = AddrRange('1024MB')),
-                membus = CoherentBus())
-system.clock = '1GHz'
-# l2cache & bus
-system.toL2Bus = CoherentBus(clock = '2GHz')
-system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-
-# connect l2c to membus
-system.l2c.mem_side = system.membus.slave
-
-# add L1 caches
-for cpu in cpus:
-    cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
-                                L1Cache(size = '32kB', assoc = 4))
-    # create the interrupt controller
-    cpu.createInterruptController()
-    # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectAllPorts(system.toL2Bus, system.membus)
-    cpu.clock = '2GHz'
-
-# connect memory to membus
-system.physmem.port = system.membus.master
-
-# connect system port to membus
-system.system_port = system.membus.slave
-
-# -----------------------
-# run simulation
-# -----------------------
-
-root = Root( full_system = False, system = system )
-root.system.mem_mode = 'atomic'
+root = BaseSESystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU,
+                    num_cpus=nb_cores).create_root()

diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index b9baba1645a79fd22339286f70357e6a091e0a38..59eb60899aa14fa0b618b209c9dfc332ca9a9b41 100644 (file)
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,20 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
+from base_config import *
 
-system = System(cpu = AtomicSimpleCPU(cpu_id=0),
-                physmem = SimpleMemory(),
-                membus = CoherentBus())
-system.clock = '1GHz'
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-# create the interrupt controller
-system.cpu.createInterruptController()
-system.cpu.connectAllPorts(system.membus)
-system.cpu.clock = '2GHz'
-
-root = Root(full_system = False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='atomic',
+                                cpu_class=AtomicSimpleCPU).create_root()

diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 1acfacbdf9b267c04d56af705887b15416ea629f..d8a904b534ec28aa59d785cb3924544c57257e24 100644 (file)
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,47 +36,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Ron Dreslinski
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
+from base_config import *
 
 nb_cores = 4
-cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
-
-# system simulated
-system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
-system.clock = '1GHz'
-
-# l2cache & bus
-system.toL2Bus = CoherentBus(clock = '2GHz')
-system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.master
-
-# connect l2c to membus
-system.l2c.mem_side = system.membus.slave
-
-# add L1 caches
-for cpu in cpus:
-    cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
-                                L1Cache(size = '32kB', assoc = 4))
-    # create the interrupt controller
-    cpu.createInterruptController()
-    # connect cpu level-1 caches to shared level-2 cache
-    cpu.connectAllPorts(system.toL2Bus, system.membus)
-    cpu.clock = '2GHz'
-
-system.system_port = system.membus.slave
-
-# connect memory to membus
-system.physmem.port = system.membus.master
-
-
-# -----------------------
-# run simulation
-# -----------------------
-
-root = Root( full_system = False, system = system )
-root.system.mem_mode = 'timing'
+root = BaseSESystem(mem_mode='timing', cpu_class=TimingSimpleCPU,
+                    num_cpus=nb_cores).create_root()

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 046ee96ddab26d603c1954fa45cda1880ddb1fe1..4b11a5d3ce8b5b972f64a98016227dbe6e466eb6 100644 (file)
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,27 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.util.addToPath('../configs/common')
-from Caches import *
-
-cpu = TimingSimpleCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
-                              L1Cache(size = '256kB'),
-                              L2Cache(size = '2MB'))
-system = System(cpu = cpu,
-                physmem = SimpleMemory(),
-                membus = CoherentBus(),
-                mem_mode = "timing")
-system.clock = '1GHz'
-system.system_port = system.membus.slave
-system.physmem.port = system.membus.master
-# create the interrupt controller
-cpu.createInterruptController()
-cpu.connectAllPorts(system.membus)
-cpu.clock = '2GHz'
+from base_config import *
 
-root = Root(full_system=False, system = system)
+root = BaseSESystemUniprocessor(mem_mode='timing',
+                                cpu_class=TimingSimpleCPU).create_root()

diff --git a/tests/long/se/10.mcf/test.py b/tests/long/se/10.mcf/test.py
index 9bd18a83fcf9ac734da446e541aa1c550338dfa2..0ea3f370d2c521c553b89b22b085e682e8df5991 100644 (file)
--- a/tests/long/se/10.mcf/test.py
+++ b/tests/long/se/10.mcf/test.py
@@ -30,5 +30,5 @@ m5.util.addToPath('../configs/common')
 from cpu2000 import mcf
 
 workload = mcf(isa, opsys, 'smred')
-root.system.cpu.workload = workload.makeLiveProcess()
+root.system.cpu[0].workload = workload.makeLiveProcess()
 root.system.physmem.range=AddrRange('256MB')

diff --git a/tests/long/se/20.parser/test.py b/tests/long/se/20.parser/test.py
index c96a46e60d5859ba6e14bc4074708e73f83758d2..fa72847c7c755c273b5e822c938e8bee85db7c0e 100644 (file)
--- a/tests/long/se/20.parser/test.py
+++ b/tests/long/se/20.parser/test.py
@@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
 from cpu2000 import parser
 
 workload = parser(isa, opsys, 'mdred')
-root.system.cpu.workload = workload.makeLiveProcess()
+root.system.cpu[0].workload = workload.makeLiveProcess()

diff --git a/tests/long/se/30.eon/test.py b/tests/long/se/30.eon/test.py
index de4d12dd846a9907551c37509fa6595a0c15274f..2ad1ef4297e3431b3c038f15df33a9dea5bd3f2f 100644 (file)
--- a/tests/long/se/30.eon/test.py
+++ b/tests/long/se/30.eon/test.py
@@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
 from cpu2000 import eon_cook
 
 workload = eon_cook(isa, opsys, 'mdred')
-root.system.cpu.workload = workload.makeLiveProcess()
+root.system.cpu[0].workload = workload.makeLiveProcess()

diff --git a/tests/long/se/40.perlbmk/test.py b/tests/long/se/40.perlbmk/test.py
index 8fe5d60473886d70f824c7a270382376c1c20b15..74c876978c4a6a8c2787062ee64b287907eaf3a5 100644 (file)
--- a/tests/long/se/40.perlbmk/test.py
+++ b/tests/long/se/40.perlbmk/test.py
@@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
 from cpu2000 import perlbmk_makerand
 
 workload = perlbmk_makerand(isa, opsys, 'lgred')
-root.system.cpu.workload = workload.makeLiveProcess()
+root.system.cpu[0].workload = workload.makeLiveProcess()

diff --git a/tests/long/se/50.vortex/test.py b/tests/long/se/50.vortex/test.py
index 92422c234e9b5451c0d3b57d7f05168b3175c12c..794a11aa17fbe4aff57faabff5acbf609bd4fb8d 100644 (file)
--- a/tests/long/se/50.vortex/test.py
+++ b/tests/long/se/50.vortex/test.py
@@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
 from cpu2000 import vortex
 
 workload = vortex(isa, opsys, 'smred')
-root.system.cpu.workload = workload.makeLiveProcess()
+root.system.cpu[0].workload = workload.makeLiveProcess()

diff --git a/tests/long/se/60.bzip2/test.py b/tests/long/se/60.bzip2/test.py
index fa74d08602636c87e214bcaa02e95ee61f80979a..c217f159cce50775f41a36cd84a1040cbfcdbbda 100644 (file)
--- a/tests/long/se/60.bzip2/test.py
+++ b/tests/long/se/60.bzip2/test.py
@@ -30,4 +30,4 @@ m5.util.addToPath('../configs/common')
 from cpu2000 import bzip2_source
 
 workload = bzip2_source(isa, opsys, 'lgred')
-root.system.cpu.workload = workload.makeLiveProcess()
+root.system.cpu[0].workload = workload.makeLiveProcess()

diff --git a/tests/long/se/70.twolf/test.py b/tests/long/se/70.twolf/test.py
index 761ec8b2e616616e0f117e8ff4098f58a36bd52e..5b99b86fa0244946db22e871f50c24f0685425dd 100644 (file)
--- a/tests/long/se/70.twolf/test.py
+++ b/tests/long/se/70.twolf/test.py
@@ -31,8 +31,8 @@ from cpu2000 import twolf
 import os
 
 workload = twolf(isa, opsys, 'smred')
-root.system.cpu.workload = workload.makeLiveProcess()
-cwd = root.system.cpu.workload[0].cwd
+root.system.cpu[0].workload = workload.makeLiveProcess()
+cwd = root.system.cpu[0].workload[0].cwd
 
 #Remove two files who's presence or absence affects execution
 sav_file = os.path.join(cwd, workload.input_set + '.sav')

diff --git a/tests/quick/se/00.hello/test.py b/tests/quick/se/00.hello/test.py
index 000181850d66de199180647884c02e9a5d8d55b4..c37f8415c76a479457e2cd34dcec6e518380bd12 100644 (file)
--- a/tests/quick/se/00.hello/test.py
+++ b/tests/quick/se/00.hello/test.py
@@ -26,7 +26,7 @@
 #
 # Authors: Steve Reinhardt
 
-root.system.cpu.workload = LiveProcess(cmd = 'hello',
-                                       executable = binpath('hello'))
-if root.system.cpu.checker != NULL:
-    root.system.cpu.checker.workload = root.system.cpu.workload
+root.system.cpu[0].workload = LiveProcess(cmd = 'hello',
+                                          executable = binpath('hello'))
+if root.system.cpu[0].checker != NULL:
+    root.system.cpu[0].checker.workload = root.system.cpu[0].workload

diff --git a/tests/quick/se/01.hello-2T-smt/test.py b/tests/quick/se/01.hello-2T-smt/test.py
index 2db81da939882f266a78cf76451c59410b37f131..885de10f3a2e30130d8c39f0de3d44d516c5eee8 100644 (file)
--- a/tests/quick/se/01.hello-2T-smt/test.py
+++ b/tests/quick/se/01.hello-2T-smt/test.py
@@ -29,5 +29,5 @@
 process1 = LiveProcess(cmd = 'hello', executable = binpath('hello'))
 process2 = LiveProcess(cmd = 'hello', executable = binpath('hello'))
 
-root.system.cpu.workload = [process1, process2]
-root.system.cpu.numThreads = 2
+root.system.cpu[0].workload = [process1, process2]
+root.system.cpu[0].numThreads = 2

diff --git a/tests/quick/se/02.insttest/test.py b/tests/quick/se/02.insttest/test.py
index 93664fbef798d8a99eb558615b33dd3b0f42b578..23e028d250c3fe2ef916863fa4295e70434ab83f 100644 (file)
--- a/tests/quick/se/02.insttest/test.py
+++ b/tests/quick/se/02.insttest/test.py
@@ -26,5 +26,5 @@
 #
 # Authors: Ali Saidi
 
-root.system.cpu.workload = LiveProcess(cmd = 'insttest',
-                                       executable = binpath('insttest'))
+root.system.cpu[0].workload = LiveProcess(cmd = 'insttest',
+                                          executable = binpath('insttest'))

diff --git a/tests/quick/se/20.eio-short/test.py b/tests/quick/se/20.eio-short/test.py
index 67d8a582c4de41fa908142fb24e25ba2ca26d282..36a86889dda20c8c9045b6b8f97e33588473fd97 100644 (file)
--- a/tests/quick/se/20.eio-short/test.py
+++ b/tests/quick/se/20.eio-short/test.py
@@ -28,6 +28,6 @@
 
 require_sim_object("EioProcess")
 
-root.system.cpu.workload = EioProcess(file = binpath('anagram',
+root.system.cpu[0].workload = EioProcess(file = binpath('anagram',
                                                      'anagram-vshort.eio.gz'))
-root.system.cpu.max_insts_any_thread = 500000
+root.system.cpu[0].max_insts_any_thread = 500000