for (size_t i = 0; i < children.size(); i++) {
AstNode *child = children[i];
- if (child->type != AST_FUNCTION && child->type != AST_TASK)
+ if (child->type != AST_FUNCTION && child->type != AST_TASK && child->type != AST_PREFIX)
child->expand_genblock(index_var, prefix, name_map);
}
--- /dev/null
+module carryadd(a, b, y);
+
+parameter WIDTH = 8;
+
+input [WIDTH-1:0] a, b;
+output [WIDTH-1:0] y;
+
+genvar i;
+generate
+ for (i = 0; i < WIDTH; i = i+1) begin:STAGE
+ wire IN1 = a[i], IN2 = b[i];
+ wire C, Y;
+ if (i == 0)
+ assign C = IN1 & IN2, Y = IN1 ^ IN2;
+ else
+ assign C = (IN1 & IN2) | ((IN1 | IN2) & STAGE[i-1].C),
+ Y = IN1 ^ IN2 ^ STAGE[i-1].C;
+ assign y[i] = Y;
+ end
+endgenerate
+
+// assert property (y == a + b);
+
+endmodule