mips.h (ISA_HAS_COND_TRAP): Not available on MIPS16.

* config/mips/mips.h (ISA_HAS_COND_TRAP): Not available on MIPS16.
* config/mips/mips.md (trap) [TARGET_MIPS16]: Emit `break 0'.

From-SVN: r50898

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4ff4a5c994fd647b66f837e40b3196e2c4336b76..cf1b7bd0f85e3541dae4197a43cbd8240052e77f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2002-03-16  Alexandre Oliva  <aoliva@redhat.com>
 
+       * config/mips/mips.h (ISA_HAS_COND_TRAP): Not available on MIPS16.
+       * config/mips/mips.md (trap) [TARGET_MIPS16]: Emit `break 0'.
+
        * config/mips/mips.md (addsi3, adddi3): Use scratch register to
        add register to non-constant into sp.
 

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index ded10123c1973b6d02ccae7a995e82085218d10e..644592d55336cba339ef6b23b4da67ddcc5ad521 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -660,7 +660,7 @@ extern void         sbss_section PARAMS ((void));
                                )
 
 /* ISA has conditional trap instructions.  */
-#define ISA_HAS_COND_TRAP      (mips_isa >= 2)
+#define ISA_HAS_COND_TRAP      (mips_isa >= 2 && ! TARGET_MIPS16)
 
 /* ISA has multiply-accumulate instructions, madd and msub.  */
 #define ISA_HAS_MADD_MSUB       (mips_isa == 32                         \

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 91df86cc0528ee109ed2fd2668e350ffd72d64cf..b9490f045e01348f465b764669d501c3c8c34498 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -546,6 +546,8 @@
 {
   if (ISA_HAS_COND_TRAP)
     return \"teq\\t$0,$0\";
+  else if (TARGET_MIPS16)
+    return \"break 0\";
   else
     return \"break\";
 }")