+2018-01-11 Bin Cheng <bin.cheng@arm.com>
+
+ PR tree-optimization/83695
+ * gimple-loop-linterchange.cc
+ (tree_loop_interchange::interchange_loops): Call scev_reset_htab to
+ reset cached scev information after interchange.
+ (pass_linterchange::execute): Remove call to scev_reset_htab.
+
2018-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm_neon.h (vfmlal_lane_low_u32, vfmlal_lane_high_u32,
oloop.m_loop->any_likely_upper_bound = false;
free_numbers_of_iterations_estimates (oloop.m_loop);
+ /* Clear all cached scev information. This is expensive but shouldn't be
+ a problem given we interchange in very limited times. */
+ scev_reset_htab ();
+
/* ??? The association between the loop data structure and the
CFG changed, so what was loop N at the source level is now
loop M. We should think of retaining the association or breaking
loop_nest.release ();
}
- if (changed_p)
- scev_reset_htab ();
-
return changed_p ? (TODO_update_ssa_only_virtuals) : 0;
}
+2018-01-11 Bin Cheng <bin.cheng@arm.com>
+
+ PR tree-optimization/83695
+ * gcc.dg/tree-ssa/pr83695.c: New test.
+
2018-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/arm/simd/fp16fml_lane_high.c: New test.
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+int a[3][3][3], b, d;
+short c;
+unsigned char e;
+
+static void f ()
+{
+ for (c = 0; c < 2; c++)
+ for (e = 0; e < 3; e++)
+ for (b = 0; b < 3; b++)
+ a[b][e][b] = 0;
+ while (1)
+ ;
+}
+
+int main ()
+{
+ if (d)
+ f ();
+ return 0;
+}