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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index fc27c620c452afed46a554c5a217b3225af0d97c..57e79a1d9f063771464d95115bbfccc827e7ad30 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -663,7 +663,6 @@ Condition Register Field (as opposed to the notation `CR[bit]`
 which accesses one bit of the 32 bit Power ISA v3.0B
 Condition Register).
 
-
 `CR{n}` refers to `CR0` when `n=0` and consequently, for CR0-7, is defined, in v3.0B pseudocode, as:
 
      CR{7-n} = CR[32+n*4:35+n*4]
@@ -689,9 +688,9 @@ analysis and research) to be as follows:
     # finally get the bit from the CR.
     CR_bit = (CR_reg & (1<<bit_index)) != 0
 
-When it comes to applying SV, it is the *CR Field* number `CR\_reg`
+When it comes to applying SV, it is the *CR Field* number `CR_reg`
 to which SV EXTRA2/3
-applies, **not** the `CR\_bit` portion (bits 3-4):
+applies, **not** the `CR_bit` portion (bits 3-4):
 
     if extra3_mode:
         spec = EXTRA3