Add caches in, fix cpu.mem param

--HG--
extra : convert_revision : 486283d83786807c72bb4601e4b9613b55d8802c

diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index 9b7ce1429113f9b6bcf9c140edfd9ae10feef206..2bf67f3b11647a535da32e21f6cba153e4bcbf5e 100644 (file)
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -34,5 +34,6 @@ system = System(cpu = AtomicSimpleCPU(),
                 membus = Bus())
 system.physmem.port = system.membus.port
 system.cpu.connectMemPorts(system.membus)
+system.cpu.mem = system.physmem
 
 root = Root(system = system)

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 8be0c0b3bae5e5b231f533ee17bf1ebf8050e132..9a5b20e88e818a87f4ebbfc801b19ab23eef6e4c 100644 (file)
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -37,8 +37,9 @@ class MyCache(BaseCache):
     tgts_per_mshr = 5
 
 cpu = TimingSimpleCPU()
-#cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
-#                              MyCache(size = '2MB'))
+cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+                              MyCache(size = '2MB'))
+cpu.mem = cpu.dcache
 
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),

diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 6bcefd74f6afef689e1859763da7118cf6b7f40b..e3945f7dcd00d7e5297c9cacc5b22b1dc7678fe7 100644 (file)
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -39,5 +39,6 @@ system = FSConfig.makeLinuxAlphaSystem('atomic')
 system.cpu = cpus
 for c in cpus:
     c.connectMemPorts(system.membus)
+    c.mem = system.physmem
 
 root = Root(clock = '2GHz', system = system)

diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index 67499ac45a2d6c48c7224bac5f93c916104d5776..ca1dd5c77c1ee9d4dd87ae95571ece32900bc22a 100644 (file)
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -35,5 +35,6 @@ cpu = AtomicSimpleCPU()
 system = FSConfig.makeLinuxAlphaSystem('atomic')
 system.cpu = cpu
 cpu.connectMemPorts(system.membus)
+cpu.mem = system.physmem
 
 root = Root(clock = '2GHz', system = system)

diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 59a783b3a08c75d88255ba47faa5edca8979c49c..967d6a2d29654570a67111ede948d85386c9961a 100644 (file)
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -39,5 +39,6 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpus
 for c in cpus:
     c.connectMemPorts(system.membus)
+    c.mem = system.physmem
 
 root = Root(clock = '2GHz', system = system)

diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 5dba7508de7551f069ea883e5df8e3dc909c699a..b3fc9d105d7ed46185285e0d2ea9b10435435aac 100644 (file)
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -35,5 +35,6 @@ cpu = TimingSimpleCPU()
 system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpu
 cpu.connectMemPorts(system.membus)
+cpu.mem = system.physmem
 
 root = Root(clock = '2GHz', system = system)