fix build with upstream Migen/MiSoC

diff --git a/make.py b/make.py
index bcd1a17a3aa4b8979d719bec8046198474b13413..8d5a44397d23e5bfe2f05466fe4543393bea4d35 100644 (file)
--- a/make.py
+++ b/make.py
@@ -7,6 +7,7 @@ from migen.util.misc import autotype
 from migen.fhdl import verilog, edif
 from migen.fhdl.structure import _Fragment
 from mibuild import tools
+from mibuild.xilinx_common import *
 
 from misoclib.gensoc import cpuif
 
@@ -136,7 +137,12 @@ BIST: {}
                if not isinstance(soc, _Fragment):
                        soc = soc.get_fragment()
                platform.finalize(soc)
-               src = verilog.convert(soc, ios)
+               so = {
+                       NoRetiming:                                     XilinxNoRetiming,
+                       MultiReg:                                       XilinxMultiReg,
+                       AsyncResetSynchronizer:         XilinxAsyncResetSynchronizer
+               }
+               src = verilog.convert(soc, ios, special_overrides=so)
                tools.write_to_file("build/litesata.v", src)
 
        if actions["build-bitstream"]:

diff --git a/targets/bist.py b/targets/bist.py
index 348498e911d0f15cf5d7a5603bf2b2c3697dc7cc..03cf31eda66af24e257447bf39c54e47fd62bd77 100644 (file)
--- a/targets/bist.py
+++ b/targets/bist.py
@@ -62,6 +62,7 @@ class GenSoC(Module):
        interrupt_map = {}
        cpu_type = None
        def __init__(self, platform, clk_freq):
+               self.clk_freq = clk_freq
                # UART <--> Wishbone bridge
                self.submodules.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600)