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radv/gfx10: fix wrong emission of GE_CNTL
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Fri, 12 Jul 2019 09:12:58 +0000 (11:12 +0200)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Fri, 12 Jul 2019 10:15:08 +0000 (12:15 +0200)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/amd/vulkan/radv_pipeline.c patch | blob | history

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 9b68650fd36bab859edea100ccacb5d69962bf15..7720990ba45cf34711eb88608a5a665802bb2b99 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3461,7 +3461,7 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
                               S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
                                                                !radv_pipeline_has_gs(pipeline)));
 
-       radeon_set_context_reg(ctx_cs, R_03096C_GE_CNTL,
+       radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
                               S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
                               S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
                               S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));