X86: Implement wrbase and wrlimit for loading pseudo descriptors.

--HG--
extra : convert_revision : fe03c4aed95ef12773e80cdb3d9cff68a2b20f02

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 4ac3a9d98556082daeff4e116eaa5c0c0ca09cd7..67e6fa1e984cd0f03559d861fdf424fc785bf43d 100644 (file)
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -936,4 +936,20 @@ let {{
                 ControlDest = newVal;
             }
             '''
+
+    class Wrbase(RegOp):
+        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+            super(Wrbase, self).__init__(dest, \
+                    src1, "NUM_INTREGS", flags, dataSize)
+        code = '''
+            SegBaseDest = psrc1;
+        '''
+
+    class Wrlimit(RegOp):
+        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
+            super(Wrlimit, self).__init__(dest, \
+                    src1, "NUM_INTREGS", flags, dataSize)
+        code = '''
+            SegLimitDest = psrc1;
+        '''
 }};

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 7a2631a9c94379fd322fdb44f20026b15f9f3137..fff60ce607556fdd45b0a94fb957e5c7cea89e97 100644 (file)
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -127,5 +127,8 @@ def operands {{
         'EferOp':        ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 73),
         'CR4Op':         ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 74),
         'CSBase':        ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
+        'SegBaseDest':   ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 75),
+        'SegLimitDest':  ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 76),
+
         'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
 }};