Handle COs driven by 1'bx

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 12b23cfe9141683a59ed0ea518d9d1cd0af00bcf..42f54209bc335398806b71a6218d8f1e6f5327da 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -355,10 +355,16 @@ struct XAigerWriter
                                                }
 
                                                int offset = 0;
-                                               for (const auto &b : rhs.bits()) {
+                                               for (auto b : rhs.bits()) {
                                                        SigBit I = sigmap(b);
-                                                       if (I != b)
-                                                               alias_map[b] = I;
+                                                       if (b == RTLIL::Sx)
+                                                               b = RTLIL::S0;
+                                                       else if (I != b) {
+                                                               if (I == RTLIL::Sx)
+                                                                       alias_map[b] = RTLIL::S0;
+                                                               else
+                                                                       alias_map[b] = I;
+                                                       }
                                                        co_bits.emplace_back(b, cell, port_name, offset++, 0);
                                                        unused_bits.erase(b);
                                                }