SigSpec(std::vector<RTLIL::SigBit> bits);
SigSpec(std::set<RTLIL::SigBit> bits);
- inline std::vector<RTLIL::SigChunk> &chunks_rw() { pack(); return chunks_; }
inline const std::vector<RTLIL::SigChunk> &chunks() const { pack(); return chunks_; }
inline const std::vector<RTLIL::SigBit> &bits() const { inline_unpack(); return bits_; }
static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);
static bool parse_rhs(const RTLIL::SigSpec &lhs, RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
- operator std::vector<RTLIL::SigBit>() const { return to_sigbit_vector(); }
+ operator std::vector<RTLIL::SigChunk>() const { return chunks(); }
+ operator std::vector<RTLIL::SigBit>() const { return bits(); }
void check() const;
};
std::set<std::string> *delete_wires_p;
void operator()(RTLIL::SigSpec &sig) {
- sig.optimize();
- for (auto &c : sig.chunks_rw())
+ std::vector<RTLIL::SigChunk> chunks = sig;
+ for (auto &c : chunks)
if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
c.wire = module->addWire(NEW_ID, c.width);
c.offset = 0;
}
+ sig = chunks;
}
};
#include "kernel/rtlil.h"
#include "kernel/log.h"
-static int next_bit_mode;
-static uint32_t next_bit_state;
-
-static RTLIL::State next_bit()
+struct SetundefWorker
{
- if (next_bit_mode == 0)
- return RTLIL::State::S0;
+ int next_bit_mode;
+ uint32_t next_bit_state;
- if (next_bit_mode == 1)
- return RTLIL::State::S1;
+ RTLIL::State next_bit()
+ {
+ if (next_bit_mode == 0)
+ return RTLIL::State::S0;
- // xorshift32
- next_bit_state ^= next_bit_state << 13;
- next_bit_state ^= next_bit_state >> 17;
- next_bit_state ^= next_bit_state << 5;
- log_assert(next_bit_state != 0);
+ if (next_bit_mode == 1)
+ return RTLIL::State::S1;
- return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1;
-}
+ // xorshift32
+ next_bit_state ^= next_bit_state << 13;
+ next_bit_state ^= next_bit_state >> 17;
+ next_bit_state ^= next_bit_state << 5;
+ log_assert(next_bit_state != 0);
+
+ return ((next_bit_state >> (next_bit_state & 15)) & 16) ? RTLIL::State::S0 : RTLIL::State::S1;
+ }
-struct SetundefWorker
-{
void operator()(RTLIL::SigSpec &sig)
{
- sig.expand();
- for (auto &c : sig.chunks_rw())
- if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1)
- c.data.bits.at(0) = next_bit();
- sig.optimize();
+ for (auto &bit : sig)
+ if (bit.wire == NULL && bit.data > RTLIL::State::S1)
+ bit = next_bit();
}
};
{
bool got_value = false;
bool undriven_mode = false;
+ SetundefWorker worker;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
}
if (args[argidx] == "-zero") {
got_value = true;
- next_bit_mode = 0;
+ worker.next_bit_mode = 0;
continue;
}
if (args[argidx] == "-one") {
got_value = true;
- next_bit_mode = 1;
+ worker.next_bit_mode = 1;
continue;
}
if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) {
got_value = true;
- next_bit_mode = 2;
- next_bit_state = atoi(args[++argidx].c_str()) + 1;
+ worker.next_bit_mode = 2;
+ worker.next_bit_state = atoi(args[++argidx].c_str()) + 1;
for (int i = 0; i < 10; i++)
- next_bit();
+ worker.next_bit();
continue;
}
break;
for (auto &c : sig.chunks()) {
RTLIL::SigSpec bits;
for (int i = 0; i < c.width; i++)
- bits.append(next_bit());
+ bits.append(worker.next_bit());
bits.optimize();
module->connections.push_back(RTLIL::SigSig(c, bits));
}
}
- module->rewrite_sigspecs(SetundefWorker());
+ module->rewrite_sigspecs(worker);
}
}
} SetundefPass;
void operator()(RTLIL::SigSpec &sig)
{
- sig.expand();
- for (auto &c : sig.chunks_rw())
- if (splitmap.count(c.wire) > 0)
- c = splitmap.at(c.wire).at(c.offset);
- sig.optimize();
+ for (auto &bit : sig)
+ if (splitmap.count(bit.wire) > 0)
+ bit = splitmap.at(bit.wire).at(bit.offset);
}
};
for (RTLIL::Cell *cell : submod.cells) {
RTLIL::Cell *new_cell = new RTLIL::Cell(*cell);
for (auto &conn : new_cell->connections)
- for (auto &c : conn.second.chunks_rw())
- if (c.wire != NULL) {
- assert(wire_flags.count(c.wire) > 0);
- c.wire = wire_flags[c.wire].new_wire;
+ for (auto &bit : conn.second)
+ if (bit.wire != NULL) {
+ assert(wire_flags.count(bit.wire) > 0);
+ bit.wire = wire_flags[bit.wire].new_wire;
}
log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
new_mod->cells[new_cell->name] = new_cell;
static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
{
normalize_sig(module, sig);
- sig.expand();
- for (size_t i = 0; i < sig.chunks().size(); i++)
+ for (auto &bit : sig)
{
- RTLIL::SigChunk &chunk = sig.chunks_rw()[i];
-
- if (chunk.wire == NULL)
+ if (bit.wire == NULL)
continue;
for (auto &cell_it : module->cells)
RTLIL::SigSpec q_norm = cell->connections[after ? "\\D" : "\\Q"];
normalize_sig(module, q_norm);
- RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]);
+ RTLIL::SigSpec d = q_norm.extract(bit, &cell->connections[after ? "\\Q" : "\\D"]);
if (d.size() != 1)
continue;
- assert(d.chunks().size() == 1);
- chunk = d.chunks()[0];
+ bit = d;
clk = cell->connections["\\CLK"];
clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
goto replaced_this_bit;
for (auto &action : sync->actions) {
RTLIL::SigSpec rspec = action.second;
RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size());
- rspec.expand(), rval.expand();
- for (int i = 0; i < int(rspec.chunks().size()); i++)
- if (rspec.chunks()[i].wire == NULL)
- rval.chunks_rw()[i] = rspec.chunks()[i];
- rspec.optimize(), rval.optimize();
+ for (int i = 0; i < SIZE(rspec); i++)
+ if (rspec[i].wire == NULL)
+ rval[i] = rspec[i];
RTLIL::SigSpec last_rval;
for (int count = 0; rval != last_rval; count++) {
last_rval = rval;
log_signal(undef2), log_signal(mod1_inputs), log_signal(inputs));
if (ignore_x_mod1) {
- sig1.expand(), sig2.expand();
- for (size_t i = 0; i < sig1.chunks().size(); i++)
- if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx))
- sig2.chunks_rw().at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
- sig1.optimize(), sig2.optimize();
+ for (int i = 0; i < SIZE(sig1); i++)
+ if (sig1[i] == RTLIL::State::Sx)
+ sig2[i] = RTLIL::State::Sx;
}
if (sig1 != sig2) {
sig.expand();
if (rtl_sig.size() != sig.size())
log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
- for (int i = 0; i < sig.size(); i++)
- if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx)
- sig.chunks_rw().at(i).data.bits.at(0) = RTLIL::State::Sx;
+ for (int i = 0; i < SIZE(sig); i++)
+ if (rtl_sig[i] == RTLIL::State::Sx)
+ sig[i] = RTLIL::State::Sx;
}
log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str());
newCell->type = cell->type;
newCell->parameters = cell->parameters;
for (auto &conn : cell->connections) {
- RTLIL::SigSpec sig = sigmap(conn.second);
- for (auto &chunk : sig.chunks_rw())
+ std::vector<RTLIL::SigChunk> chunks = sigmap(conn.second);
+ for (auto &chunk : chunks)
if (chunk.wire != NULL)
chunk.wire = newMod->wires.at(chunk.wire->name);
- newCell->connections[conn.first] = sig;
+ newCell->connections[conn.first] = chunks;
}
newMod->add(newCell);
}
static bool singleton_mode;
static RTLIL::Module *module;
-static RTLIL::SigChunk last_hi, last_lo;
+static RTLIL::SigBit last_hi, last_lo;
void hilomap_worker(RTLIL::SigSpec &sig)
{
- sig.expand();
- for (auto &c : sig.chunks_rw()) {
- if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
- if (!singleton_mode || last_hi.width == 0) {
- last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));
+ for (auto &bit : sig) {
+ if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
+ if (!singleton_mode || last_hi == RTLIL::State::Sm) {
+ last_hi = module->addWire(NEW_ID);
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = RTLIL::escape_id(hicell_celltype);
cell->connections[RTLIL::escape_id(hicell_portname)] = last_hi;
module->add(cell);
}
- c = last_hi;
+ bit = last_hi;
}
- if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S0) && !locell_celltype.empty()) {
- if (!singleton_mode || last_lo.width == 0) {
- last_lo = RTLIL::SigChunk(module->addWire(NEW_ID));
+ if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
+ if (!singleton_mode || last_lo == RTLIL::State::Sm) {
+ last_lo = module->addWire(NEW_ID);
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = RTLIL::escape_id(locell_celltype);
cell->connections[RTLIL::escape_id(locell_portname)] = last_lo;
module->add(cell);
}
- c = last_lo;
+ bit = last_lo;
}
}
- sig.optimize();
}
struct HilomapPass : public Pass {
if (!design->selected(module))
continue;
- last_hi = RTLIL::SigChunk();
- last_lo = RTLIL::SigChunk();
+ last_hi = RTLIL::State::Sm;
+ last_lo = RTLIL::State::Sm;
module->rewrite_sigspecs(hilomap_worker);
}
static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
{
- for (size_t i = 0; i < sig.chunks().size(); i++) {
- if (sig.chunks()[i].wire == NULL)
- continue;
- std::string wire_name = sig.chunks()[i].wire->name;
- apply_prefix(prefix, wire_name);
- assert(module->wires.count(wire_name) > 0);
- sig.chunks_rw()[i].wire = module->wires[wire_name];
- }
+ std::vector<RTLIL::SigChunk> chunks = sig;
+ for (auto &chunk : chunks)
+ if (chunk.wire != NULL) {
+ std::string wire_name = chunk.wire->name;
+ apply_prefix(prefix, wire_name);
+ assert(module->wires.count(wire_name) > 0);
+ chunk.wire = module->wires[wire_name];
+ }
+ sig = chunks;
}
struct TechmapWorker
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