intel/tools: Add unit tests for assembler

v1: Pass executable object from meson to test(Dylan Baker)
v2: Ignore generated output files from git status(Matt Turner)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

diff --git a/.gitignore b/.gitignore
index a8917c269b12dd3c3928980f0cef5915b9728a08..825ad5fd16564c5d8d086c5397f5a20a22382268 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,4 @@
 *.pyc
 *.pyo
+*.out
 build

diff --git a/src/intel/tools/meson.build b/src/intel/tools/meson.build
index 8ed98f891e90803e59c71a11a92ec03398dfe757..4aa09d99ceed33d692a364b2dd6c9d9ee2c610a9 100644 (file)
--- a/src/intel/tools/meson.build
+++ b/src/intel/tools/meson.build
@@ -154,3 +154,21 @@ i965_asm = executable(
    c_args : [c_vis_args, no_override_init_args],
    install : true
 )
+
+asm_testcases = [
+   ['brw', 'tests/gen4'],
+   ['g4x', 'tests/gen4.5'],
+   ['ilk', 'tests/gen5'],
+   ['snb', 'tests/gen6'],
+   ['ivb', 'tests/gen7'],
+   ['hsw', 'tests/gen7.5'],
+   ['bdw', 'tests/gen8'],
+   ['skl', 'tests/gen9'],
+]
+
+test_runner = find_program('tests/run-test.sh')
+foreach testcase : asm_testcases
+   test('i965_asm : ' + testcase[1], test_runner,
+        args : [i965_asm, testcase[1], testcase[0]],
+        env : ['srcdir=' + meson.current_source_dir()])
+endforeach

diff --git a/src/intel/tools/tests/gen4.5/add.asm b/src/intel/tools/tests/gen4.5/add.asm
new file mode 100644 (file)
index 0000000..1646fb1
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/add.asm
@@ -0,0 +1,49 @@
+add(16)         g10<1>UW        g1.4<2,4,0>UW   0x10101010V     { align1 };
+add(8)          g6<1>F          g10<8,8,1>UW    -g1<0,1,0>F     { align1 };
+add(8)          g8<1>F          g10.8<8,8,1>UW  -g1<0,1,0>F     { align1 sechalf };
+add(16)         g4<1>F          g18<8,8,1>F     g6<8,8,1>F      { align1 compr };
+add(1)          m14.4<1>D       g8.4<0,1,0>D    16D             { align1 nomask };
+add(8)          g5<1>.xD        g2<4>.xD        64D             { align16 };
+add(8)          g4<1>.xD        g5<4>.xD        g4<4>.xD        { align16 };
+add(8)          g3<1>F          g3<4>F          g5<4>F          { align16 };
+add(16)         g24<1>F         g20<8,8,1>F     0x3f800000F  /* 1F */ { align1 compr };
+add(16)         g14<1>D         g14<8,8,1>D     1D              { align1 compr };
+add(8)          m5<1>.xyzF      g10<4>.xyzzF    g8<4>.xyzzF     { align16 NoDDClr };
+add.le.f0.0(16) g6<1>F          g8<8,8,1>F      g4<8,8,1>F      { align1 compr };
+add(16)         m3<1>F          g4<8,8,1>F      g12<8,8,1>F     { align1 compr4 };
+add(8)          a0<1>UW         g4<16,8,2>UW    0x0040UW        { align1 };
+add(8)          a0<1>UW         g5<16,8,2>UW    0x0040UW        { align1 sechalf };
+add(8)          g3<1>.xyF       g2<4>.xyyyF     0x3f800000F  /* 1F */ { align16 };
+add(16)         m4<1>F          -g6<8,8,1>F     0x3f800000F  /* 1F */ { align1 compr4 };
+add(16)         m2<1>D          g6<8,8,1>D      g8.3<0,1,0>D    { align1 compr };
+add(16)         m14<1>D         g4<8,8,1>D      12D             { align1 compr };
+add.sat(16)     g6<1>F          g4<8,8,1>F      g2.1<0,1,0>F    { align1 compr };
+add(8)          g37<1>UW        g1.4<2,4,0>UW   0x10101010V     { align1 };
+add(8)          g38<1>D         g2<0,1,0>D      1D              { align1 };
+add(8)          m5<1>.xF        g3<4>.xF        0x3f000000F  /* 0.5F */ { align16 };
+add(16)         g4<1>D          g2<0,1,0>D      -g2.2<0,1,0>D   { align1 compr };
+add.sat(8)      m5<1>F          g7<4>F          g8<4>F          { align16 };
+add(8)          g31<1>.xyzF     g28<4>.xyzzF    0x30300000VF /* [0F, 0F, 1F, 1F]VF */ { align16 };
+add.sat(8)      m5<1>.xyzF      g25<4>.xyzzF    g26<4>.xyzzF    { align16 NoDDClr };
+add.ge.f0.0(8)  g8<1>.xF        -g8<4>.xF       0x3f800000F  /* 1F */ { align16 };
+add(16)         g4.1<2>UW       g4.1<16,8,2>UW  g6<16,8,2>UW    { align1 compr };
+add.ge.f0.0(16) g4<1>F          -g6<8,8,1>F     0x3f800000F  /* 1F */ { align1 compr };
+add(8)          g4<1>.xyF       g4<4>.xyyyF     0xbf800000F  /* -1F */ { align16 NoDDClr };
+add(8)          m5<1>.xyzF      g4<4>.xyzzF     g2<0>.xyzzF     { align16 };
+add.sat(16)     m6<1>F          g2<0,1,0>F      g2.4<0,1,0>F    { align1 compr4 };
+add(8)          m5<1>.zwF       g8<4>.xxxyF     g9<4>.xxxyF     { align16 NoDDChk };
+add(8)          g4<1>.xUD       g4<4>.xUD       0x00000040UD    { align16 };
+add.sat(8)      m5<1>.yF        g1<0>.zF        0x3f000000F  /* 0.5F */ { align16 };
+add(16)         m14<1>UD        g4<8,8,1>UD     0x00000110UD    { align1 compr };
+add(8)          g5<1>F          -g9<4>.xyxyF    g9<4>.zwzwF     { align16 sechalf };
+add.sat(8)      m5<1>.yF        g6<4>.xF        g7<4>.xF        { align16 NoDDClr,NoDDChk };
+add.sat(8)      m5<1>.wF        g6<4>.xF        g7<4>.xF        { align16 NoDDChk };
+add.ge.f0.0(16) g16<1>F         g18<8,8,1>F     g10<8,8,1>F     { align1 compr };
+add.sat(8)      m5<1>.yF        -g1<0>.xF       0x3f000000F  /* 0.5F */ { align16 NoDDClr };
+add.sat(8)      m5<1>.zF        g3<4>.yF        0x40000000F  /* 2F */ { align16 NoDDClr,NoDDChk };
+add.sat(8)      m5<1>.wF        g3<4>.yF        0xc0000000F  /* -2F */ { align16 NoDDChk };
+add(8)          m5<1>F          g3<4>F          0x2020a038VF /* [1.5F, -0.5F, 0.5F, 0.5F]VF */ { align16 };
+add(8)          g5<1>.zF        g4<4>.xF        0xbf800000F  /* -1F */ { align16 NoDDClr,NoDDChk };
+add(8)          m5<1>.xyF       g12<4>.xyyyF    0x3f000000F  /* 0.5F */ { align16 NoDDClr };
+add(8)          m5<1>.wF        -g3<4>.xF       0x3f800000F  /* 1F */ { align16 NoDDClr,NoDDChk };
+add(8)          g5<1>.xyF       g3<0>.xyyyF     g4<4>.xyyyF     { align16 NoDDClr };

diff --git a/src/intel/tools/tests/gen4.5/add.expected b/src/intel/tools/tests/gen4.5/add.expected
new file mode 100644 (file)
index 0000000..29656d9
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/add.expected
@@ -0,0 +1,49 @@
+40 00 80 00 29 6d 40 21 28 00 48 00 10 10 10 10
+40 00 60 00 3d 75 c0 20 40 01 8d 00 20 40 00 00
+40 10 60 00 3d 75 00 21 50 01 8d 00 20 40 00 00
+40 20 80 00 bd 77 80 20 40 02 8d 00 c0 00 8d 00
+40 02 00 00 a6 1c d0 21 10 01 00 00 10 00 00 00
+40 01 60 00 a5 1c a1 20 40 00 60 00 40 00 00 00
+40 01 60 00 a5 14 81 20 a0 00 60 00 80 00 60 00
+40 01 60 00 bd 77 6f 20 64 00 6e 00 a4 00 6e 00
+40 20 80 00 bd 7f 00 23 80 02 8d 00 00 00 80 3f
+40 20 80 00 a5 1c c0 21 c0 01 8d 00 01 00 00 00
+40 05 60 00 be 77 a7 20 44 01 6a 00 04 01 6a 00
+40 20 80 06 bd 77 c0 20 00 01 8d 00 80 00 8d 00
+40 20 80 00 be 77 60 30 80 00 8d 00 80 01 8d 00
+40 00 60 00 28 2d 00 22 80 00 ae 00 40 00 40 00
+40 10 60 00 28 2d 00 22 a0 00 ae 00 40 00 40 00
+40 01 60 00 bd 7f 63 20 44 00 65 00 00 00 80 3f
+40 20 80 00 be 7f 80 30 c0 40 8d 00 00 00 80 3f
+40 20 80 00 a6 14 40 20 c0 00 8d 00 0c 01 00 00
+40 20 80 00 a6 1c c0 21 80 00 8d 00 0c 00 00 00
+40 20 80 80 bd 77 c0 20 80 00 8d 00 44 00 00 00
+40 00 60 00 29 6d a0 24 28 00 48 00 10 10 10 10
+40 00 60 00 a5 1c c0 24 40 00 00 00 01 00 00 00
+40 01 60 00 be 7f a1 20 60 00 60 00 00 00 00 3f
+40 20 80 00 a5 14 80 20 40 00 00 00 48 40 00 00
+40 01 60 80 be 77 af 20 e4 00 6e 00 04 01 6e 00
+40 01 60 00 bd 5f e7 23 84 03 6a 00 00 00 30 30
+40 05 60 80 be 77 a7 20 24 03 6a 00 44 03 6a 00
+40 01 60 04 bd 7f 01 21 00 41 60 00 00 00 80 3f
+40 20 80 00 29 25 82 40 82 00 ae 00 c0 00 ae 00
+40 20 80 04 bd 7f 80 20 c0 40 8d 00 00 00 80 3f
+40 05 60 00 bd 7f 83 20 84 00 65 00 00 00 80 bf
+40 01 60 00 be 77 a7 20 84 00 6a 00 44 00 0a 00
+40 20 80 80 be 77 c0 30 40 00 00 00 50 00 00 00
+40 09 60 00 be 77 ac 20 00 01 64 00 20 01 64 00
+40 01 60 00 21 0c 81 20 80 00 60 00 40 00 00 00
+40 01 60 80 be 7f a2 20 2a 00 0a 00 00 00 00 3f
+40 20 80 00 22 0c c0 21 80 00 8d 00 10 01 00 00
+40 11 60 00 bd 77 af 20 24 41 64 00 2e 01 6e 00
+40 0d 60 80 be 77 a2 20 c0 00 60 00 e0 00 60 00
+40 09 60 80 be 77 a8 20 c0 00 60 00 e0 00 60 00
+40 20 80 04 bd 77 00 22 40 02 8d 00 40 01 8d 00
+40 05 60 80 be 7f a2 20 20 40 00 00 00 00 00 3f
+40 0d 60 80 be 7f a4 20 65 00 65 00 00 00 00 40
+40 09 60 80 be 7f a8 20 65 00 65 00 00 00 00 c0
+40 01 60 00 be 5f af 20 64 00 6e 00 38 a0 20 20
+40 0d 60 00 bd 7f a4 20 80 00 60 00 00 00 80 bf
+40 05 60 00 be 7f a3 20 84 01 65 00 00 00 00 3f
+40 0d 60 00 be 7f a8 20 60 40 60 00 00 00 80 3f
+40 05 60 00 bd 77 a3 20 64 00 05 00 84 00 65 00

diff --git a/src/intel/tools/tests/gen4.5/and.asm b/src/intel/tools/tests/gen4.5/and.asm
new file mode 100644 (file)
index 0000000..1c73127
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/and.asm
@@ -0,0 +1,17 @@
+and(8)          g9<1>.wUD       g9<4>.wUD       524032D         { align16 };
+and(16)         g4<1>D          g6<8,8,1>D      1D              { align1 compr };
+and(8)          g10<1>.xD       g10<4>.xD       1D              { align16 };
+and(16)         g6<1>UD         g10<8,8,1>UD    g8<8,8,1>UD     { align1 compr };
+and.nz.f0.0(16) null<1>D        g6<8,8,1>UD     1D              { align1 compr };
+and(16)         g4<1>D          g8<8,8,1>UD     1D              { align1 compr };
+and(8)          g2<1>D          g2<8,8,1>UD     1D              { align1 };
+and.nz.f0.0(8)  null<1>.xD      g9<4>.xUD       1D              { align16 };
+and(16)         g12<1>UD        g2.4<0,1,0>UD   0x80000000UD    { align1 compr };
+and.nz.f0.0(16) g110<1>D        g6<8,8,1>D      1D              { align1 compr };
+and(1)          g10<1>UD        f0<0,1,0>UW     0x0000000fUD    { align1 nomask };
+and(8)          g17<1>.xUD      g1<0>.xUD       0x80000000UD    { align16 };
+and.nz.f0.0(16) g6<1>D          g4<8,8,1>UD     1D              { align1 compr };
+and(8)          g5<1>.xUD       g1<0>.xUD       g1<0>.yUD       { align16 };
+and(8)          g8<1>.xD        g7<4>.xUD       1D              { align16 };
+and.nz.f0.0(8)  g6<1>.xD        g6<4>.xD        1D              { align16 };
+and.nz.f0.0(1)  null<1>UD       g1.6<0,1,0>UD   0x04000000UD    { align1 };

diff --git a/src/intel/tools/tests/gen4.5/and.expected b/src/intel/tools/tests/gen4.5/and.expected
new file mode 100644 (file)
index 0000000..4124a19
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/and.expected
@@ -0,0 +1,17 @@
+05 01 60 00 21 1c 28 21 2f 01 6f 00 00 ff 07 00
+05 20 80 00 a5 1c 80 20 c0 00 8d 00 01 00 00 00
+05 01 60 00 a5 1c 41 21 40 01 60 00 01 00 00 00
+05 20 80 00 21 04 c0 20 40 01 8d 00 00 01 8d 00
+05 20 80 02 24 1c 00 20 c0 00 8d 00 01 00 00 00
+05 20 80 00 25 1c 80 20 00 01 8d 00 01 00 00 00
+05 00 60 00 25 1c 40 20 40 00 8d 00 01 00 00 00
+05 01 60 02 24 1c 01 20 20 01 60 00 01 00 00 00
+05 20 80 00 21 0c 80 21 50 00 00 00 00 00 00 80
+05 20 80 02 a5 1c c0 2d c0 00 8d 00 01 00 00 00
+05 02 00 00 01 0d 40 21 00 06 00 00 0f 00 00 00
+05 01 60 00 21 0c 21 22 20 00 00 00 00 00 00 80
+05 20 80 02 25 1c c0 20 80 00 8d 00 01 00 00 00
+05 01 60 00 21 04 a1 20 20 00 00 00 25 00 05 00
+05 01 60 00 25 1c 01 21 e0 00 60 00 01 00 00 00
+05 01 60 02 a5 1c c1 20 c0 00 60 00 01 00 00 00
+05 00 00 02 20 0c 00 20 38 00 00 00 00 00 00 04

diff --git a/src/intel/tools/tests/gen4.5/asr.asm b/src/intel/tools/tests/gen4.5/asr.asm
new file mode 100644 (file)
index 0000000..3fdb60d
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/asr.asm
@@ -0,0 +1,5 @@
+asr(16)         g4<1>D          -g1.6<0,1,0>D   31D             { align1 compr };
+asr.nz.f0.0(16) null<1>D        -g1.6<0,1,0>D   31D             { align1 compr };
+asr(8)          g4<1>D          g5<4>D          g4<4>UD         { align16 };
+asr(8)          g11<1>.xD       g5<4>.xD        0x00000002UD    { align16 };
+asr(16)         g10<1>D         g6<8,8,1>D      0x00000002UD    { align1 compr };

diff --git a/src/intel/tools/tests/gen4.5/asr.expected b/src/intel/tools/tests/gen4.5/asr.expected
new file mode 100644 (file)
index 0000000..ed23189
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/asr.expected
@@ -0,0 +1,5 @@
+0c 20 80 00 a5 1c 80 20 38 40 00 00 1f 00 00 00
+0c 20 80 02 a4 1c 00 20 38 40 00 00 1f 00 00 00
+0c 01 60 00 a5 04 8f 20 a4 00 6e 00 84 00 6e 00
+0c 01 60 00 a5 0c 61 21 a0 00 60 00 02 00 00 00
+0c 20 80 00 a5 0c 40 21 c0 00 8d 00 02 00 00 00

diff --git a/src/intel/tools/tests/gen4.5/break.asm b/src/intel/tools/tests/gen4.5/break.asm
new file mode 100644 (file)
index 0000000..7101856
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/break.asm
@@ -0,0 +1,5 @@
+(-f0.0) break(16) Jump: 10      Pop: 0                          { align1 };
+break(16)       Jump: 5         Pop: 1                          { align1 };
+(+f0.0) break(16) Jump: 141     Pop: 0                          { align1 };
+(+f0.0.x) break(8) Jump: 16     Pop: 0                          { align16 };
+break(8)        Jump: 6         Pop: 2                          { align16 };

diff --git a/src/intel/tools/tests/gen4.5/break.expected b/src/intel/tools/tests/gen4.5/break.expected
new file mode 100644 (file)
index 0000000..2ab4122
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/break.expected
@@ -0,0 +1,5 @@
+28 00 91 00 00 1c 00 34 00 14 60 00 0a 00 00 00
+28 00 80 00 00 1c 00 34 00 14 60 00 05 00 01 00
+28 00 81 00 00 1c 00 34 00 14 60 00 8d 00 00 00
+28 01 62 00 00 1c 0f 34 04 14 6e 00 10 00 00 00
+28 01 60 00 00 1c 0f 34 04 14 6e 00 06 00 02 00

diff --git a/src/intel/tools/tests/gen4.5/cmp.asm b/src/intel/tools/tests/gen4.5/cmp.asm
new file mode 100644 (file)
index 0000000..a0e66e1
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/cmp.asm
@@ -0,0 +1,80 @@
+cmp.nz.f0.0(8)  null<1>F        g3<0>.xyzzF     0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16 };
+cmp.nz.f0.0(8)  null<1>D        g7<4>.xyzzD     0D              { align16 };
+cmp.ge.f0.0(16) g6<1>F          g4<8,8,1>F      0x3189705fF  /* 4e-09F */ { align1 compr };
+cmp.l.f0.0(16)  g8<1>F          g4<8,8,1>F      0x3189705fF  /* 4e-09F */ { align1 compr };
+cmp.l.f0.0(16)  g8<1>F          g4<8,8,1>F      g6<8,8,1>F      { align1 compr };
+cmp.ge.f0.0(16) g10<1>F         g4<8,8,1>F      g6<8,8,1>F      { align1 compr };
+cmp.z.f0.0(8)   g10<1>.xD       g4<0>.xD        0D              { align16 };
+cmp.l.f0.0(8)   g7<1>.xF        g7<4>.xF        0x3189705fF  /* 4e-09F */ { align16 };
+cmp.ge.f0.0(8)  g6<1>.xF        g2<0>.xF        g6<4>.xF        { align16 };
+cmp.z.f0.0(8)   null<1>F        g3<0>.zwwwF     g3<0>.xyyyF     { align16 };
+cmp.ge.f0.0(16) null<1>D        g14<8,8,1>D     16D             { align1 compr };
+cmp.l.f0.0(16)  null<1>D        g2<0,1,0>D      1D              { align1 compr };
+cmp.z.f0.0(16)  g8<1>F          g32<8,8,1>F     g2.3<0,1,0>F    { align1 compr };
+cmp.ge.f0.0(16) null<1>F        g6<8,8,1>F      0x0F  /* 0F */  { align1 compr };
+cmp.nz.f0.0(8)  null<1>F        g12<4>.xyyyF    g1<0>.xyyyF     { align16 };
+cmp.z.f0.0(8)   null<1>D        g6<4>D          g2.4<0>D        { align16 };
+cmp.z.f0.0(16)  g6<1>D          g2.1<0,1,0>D    39D             { align1 compr };
+cmp.z.f0.0(16)  g4<1>F          g2.1<0,1,0>F    0x41000000F  /* 8F */ { align1 compr };
+cmp.z.f0.0(8)   g5<1>.xD        g5<4>.xD        g1<0>.zD        { align16 };
+cmp.l.f0.0(8)   g3<1>.xyF       g1<0>.xyyyF     g1<0>.zwwwF     { align16 };
+cmp.z.f0.0(16)  null<1>D        g2<0,1,0>D      1D              { align1 compr };
+cmp.z.f0.0(16)  null<1>F        g14<8,8,1>F     g2.1<0,1,0>F    { align1 compr };
+cmp.z.f0.0(8)   g6<1>.xF        g6<4>.xF        g3<0>.yF        { align16 };
+cmp.nz.f0.0(16) g4<1>F          g6<8,8,1>F      g2.2<0,1,0>F    { align1 compr };
+cmp.ge.f0.0(16) null<1>F        (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
+cmp.nz.f0.0(16) null<1>D        g2<0,1,0>D      0D              { align1 compr };
+cmp.nz.f0.0(8)  g5<1>F          g5<8,8,1>F      g38<8,8,1>F     { align1 };
+cmp.ge.f0.0(8)  null<1>.xD      g5<4>.xD        4D              { align16 };
+cmp.nz.f0.0(16) null<1>F        g2.4<0,1,0>F    0x0F  /* 0F */  { align1 compr };
+cmp.z.f0.0(16)  null<1>F        g4.1<0,1,0>F    0x3f800000F  /* 1F */ { align1 compr };
+cmp.ge.f0.0(16) g4<1>D          g2<0,1,0>D      1D              { align1 compr };
+cmp.nz.f0.0(16) g4<1>D          g2.1<0,1,0>D    0D              { align1 compr };
+cmp.z.f0.0(16)  g8<1>D          g6<8,8,1>D      g2.5<0,1,0>D    { align1 compr };
+cmp.l.f0.0(16)  null<1>F        g4<8,8,1>F      g2.5<0,1,0>F    { align1 compr };
+cmp.l.f0.0(16)  g6<1>D          g3<0,1,0>D      1D              { align1 compr };
+cmp.ge.f0.0(8)  null<1>F        g32<4>.xF       0x0F  /* 0F */  { align16 };
+cmp.l.f0.0(8)   null<1>F        g23<4>.xF       0x43000000F  /* 128F */ { align16 };
+cmp.le.f0.0(8)  g32<1>.xF       g32<4>.xF       0x0F  /* 0F */  { align16 };
+cmp.ge.f0.0(16) g4<1>D          g2.3<0,1,0>D    g2<0,1,0>D      { align1 compr };
+cmp.nz.f0.0(8)  g3<1>.xD        g1<0>.xD        g1<0>.yD        { align16 };
+cmp.nz.f0.0(8)  g3<1>.xyzF      g1<0>.xyzzF     g1.4<0>.xyzzF   { align16 };
+cmp.nz.f0.0(8)  null<1>F        g1<0>.xF        0x0F  /* 0F */  { align16 };
+cmp.le.f0.0(8)  g5<1>.xD        g1<0>.xD        0D              { align16 };
+cmp.l.f0.0(16)  g4<1>D          g2.1<0,1,0>D    g2<0,1,0>D      { align1 compr };
+cmp.ge.f0.0(8)  g3<1>D          g1<0>D          g1.4<0>D        { align16 };
+cmp.le.f0.0(16) null<1>F        g4<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 compr };
+cmp.le.f0.0(16) g20<1>F         g4<8,8,1>F      0x461c3f9aF  /* 9999.9F */ { align1 compr };
+cmp.z.f0.0(8)   null<1>F        g3<0>.xyzzF     0x6e6e6c6aVF /* [13F, 14F, 15F, 15F]VF */ { align16 };
+cmp.nz.f0.0(8)  null<1>D        g1<0>.xyzzD     g1.4<0>.xyzzD   { align16 };
+cmp.ge.f0.0(8)  null<1>.xD      g5<4>.xD        g3<0>.xD        { align16 };
+cmp.nz.f0.0(16) g8<1>F          g2.2<0,1,0>F    0x0F  /* 0F */  { align1 compr };
+cmp.l.f0.0(8)   null<1>F        g1<0>F          g3<4>F          { align16 };
+cmp.g.f0.0(8)   g7<1>.xF        g2<4>.xF        0x0F  /* 0F */  { align16 };
+cmp.g.f0.0(8)   null<1>.xF      g2<4>.yF        0x0F  /* 0F */  { align16 };
+cmp.nz.f0.0(16) null<1>D        g16<8,8,1>D     g12<8,8,1>D     { align1 compr };
+cmp.l.f0.0(16)  null<1>F        g2<0,1,0>F      0x0F  /* 0F */  { align1 compr };
+cmp.z.f0.0(8)   null<1>.xD      g1<0>.xD        1D              { align16 };
+cmp.nz.f0.0(16) g6<1>D          g4<8,8,1>D      g2.2<0,1,0>D    { align1 compr };
+cmp.g.f0.0(16)  g16<1>F         (abs)g8<8,8,1>F 0x3f800000F  /* 1F */ { align1 compr };
+cmp.l.f0.0(8)   g5<1>.xD        g1<0>.yD        g1<0>.xD        { align16 };
+cmp.ge.f0.0(8)  g6<1>.xF        g3<4>.xF        0x41f00000F  /* 30F */ { align16 };
+cmp.g.f0.0(16)  null<1>D        g2.1<0,1,0>D    0D              { align1 compr };
+cmp.ge.f0.0(16) null<1>D        g4<8,8,1>D      g2.1<0,1,0>D    { align1 compr };
+cmp.le.f0.0(8)  null<1>.xF      g8<4>.xF        0x3f000000F  /* 0.5F */ { align16 };
+cmp.ge.f0.0(8)  null<1>.xF      g22<4>.xF       g10<4>.xF       { align16 };
+cmp.z.f0.0(8)   g9<1>.xF        g1<0>.xF        0x40b79581F  /* 5.737F */ { align16 };
+cmp.z.f0.0(16)  null<1>D        g6<8,8,1>D      g2<0,1,0>D      { align1 compr };
+cmp.nz.f0.0(16) null<1>F        g4<8,8,1>F      g8<8,8,1>F      { align1 compr };
+(+f0.1) cmp.z.f0.1(16) null<1>D g6<8,8,1>D      0D              { align1 compr };
+cmp.nz.f0.0(8)  g11<1>.xD       g4<4>.xD        10D             { align16 };
+cmp.nz.f0.0(8)  g3<1>F          g3<4>F          0x0F  /* 0F */  { align16 };
+cmp.le.f0.0(16) g4<1>D          g2<0,1,0>D      0D              { align1 compr };
+cmp.l.f0.0(8)   null<1>.xD      g6<4>.xD        g5<4>.xD        { align16 };
+cmp.ge.f0.0(8)  g10<1>.xD       g5<4>.xD        2D              { align16 };
+cmp.g.f0.0(8)   null<1>.xD      g3<0>.zD        4D              { align16 };
+cmp.g.f0.0(16)  null<1>F        g20<8,8,1>F     0x0F  /* 0F */  { align1 compr };
+cmp.l.f0.0(16)  null<1>D        g2<0,1,0>D      g6<8,8,1>D      { align1 compr };
+(+f0.1) cmp.nz.f0.1(16) null<1>UW g0<8,8,1>UW   g0<8,8,1>UW     { align1 };
+cmp.le.f0.0(8)  g3<1>.xUD       g1<0>.xUD       0x00000001UD    { align16 };
+cmp.g.f0.0(8)   g8<1>.xD        g1<0>.xD        2D              { align16 };

diff --git a/src/intel/tools/tests/gen4.5/cmp.expected b/src/intel/tools/tests/gen4.5/cmp.expected
new file mode 100644 (file)
index 0000000..24ae8d5
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/cmp.expected
@@ -0,0 +1,80 @@
+10 01 60 02 bc 5f 0f 20 64 00 0a 00 64 6e 74 74
+10 01 60 02 a4 1c 0f 20 e4 00 6a 00 00 00 00 00
+10 20 80 04 bd 7f c0 20 80 00 8d 00 5f 70 89 31
+10 20 80 05 bd 7f 00 21 80 00 8d 00 5f 70 89 31
+10 20 80 05 bd 77 00 21 80 00 8d 00 c0 00 8d 00
+10 20 80 04 bd 77 40 21 80 00 8d 00 c0 00 8d 00
+10 01 60 01 a5 1c 41 21 80 00 00 00 00 00 00 00
+10 01 60 05 bd 7f e1 20 e0 00 60 00 5f 70 89 31
+10 01 60 04 bd 77 c1 20 40 00 00 00 c0 00 60 00
+10 01 60 01 bc 77 0f 20 6e 00 0f 00 64 00 05 00
+10 20 80 04 a4 1c 00 20 c0 01 8d 00 10 00 00 00
+10 20 80 05 a4 1c 00 20 40 00 00 00 01 00 00 00
+10 20 80 01 bd 77 00 21 00 04 8d 00 4c 00 00 00
+10 20 80 04 bc 7f 00 20 c0 00 8d 00 00 00 00 00
+10 01 60 02 bc 77 0f 20 84 01 65 00 24 00 05 00
+10 01 60 01 a4 14 0f 20 c4 00 6e 00 54 00 0e 00
+10 20 80 01 a5 1c c0 20 44 00 00 00 27 00 00 00
+10 20 80 01 bd 7f 80 20 44 00 00 00 00 00 00 41
+10 01 60 01 a5 14 a1 20 a0 00 60 00 2a 00 0a 00
+10 01 60 05 bd 77 63 20 24 00 05 00 2e 00 0f 00
+10 20 80 01 a4 1c 00 20 40 00 00 00 01 00 00 00
+10 20 80 01 bc 77 00 20 c0 01 8d 00 44 00 00 00
+10 01 60 01 bd 77 c1 20 c0 00 60 00 65 00 05 00
+10 20 80 02 bd 77 80 20 c0 00 8d 00 48 00 00 00
+10 20 80 04 bc 77 00 20 00 22 8d 00 00 21 8d 00
+10 20 80 02 a4 1c 00 20 40 00 00 00 00 00 00 00
+10 00 60 02 bd 77 a0 20 a0 00 8d 00 c0 04 8d 00
+10 01 60 04 a4 1c 01 20 a0 00 60 00 04 00 00 00
+10 20 80 02 bc 7f 00 20 50 00 00 00 00 00 00 00
+10 20 80 01 bc 7f 00 20 84 00 00 00 00 00 80 3f
+10 20 80 04 a5 1c 80 20 40 00 00 00 01 00 00 00
+10 20 80 02 a5 1c 80 20 44 00 00 00 00 00 00 00
+10 20 80 01 a5 14 00 21 c0 00 8d 00 54 00 00 00
+10 20 80 05 bc 77 00 20 80 00 8d 00 54 00 00 00
+10 20 80 05 a5 1c c0 20 60 00 00 00 01 00 00 00
+10 01 60 04 bc 7f 0f 20 00 04 60 00 00 00 00 00
+10 01 60 05 bc 7f 0f 20 e0 02 60 00 00 00 00 43
+10 01 60 06 bd 7f 01 24 00 04 60 00 00 00 00 00
+10 20 80 04 a5 14 80 20 4c 00 00 00 40 00 00 00
+10 01 60 02 a5 14 61 20 20 00 00 00 25 00 05 00
+10 01 60 02 bd 77 67 20 24 00 0a 00 34 00 0a 00
+10 01 60 02 bc 7f 0f 20 20 00 00 00 00 00 00 00
+10 01 60 06 a5 1c a1 20 20 00 00 00 00 00 00 00
+10 20 80 05 a5 14 80 20 44 00 00 00 40 00 00 00
+10 01 60 04 a5 14 6f 20 24 00 0e 00 34 00 0e 00
+10 20 80 06 bc 7f 00 20 80 00 8d 00 00 00 00 3f
+10 20 80 06 bd 7f 80 22 80 00 8d 00 9a 3f 1c 46
+10 01 60 01 bc 5f 0f 20 64 00 0a 00 6a 6c 6e 6e
+10 01 60 02 a4 14 0f 20 24 00 0a 00 34 00 0a 00
+10 01 60 04 a4 14 01 20 a0 00 60 00 60 00 00 00
+10 20 80 02 bd 7f 00 21 48 00 00 00 00 00 00 00
+10 01 60 05 bc 77 0f 20 24 00 0e 00 64 00 6e 00
+10 01 60 03 bd 7f e1 20 40 00 60 00 00 00 00 00
+10 01 60 03 bc 7f 01 20 45 00 65 00 00 00 00 00
+10 20 80 02 a4 14 00 20 00 02 8d 00 80 01 8d 00
+10 20 80 05 bc 7f 00 20 40 00 00 00 00 00 00 00
+10 01 60 01 a4 1c 01 20 20 00 00 00 01 00 00 00
+10 20 80 02 a5 14 c0 20 80 00 8d 00 48 00 00 00
+10 20 80 03 bd 7f 00 22 00 21 8d 00 00 00 80 3f
+10 01 60 05 a5 14 a1 20 25 00 05 00 20 00 00 00
+10 01 60 04 bd 7f c1 20 60 00 60 00 00 00 f0 41
+10 20 80 03 a4 1c 00 20 44 00 00 00 00 00 00 00
+10 20 80 04 a4 14 00 20 80 00 8d 00 44 00 00 00
+10 01 60 06 bc 7f 01 20 00 01 60 00 00 00 00 3f
+10 01 60 04 bc 77 01 20 c0 02 60 00 40 01 60 00
+10 01 60 01 bd 7f 21 21 20 00 00 00 81 95 b7 40
+10 20 80 01 a4 14 00 20 c0 00 8d 00 40 00 00 00
+10 20 80 02 bc 77 00 20 80 00 8d 00 00 01 8d 00
+10 20 81 01 a4 1c 00 20 c0 00 8d 02 00 00 00 00
+10 01 60 02 a5 1c 61 21 80 00 60 00 0a 00 00 00
+10 01 60 02 bd 7f 6f 20 64 00 6e 00 00 00 00 00
+10 20 80 06 a5 1c 80 20 40 00 00 00 00 00 00 00
+10 01 60 05 a4 14 01 20 c0 00 60 00 a0 00 60 00
+10 01 60 04 a5 1c 41 21 a0 00 60 00 02 00 00 00
+10 01 60 03 a4 1c 01 20 6a 00 0a 00 04 00 00 00
+10 20 80 03 bc 7f 00 20 80 02 8d 00 00 00 00 00
+10 20 80 05 a4 14 00 20 40 00 00 00 c0 00 8d 00
+10 00 81 02 28 25 00 20 00 00 8d 02 00 00 8d 00
+10 01 60 06 21 0c 61 20 20 00 00 00 01 00 00 00
+10 01 60 03 a5 1c 01 21 20 00 00 00 02 00 00 00

diff --git a/src/intel/tools/tests/gen4.5/cont.asm b/src/intel/tools/tests/gen4.5/cont.asm
new file mode 100644 (file)
index 0000000..a03dd98
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/cont.asm
@@ -0,0 +1,2 @@
+cont(16)        Jump: 4         Pop: 1                          { align1 };
+cont(8)         Jump: 4         Pop: 1                          { align16 };

diff --git a/src/intel/tools/tests/gen4.5/cont.expected b/src/intel/tools/tests/gen4.5/cont.expected
new file mode 100644 (file)
index 0000000..c40dc1c
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/cont.expected
@@ -0,0 +1,2 @@
+29 00 80 00 00 1c 00 34 00 14 60 00 04 00 01 00
+29 01 60 00 00 1c 0f 34 04 14 6e 00 04 00 01 00

diff --git a/src/intel/tools/tests/gen4.5/do.asm b/src/intel/tools/tests/gen4.5/do.asm
new file mode 100644 (file)
index 0000000..f0121e9
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/do.asm
@@ -0,0 +1,2 @@
+do(16)                                                          { align1 };
+do(8)                                                           { align16 };

diff --git a/src/intel/tools/tests/gen4.5/do.expected b/src/intel/tools/tests/gen4.5/do.expected
new file mode 100644 (file)
index 0000000..4ca58b7
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/do.expected
@@ -0,0 +1,2 @@
+26 00 80 00 9c 73 00 20 00 00 8d 00 00 00 8d 00
+26 01 60 00 9c 73 0f 20 04 00 6e 00 04 00 6e 00

diff --git a/src/intel/tools/tests/gen4.5/dp2.asm b/src/intel/tools/tests/gen4.5/dp2.asm
new file mode 100644 (file)
index 0000000..6411dbd
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/dp2.asm
@@ -0,0 +1,7 @@
+dp2(8)          g7<1>.xF        g7<4>.xyyyF     g7<4>.xyyyF     { align16 };
+dp2(8)          m5<1>.xF        g1<0>.yF        g1<0>.yF        { align16 };
+dp2(8)          m5<1>.yzF       g1<0>.xF        g1<0>.zwwwF     { align16 NoDDClr };
+dp2(8)          m5<1>.wF        g1<0>.ywwwF     g1<0>.wyyyF     { align16 NoDDChk };
+dp2(8)          g4<1>.yF        g1<0>.xyyyF     g1.4<0>.xyyyF   { align16 NoDDClr };
+dp2(8)          g4<1>.zF        g1<0>.xyyyF     g1.4<0>.zwwwF   { align16 NoDDClr,NoDDChk };
+dp2(8)          g4<1>.wF        g1<0>.xyyyF     g2<0>.xyyyF     { align16 NoDDChk };

diff --git a/src/intel/tools/tests/gen4.5/dp2.expected b/src/intel/tools/tests/gen4.5/dp2.expected
new file mode 100644 (file)
index 0000000..491895d
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/dp2.expected
@@ -0,0 +1,7 @@
+57 01 60 00 bd 77 e1 20 e4 00 65 00 e4 00 65 00
+57 01 60 00 be 77 a1 20 25 00 05 00 25 00 05 00
+57 05 60 00 be 77 a6 20 20 00 00 00 2e 00 0f 00
+57 09 60 00 be 77 a8 20 2d 00 0f 00 27 00 05 00
+57 05 60 00 bd 77 82 20 24 00 05 00 34 00 05 00
+57 0d 60 00 bd 77 84 20 24 00 05 00 3e 00 0f 00
+57 09 60 00 bd 77 88 20 24 00 05 00 44 00 05 00

diff --git a/src/intel/tools/tests/gen4.5/dp3.asm b/src/intel/tools/tests/gen4.5/dp3.asm
new file mode 100644 (file)
index 0000000..09cc1ab
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/dp3.asm
@@ -0,0 +1,9 @@
+dp3(8)          g5<1>.xF        g5<4>.xyzzF     g5<4>.xyzzF     { align16 };
+dp3(8)          m5<1>.xF        g3<0>.xyzzF     g6<4>.xyzzF     { align16 NoDDClr };
+dp3(8)          m5<1>.yF        g3.4<0>.xyzzF   g6<4>.xyzzF     { align16 NoDDClr,NoDDChk };
+dp3(8)          g19<1>.xF       g3<0>.xyzzF     g3.4<0>.xyzzF   { align16 NoDDClr };
+dp3(8)          g19<1>.yF       g3<0>.xyzzF     g4<0>.xyzzF     { align16 NoDDClr,NoDDChk };
+dp3(8)          g19<1>.zF       g3<0>.xyzzF     g4.4<0>.xyzzF   { align16 NoDDChk };
+dp3(8)          m5<1>.xF        g4<4>.xyzzF     g5<4>.xyzzF     { align16 };
+dp3.le.f0.0(8)  g18<1>.xF       g17<4>.xyzzF    g3.4<0>.xyzzF   { align16 };
+dp3.sat(8)      g4<1>.xF        g4<4>.xyzzF     g5<4>.xyzzF     { align16 };

diff --git a/src/intel/tools/tests/gen4.5/dp3.expected b/src/intel/tools/tests/gen4.5/dp3.expected
new file mode 100644 (file)
index 0000000..82f5b36
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/dp3.expected
@@ -0,0 +1,9 @@
+56 01 60 00 bd 77 a1 20 a4 00 6a 00 a4 00 6a 00
+56 05 60 00 be 77 a1 20 64 00 0a 00 c4 00 6a 00
+56 0d 60 00 be 77 a2 20 74 00 0a 00 c4 00 6a 00
+56 05 60 00 bd 77 61 22 64 00 0a 00 74 00 0a 00
+56 0d 60 00 bd 77 62 22 64 00 0a 00 84 00 0a 00
+56 09 60 00 bd 77 64 22 64 00 0a 00 94 00 0a 00
+56 01 60 00 be 77 a1 20 84 00 6a 00 a4 00 6a 00
+56 01 60 06 bd 77 41 22 24 02 6a 00 74 00 0a 00
+56 01 60 80 bd 77 81 20 84 00 6a 00 a4 00 6a 00

diff --git a/src/intel/tools/tests/gen4.5/dp4.asm b/src/intel/tools/tests/gen4.5/dp4.asm
new file mode 100644 (file)
index 0000000..5394d78
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/dp4.asm
@@ -0,0 +1,5 @@
+dp4(8)          g6<1>.xF        g3<4>F          g1<0>F          { align16 };
+dp4(8)          g4<1>.xF        g5<4>F          g1<0>F          { align16 NoDDClr };
+dp4(8)          g4<1>.yF        g5<4>F          g1.4<0>F        { align16 NoDDClr,NoDDChk };
+dp4(8)          g4<1>.wF        g5<4>F          g2.4<0>F        { align16 NoDDChk };
+dp4(8)          m5<1>.xF        g4<4>F          g5<4>F          { align16 };

diff --git a/src/intel/tools/tests/gen4.5/dp4.expected b/src/intel/tools/tests/gen4.5/dp4.expected
new file mode 100644 (file)
index 0000000..99bf76d
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/dp4.expected
@@ -0,0 +1,5 @@
+54 01 60 00 bd 77 c1 20 64 00 6e 00 24 00 0e 00
+54 05 60 00 bd 77 81 20 a4 00 6e 00 24 00 0e 00
+54 0d 60 00 bd 77 82 20 a4 00 6e 00 34 00 0e 00
+54 09 60 00 bd 77 88 20 a4 00 6e 00 54 00 0e 00
+54 01 60 00 be 77 a1 20 84 00 6e 00 a4 00 6e 00

diff --git a/src/intel/tools/tests/gen4.5/dph.asm b/src/intel/tools/tests/gen4.5/dph.asm
new file mode 100644 (file)
index 0000000..16c9d52
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/dph.asm
@@ -0,0 +1,5 @@
+dph(8)          m5<1>.xF        g4<4>.xyzxF     g5<4>F          { align16 };
+dph.sat(8)      m5<1>F          g1<0>.xyzxF     g3<4>F          { align16 };
+dph(8)          g5<1>.xF        g4<4>.xyzxF     g1<0>F          { align16 NoDDClr };
+dph(8)          g5<1>.yF        g4<4>.xyzxF     g1.4<0>F        { align16 NoDDClr,NoDDChk };
+dph(8)          g6<1>.wF        g5<4>.xyzxF     g2.4<0>F        { align16 NoDDChk };

diff --git a/src/intel/tools/tests/gen4.5/dph.expected b/src/intel/tools/tests/gen4.5/dph.expected
new file mode 100644 (file)
index 0000000..aed1eae
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/dph.expected
@@ -0,0 +1,5 @@
+55 01 60 00 be 77 a1 20 84 00 62 00 a4 00 6e 00
+55 01 60 80 be 77 af 20 24 00 02 00 64 00 6e 00
+55 05 60 00 bd 77 a1 20 84 00 62 00 24 00 0e 00
+55 0d 60 00 bd 77 a2 20 84 00 62 00 34 00 0e 00
+55 09 60 00 bd 77 c8 20 a4 00 62 00 54 00 0e 00

diff --git a/src/intel/tools/tests/gen4.5/else.asm b/src/intel/tools/tests/gen4.5/else.asm
new file mode 100644 (file)
index 0000000..7ce3494
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/else.asm
@@ -0,0 +1,2 @@
+else(16)        Jump: 7         Pop: 1                          { align1 switch };
+else(8)         Jump: 3         Pop: 1                          { align16 switch };

diff --git a/src/intel/tools/tests/gen4.5/else.expected b/src/intel/tools/tests/gen4.5/else.expected
new file mode 100644 (file)
index 0000000..c56d124
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/else.expected
@@ -0,0 +1,2 @@
+24 80 80 00 00 1c 00 34 00 14 60 00 07 00 01 00
+24 81 60 00 00 1c 0f 34 04 14 6e 00 03 00 01 00

diff --git a/src/intel/tools/tests/gen4.5/endif.asm b/src/intel/tools/tests/gen4.5/endif.asm
new file mode 100644 (file)
index 0000000..6c71e4a
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/endif.asm
@@ -0,0 +1,2 @@
+endif(16)       Pop: 1                                          { align1 switch };
+endif(8)        Pop: 1                                          { align16 switch };

diff --git a/src/intel/tools/tests/gen4.5/endif.expected b/src/intel/tools/tests/gen4.5/endif.expected
new file mode 100644 (file)
index 0000000..99daf4c
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/endif.expected
@@ -0,0 +1,2 @@
+25 80 80 00 84 1c 00 20 00 00 8d 00 00 00 01 00
+25 81 60 00 84 1c 0f 20 04 00 6e 00 00 00 01 00

diff --git a/src/intel/tools/tests/gen4.5/frc.asm b/src/intel/tools/tests/gen4.5/frc.asm
new file mode 100644 (file)
index 0000000..02e11fc
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/frc.asm
@@ -0,0 +1,4 @@
+frc.sat(8)      m5<1>F          g3<4>F                          { align16 };
+frc(8)          g7<1>.xF        (abs)g1<0>.xF                   { align16 };
+frc(16)         g4<1>F          g2<0,1,0>F                      { align1 compr };
+frc(16)         m3<1>F          g10<8,8,1>F                     { align1 compr4 };

diff --git a/src/intel/tools/tests/gen4.5/frc.expected b/src/intel/tools/tests/gen4.5/frc.expected
new file mode 100644 (file)
index 0000000..591f73d
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/frc.expected
@@ -0,0 +1,4 @@
+43 01 60 80 be 03 af 20 64 00 6e 00 00 00 00 00
+43 01 60 00 bd 03 e1 20 20 20 00 00 00 00 00 00
+43 20 80 00 bd 03 80 20 40 00 00 00 00 00 00 00
+43 20 80 00 be 03 60 30 40 01 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen4.5/if.asm b/src/intel/tools/tests/gen4.5/if.asm
new file mode 100644 (file)
index 0000000..db56aca
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/if.asm
@@ -0,0 +1,2 @@
+(+f0.0) if(16)  Jump: 15                                        { align1 switch };
+(+f0.0.x) if(8) Jump: 7                                         { align16 switch };

diff --git a/src/intel/tools/tests/gen4.5/if.expected b/src/intel/tools/tests/gen4.5/if.expected
new file mode 100644 (file)
index 0000000..cef4838
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/if.expected
@@ -0,0 +1,2 @@
+22 80 81 00 00 1c 00 34 00 14 60 00 0f 00 00 00
+22 81 62 00 00 1c 0f 34 04 14 6e 00 07 00 00 00

diff --git a/src/intel/tools/tests/gen4.5/iff.asm b/src/intel/tools/tests/gen4.5/iff.asm
new file mode 100644 (file)
index 0000000..1ff0b17
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/iff.asm
@@ -0,0 +1,3 @@
+(-f0.0) iff(16) Jump: 5                                         { align1 switch };
+(+f0.0.x) iff(8) Jump: 11                                       { align16 switch };
+(+f0.0) iff(16) Jump: 7                                         { align1 switch };

diff --git a/src/intel/tools/tests/gen4.5/iff.expected b/src/intel/tools/tests/gen4.5/iff.expected
new file mode 100644 (file)
index 0000000..4ed2705
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/iff.expected
@@ -0,0 +1,3 @@
+23 80 91 00 00 1c 00 34 00 14 60 00 05 00 00 00
+23 81 62 00 00 1c 0f 34 04 14 6e 00 0b 00 00 00
+23 80 81 00 00 1c 00 34 00 14 60 00 07 00 00 00

diff --git a/src/intel/tools/tests/gen4.5/jmpi.asm b/src/intel/tools/tests/gen4.5/jmpi.asm
new file mode 100644 (file)
index 0000000..65d0d53
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/jmpi.asm
@@ -0,0 +1 @@
+(+f0.0) jmpi(1) 0x00000002UD                                    { align1 nomask };

diff --git a/src/intel/tools/tests/gen4.5/jmpi.expected b/src/intel/tools/tests/gen4.5/jmpi.expected
new file mode 100644 (file)
index 0000000..682e0a7
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/jmpi.expected
@@ -0,0 +1 @@
+20 02 01 00 00 0c 00 34 00 14 00 00 02 00 00 00

diff --git a/src/intel/tools/tests/gen4.5/mach.asm b/src/intel/tools/tests/gen4.5/mach.asm
new file mode 100644 (file)
index 0000000..5e0ccc5
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/mach.asm
@@ -0,0 +1 @@
+mach(8)         null<1>D        g1<0>.xD        g1<0>.yD        { align16 };

diff --git a/src/intel/tools/tests/gen4.5/mach.expected b/src/intel/tools/tests/gen4.5/mach.expected
new file mode 100644 (file)
index 0000000..90d1371
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/mach.expected
@@ -0,0 +1 @@
+49 01 60 00 a4 14 0f 20 20 00 00 00 25 00 05 00

diff --git a/src/intel/tools/tests/gen4.5/mov.asm b/src/intel/tools/tests/gen4.5/mov.asm
new file mode 100644 (file)
index 0000000..70bb68f
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/mov.asm
@@ -0,0 +1,102 @@
+mov(8)          m2<1>UD         g1<8,8,1>UD                     { align1 nomask };
+mov(8)          g9<1>.xyzUD     0x00000000UD                    { align16 };
+mov.sat(8)      m5<1>F          g4<4>F                          { align16 };
+mov(8)          m4<1>F          g6<4>F                          { align16 };
+mov(8)          m2<1>UD         g9<4>UD                         { align16 };
+mov(16)         g6<1>D          1065353216D                     { align1 compr };
+mov.nz.f0.0(16) null<1>D        g2<0,1,0>D                      { align1 compr };
+mov(16)         m3<1>F          0x0F             /* 0F */       { align1 compr4 };
+mov(16)         m4<1>F          g4<8,8,1>F                      { align1 compr4 };
+mov(8)          m2<1>UD         0x00000000UD                    { align16 };
+mov(8)          g8<1>F          0x30003000VF    /* [0F, 1F, 0F, 1F]VF */ { align16 };
+mov(8)          g7<1>.xD        0D                              { align16 };
+(+f0.0.any4h) mov(8) g7<1>.xD   -1D                             { align16 };
+mov(16)         m3<1>F          g4<8,8,1>D                      { align1 compr4 };
+mov(1)          m14<1>D         0D                              { align1 nomask };
+mov(8)          m15<1>D         g3<0>D                          { align16 };
+mov(1)          m14<1>D         g8<0,1,0>D                      { align1 nomask };
+mov(16)         g12<1>F         g4<8,8,1>UW                     { align1 compr };
+mov(16)         g4<1>D          g12<8,8,1>F                     { align1 compr };
+mov(16)         g12<1>F         g4<8,8,1>D                      { align1 compr };
+mov(8)          m15<1>D         g2<4>.xUD                       { align16 };
+mov(8)          g7<1>.xD        g4<0>.yD                        { align16 };
+mov(8)          g7<1>.xD        g10<4>.xD                       { align16 NoDDClr };
+mov(8)          g7<1>.yD        g4<0>.yD                        { align16 NoDDChk };
+mov(16)         m2<1>UD         0x00000000UD                    { align1 compr };
+mov(16)         m6<1>D          g9.3<0,1,0>D                    { align1 compr };
+mov(16)         m8<1>UD         0D                              { align1 compr };
+mov(16)         m2<1>D          g4<8,8,1>F                      { align1 compr };
+mov(8)          m5<1>.xF        g3<4>.xD                        { align16 NoDDClr };
+mov(8)          m5<1>.yzwD      0D                              { align16 NoDDChk };
+mov.sat(16)     m3<1>F          g2<0,1,0>F                      { align1 compr4 };
+mov(8)          m6<1>F          0x50484030VF    /* [1F, 2F, 3F, 4F]VF */ { align16 };
+mov(8)          m3<1>F          0x42fc6666F      /* 126.2F */   { align1 };
+mov(8)          m3<1>F          0x42fc6666F      /* 126.2F */   { align1 sechalf };
+mov(8)          m5<1>.wD        g8<4>.wD                        { align16 NoDDChk };
+mov(8)          g6<1>.xD        g6<4>.xF                        { align16 };
+mov(8)          m3<1>F          g[a0]<VxH,1,0>F                 { align1 };
+mov(8)          m7<1>F          g[a0]<VxH,1,0>F                 { align1 sechalf };
+mov(8)          g20<1>.yD       -1070881309D                    { align16 NoDDClr };
+mov(8)          g20<1>.zD       1091044167D                     { align16 NoDDChk };
+mov(8)          g28<1>.zD       -1102236248D                    { align16 NoDDClr,NoDDChk };
+mov(8)          g5<1>.xD        acc0<4>D                        { align16 };
+mov(8)          m13<1>.wD       1107296256D                     { align16 NoDDClr };
+mov(8)          g11<1>.yzwD     0x48403000VF    /* [0F, 1F, 2F, 3F]VF */ { align16 };
+mov(8)          m13<1>.xyzF     0x7f7e7dVF      /* [29F, 30F, 31F, 0F]VF */ { align16 NoDDChk };
+mov(16)         m3<1>UD         g4<8,8,1>UD                     { align1 compr4 };
+mov(8)          m6<1>.xF        0x0F             /* 0F */       { align16 };
+(+f0.0.all4h) mov(8) g3<1>.xD   -1D                             { align16 };
+mov(8)          g3<1>F          g2<0,1,0>D                      { align1 };
+mov(8)          m3<1>F          g2<8,8,1>D                      { align1 };
+mov(8)          m5<1>.yF        g3<4>.xD                        { align16 NoDDClr,NoDDChk };
+mov(8)          m5<1>.wF        g3<4>.xD                        { align16 NoDDChk };
+mov(8)          g3<1>.xF        g3<4>.xD                        { align16 NoDDClr };
+mov(8)          g3<1>.yF        g4<4>.xD                        { align16 NoDDClr,NoDDChk };
+mov(8)          g3<1>.wF        g4<4>.xD                        { align16 NoDDChk };
+mov(8)          g8<1>UD         g2<4>UD                         { align16 };
+mov(8)          g7<1>.xF        g3<0>.xD                        { align16 };
+mov(8)          g6<1>.xF        -g5<4>.yF                       { align16 NoDDClr };
+mov.nz.f0.0(16) g4<1>F          -(abs)g2<0,1,0>F                { align1 compr };
+(+f0.0) mov(16) g4<1>F          0xbf800000F      /* -1F */      { align1 compr };
+mov(16)         g24<1>D         g42<8,8,1>D                     { align1 compr };
+mov(8)          g8<1>F          g[a0]<VxH,1,0>F                 { align1 };
+mov(8)          g9<1>F          g[a0]<VxH,1,0>F                 { align1 sechalf };
+mov(8)          g3<1>.xyzF      0x0F             /* 0F */       { align16 };
+mov(16)         m2<1>UD         g28<8,8,1>UW                    { align1 compr };
+mov(8)          m3<1>D          g2<0,1,0>D                      { align1 };
+mov(8)          m3<1>D          g2<0,1,0>D                      { align1 sechalf };
+mov(1)          m14.2<1>UD      0x00000000UD                    { align1 nomask };
+mov(8)          g5<1>.zD        g1.4<0>.xD                      { align16 NoDDClr,NoDDChk };
+mov.sat(8)      m5<1>.wF        g20<4>.wF                       { align16 NoDDChk };
+mov(8)          g26<1>.xyzUD    0x00000000UD                    { align16 NoDDClr };
+mov(8)          m9<1>.xyD       g4<0>.yzzzD                     { align16 NoDDClr };
+mov(8)          m5<1>F          g3<4>D                          { align16 };
+mov(8)          m3<1>F          g4<8,8,1>F                      { align1 nomask };
+mov.sat(8)      m5<1>.zF        0x3eaaaaabF      /* 0.333333F */ { align16 };
+mov.sat(8)      m5<1>.wF        0x3dcccccdF      /* 0.1F */     { align16 NoDDClr };
+mov(8)          m5<1>.zD        g3<4>.zD                        { align16 NoDDClr,NoDDChk };
+mov(8)          m13<1>.yD       1107820544D                     { align16 NoDDClr,NoDDChk };
+mov.sat(8)      m5<1>.wF        0x3f800000F      /* 1F */       { align16 NoDDChk };
+mov.sat(8)      m5<1>F          g3<4>D                          { align16 };
+mov.sat(8)      m5<1>.zF        0x3f666660F      /* 0.9F */     { align16 NoDDClr,NoDDChk };
+mov(16)         g10<1>F         g2<0,1,0>F                      { align1 compr };
+mov(16)         g10<1>F         0x3f800000F      /* 1F */       { align1 compr };
+mov(8)          m15<1>D         0D                              { align16 };
+mov.sat(16)     g4<1>F          g2<0,1,0>F                      { align1 compr };
+mov(8)          g2<1>.xyzF      g2<4>.wF                        { align16 };
+mov(8)          g5<1>.xyzF      0x7f7e7dVF      /* [29F, 30F, 31F, 0F]VF */ { align16 NoDDChk };
+mov.sat(8)      m5<1>.xF        g4<4>.xF                        { align16 NoDDClr };
+mov.sat(8)      m5<1>.yzF       g5<4>.xxyyF                     { align16 NoDDClr,NoDDChk };
+mov(1)          f0.1<1>UW       g0<0,1,0>UW                     { align1 nomask };
+mov(1)          g0<1>UW         f0.1<0,1,0>UW                   { align1 nomask };
+mov(8)          m5<1>.zwF       0x30000000VF    /* [0F, 0F, 0F, 1F]VF */ { align16 NoDDClr };
+mov.sat(8)      m5<1>.xF        g5<4>.xD                        { align16 NoDDClr };
+mov.sat(8)      m5<1>.yF        g5<4>.xD                        { align16 NoDDClr,NoDDChk };
+mov.sat(8)      m5<1>.wF        g5<4>.xD                        { align16 NoDDChk };
+mov(8)          g6<1>.yzD       0xf7c000VF      /* [0F, -2F, -23F, 0F]VF */ { align16 NoDDChk };
+mov(8)          m2<1>.xyzUD     0x00000000UD                    { align16 NoDDClr };
+mov(8)          m2<1>.wUD       g8<4>.xUD                       { align16 NoDDChk };
+mov(8)          g5<1>F          g3<4>UD                         { align16 };
+mov.nz.f0.0(8)  null<1>.xD      g8<4>.xD                        { align16 };
+mov.nz.f0.0(8)  g8<1>F          -(abs)g1<0>F                    { align16 };
+(+f0.0) mov(8)  g8<1>F          0xbf800000F      /* -1F */      { align16 };

diff --git a/src/intel/tools/tests/gen4.5/mov.expected b/src/intel/tools/tests/gen4.5/mov.expected
new file mode 100644 (file)
index 0000000..8273f50
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/mov.expected
@@ -0,0 +1,102 @@
+01 02 60 00 22 00 40 20 20 00 8d 00 00 00 00 00
+01 01 60 00 61 00 27 21 00 00 00 00 00 00 00 00
+01 01 60 80 be 03 af 20 84 00 6e 00 00 00 00 00
+01 01 60 00 be 03 8f 20 c4 00 6e 00 00 00 00 00
+01 01 60 00 22 00 4f 20 24 01 6e 00 00 00 00 00
+01 20 80 00 e5 10 c0 20 00 00 00 00 00 00 80 3f
+01 20 80 02 a4 00 00 20 40 00 00 00 00 00 00 00
+01 20 80 00 fe 73 60 30 00 00 00 00 00 00 00 00
+01 20 80 00 be 03 80 30 80 00 8d 00 00 00 00 00
+01 01 60 00 62 00 4f 20 00 00 00 00 00 00 00 00
+01 01 60 00 fd 52 0f 21 00 00 00 00 00 30 00 30
+01 01 60 00 e5 10 e1 20 00 00 00 00 00 00 00 00
+01 01 66 00 e5 10 e1 20 00 00 00 00 ff ff ff ff
+01 20 80 00 be 00 60 30 80 00 8d 00 00 00 00 00
+01 02 00 00 e6 10 c0 21 00 00 00 00 00 00 00 00
+01 01 60 00 a6 00 ef 21 64 00 0e 00 00 00 00 00
+01 02 00 00 a6 00 c0 21 00 01 00 00 00 00 00 00
+01 20 80 00 3d 01 80 21 80 00 8d 00 00 00 00 00
+01 20 80 00 a5 03 80 20 80 01 8d 00 00 00 00 00
+01 20 80 00 bd 00 80 21 80 00 8d 00 00 00 00 00
+01 01 60 00 26 00 ef 21 40 00 60 00 00 00 00 00
+01 01 60 00 a5 00 e1 20 85 00 05 00 00 00 00 00
+01 05 60 00 a5 00 e1 20 40 01 60 00 00 00 00 00
+01 09 60 00 a5 00 e2 20 85 00 05 00 00 00 00 00
+01 20 80 00 62 00 40 20 00 00 00 00 00 00 00 00
+01 20 80 00 a6 00 c0 20 2c 01 00 00 00 00 00 00
+01 20 80 00 e2 10 00 21 00 00 00 00 00 00 00 00
+01 20 80 00 a6 03 40 20 80 00 8d 00 00 00 00 00
+01 05 60 00 be 00 a1 20 60 00 60 00 00 00 00 00
+01 09 60 00 e6 10 ae 20 00 00 00 00 00 00 00 00
+01 20 80 80 be 03 60 30 40 00 00 00 00 00 00 00
+01 01 60 00 fe 52 cf 20 00 00 00 00 30 40 48 50
+01 00 60 00 fe 73 60 20 00 00 00 00 66 66 fc 42
+01 10 60 00 fe 73 60 20 00 00 00 00 66 66 fc 42
+01 09 60 00 a6 00 a8 20 0f 01 6f 00 00 00 00 00
+01 01 60 00 a5 03 c1 20 c0 00 60 00 00 00 00 00
+01 00 60 00 be 03 60 20 00 80 e0 01 00 00 00 00
+01 10 60 00 be 03 e0 20 00 80 e0 01 00 00 00 00
+01 05 60 00 e5 10 82 22 00 00 00 00 e3 a5 2b c0
+01 09 60 00 e5 10 84 22 00 00 00 00 47 03 08 41
+01 0d 60 00 e5 10 84 23 00 00 00 00 a8 35 4d be
+01 01 60 00 85 00 a1 20 04 04 6e 00 00 00 00 00
+01 05 60 00 e6 10 a8 21 00 00 00 00 00 00 00 42
+01 01 60 00 e5 52 6e 21 00 00 00 00 00 30 40 48
+01 09 60 00 fe 52 a7 21 00 00 00 00 7d 7e 7f 00
+01 20 80 00 22 00 60 30 80 00 8d 00 00 00 00 00
+01 01 60 00 fe 73 c1 20 00 00 00 00 00 00 00 00
+01 01 67 00 e5 10 61 20 00 00 00 00 ff ff ff ff
+01 00 60 00 bd 00 60 20 40 00 00 00 00 00 00 00
+01 00 60 00 be 00 60 20 40 00 8d 00 00 00 00 00
+01 0d 60 00 be 00 a2 20 60 00 60 00 00 00 00 00
+01 09 60 00 be 00 a8 20 60 00 60 00 00 00 00 00
+01 05 60 00 bd 00 61 20 60 00 60 00 00 00 00 00
+01 0d 60 00 bd 00 62 20 80 00 60 00 00 00 00 00
+01 09 60 00 bd 00 68 20 80 00 60 00 00 00 00 00
+01 01 60 00 21 00 0f 21 44 00 6e 00 00 00 00 00
+01 01 60 00 bd 00 e1 20 60 00 00 00 00 00 00 00
+01 05 60 00 bd 03 c1 20 a5 40 65 00 00 00 00 00
+01 20 80 02 bd 03 80 20 40 60 00 00 00 00 00 00
+01 20 81 00 fd 73 80 20 00 00 00 00 00 00 80 bf
+01 20 80 00 a5 00 00 23 40 05 8d 00 00 00 00 00
+01 00 60 00 bd 03 00 21 00 80 e0 01 00 00 00 00
+01 10 60 00 bd 03 20 21 00 80 e0 01 00 00 00 00
+01 01 60 00 fd 73 67 20 00 00 00 00 00 00 00 00
+01 20 80 00 22 01 40 20 80 03 8d 00 00 00 00 00
+01 00 60 00 a6 00 60 20 40 00 00 00 00 00 00 00
+01 10 60 00 a6 00 60 20 40 00 00 00 00 00 00 00
+01 02 00 00 62 00 c8 21 00 00 00 00 00 00 00 00
+01 0d 60 00 a5 00 a4 20 30 00 00 00 00 00 00 00
+01 09 60 80 be 03 a8 20 8f 02 6f 00 00 00 00 00
+01 05 60 00 61 00 47 23 00 00 00 00 00 00 00 00
+01 05 60 00 a6 00 23 21 89 00 0a 00 00 00 00 00
+01 01 60 00 be 00 af 20 64 00 6e 00 00 00 00 00
+01 02 60 00 be 03 60 20 80 00 8d 00 00 00 00 00
+01 01 60 80 fe 73 a4 20 00 00 00 00 ab aa aa 3e
+01 05 60 80 fe 73 a8 20 00 00 00 00 cd cc cc 3d
+01 0d 60 00 a6 00 a4 20 6a 00 6a 00 00 00 00 00
+01 0d 60 00 e6 10 a2 21 00 00 00 00 00 00 08 42
+01 09 60 80 fe 73 a8 20 00 00 00 00 00 00 80 3f
+01 01 60 80 be 00 af 20 64 00 6e 00 00 00 00 00
+01 0d 60 80 fe 73 a4 20 00 00 00 00 60 66 66 3f
+01 20 80 00 bd 03 40 21 40 00 00 00 00 00 00 00
+01 20 80 00 fd 73 40 21 00 00 00 00 00 00 80 3f
+01 01 60 00 e6 10 ef 21 00 00 00 00 00 00 00 00
+01 20 80 80 bd 03 80 20 40 00 00 00 00 00 00 00
+01 01 60 00 bd 03 47 20 4f 00 6f 00 00 00 00 00
+01 09 60 00 fd 52 a7 20 00 00 00 00 7d 7e 7f 00
+01 05 60 80 be 03 a1 20 80 00 60 00 00 00 00 00
+01 0d 60 80 be 03 a6 20 a0 00 65 00 00 00 00 00
+01 02 00 00 28 01 02 26 00 00 00 00 00 00 00 00
+01 02 00 00 09 01 00 20 02 06 00 00 00 00 00 00
+01 05 60 00 fe 52 ac 20 00 00 00 00 00 00 00 30
+01 05 60 80 be 00 a1 20 a0 00 60 00 00 00 00 00
+01 0d 60 80 be 00 a2 20 a0 00 60 00 00 00 00 00
+01 09 60 80 be 00 a8 20 a0 00 60 00 00 00 00 00
+01 09 60 00 e5 52 c6 20 00 00 00 00 00 c0 f7 00
+01 05 60 00 62 00 47 20 00 00 00 00 00 00 00 00
+01 09 60 00 22 00 48 20 00 01 60 00 00 00 00 00
+01 01 60 00 3d 00 af 20 64 00 6e 00 00 00 00 00
+01 01 60 02 a4 00 01 20 00 01 60 00 00 00 00 00
+01 01 60 02 bd 03 0f 21 24 60 0e 00 00 00 00 00
+01 01 61 00 fd 73 0f 21 00 00 00 00 00 00 80 bf

diff --git a/src/intel/tools/tests/gen4.5/mul.asm b/src/intel/tools/tests/gen4.5/mul.asm
new file mode 100644 (file)
index 0000000..6d1247e
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/mul.asm
@@ -0,0 +1,37 @@
+mul(16)         m3<1>F          g10<8,8,1>F     g12<8,8,1>F     { align1 compr4 };
+mul(8)          g8<1>.xyzF      g6<4>.xyzzF     g8<4>.wF        { align16 };
+mul(8)          g9<1>.wUD       g7<4>.wF        0x45000000F  /* 2048F */ { align16 };
+mul(16)         g22<1>F         g18<8,8,1>F     g20<8,8,1>F     { align1 compr };
+mul(8)          g8<1>.xD        g8<4>.xD        g5<0>.xD        { align16 };
+mul(8)          g8<1>.xD        g8<4>.xD        32D             { align16 };
+mul(16)         g22<1>F         g16<8,8,1>F     0x41800000F  /* 16F */ { align1 compr };
+mul(16)         m3<1>F          g6<8,8,1>F      0x3b800000F  /* 0.00390625F */ { align1 compr4 };
+mul(8)          m5<1>.xyF       g3<4>.xyyyF     0x3f000000F  /* 0.5F */ { align16 NoDDClr };
+mul(8)          g5<1>F          g3<4>F          0x37800000F  /* 1.52588e-05F */ { align16 };
+mul.sat(16)     m2<1>F          g14<8,8,1>F     g6<8,8,1>F      { align1 compr };
+mul(8)          acc0<1>D        g1<0>.xD        g1<0>.yD        { align16 };
+mul(8)          m5<1>F          g3<4>F          0x3f000000F  /* 0.5F */ { align16 };
+mul(16)         g4<1>D          g6<8,8,1>D      g2<0,1,0>D      { align1 compr };
+mul.sat(16)     g18<1>F         g16<8,8,1>F     g14<8,8,1>F     { align1 compr };
+mul(8)          g4<1>F          g4<8,8,1>F      g55<8,8,1>F     { align1 };
+mul(8)          g26<1>.wUD      g29<4>.wF       0x45000000F  /* 2048F */ { align16 NoDDChk };
+mul(8)          g2<1>.xyzF      g2<4>.wF        0x40404830VF /* [1F, 3F, 2F, 2F]VF */ { align16 };
+mul(16)         g4<1>D          g2<0,1,0>UW     g2.2<0,1,0>D    { align1 compr };
+mul.sat(8)      g6<1>.xyzF      g6<4>.xyzzF     g7<4>.xF        { align16 };
+mul.sat(8)      m5<1>F          g6<4>F          0x3b800000F  /* 0.00390625F */ { align16 };
+mul.sat(8)      m5<1>.xyzF      g3<4>.xyzzF     0x3f000000F  /* 0.5F */ { align16 NoDDClr };
+mul.g.f0.0(16)  null<1>F        g10<8,8,1>F     g12<8,8,1>F     { align1 compr };
+mul.l.f0.0(8)   null<1>.xF      g1<0>.zF        g1<0>.yF        { align16 };
+mul.l.f0.0(16)  null<1>F        g2.2<0,1,0>F    g2.1<0,1,0>F    { align1 compr };
+mul.l.f0.0(16)  g14<1>F         g10<8,8,1>F     g12<8,8,1>F     { align1 compr };
+mul(8)          m5<1>.xyF       g3<4>.xyyyF     0x3f000000F  /* 0.5F */ { align16 NoDDChk };
+mul.nz.f0.0(16) g16<1>F         g10<8,8,1>F     g12<8,8,1>F     { align1 compr };
+mul.sat(8)      m6<1>.xyzF      g32<4>.xF       g30<4>.xyzzF    { align16 NoDDClr };
+mul.nz.f0.0(16) g6<1>F          g4<8,8,1>F      0x3f808000F  /* 1.00391F */ { align1 compr };
+mul.sat(8)      m5<1>.xyF       g1<0>.wzzzF     g3<4>.wzzzF     { align16 };
+mul.sat(8)      m5<1>F          g4<4>F          0x20303030VF /* [1F, 1F, 1F, 0.5F]VF */ { align16 };
+mul(8)          m5<1>F          g3<4>F          0x20305454VF /* [5F, 5F, 1F, 0.5F]VF */ { align16 };
+mul(8)          m6<1>.xyzF      g12<4>.xyzzF    g13<4>.xF       { align16 NoDDClr };
+mul(8)          m5<1>.xyzF      g3<4>.xyzzF     0x30302020VF /* [0.5F, 0.5F, 1F, 1F]VF */ { align16 NoDDClr };
+mul(8)          m5<1>.zF        g3<4>.zF        0x3f000000F  /* 0.5F */ { align16 NoDDClr,NoDDChk };
+mul(8)          m5<1>F          g3<4>F          g1<0>.xF        { align16 };

diff --git a/src/intel/tools/tests/gen4.5/mul.expected b/src/intel/tools/tests/gen4.5/mul.expected
new file mode 100644 (file)
index 0000000..bcd42f8
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/mul.expected
@@ -0,0 +1,37 @@
+41 20 80 00 be 77 60 30 40 01 8d 00 80 01 8d 00
+41 01 60 00 bd 77 07 21 c4 00 6a 00 0f 01 6f 00
+41 01 60 00 a1 7f 28 21 ef 00 6f 00 00 00 00 45
+41 20 80 00 bd 77 c0 22 40 02 8d 00 80 02 8d 00
+41 01 60 00 a5 14 01 21 00 01 60 00 a0 00 00 00
+41 01 60 00 a5 1c 01 21 00 01 60 00 20 00 00 00
+41 20 80 00 bd 7f c0 22 00 02 8d 00 00 00 80 41
+41 20 80 00 be 7f 60 30 c0 00 8d 00 00 00 80 3b
+41 05 60 00 be 7f a3 20 64 00 65 00 00 00 00 3f
+41 01 60 00 bd 7f af 20 64 00 6e 00 00 00 80 37
+41 20 80 80 be 77 40 20 c0 01 8d 00 c0 00 8d 00
+41 01 60 00 a4 14 0f 24 20 00 00 00 25 00 05 00
+41 01 60 00 be 7f af 20 64 00 6e 00 00 00 00 3f
+41 20 80 00 a5 14 80 20 c0 00 8d 00 40 00 00 00
+41 20 80 80 bd 77 40 22 00 02 8d 00 c0 01 8d 00
+41 00 60 00 bd 77 80 20 80 00 8d 00 e0 06 8d 00
+41 09 60 00 a1 7f 48 23 af 03 6f 00 00 00 00 45
+41 01 60 00 bd 5f 47 20 4f 00 6f 00 30 48 40 40
+41 20 80 00 25 15 80 20 40 00 00 00 48 00 00 00
+41 01 60 80 bd 77 c7 20 c4 00 6a 00 e0 00 60 00
+41 01 60 80 be 7f af 20 c4 00 6e 00 00 00 80 3b
+41 05 60 80 be 7f a7 20 64 00 6a 00 00 00 00 3f
+41 20 80 03 bc 77 00 20 40 01 8d 00 80 01 8d 00
+41 01 60 05 bc 77 01 20 2a 00 0a 00 25 00 05 00
+41 20 80 05 bc 77 00 20 48 00 00 00 44 00 00 00
+41 20 80 05 bd 77 c0 21 40 01 8d 00 80 01 8d 00
+41 09 60 00 be 7f a3 20 64 00 65 00 00 00 00 3f
+41 20 80 02 bd 77 00 22 40 01 8d 00 80 01 8d 00
+41 05 60 80 be 77 c7 20 00 04 60 00 c4 03 6a 00
+41 20 80 02 bd 7f c0 20 80 00 8d 00 00 80 80 3f
+41 01 60 80 be 77 a3 20 2b 00 0a 00 6b 00 6a 00
+41 01 60 80 be 5f af 20 84 00 6e 00 30 30 30 20
+41 01 60 00 be 5f af 20 64 00 6e 00 54 54 30 20
+41 05 60 00 be 77 c7 20 84 01 6a 00 a0 01 60 00
+41 05 60 00 be 5f a7 20 64 00 6a 00 20 20 30 30
+41 0d 60 00 be 7f a4 20 6a 00 6a 00 00 00 00 3f
+41 01 60 00 be 77 af 20 64 00 6e 00 20 00 00 00

diff --git a/src/intel/tools/tests/gen4.5/not.asm b/src/intel/tools/tests/gen4.5/not.asm
new file mode 100644 (file)
index 0000000..e245cb4
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/not.asm
@@ -0,0 +1,3 @@
+not(16)         g6<1>D          -g4<8,8,1>D                     { align1 compr };
+not(8)          g2<1>D          -g2<8,8,1>D                     { align1 };
+not(8)          g5<1>.xD        g5<4>.xD                        { align16 };

diff --git a/src/intel/tools/tests/gen4.5/not.expected b/src/intel/tools/tests/gen4.5/not.expected
new file mode 100644 (file)
index 0000000..9349818
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/not.expected
@@ -0,0 +1,3 @@
+04 20 80 00 a5 00 c0 20 80 40 8d 00 00 00 00 00
+04 00 60 00 a5 00 40 20 40 40 8d 00 00 00 00 00
+04 01 60 00 a5 00 a1 20 a0 00 60 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen4.5/or.asm b/src/intel/tools/tests/gen4.5/or.asm
new file mode 100644 (file)
index 0000000..c9a41db
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/or.asm
@@ -0,0 +1,6 @@
+or(8)           g13<1>.xUD      g13<4>.xUD      g14<4>.xUD      { align16 };
+or(8)           g3<1>UD         g3<8,8,1>UD     g5<8,8,1>UD     { align1 };
+or(16)          g12<1>UD        g14<8,8,1>UD    g20<8,8,1>UD    { align1 compr };
+(+f0.0) or(16)  g12<1>UD        g12<8,8,1>UD    0x3f800000UD    { align1 compr };
+or(8)           m2<1>.wUD       g10<4>.xUD      g11<4>.xUD      { align16 };
+(+f0.0) or(8)   g17<1>.xUD      g17<4>.xUD      0x3f800000UD    { align16 };

diff --git a/src/intel/tools/tests/gen4.5/or.expected b/src/intel/tools/tests/gen4.5/or.expected
new file mode 100644 (file)
index 0000000..b3e96ff
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/or.expected
@@ -0,0 +1,6 @@
+06 01 60 00 21 04 a1 21 a0 01 60 00 c0 01 60 00
+06 00 60 00 21 04 60 20 60 00 8d 00 a0 00 8d 00
+06 20 80 00 21 04 80 21 c0 01 8d 00 80 02 8d 00
+06 20 81 00 21 0c 80 21 80 01 8d 00 00 00 80 3f
+06 01 60 00 22 04 48 20 40 01 60 00 60 01 60 00
+06 01 61 00 21 0c 21 22 20 02 60 00 00 00 80 3f

diff --git a/src/intel/tools/tests/gen4.5/pln.asm b/src/intel/tools/tests/gen4.5/pln.asm
new file mode 100644 (file)
index 0000000..8747d5f
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/pln.asm
@@ -0,0 +1,3 @@
+pln(16)         g10<1>F         g3.4<0,1,0>F    g6<8,8,1>F      { align1 compr };
+pln(8)          g37<1>F         g4.4<0,1,0>F    g38<8,8,1>F     { align1 };
+pln(16)         m4<1>F          g5.4<0,1,0>F    g6<8,8,1>F      { align1 compr4 };

diff --git a/src/intel/tools/tests/gen4.5/pln.expected b/src/intel/tools/tests/gen4.5/pln.expected
new file mode 100644 (file)
index 0000000..495f81a
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/pln.expected
@@ -0,0 +1,3 @@
+5a 20 80 00 bd 77 40 21 70 00 00 00 c0 00 8d 00
+5a 00 60 00 bd 77 a0 24 90 00 00 00 c0 04 8d 00
+5a 20 80 00 be 77 80 30 b0 00 00 00 c0 00 8d 00

diff --git a/src/intel/tools/tests/gen4.5/rndd.asm b/src/intel/tools/tests/gen4.5/rndd.asm
new file mode 100644 (file)
index 0000000..aa02286
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/rndd.asm
@@ -0,0 +1,4 @@
+rndd(16)        g16<1>F         g24<8,8,1>F                     { align1 compr };
+rndd(8)         g6<1>.xF        g1<0>.xF                        { align16 };
+rndd(8)         g6<1>.xF        (abs)g1<0>.xF                   { align16 NoDDClr };
+rndd(8)         g6<1>.yF        g7<4>.xF                        { align16 NoDDClr,NoDDChk };

diff --git a/src/intel/tools/tests/gen4.5/rndd.expected b/src/intel/tools/tests/gen4.5/rndd.expected
new file mode 100644 (file)
index 0000000..2d59a92
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/rndd.expected
@@ -0,0 +1,4 @@
+45 20 80 00 bd 03 00 22 00 03 8d 00 00 00 00 00
+45 01 60 00 bd 03 c1 20 20 00 00 00 00 00 00 00
+45 05 60 00 bd 03 c1 20 20 20 00 00 00 00 00 00
+45 0d 60 00 bd 03 c2 20 e0 00 60 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen4.5/sel.asm b/src/intel/tools/tests/gen4.5/sel.asm
new file mode 100644 (file)
index 0000000..bda5ae6
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/sel.asm
@@ -0,0 +1,31 @@
+(+f0.0.any4h) sel(8) g7<1>UD    g9<4>UD         g8<4>UD         { align16 };
+(+f0.0) sel(8)  g10<1>.xyUD     g7<4>.xyyyUD    g3<0>.zwwwUD    { align16 };
+(+f0.0.all4h) sel(8) g6<1>UD    g6<4>UD         g7<4>UD         { align16 };
+(+f0.0) sel(16) g6<1>UD         g40<8,8,1>UD    g46<8,8,1>UD    { align1 compr };
+(+f0.0) sel(16) m3<1>UD         g30<8,8,1>UD    0x3f800000UD    { align1 compr4 };
+(+f0.0) sel(16) g10<1>F         g6<8,8,1>F      0x0F  /* 0F */  { align1 compr };
+(-f0.0) sel(16) g4<1>UD         g6<8,8,1>UD     0x00000000UD    { align1 compr };
+(+f0.0.x) sel(8) g6<1>.xUD      g6<4>.yUD       0x41a80000UD    { align16 };
+(-f0.0.x) sel(8) g6<1>.xUD      g6<4>.xUD       0x41b80000UD    { align16 };
+(+f0.0) sel(16) g4<1>F          (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
+(+f0.0) sel(16) m3<1>UD         g18<8,8,1>UD    g24<8,8,1>UD    { align1 compr4 };
+(+f0.0.x) sel(8) g10<1>.xUD     g9<4>.yUD       g9<4>.xUD       { align16 };
+(+f0.0) sel(16) g28<1>UD        g8<0,1,0>UD     0x00000000UD    { align1 compr };
+(+f0.0) sel(8)  g28<1>.yF       g32<4>.xF       0x0F  /* 0F */  { align16 };
+(-f0.0.z) sel(8) g28<1>.zUD     g31<4>.xUD      0x00000000UD    { align16 };
+(+f0.0) sel.sat(8) m5<1>F       g1<0>F          g3<4>F          { align16 };
+(-f0.0) sel(16) g8<1>F          (abs)g6<8,8,1>F 0x3f800000F  /* 1F */ { align1 compr };
+(-f0.0) sel(16) m3<1>UD         g14<8,8,1>UD    0x3f00022fUD    { align1 compr4 };
+(+f0.0) sel(16) m4<1>F          g4<8,8,1>F      g6<8,8,1>F      { align1 compr4 };
+(-f0.0.y) sel(8) g3<1>.yUD      g4<4>.xUD       0x00000000UD    { align16 };
+(+f0.0) sel(8)  g5<1>UD         g3<4>UD         0x00000000UD    { align16 };
+(+f0.0.y) sel(8) g3<1>.yUD      g1<0>.wUD       g1<0>.zUD       { align16 };
+(+f0.0) sel(8)  g5<1>.xyF       g1<0>.xyyyF     g1<0>.zF        { align16 };
+(+f0.0.x) sel(8) g5<1>.xF       g1<0>.xF        -g1<0>.xF       { align16 };
+(-f0.0) sel(8)  g5<1>.wUD       g5<4>.wUD       0x3f800000UD    { align16 };
+(-f0.0) sel(8)  g4<1>.xyzF      (abs)g4<4>.xyzzF 0x3f800000F  /* 1F */ { align16 };
+(+f0.0.x) sel(8) g4<1>.xD       -g4<4>.xD       0D              { align16 };
+(+f0.0) sel(16) g4<1>D          -g6<8,8,1>D     -1D             { align1 compr };
+(-f0.0.x) sel(8) g3<1>.xF       (abs)g3<4>.xF   0x3f800000F  /* 1F */ { align16 };
+(+f0.0) sel(16) m3<1>F          g4<8,8,1>F      0x3f800000F  /* 1F */ { align1 compr4 };
+(+f0.0) sel.sat(8) m5<1>F       g6<4>F          0xbf800000F  /* -1F */ { align16 };

diff --git a/src/intel/tools/tests/gen4.5/sel.expected b/src/intel/tools/tests/gen4.5/sel.expected
new file mode 100644 (file)
index 0000000..d64a1da
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/sel.expected
@@ -0,0 +1,31 @@
+02 01 66 00 21 04 ef 20 24 01 6e 00 04 01 6e 00
+02 01 61 00 21 04 43 21 e4 00 65 00 6e 00 0f 00
+02 01 67 00 21 04 cf 20 c4 00 6e 00 e4 00 6e 00
+02 20 81 00 21 04 c0 20 00 05 8d 00 c0 05 8d 00
+02 20 81 00 22 0c 60 30 c0 03 8d 00 00 00 80 3f
+02 20 81 00 bd 7f 40 21 c0 00 8d 00 00 00 00 00
+02 20 91 00 21 0c 80 20 c0 00 8d 00 00 00 00 00
+02 01 62 00 21 0c c1 20 c5 00 65 00 00 00 a8 41
+02 01 72 00 21 0c c1 20 c0 00 60 00 00 00 b8 41
+02 20 81 00 bd 77 80 20 00 22 8d 00 00 21 8d 00
+02 20 81 00 22 04 60 30 40 02 8d 00 00 03 8d 00
+02 01 62 00 21 04 41 21 25 01 65 00 20 01 60 00
+02 20 81 00 21 0c 80 23 00 01 00 00 00 00 00 00
+02 01 61 00 bd 7f 82 23 00 04 60 00 00 00 00 00
+02 01 74 00 21 0c 84 23 e0 03 60 00 00 00 00 00
+02 01 61 80 be 77 af 20 24 00 0e 00 64 00 6e 00
+02 20 91 00 bd 7f 00 21 c0 20 8d 00 00 00 80 3f
+02 20 91 00 22 0c 60 30 c0 01 8d 00 2f 02 00 3f
+02 20 81 00 be 77 80 30 80 00 8d 00 c0 00 8d 00
+02 01 73 00 21 0c 62 20 80 00 60 00 00 00 00 00
+02 01 61 00 21 0c af 20 64 00 6e 00 00 00 00 00
+02 01 63 00 21 04 62 20 2f 00 0f 00 2a 00 0a 00
+02 01 61 00 bd 77 a3 20 24 00 05 00 2a 00 0a 00
+02 01 62 00 bd 77 a1 20 20 00 00 00 20 40 00 00
+02 01 71 00 21 0c a8 20 af 00 6f 00 00 00 80 3f
+02 01 71 00 bd 7f 87 20 84 20 6a 00 00 00 80 3f
+02 01 62 00 a5 1c 81 20 80 40 60 00 00 00 00 00
+02 20 81 00 a5 1c 80 20 c0 40 8d 00 ff ff ff ff
+02 01 72 00 bd 7f 61 20 60 20 60 00 00 00 80 3f
+02 20 81 00 be 7f 60 30 80 00 8d 00 00 00 80 3f
+02 01 61 80 be 7f af 20 c4 00 6e 00 00 00 80 bf

diff --git a/src/intel/tools/tests/gen4.5/send.asm b/src/intel/tools/tests/gen4.5/send.asm
new file mode 100644 (file)
index 0000000..dc543f1
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/send.asm
@@ -0,0 +1,222 @@
+send(16) 2      g12<1>F         g10<8,8,1>F     0x01110001
+                            math MsgDesc: inv mlen 1 rlen 1                 { align1 compr };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 EOT };
+send(8) 1       g8<1>.wF        g6<4>.wF        0x01110001
+                            math MsgDesc: inv mlen 1 rlen 1                 { align16 };
+send(8) 1       null<1>F        g0<4>F          0x8650c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 5 rlen 0 { align16 EOT };
+send(8) 1       null<1>F        g0<4>F          0x8640c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 4 rlen 0 { align16 EOT };
+send(8) 13      g0<1>F          g0<4>F          0x053190ff
+                            write MsgDesc: OWord dual block write MsgCtrl = 0x0 Surface = 255 mlen 3 rlen 1 { align16 };
+send(8) 14      g9<1>F          g0<4>F          0x042150ff
+                            read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 255 mlen 2 rlen 1 { align16 };
+send(8) 1       null<1>F        g0<4>F          0x8680c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 8 rlen 0 { align16 EOT };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02780001
+                            sampler MsgDesc: (1, 0, 0, ) mlen 7 rlen 8      { align1 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02580001
+                            sampler MsgDesc: (1, 0, 0, ) mlen 5 rlen 8      { align1 };
+send(8) 14      g3<1>UD         g0<4>F          0x04211000
+                            read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 0 mlen 2 rlen 1 { align16 };
+send(8) 1       g6<1>.xF        g6<4>.xF        0x01110004
+                            math MsgDesc: sqrt mlen 1 rlen 1                { align16 };
+send(16) 1      g26<1>UW        g0<8,8,1>UW     0x02382001
+                            sampler MsgDesc: (1, 0, 2, ) mlen 3 rlen 8      { align1 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02983001
+                            sampler MsgDesc: (1, 0, 3, ) mlen 9 rlen 8      { align1 };
+send(8) 1       null<1>F        g0<4>F          0x06d04400
+                            urb MsgDesc: 0 urb_write interleave used mlen 13 rlen 0 { align16 };
+send(8) 1       null<1>F        g0<4>F          0x8650c460
+                            urb MsgDesc: 6 urb_write interleave used complete mlen 5 rlen 0 { align16 EOT };
+send(8) 1       null<1>F        g0<4>F          0x8660c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 6 rlen 0 { align16 EOT };
+send(8) 2       g6<1>F          g4<8,8,1>F      0x0121000a
+                            math MsgDesc: pow mlen 2 rlen 1                 { align1 };
+send(16) 1      g16<1>UW        g0<8,8,1>UW     0x02380001
+                            sampler MsgDesc: (1, 0, 0, ) mlen 3 rlen 8      { align1 };
+send(16) 2      g6<1>F          g4<8,8,1>F      0x01110007
+                            math MsgDesc: cos mlen 1 rlen 1                 { align1 compr };
+send(16) 13     g8<1>UW         g0<8,8,1>F      0x02383001
+                            sampler MsgDesc: (1, 0, 3, ) mlen 3 rlen 8      { align1 };
+send(16) 2      g4<1>F          g2.4<0,1,0>F    0x01110081
+                            math MsgDesc: inv scalar mlen 1 rlen 1          { align1 compr };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02980001
+                            sampler MsgDesc: (1, 0, 0, ) mlen 9 rlen 8      { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85e04800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 14 rlen 0 { align1 EOT };
+send(8) 1       null<1>F        g0<4>F          0x8670c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 7 rlen 0 { align16 EOT };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x85604c00
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 EOT };
+send(8) 1       null<1>F        g0<4>F          0x8680c460
+                            urb MsgDesc: 6 urb_write interleave used complete mlen 8 rlen 0 { align16 EOT };
+send(8) 1       g5<1>.yF        g6<4>.xF        0x01110006
+                            math MsgDesc: sin mlen 1 rlen 1                 { align16 };
+send(8) 1       g7<1>.xD        g1<0>.zD        0x0121001c
+                            math MsgDesc: intdiv signed mlen 2 rlen 1       { align16 };
+send(8) 1       null<1>F        g0<4>F          0x8640c460
+                            urb MsgDesc: 6 urb_write interleave used complete mlen 4 rlen 0 { align16 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85c04800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 12 rlen 0 { align1 EOT };
+send(8) 1       null<1>F        g0<4>F          0x86b0c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 11 rlen 0 { align16 EOT };
+send(16) 2      g6<1>F          g4<8,8,1>F      0x01110003
+                            math MsgDesc: exp mlen 1 rlen 1                 { align1 compr };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02983005
+                            sampler MsgDesc: (5, 0, 3, ) mlen 9 rlen 8      { align1 };
+send(16) 1      g12<1>UW        g0<8,8,1>UW     0x02983006
+                            sampler MsgDesc: (6, 0, 3, ) mlen 9 rlen 8      { align1 };
+send(16) 1      g20<1>UW        g0<8,8,1>UW     0x02983007
+                            sampler MsgDesc: (7, 0, 3, ) mlen 9 rlen 8      { align1 };
+send(16) 1      g28<1>UW        g0<8,8,1>UW     0x02983008
+                            sampler MsgDesc: (8, 0, 3, ) mlen 9 rlen 8      { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04000
+                            write MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04001
+                            write MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04002
+                            write MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04803
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 EOT };
+send(8) 2       g4<1>D          g2.4<0,1,0>D    0x0121009c
+                            math MsgDesc: intdiv signed scalar mlen 2 rlen 1 { align1 };
+send(16) 14     g8<1>UW         null<8,8,1>F    0x04120301
+                            read MsgDesc: OWord Block Read MsgCtrl = 0x3 Surface = 1 mlen 1 rlen 2 { align1 nomask };
+send(8) 1       g30<1>.xF       (abs)g30<4>.xF  0x01110005
+                            math MsgDesc: rsq mlen 1 rlen 1                 { align16 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02981001
+                            sampler MsgDesc: (1, 0, 1, ) mlen 9 rlen 8      { align1 };
+send(16) 2      g4<1>F          g2<0,1,0>F      0x01110086
+                            math MsgDesc: sin scalar mlen 1 rlen 1          { align1 compr };
+send(16) 2      g6<1>F          g2<0,1,0>F      0x01110087
+                            math MsgDesc: cos scalar mlen 1 rlen 1          { align1 compr };
+send(16) 2      g4<1>F          g2.1<0,1,0>F    0x01110085
+                            math MsgDesc: rsq scalar mlen 1 rlen 1          { align1 compr };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85f04800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 15 rlen 0 { align1 EOT };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02982001
+                            sampler MsgDesc: (1, 0, 2, ) mlen 9 rlen 8      { align1 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02580304
+                            sampler MsgDesc: (4, 3, 0, ) mlen 5 rlen 8      { align1 };
+send(8) 1       g5<1>.xF        g1<0>.xF        0x01110002
+                            math MsgDesc: log mlen 1 rlen 1                 { align16 };
+send(8) 1       g6<1>UW         g0<8,8,1>UW     0x02640001
+                            sampler MsgDesc: (1, 0, 0, ) mlen 6 rlen 4      { align1 };
+send(8) 1       g10<1>UW        g0<8,8,1>UW     0x02641001
+                            sampler MsgDesc: (1, 0, 1, ) mlen 6 rlen 4      { align1 };
+send(8) 2       g4<1>F          g2<0,1,0>F      0x012100ca
+                            math MsgDesc: pow sat scalar mlen 2 rlen 1      { align1 };
+send(16) 1      g16<1>UW        g0<8,8,1>UW     0x02982102
+                            sampler MsgDesc: (2, 1, 2, ) mlen 9 rlen 8      { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04801
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 EOT };
+send(8) 1       null<1>F        g0<4>F          0x8690c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 9 rlen 0 { align16 EOT };
+send(8) 1       null<1>F        g0<4>F          0x86c0c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 12 rlen 0 { align16 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04802
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 EOT };
+send(16) 1      g20<1>UW        g0<8,8,1>UW     0x02580102
+                            sampler MsgDesc: (2, 1, 0, ) mlen 5 rlen 8      { align1 };
+send(8) 1       null<1>F        g0<4>F          0x86a0c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 10 rlen 0 { align16 EOT };
+send(16) 2      g4<1>F          g2<0,1,0>F      0x01110082
+                            math MsgDesc: log scalar mlen 1 rlen 1          { align1 compr };
+send(16) 1      g14<1>UW        g0<8,8,1>UW     0x02382102
+                            sampler MsgDesc: (2, 1, 2, ) mlen 3 rlen 8      { align1 };
+send(16) 1      g26<1>UW        g0<8,8,1>UW     0x02382203
+                            sampler MsgDesc: (3, 2, 2, ) mlen 3 rlen 8      { align1 };
+send(16) 1      g26<1>UW        g0<8,8,1>UW     0x02580203
+                            sampler MsgDesc: (3, 2, 0, ) mlen 5 rlen 8      { align1 };
+send(16) 1      g34<1>UW        g0<8,8,1>UW     0x02382304
+                            sampler MsgDesc: (4, 3, 2, ) mlen 3 rlen 8      { align1 };
+send(16) 1      g42<1>UW        g0<8,8,1>UW     0x02382405
+                            sampler MsgDesc: (5, 4, 2, ) mlen 3 rlen 8      { align1 };
+send(16) 1      g42<1>UW        g0<8,8,1>UW     0x02580405
+                            sampler MsgDesc: (5, 4, 0, ) mlen 5 rlen 8      { align1 };
+send(16) 1      g50<1>UW        g0<8,8,1>UW     0x02382506
+                            sampler MsgDesc: (6, 5, 2, ) mlen 3 rlen 8      { align1 };
+send(16) 1      g50<1>UW        g0<8,8,1>UW     0x02580506
+                            sampler MsgDesc: (6, 5, 0, ) mlen 5 rlen 8      { align1 };
+send(16) 1      g58<1>UW        g0<8,8,1>UW     0x02382607
+                            sampler MsgDesc: (7, 6, 2, ) mlen 3 rlen 8      { align1 };
+send(16) 1      g58<1>UW        g0<8,8,1>UW     0x02580607
+                            sampler MsgDesc: (7, 6, 0, ) mlen 5 rlen 8      { align1 };
+send(16) 1      g66<1>UW        g0<8,8,1>UW     0x02382708
+                            sampler MsgDesc: (8, 7, 2, ) mlen 3 rlen 8      { align1 };
+send(16) 1      g66<1>UW        g0<8,8,1>UW     0x02580708
+                            sampler MsgDesc: (8, 7, 0, ) mlen 5 rlen 8      { align1 };
+send(8) 1       null<1>F        g0<4>F          0x86d0c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 13 rlen 0 { align16 EOT };
+send(8) 1       g10<1>UW        g0<8,8,1>UW     0x02641102
+                            sampler MsgDesc: (2, 1, 1, ) mlen 6 rlen 4      { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85b04800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 11 rlen 0 { align1 EOT };
+send(8) 2       g3<1>F          g0<4>F          0x02211505
+                            sampler MsgDesc: (5, 5, 1, ) mlen 2 rlen 1      { align16 };
+send(16) 2      g4<1>F          g2<0,1,0>F      0x011100c4
+                            math MsgDesc: sqrt sat scalar mlen 1 rlen 1     { align1 compr };
+send(16) 2      g4<1>F          g2<0,1,0>F      0x011100c3
+                            math MsgDesc: exp sat scalar mlen 1 rlen 1      { align1 compr };
+send(8) 2       g3<1>F          g0<4>F          0x02211000
+                            sampler MsgDesc: (0, 0, 1, ) mlen 2 rlen 1      { align16 };
+send(16) 13     g24<1>UW        g0<8,8,1>F      0x02383002
+                            sampler MsgDesc: (2, 0, 3, ) mlen 3 rlen 8      { align1 };
+send(8) 1       g3<1>F          g1<0>F          0x01110044
+                            math MsgDesc: sqrt sat mlen 1 rlen 1            { align16 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02983002
+                            sampler MsgDesc: (2, 0, 3, ) mlen 9 rlen 8      { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04003
+                            write MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04804
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04004
+                            write MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04805
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04005
+                            write MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04806
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04006
+                            write MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04807
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 EOT };
+send(8) 1       g8<1>UW         g0<8,8,1>UW     0x02742001
+                            sampler MsgDesc: (1, 0, 2, ) mlen 7 rlen 4      { align1 };
+send(16) 1      g12<1>UW        g0<8,8,1>UW     0x02780102
+                            sampler MsgDesc: (2, 1, 0, ) mlen 7 rlen 8      { align1 };
+send(8) 1       null<1>F        g0<4>F          0x8620c460
+                            urb MsgDesc: 6 urb_write interleave used complete mlen 2 rlen 0 { align16 EOT };
+send(16) 2      g6<1>F          g2<0,1,0>F      0x01110084
+                            math MsgDesc: sqrt scalar mlen 1 rlen 1         { align1 compr };
+send(8) 1       g3<1>F          g1<0>F          0x01110043
+                            math MsgDesc: exp sat mlen 1 rlen 1             { align16 };
+send(8) 2       g4<1>F          g2<0,1,0>F      0x0121008a
+                            math MsgDesc: pow scalar mlen 2 rlen 1          { align1 };
+send(8) 1       g8<1>UW         g0<8,8,1>UW     0x02640102
+                            sampler MsgDesc: (2, 1, 0, ) mlen 6 rlen 4      { align1 };
+send(16) 2      g4<1>F          g2<0,1,0>F      0x01110083
+                            math MsgDesc: exp scalar mlen 1 rlen 1          { align1 compr };
+send(8) 1       g8<1>UW         g0<8,8,1>UW     0x02a42001
+                            sampler MsgDesc: (1, 0, 2, ) mlen 10 rlen 4     { align1 };
+send(16) 1      g14<1>UW        g0<8,8,1>UW     0x02580003
+                            sampler MsgDesc: (3, 0, 0, ) mlen 5 rlen 8      { align1 };
+send(16) 1      g22<1>UW        g0<8,8,1>UW     0x02580004
+                            sampler MsgDesc: (4, 0, 0, ) mlen 5 rlen 8      { align1 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02580f10
+                            sampler MsgDesc: (16, 15, 0, ) mlen 5 rlen 8    { align1 };
+send(8) 2       g3<1>F          g0<4>F          0x02211303
+                            sampler MsgDesc: (3, 3, 1, ) mlen 2 rlen 1      { align16 };
+send(8) 1       g3<1>F          g1<0>F          0x0121004a
+                            math MsgDesc: pow sat mlen 2 rlen 1             { align16 };
+send(16) 1      g10<1>UW        g0<8,8,1>UW     0x02382004
+                            sampler MsgDesc: (4, 0, 2, ) mlen 3 rlen 8      { align1 };
+send(16) 1      g10<1>UW        g0<8,8,1>UW     0x02382003
+                            sampler MsgDesc: (3, 0, 2, ) mlen 3 rlen 8      { align1 };
+send(16) 1      g10<1>UW        g0<8,8,1>UW     0x02382002
+                            sampler MsgDesc: (2, 0, 2, ) mlen 3 rlen 8      { align1 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02580002
+                            sampler MsgDesc: (2, 0, 0, ) mlen 5 rlen 8      { align1 };

diff --git a/src/intel/tools/tests/gen4.5/send.expected b/src/intel/tools/tests/gen4.5/send.expected
new file mode 100644 (file)
index 0000000..4cd64a5
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/send.expected
@@ -0,0 +1,111 @@
+31 20 80 02 bd 0f 80 21 40 01 8d 00 01 00 11 01
+31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 a0 85
+31 01 60 01 bd 0f 08 21 cf 00 6f 00 01 00 11 01
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 50 86
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 40 86
+31 01 60 0d bd 0f 0f 20 04 00 6e 00 ff 90 31 05
+31 01 60 0e bd 0f 2f 21 04 00 6e 00 ff 50 21 04
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 80 86
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 00 78 02
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 00 58 02
+31 01 60 0e a1 0f 6f 20 04 00 6e 00 00 10 21 04
+31 01 60 01 bd 0f c1 20 c0 00 60 00 04 00 11 01
+31 00 80 01 29 0d 40 23 00 00 8d 00 01 20 38 02
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 30 98 02
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 44 d0 06
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 60 c4 50 86
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 60 86
+31 00 60 02 bd 0f c0 20 80 00 8d 00 0a 00 21 01
+31 00 80 01 29 0d 00 22 00 00 8d 00 01 00 38 02
+31 20 80 02 bd 0f c0 20 80 00 8d 00 07 00 11 01
+31 00 80 0d a9 0f 00 21 00 00 8d 00 01 30 38 02
+31 20 80 02 bd 0f 80 20 50 00 00 00 81 00 11 01
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 00 98 02
+31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 e0 85
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 70 86
+31 00 60 01 28 0d 00 20 00 00 8d 00 00 4c 60 85
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 60 c4 80 86
+31 01 60 01 bd 0f a2 20 c0 00 60 00 06 00 11 01
+31 01 60 01 a5 0c e1 20 2a 00 0a 00 1c 00 21 01
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 60 c4 40 86
+31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 c0 85
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 b0 86
+31 20 80 02 bd 0f c0 20 80 00 8d 00 03 00 11 01
+31 00 80 01 29 0d 80 20 00 00 8d 00 05 30 98 02
+31 00 80 01 29 0d 80 21 00 00 8d 00 06 30 98 02
+31 00 80 01 29 0d 80 22 00 00 8d 00 07 30 98 02
+31 00 80 01 29 0d 80 23 00 00 8d 00 08 30 98 02
+31 00 80 01 28 0d 00 20 00 00 8d 00 00 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 01 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 02 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 03 48 a0 85
+31 00 60 02 a5 0c 80 20 50 00 00 00 9c 00 21 01
+31 02 80 0e 89 0f 00 21 00 00 8d 00 01 03 12 04
+31 01 60 01 bd 0f c1 23 c0 23 60 00 05 00 11 01
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 10 98 02
+31 20 80 02 bd 0f 80 20 40 00 00 00 86 00 11 01
+31 20 80 02 bd 0f c0 20 40 00 00 00 87 00 11 01
+31 20 80 02 bd 0f 80 20 44 00 00 00 85 00 11 01
+31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 f0 85
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 20 98 02
+31 00 80 01 29 0d 80 20 00 00 8d 00 04 03 58 02
+31 01 60 01 bd 0f a1 20 20 00 00 00 02 00 11 01
+31 00 60 01 29 0d c0 20 00 00 8d 00 01 00 64 02
+31 00 60 01 29 0d 40 21 00 00 8d 00 01 10 64 02
+31 00 60 02 bd 0f 80 20 40 00 00 00 ca 00 21 01
+31 00 80 01 29 0d 00 22 00 00 8d 00 02 21 98 02
+31 00 80 01 28 0d 00 20 00 00 8d 00 01 48 a0 85
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 90 86
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 c0 86
+31 00 80 01 28 0d 00 20 00 00 8d 00 02 48 a0 85
+31 00 80 01 29 0d 80 22 00 00 8d 00 02 01 58 02
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 a0 86
+31 20 80 02 bd 0f 80 20 40 00 00 00 82 00 11 01
+31 00 80 01 29 0d c0 21 00 00 8d 00 02 21 38 02
+31 00 80 01 29 0d 40 23 00 00 8d 00 03 22 38 02
+31 00 80 01 29 0d 40 23 00 00 8d 00 03 02 58 02
+31 00 80 01 29 0d 40 24 00 00 8d 00 04 23 38 02
+31 00 80 01 29 0d 40 25 00 00 8d 00 05 24 38 02
+31 00 80 01 29 0d 40 25 00 00 8d 00 05 04 58 02
+31 00 80 01 29 0d 40 26 00 00 8d 00 06 25 38 02
+31 00 80 01 29 0d 40 26 00 00 8d 00 06 05 58 02
+31 00 80 01 29 0d 40 27 00 00 8d 00 07 26 38 02
+31 00 80 01 29 0d 40 27 00 00 8d 00 07 06 58 02
+31 00 80 01 29 0d 40 28 00 00 8d 00 08 27 38 02
+31 00 80 01 29 0d 40 28 00 00 8d 00 08 07 58 02
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 d0 86
+31 00 60 01 29 0d 40 21 00 00 8d 00 02 11 64 02
+31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 b0 85
+31 01 60 02 bd 0f 6f 20 04 00 6e 00 05 15 21 02
+31 20 80 02 bd 0f 80 20 40 00 00 00 c4 00 11 01
+31 20 80 02 bd 0f 80 20 40 00 00 00 c3 00 11 01
+31 01 60 02 bd 0f 6f 20 04 00 6e 00 00 10 21 02
+31 00 80 0d a9 0f 00 23 00 00 8d 00 02 30 38 02
+31 01 60 01 bd 0f 6f 20 24 00 0e 00 44 00 11 01
+31 00 80 01 29 0d 80 20 00 00 8d 00 02 30 98 02
+31 00 80 01 28 0d 00 20 00 00 8d 00 03 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 04 48 a0 85
+31 00 80 01 28 0d 00 20 00 00 8d 00 04 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 05 48 a0 85
+31 00 80 01 28 0d 00 20 00 00 8d 00 05 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 06 48 a0 85
+31 00 80 01 28 0d 00 20 00 00 8d 00 06 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 07 48 a0 85
+31 00 60 01 29 0d 00 21 00 00 8d 00 01 20 74 02
+31 00 80 01 29 0d 80 21 00 00 8d 00 02 01 78 02
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 60 c4 20 86
+31 20 80 02 bd 0f c0 20 40 00 00 00 84 00 11 01
+31 01 60 01 bd 0f 6f 20 24 00 0e 00 43 00 11 01
+31 00 60 02 bd 0f 80 20 40 00 00 00 8a 00 21 01
+31 00 60 01 29 0d 00 21 00 00 8d 00 02 01 64 02
+31 20 80 02 bd 0f 80 20 40 00 00 00 83 00 11 01
+31 00 60 01 29 0d 00 21 00 00 8d 00 01 20 a4 02
+31 00 80 01 29 0d c0 21 00 00 8d 00 03 00 58 02
+31 00 80 01 29 0d c0 22 00 00 8d 00 04 00 58 02
+31 00 80 01 29 0d 80 20 00 00 8d 00 10 0f 58 02
+31 01 60 02 bd 0f 6f 20 04 00 6e 00 03 13 21 02
+31 01 60 01 bd 0f 6f 20 24 00 0e 00 4a 00 21 01
+31 00 80 01 29 0d 40 21 00 00 8d 00 04 20 38 02
+31 00 80 01 29 0d 40 21 00 00 8d 00 03 20 38 02
+31 00 80 01 29 0d 40 21 00 00 8d 00 02 20 38 02
+31 00 80 01 29 0d 80 20 00 00 8d 00 02 00 58 02

diff --git a/src/intel/tools/tests/gen4.5/shl.asm b/src/intel/tools/tests/gen4.5/shl.asm
new file mode 100644 (file)
index 0000000..65badb5
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/shl.asm
@@ -0,0 +1,5 @@
+shl(8)          g4<1>.xD        g1<0>.yD        0x00000004UD    { align16 };
+shl(16)         g4<1>D          g2.4<0,1,0>D    0x00000004UD    { align1 compr };
+shl(16)         m14<1>D         g2<0,1,0>D      0x00000004UD    { align1 compr };
+shl(8)          g11<1>.xUD      g11<4>.xUD      4D              { align16 };
+shl(8)          g5<1>D          g3<4>D          g4<4>UD         { align16 };

diff --git a/src/intel/tools/tests/gen4.5/shl.expected b/src/intel/tools/tests/gen4.5/shl.expected
new file mode 100644 (file)
index 0000000..a46c70a
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/shl.expected
@@ -0,0 +1,5 @@
+09 01 60 00 a5 0c 81 20 25 00 05 00 04 00 00 00
+09 20 80 00 a5 0c 80 20 50 00 00 00 04 00 00 00
+09 20 80 00 a6 0c c0 21 40 00 00 00 04 00 00 00
+09 01 60 00 21 1c 61 21 60 01 60 00 04 00 00 00
+09 01 60 00 a5 04 af 20 64 00 6e 00 84 00 6e 00

diff --git a/src/intel/tools/tests/gen4.5/shr.asm b/src/intel/tools/tests/gen4.5/shr.asm
new file mode 100644 (file)
index 0000000..3900d16
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/shr.asm
@@ -0,0 +1 @@
+shr(1)          g10.4<1>UD      g10.4<0,1,0>UD  0x00000004UD    { align1 nomask };

diff --git a/src/intel/tools/tests/gen4.5/shr.expected b/src/intel/tools/tests/gen4.5/shr.expected
new file mode 100644 (file)
index 0000000..e9e16d1
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/shr.expected
@@ -0,0 +1 @@
+08 02 00 00 21 0c 50 21 50 01 00 00 04 00 00 00

diff --git a/src/intel/tools/tests/gen4.5/while.asm b/src/intel/tools/tests/gen4.5/while.asm
new file mode 100644 (file)
index 0000000..9f9645f
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/while.asm
@@ -0,0 +1,4 @@
+while(16)       Jump: -10                                       { align1 };
+while(8)        Jump: -16                                       { align16 };
+(-f0.0) while(16) Jump: -11                                     { align1 };
+(-f0.0.x) while(8) Jump: -11                                    { align16 };

diff --git a/src/intel/tools/tests/gen4.5/while.expected b/src/intel/tools/tests/gen4.5/while.expected
new file mode 100644 (file)
index 0000000..9707936
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/while.expected
@@ -0,0 +1,4 @@
+27 00 80 00 00 1c 00 34 00 14 60 00 f6 ff 00 00
+27 01 60 00 00 1c 0f 34 04 14 6e 00 f0 ff 00 00
+27 00 91 00 00 1c 00 34 00 14 60 00 f5 ff 00 00
+27 01 72 00 00 1c 0f 34 04 14 6e 00 f5 ff 00 00

diff --git a/src/intel/tools/tests/gen4.5/xor.asm b/src/intel/tools/tests/gen4.5/xor.asm
new file mode 100644 (file)
index 0000000..bcaaea8
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/xor.asm
@@ -0,0 +1,2 @@
+xor(16)         g4<1>UD         g2<0,1,0>UD     g2.1<0,1,0>UD   { align1 compr };
+xor(8)          g5<1>.xUD       g1<0>.xUD       g1<0>.yUD       { align16 };

diff --git a/src/intel/tools/tests/gen4.5/xor.expected b/src/intel/tools/tests/gen4.5/xor.expected
new file mode 100644 (file)
index 0000000..f5d2ef3
--- /dev/null
+++ b/src/intel/tools/tests/gen4.5/xor.expected
@@ -0,0 +1,2 @@
+07 20 80 00 21 04 80 20 40 00 00 00 44 00 00 00
+07 01 60 00 21 04 a1 20 20 00 00 00 25 00 05 00

diff --git a/src/intel/tools/tests/gen4/add.asm b/src/intel/tools/tests/gen4/add.asm
new file mode 100644 (file)
index 0000000..6c87d8c
--- /dev/null
+++ b/src/intel/tools/tests/gen4/add.asm
@@ -0,0 +1,48 @@
+add(16)         g10<1>UW        g1.4<2,4,0>UW   0x10101010V     { align1 };
+add(16)         g6<1>F          g10<8,8,1>UW    -g1<0,1,0>F     { align1 compr };
+add(16)         g4<1>F          g18<8,8,1>F     g6<8,8,1>F      { align1 compr };
+add(1)          m14.4<1>D       g8.4<0,1,0>D    16D             { align1 nomask };
+add(8)          g5<1>.xD        g2<4>.xD        64D             { align16 };
+add(8)          g4<1>.xD        g5<4>.xD        g4<4>.xD        { align16 };
+add(8)          g3<1>F          g3<4>F          g5<4>F          { align16 };
+add(16)         g24<1>F         g20<8,8,1>F     0x3f800000F  /* 1F */ { align1 compr };
+add(16)         g14<1>D         g14<8,8,1>D     1D              { align1 compr };
+add(8)          m5<1>.xyzF      g10<4>.xyzzF    g8<4>.xyzzF     { align16 NoDDClr };
+add.le.f0.0(16) g6<1>F          g8<8,8,1>F      g4<8,8,1>F      { align1 compr };
+add(8)          a0<1>UW         g4<16,8,2>UW    0x0040UW        { align1 };
+add(8)          a0<1>UW         g5<16,8,2>UW    0x0040UW        { align1 sechalf };
+add(8)          g3<1>.xyF       g2<4>.xyyyF     0x3f800000F  /* 1F */ { align16 };
+add(16)         m2<1>D          g6<8,8,1>D      g8.3<0,1,0>D    { align1 compr };
+add(16)         m14<1>D         g4<8,8,1>D      12D             { align1 compr };
+add.sat(16)     g6<1>F          g4<8,8,1>F      g2.1<0,1,0>F    { align1 compr };
+add(8)          g37<1>UW        g1.4<2,4,0>UW   0x10101010V     { align1 };
+add(8)          g37<1>F         g37<8,8,1>UW    -g1<0,1,0>F     { align1 };
+add(8)          g37<1>D         g2<0,1,0>D      1D              { align1 };
+add(8)          m5<1>.xF        g3<4>.xF        0x3f000000F  /* 0.5F */ { align16 };
+add(16)         g4<1>D          g2<0,1,0>D      -g2.2<0,1,0>D   { align1 compr };
+add.sat(8)      m5<1>F          g7<4>F          g8<4>F          { align16 };
+add(8)          g31<1>.xyzF     g28<4>.xyzzF    0x30300000VF /* [0F, 0F, 1F, 1F]VF */ { align16 };
+add.sat(8)      m5<1>.xyzF      g25<4>.xyzzF    g26<4>.xyzzF    { align16 NoDDClr };
+add.ge.f0.0(8)  g8<1>.xF        -g8<4>.xF       0x3f800000F  /* 1F */ { align16 };
+add(16)         g4.1<2>UW       g4.1<16,8,2>UW  g6<16,8,2>UW    { align1 compr };
+add.ge.f0.0(16) g4<1>F          -g6<8,8,1>F     0x3f800000F  /* 1F */ { align1 compr };
+add(8)          g4<1>.xyF       g4<4>.xyyyF     0xbf800000F  /* -1F */ { align16 NoDDClr };
+add(8)          m5<1>.xyzF      g4<4>.xyzzF     g2<0>.xyzzF     { align16 };
+add(16)         m2<1>F          -g16<8,8,1>F    0x3f800000F  /* 1F */ { align1 compr };
+add(8)          m5<1>.zwF       g8<4>.xxxyF     g9<4>.xxxyF     { align16 NoDDChk };
+add(8)          g4<1>.xUD       g4<4>.xUD       0x00000040UD    { align16 };
+add.sat(8)      m5<1>.yF        g1<0>.zF        0x3f000000F  /* 0.5F */ { align16 };
+add(16)         m2<1>F          g22<8,8,1>F     g2<0,1,0>F      { align1 compr };
+add(16)         m14<1>UD        g4<8,8,1>UD     0x00000110UD    { align1 compr };
+add(8)          g5<1>F          -g9<4>.xyxyF    g9<4>.zwzwF     { align16 sechalf };
+add.sat(8)      m5<1>.yF        g6<4>.xF        g7<4>.xF        { align16 NoDDClr,NoDDChk };
+add.sat(8)      m5<1>.wF        g6<4>.xF        g7<4>.xF        { align16 NoDDChk };
+add.ge.f0.0(16) g16<1>F         g18<8,8,1>F     g10<8,8,1>F     { align1 compr };
+add.sat(8)      m5<1>.yF        -g1<0>.xF       0x3f000000F  /* 0.5F */ { align16 NoDDClr };
+add.sat(8)      m5<1>.zF        g3<4>.yF        0x40000000F  /* 2F */ { align16 NoDDClr,NoDDChk };
+add.sat(8)      m5<1>.wF        g3<4>.yF        0xc0000000F  /* -2F */ { align16 NoDDChk };
+add(8)          m5<1>F          g3<4>F          0x2020a038VF /* [1.5F, -0.5F, 0.5F, 0.5F]VF */ { align16 };
+add(8)          g5<1>.zF        g4<4>.xF        0xbf800000F  /* -1F */ { align16 NoDDClr,NoDDChk };
+add(8)          m5<1>.xyF       g12<4>.xyyyF    0x3f000000F  /* 0.5F */ { align16 NoDDClr };
+add(8)          m5<1>.wF        -g3<4>.xF       0x3f800000F  /* 1F */ { align16 NoDDClr,NoDDChk };
+add(8)          g5<1>.xyF       g3<0>.xyyyF     g4<4>.xyyyF     { align16 NoDDClr };

diff --git a/src/intel/tools/tests/gen4/add.expected b/src/intel/tools/tests/gen4/add.expected
new file mode 100644 (file)
index 0000000..3a1f8ae
--- /dev/null
+++ b/src/intel/tools/tests/gen4/add.expected
@@ -0,0 +1,48 @@
+40 00 80 00 29 6d 40 21 28 00 48 00 10 10 10 10
+40 20 80 00 3d 75 c0 20 40 01 8d 00 20 40 00 00
+40 20 80 00 bd 77 80 20 40 02 8d 00 c0 00 8d 00
+40 02 00 00 a6 1c d0 21 10 01 00 00 10 00 00 00
+40 01 60 00 a5 1c a1 20 40 00 60 00 40 00 00 00
+40 01 60 00 a5 14 81 20 a0 00 60 00 80 00 60 00
+40 01 60 00 bd 77 6f 20 64 00 6e 00 a4 00 6e 00
+40 20 80 00 bd 7f 00 23 80 02 8d 00 00 00 80 3f
+40 20 80 00 a5 1c c0 21 c0 01 8d 00 01 00 00 00
+40 05 60 00 be 77 a7 20 44 01 6a 00 04 01 6a 00
+40 20 80 06 bd 77 c0 20 00 01 8d 00 80 00 8d 00
+40 00 60 00 28 2d 00 22 80 00 ae 00 40 00 40 00
+40 10 60 00 28 2d 00 22 a0 00 ae 00 40 00 40 00
+40 01 60 00 bd 7f 63 20 44 00 65 00 00 00 80 3f
+40 20 80 00 a6 14 40 20 c0 00 8d 00 0c 01 00 00
+40 20 80 00 a6 1c c0 21 80 00 8d 00 0c 00 00 00
+40 20 80 80 bd 77 c0 20 80 00 8d 00 44 00 00 00
+40 00 60 00 29 6d a0 24 28 00 48 00 10 10 10 10
+40 00 60 00 3d 75 a0 24 a0 04 8d 00 20 40 00 00
+40 00 60 00 a5 1c a0 24 40 00 00 00 01 00 00 00
+40 01 60 00 be 7f a1 20 60 00 60 00 00 00 00 3f
+40 20 80 00 a5 14 80 20 40 00 00 00 48 40 00 00
+40 01 60 80 be 77 af 20 e4 00 6e 00 04 01 6e 00
+40 01 60 00 bd 5f e7 23 84 03 6a 00 00 00 30 30
+40 05 60 80 be 77 a7 20 24 03 6a 00 44 03 6a 00
+40 01 60 04 bd 7f 01 21 00 41 60 00 00 00 80 3f
+40 20 80 00 29 25 82 40 82 00 ae 00 c0 00 ae 00
+40 20 80 04 bd 7f 80 20 c0 40 8d 00 00 00 80 3f
+40 05 60 00 bd 7f 83 20 84 00 65 00 00 00 80 bf
+40 01 60 00 be 77 a7 20 84 00 6a 00 44 00 0a 00
+40 20 80 00 be 7f 40 20 00 42 8d 00 00 00 80 3f
+40 09 60 00 be 77 ac 20 00 01 64 00 20 01 64 00
+40 01 60 00 21 0c 81 20 80 00 60 00 40 00 00 00
+40 01 60 80 be 7f a2 20 2a 00 0a 00 00 00 00 3f
+40 20 80 00 be 77 40 20 c0 02 8d 00 40 00 00 00
+40 20 80 00 22 0c c0 21 80 00 8d 00 10 01 00 00
+40 11 60 00 bd 77 af 20 24 41 64 00 2e 01 6e 00
+40 0d 60 80 be 77 a2 20 c0 00 60 00 e0 00 60 00
+40 09 60 80 be 77 a8 20 c0 00 60 00 e0 00 60 00
+40 20 80 04 bd 77 00 22 40 02 8d 00 40 01 8d 00
+40 05 60 80 be 7f a2 20 20 40 00 00 00 00 00 3f
+40 0d 60 80 be 7f a4 20 65 00 65 00 00 00 00 40
+40 09 60 80 be 7f a8 20 65 00 65 00 00 00 00 c0
+40 01 60 00 be 5f af 20 64 00 6e 00 38 a0 20 20
+40 0d 60 00 bd 7f a4 20 80 00 60 00 00 00 80 bf
+40 05 60 00 be 7f a3 20 84 01 65 00 00 00 00 3f
+40 0d 60 00 be 7f a8 20 60 40 60 00 00 00 80 3f
+40 05 60 00 bd 77 a3 20 64 00 05 00 84 00 65 00

diff --git a/src/intel/tools/tests/gen4/and.asm b/src/intel/tools/tests/gen4/and.asm
new file mode 100644 (file)
index 0000000..d04c381
--- /dev/null
+++ b/src/intel/tools/tests/gen4/and.asm
@@ -0,0 +1,17 @@
+and(8)          g9<1>.wUD       g9<4>.wUD       524032D         { align16 };
+and(16)         g4<1>D          g6<8,8,1>D      1D              { align1 compr };
+and(8)          g10<1>.xD       g10<4>.xD       1D              { align16 };
+and(16)         g6<1>UD         g10<8,8,1>UD    g8<8,8,1>UD     { align1 compr };
+and.nz.f0.0(16) null<1>D        g6<8,8,1>UD     1D              { align1 compr };
+and(16)         g4<1>D          g8<8,8,1>UD     1D              { align1 compr };
+and(8)          g2<1>D          g2<8,8,1>UD     1D              { align1 };
+and.nz.f0.0(8)  null<1>.xD      g9<4>.xUD       1D              { align16 };
+and(16)         g12<1>UD        g2.4<0,1,0>UD   0x80000000UD    { align1 compr };
+and.nz.f0.0(16) g110<1>D        g6<8,8,1>D      1D              { align1 compr };
+and(8)          g17<1>.xUD      g1<0>.xUD       0x80000000UD    { align16 };
+and.nz.f0.0(16) g6<1>D          g4<8,8,1>UD     1D              { align1 compr };
+and(1)          g12<1>UD        f0<0,1,0>UW     0x0000000fUD    { align1 nomask };
+and(8)          g5<1>.xUD       g1<0>.xUD       g1<0>.yUD       { align16 };
+and(8)          g8<1>.xD        g7<4>.xUD       1D              { align16 };
+and.nz.f0.0(8)  g6<1>.xD        g6<4>.xD        1D              { align16 };
+and.nz.f0.0(1)  null<1>UD       g1.6<0,1,0>UD   0x04000000UD    { align1 };

diff --git a/src/intel/tools/tests/gen4/and.expected b/src/intel/tools/tests/gen4/and.expected
new file mode 100644 (file)
index 0000000..0405439
--- /dev/null
+++ b/src/intel/tools/tests/gen4/and.expected
@@ -0,0 +1,17 @@
+05 01 60 00 21 1c 28 21 2f 01 6f 00 00 ff 07 00
+05 20 80 00 a5 1c 80 20 c0 00 8d 00 01 00 00 00
+05 01 60 00 a5 1c 41 21 40 01 60 00 01 00 00 00
+05 20 80 00 21 04 c0 20 40 01 8d 00 00 01 8d 00
+05 20 80 02 24 1c 00 20 c0 00 8d 00 01 00 00 00
+05 20 80 00 25 1c 80 20 00 01 8d 00 01 00 00 00
+05 00 60 00 25 1c 40 20 40 00 8d 00 01 00 00 00
+05 01 60 02 24 1c 01 20 20 01 60 00 01 00 00 00
+05 20 80 00 21 0c 80 21 50 00 00 00 00 00 00 80
+05 20 80 02 a5 1c c0 2d c0 00 8d 00 01 00 00 00
+05 01 60 00 21 0c 21 22 20 00 00 00 00 00 00 80
+05 20 80 02 25 1c c0 20 80 00 8d 00 01 00 00 00
+05 02 00 00 01 0d 80 21 00 06 00 00 0f 00 00 00
+05 01 60 00 21 04 a1 20 20 00 00 00 25 00 05 00
+05 01 60 00 25 1c 01 21 e0 00 60 00 01 00 00 00
+05 01 60 02 a5 1c c1 20 c0 00 60 00 01 00 00 00
+05 00 00 02 20 0c 00 20 38 00 00 00 00 00 00 04

diff --git a/src/intel/tools/tests/gen4/asr.asm b/src/intel/tools/tests/gen4/asr.asm
new file mode 100644 (file)
index 0000000..3fdb60d
--- /dev/null
+++ b/src/intel/tools/tests/gen4/asr.asm
@@ -0,0 +1,5 @@
+asr(16)         g4<1>D          -g1.6<0,1,0>D   31D             { align1 compr };
+asr.nz.f0.0(16) null<1>D        -g1.6<0,1,0>D   31D             { align1 compr };
+asr(8)          g4<1>D          g5<4>D          g4<4>UD         { align16 };
+asr(8)          g11<1>.xD       g5<4>.xD        0x00000002UD    { align16 };
+asr(16)         g10<1>D         g6<8,8,1>D      0x00000002UD    { align1 compr };

diff --git a/src/intel/tools/tests/gen4/asr.expected b/src/intel/tools/tests/gen4/asr.expected
new file mode 100644 (file)
index 0000000..ed23189
--- /dev/null
+++ b/src/intel/tools/tests/gen4/asr.expected
@@ -0,0 +1,5 @@
+0c 20 80 00 a5 1c 80 20 38 40 00 00 1f 00 00 00
+0c 20 80 02 a4 1c 00 20 38 40 00 00 1f 00 00 00
+0c 01 60 00 a5 04 8f 20 a4 00 6e 00 84 00 6e 00
+0c 01 60 00 a5 0c 61 21 a0 00 60 00 02 00 00 00
+0c 20 80 00 a5 0c 40 21 c0 00 8d 00 02 00 00 00

diff --git a/src/intel/tools/tests/gen4/break.asm b/src/intel/tools/tests/gen4/break.asm
new file mode 100644 (file)
index 0000000..35a5beb
--- /dev/null
+++ b/src/intel/tools/tests/gen4/break.asm
@@ -0,0 +1,5 @@
+(-f0.0) break(16) Jump: 10      Pop: 0                          { align1 };
+break(16)       Jump: 5         Pop: 1                          { align1 };
+(+f0.0) break(16) Jump: 156     Pop: 0                          { align1 };
+(+f0.0.x) break(8) Jump: 16     Pop: 0                          { align16 };
+break(8)        Jump: 6         Pop: 2                          { align16 };

diff --git a/src/intel/tools/tests/gen4/break.expected b/src/intel/tools/tests/gen4/break.expected
new file mode 100644 (file)
index 0000000..644aa5d
--- /dev/null
+++ b/src/intel/tools/tests/gen4/break.expected
@@ -0,0 +1,5 @@
+28 00 91 00 00 1c 00 34 00 14 60 00 0a 00 00 00
+28 00 80 00 00 1c 00 34 00 14 60 00 05 00 01 00
+28 00 81 00 00 1c 00 34 00 14 60 00 9c 00 00 00
+28 01 62 00 00 1c 0f 34 04 14 6e 00 10 00 00 00
+28 01 60 00 00 1c 0f 34 04 14 6e 00 06 00 02 00

diff --git a/src/intel/tools/tests/gen4/cmp.asm b/src/intel/tools/tests/gen4/cmp.asm
new file mode 100644 (file)
index 0000000..93ec966
--- /dev/null
+++ b/src/intel/tools/tests/gen4/cmp.asm
@@ -0,0 +1,80 @@
+cmp.l.f0.0(8)   null<1>F        g8<4>.wF        0x0F  /* 0F */  { align16 };
+cmp.nz.f0.0(8)  null<1>F        g3<0>.xyzzF     0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16 };
+cmp.nz.f0.0(8)  null<1>D        g7<4>.xyzzD     0D              { align16 };
+cmp.ge.f0.0(16) g6<1>F          g4<8,8,1>F      0x3189705fF  /* 4e-09F */ { align1 compr };
+cmp.l.f0.0(16)  g8<1>F          g4<8,8,1>F      0x3189705fF  /* 4e-09F */ { align1 compr };
+cmp.l.f0.0(16)  g8<1>F          g4<8,8,1>F      g6<8,8,1>F      { align1 compr };
+cmp.ge.f0.0(16) g10<1>F         g4<8,8,1>F      g6<8,8,1>F      { align1 compr };
+cmp.z.f0.0(8)   g10<1>.xD       g4<0>.xD        0D              { align16 };
+cmp.l.f0.0(8)   g7<1>.xF        g7<4>.xF        0x3189705fF  /* 4e-09F */ { align16 };
+cmp.ge.f0.0(8)  g6<1>.xF        g2<0>.xF        g6<4>.xF        { align16 };
+cmp.z.f0.0(8)   null<1>F        g3<0>.zwwwF     g3<0>.xyyyF     { align16 };
+cmp.ge.f0.0(16) null<1>D        g14<8,8,1>D     16D             { align1 compr };
+cmp.l.f0.0(16)  null<1>D        g2<0,1,0>D      1D              { align1 compr };
+cmp.z.f0.0(16)  g8<1>F          g32<8,8,1>F     g2.3<0,1,0>F    { align1 compr };
+cmp.ge.f0.0(16) null<1>F        g6<8,8,1>F      0x0F  /* 0F */  { align1 compr };
+cmp.nz.f0.0(8)  null<1>F        g12<4>.xyyyF    g1<0>.xyyyF     { align16 };
+cmp.z.f0.0(8)   null<1>D        g6<4>D          g2.4<0>D        { align16 };
+cmp.z.f0.0(16)  g6<1>D          g2.1<0,1,0>D    39D             { align1 compr };
+cmp.ge.f0.0(8)  null<1>F        g5<4>.xF        0x0F  /* 0F */  { align16 };
+cmp.le.f0.0(8)  g5<1>.xF        g5<4>.xF        0x0F  /* 0F */  { align16 };
+cmp.z.f0.0(16)  g4<1>F          g2.1<0,1,0>F    0x41000000F  /* 8F */ { align1 compr };
+cmp.z.f0.0(8)   g5<1>.xD        g5<4>.xD        g1<0>.zD        { align16 };
+cmp.l.f0.0(8)   g3<1>.xyF       g1<0>.xyyyF     g1<0>.zwwwF     { align16 };
+cmp.z.f0.0(16)  null<1>D        g2<0,1,0>D      1D              { align1 compr };
+cmp.z.f0.0(16)  null<1>F        g14<8,8,1>F     g2.1<0,1,0>F    { align1 compr };
+cmp.z.f0.0(8)   g6<1>.xF        g6<4>.xF        g3<0>.yF        { align16 };
+cmp.nz.f0.0(16) g4<1>F          g6<8,8,1>F      g2.2<0,1,0>F    { align1 compr };
+cmp.ge.f0.0(16) null<1>F        (abs)g14<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
+cmp.nz.f0.0(8)  g5<1>F          g5<8,8,1>F      g37<8,8,1>F     { align1 };
+cmp.ge.f0.0(8)  null<1>.xD      g5<4>.xD        4D              { align16 };
+cmp.nz.f0.0(16) null<1>F        g2.4<0,1,0>F    0x0F  /* 0F */  { align1 compr };
+cmp.z.f0.0(16)  null<1>F        g4.1<0,1,0>F    0x3f800000F  /* 1F */ { align1 compr };
+cmp.ge.f0.0(16) g4<1>D          g2<0,1,0>D      1D              { align1 compr };
+cmp.nz.f0.0(16) g4<1>D          g2.1<0,1,0>D    0D              { align1 compr };
+cmp.z.f0.0(16)  g8<1>D          g6<8,8,1>D      g2.5<0,1,0>D    { align1 compr };
+cmp.nz.f0.0(16) null<1>D        g2<0,1,0>D      0D              { align1 compr };
+cmp.l.f0.0(16)  null<1>F        g4<8,8,1>F      g2.5<0,1,0>F    { align1 compr };
+cmp.l.f0.0(16)  g6<1>D          g3<0,1,0>D      1D              { align1 compr };
+cmp.ge.f0.0(16) g4<1>D          g2.3<0,1,0>D    g2<0,1,0>D      { align1 compr };
+cmp.nz.f0.0(8)  g3<1>.xD        g1<0>.xD        g1<0>.yD        { align16 };
+cmp.nz.f0.0(8)  g3<1>.xyzF      g1<0>.xyzzF     g1.4<0>.xyzzF   { align16 };
+cmp.nz.f0.0(8)  null<1>F        g1<0>.xF        0x0F  /* 0F */  { align16 };
+cmp.le.f0.0(8)  g5<1>.xD        g1<0>.xD        0D              { align16 };
+cmp.l.f0.0(16)  g4<1>D          g2.1<0,1,0>D    g2<0,1,0>D      { align1 compr };
+cmp.ge.f0.0(8)  g3<1>D          g1<0>D          g1.4<0>D        { align16 };
+cmp.le.f0.0(16) null<1>F        g4<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 compr };
+cmp.le.f0.0(16) g20<1>F         g4<8,8,1>F      0x461c3f9aF  /* 9999.9F */ { align1 compr };
+cmp.z.f0.0(8)   null<1>F        g3<0>.xyzzF     0x6e6e6c6aVF /* [13F, 14F, 15F, 15F]VF */ { align16 };
+cmp.nz.f0.0(8)  null<1>D        g1<0>.xyzzD     g1.4<0>.xyzzD   { align16 };
+cmp.ge.f0.0(8)  null<1>.xD      g5<4>.xD        g3<0>.xD        { align16 };
+cmp.g.f0.0(8)   g4<1>F          g3<4>F          0x3f000000F  /* 0.5F */ { align16 };
+cmp.nz.f0.0(16) g8<1>F          g2.2<0,1,0>F    0x0F  /* 0F */  { align1 compr };
+cmp.l.f0.0(8)   null<1>F        g1<0>F          g3<4>F          { align16 };
+cmp.g.f0.0(8)   null<1>.xF      g2<4>.yF        0x0F  /* 0F */  { align16 };
+cmp.nz.f0.0(16) null<1>D        g16<8,8,1>D     g12<8,8,1>D     { align1 compr };
+cmp.l.f0.0(16)  null<1>F        g2<0,1,0>F      0x0F  /* 0F */  { align1 compr };
+cmp.z.f0.0(8)   null<1>.xD      g1<0>.xD        1D              { align16 };
+cmp.nz.f0.0(16) g6<1>D          g4<8,8,1>D      g2.2<0,1,0>D    { align1 compr };
+cmp.g.f0.0(16)  g16<1>F         (abs)g8<8,8,1>F 0x3f800000F  /* 1F */ { align1 compr };
+cmp.l.f0.0(8)   g5<1>.xD        g1<0>.yD        g1<0>.xD        { align16 };
+cmp.ge.f0.0(8)  g6<1>.xF        g3<4>.xF        0x41f00000F  /* 30F */ { align16 };
+cmp.g.f0.0(16)  null<1>D        g2.1<0,1,0>D    0D              { align1 compr };
+cmp.ge.f0.0(16) null<1>D        g4<8,8,1>D      g2.1<0,1,0>D    { align1 compr };
+cmp.le.f0.0(8)  null<1>.xF      g8<4>.xF        0x3f000000F  /* 0.5F */ { align16 };
+cmp.ge.f0.0(8)  null<1>.xF      g22<4>.xF       g10<4>.xF       { align16 };
+cmp.z.f0.0(8)   g9<1>.xF        g1<0>.xF        0x40b79581F  /* 5.737F */ { align16 };
+cmp.z.f0.0(16)  null<1>D        g6<8,8,1>D      g2<0,1,0>D      { align1 compr };
+cmp.nz.f0.0(16) null<1>F        g4<8,8,1>F      g8<8,8,1>F      { align1 compr };
+(+f0.1) cmp.z.f0.1(16) null<1>D g6<8,8,1>D      0D              { align1 compr };
+cmp.nz.f0.0(8)  g11<1>.xD       g4<4>.xD        10D             { align16 };
+cmp.nz.f0.0(8)  g3<1>F          g3<4>F          0x0F  /* 0F */  { align16 };
+cmp.le.f0.0(16) g4<1>D          g2<0,1,0>D      0D              { align1 compr };
+cmp.l.f0.0(8)   null<1>.xD      g6<4>.xD        g5<4>.xD        { align16 };
+cmp.ge.f0.0(8)  g10<1>.xD       g5<4>.xD        2D              { align16 };
+cmp.g.f0.0(8)   null<1>.xD      g3<0>.zD        4D              { align16 };
+cmp.g.f0.0(16)  null<1>F        g20<8,8,1>F     0x0F  /* 0F */  { align1 compr };
+cmp.l.f0.0(16)  null<1>D        g2<0,1,0>D      g6<8,8,1>D      { align1 compr };
+(+f0.1) cmp.nz.f0.1(16) null<1>UW g0<8,8,1>UW   g0<8,8,1>UW     { align1 };
+cmp.le.f0.0(8)  g3<1>.xUD       g1<0>.xUD       0x00000001UD    { align16 };
+cmp.g.f0.0(8)   g8<1>.xD        g1<0>.xD        2D              { align16 };

diff --git a/src/intel/tools/tests/gen4/cmp.expected b/src/intel/tools/tests/gen4/cmp.expected
new file mode 100644 (file)
index 0000000..de8d9f6
--- /dev/null
+++ b/src/intel/tools/tests/gen4/cmp.expected
@@ -0,0 +1,80 @@
+10 01 60 05 bc 7f 0f 20 0f 01 6f 00 00 00 00 00
+10 01 60 02 bc 5f 0f 20 64 00 0a 00 64 6e 74 74
+10 01 60 02 a4 1c 0f 20 e4 00 6a 00 00 00 00 00
+10 20 80 04 bd 7f c0 20 80 00 8d 00 5f 70 89 31
+10 20 80 05 bd 7f 00 21 80 00 8d 00 5f 70 89 31
+10 20 80 05 bd 77 00 21 80 00 8d 00 c0 00 8d 00
+10 20 80 04 bd 77 40 21 80 00 8d 00 c0 00 8d 00
+10 01 60 01 a5 1c 41 21 80 00 00 00 00 00 00 00
+10 01 60 05 bd 7f e1 20 e0 00 60 00 5f 70 89 31
+10 01 60 04 bd 77 c1 20 40 00 00 00 c0 00 60 00
+10 01 60 01 bc 77 0f 20 6e 00 0f 00 64 00 05 00
+10 20 80 04 a4 1c 00 20 c0 01 8d 00 10 00 00 00
+10 20 80 05 a4 1c 00 20 40 00 00 00 01 00 00 00
+10 20 80 01 bd 77 00 21 00 04 8d 00 4c 00 00 00
+10 20 80 04 bc 7f 00 20 c0 00 8d 00 00 00 00 00
+10 01 60 02 bc 77 0f 20 84 01 65 00 24 00 05 00
+10 01 60 01 a4 14 0f 20 c4 00 6e 00 54 00 0e 00
+10 20 80 01 a5 1c c0 20 44 00 00 00 27 00 00 00
+10 01 60 04 bc 7f 0f 20 a0 00 60 00 00 00 00 00
+10 01 60 06 bd 7f a1 20 a0 00 60 00 00 00 00 00
+10 20 80 01 bd 7f 80 20 44 00 00 00 00 00 00 41
+10 01 60 01 a5 14 a1 20 a0 00 60 00 2a 00 0a 00
+10 01 60 05 bd 77 63 20 24 00 05 00 2e 00 0f 00
+10 20 80 01 a4 1c 00 20 40 00 00 00 01 00 00 00
+10 20 80 01 bc 77 00 20 c0 01 8d 00 44 00 00 00
+10 01 60 01 bd 77 c1 20 c0 00 60 00 65 00 05 00
+10 20 80 02 bd 77 80 20 c0 00 8d 00 48 00 00 00
+10 20 80 04 bc 77 00 20 c0 21 8d 00 00 21 8d 00
+10 00 60 02 bd 77 a0 20 a0 00 8d 00 a0 04 8d 00
+10 01 60 04 a4 1c 01 20 a0 00 60 00 04 00 00 00
+10 20 80 02 bc 7f 00 20 50 00 00 00 00 00 00 00
+10 20 80 01 bc 7f 00 20 84 00 00 00 00 00 80 3f
+10 20 80 04 a5 1c 80 20 40 00 00 00 01 00 00 00
+10 20 80 02 a5 1c 80 20 44 00 00 00 00 00 00 00
+10 20 80 01 a5 14 00 21 c0 00 8d 00 54 00 00 00
+10 20 80 02 a4 1c 00 20 40 00 00 00 00 00 00 00
+10 20 80 05 bc 77 00 20 80 00 8d 00 54 00 00 00
+10 20 80 05 a5 1c c0 20 60 00 00 00 01 00 00 00
+10 20 80 04 a5 14 80 20 4c 00 00 00 40 00 00 00
+10 01 60 02 a5 14 61 20 20 00 00 00 25 00 05 00
+10 01 60 02 bd 77 67 20 24 00 0a 00 34 00 0a 00
+10 01 60 02 bc 7f 0f 20 20 00 00 00 00 00 00 00
+10 01 60 06 a5 1c a1 20 20 00 00 00 00 00 00 00
+10 20 80 05 a5 14 80 20 44 00 00 00 40 00 00 00
+10 01 60 04 a5 14 6f 20 24 00 0e 00 34 00 0e 00
+10 20 80 06 bc 7f 00 20 80 00 8d 00 00 00 00 3f
+10 20 80 06 bd 7f 80 22 80 00 8d 00 9a 3f 1c 46
+10 01 60 01 bc 5f 0f 20 64 00 0a 00 6a 6c 6e 6e
+10 01 60 02 a4 14 0f 20 24 00 0a 00 34 00 0a 00
+10 01 60 04 a4 14 01 20 a0 00 60 00 60 00 00 00
+10 01 60 03 bd 7f 8f 20 64 00 6e 00 00 00 00 3f
+10 20 80 02 bd 7f 00 21 48 00 00 00 00 00 00 00
+10 01 60 05 bc 77 0f 20 24 00 0e 00 64 00 6e 00
+10 01 60 03 bc 7f 01 20 45 00 65 00 00 00 00 00
+10 20 80 02 a4 14 00 20 00 02 8d 00 80 01 8d 00
+10 20 80 05 bc 7f 00 20 40 00 00 00 00 00 00 00
+10 01 60 01 a4 1c 01 20 20 00 00 00 01 00 00 00
+10 20 80 02 a5 14 c0 20 80 00 8d 00 48 00 00 00
+10 20 80 03 bd 7f 00 22 00 21 8d 00 00 00 80 3f
+10 01 60 05 a5 14 a1 20 25 00 05 00 20 00 00 00
+10 01 60 04 bd 7f c1 20 60 00 60 00 00 00 f0 41
+10 20 80 03 a4 1c 00 20 44 00 00 00 00 00 00 00
+10 20 80 04 a4 14 00 20 80 00 8d 00 44 00 00 00
+10 01 60 06 bc 7f 01 20 00 01 60 00 00 00 00 3f
+10 01 60 04 bc 77 01 20 c0 02 60 00 40 01 60 00
+10 01 60 01 bd 7f 21 21 20 00 00 00 81 95 b7 40
+10 20 80 01 a4 14 00 20 c0 00 8d 00 40 00 00 00
+10 20 80 02 bc 77 00 20 80 00 8d 00 00 01 8d 00
+10 20 81 01 a4 1c 00 20 c0 00 8d 02 00 00 00 00
+10 01 60 02 a5 1c 61 21 80 00 60 00 0a 00 00 00
+10 01 60 02 bd 7f 6f 20 64 00 6e 00 00 00 00 00
+10 20 80 06 a5 1c 80 20 40 00 00 00 00 00 00 00
+10 01 60 05 a4 14 01 20 c0 00 60 00 a0 00 60 00
+10 01 60 04 a5 1c 41 21 a0 00 60 00 02 00 00 00
+10 01 60 03 a4 1c 01 20 6a 00 0a 00 04 00 00 00
+10 20 80 03 bc 7f 00 20 80 02 8d 00 00 00 00 00
+10 20 80 05 a4 14 00 20 40 00 00 00 c0 00 8d 00
+10 00 81 02 28 25 00 20 00 00 8d 02 00 00 8d 00
+10 01 60 06 21 0c 61 20 20 00 00 00 01 00 00 00
+10 01 60 03 a5 1c 01 21 20 00 00 00 02 00 00 00

diff --git a/src/intel/tools/tests/gen4/cont.asm b/src/intel/tools/tests/gen4/cont.asm
new file mode 100644 (file)
index 0000000..a03dd98
--- /dev/null
+++ b/src/intel/tools/tests/gen4/cont.asm
@@ -0,0 +1,2 @@
+cont(16)        Jump: 4         Pop: 1                          { align1 };
+cont(8)         Jump: 4         Pop: 1                          { align16 };

diff --git a/src/intel/tools/tests/gen4/cont.expected b/src/intel/tools/tests/gen4/cont.expected
new file mode 100644 (file)
index 0000000..c40dc1c
--- /dev/null
+++ b/src/intel/tools/tests/gen4/cont.expected
@@ -0,0 +1,2 @@
+29 00 80 00 00 1c 00 34 00 14 60 00 04 00 01 00
+29 01 60 00 00 1c 0f 34 04 14 6e 00 04 00 01 00

diff --git a/src/intel/tools/tests/gen4/do.asm b/src/intel/tools/tests/gen4/do.asm
new file mode 100644 (file)
index 0000000..f0121e9
--- /dev/null
+++ b/src/intel/tools/tests/gen4/do.asm
@@ -0,0 +1,2 @@
+do(16)                                                          { align1 };
+do(8)                                                           { align16 };

diff --git a/src/intel/tools/tests/gen4/do.expected b/src/intel/tools/tests/gen4/do.expected
new file mode 100644 (file)
index 0000000..4ca58b7
--- /dev/null
+++ b/src/intel/tools/tests/gen4/do.expected
@@ -0,0 +1,2 @@
+26 00 80 00 9c 73 00 20 00 00 8d 00 00 00 8d 00
+26 01 60 00 9c 73 0f 20 04 00 6e 00 04 00 6e 00

diff --git a/src/intel/tools/tests/gen4/dp2.asm b/src/intel/tools/tests/gen4/dp2.asm
new file mode 100644 (file)
index 0000000..6411dbd
--- /dev/null
+++ b/src/intel/tools/tests/gen4/dp2.asm
@@ -0,0 +1,7 @@
+dp2(8)          g7<1>.xF        g7<4>.xyyyF     g7<4>.xyyyF     { align16 };
+dp2(8)          m5<1>.xF        g1<0>.yF        g1<0>.yF        { align16 };
+dp2(8)          m5<1>.yzF       g1<0>.xF        g1<0>.zwwwF     { align16 NoDDClr };
+dp2(8)          m5<1>.wF        g1<0>.ywwwF     g1<0>.wyyyF     { align16 NoDDChk };
+dp2(8)          g4<1>.yF        g1<0>.xyyyF     g1.4<0>.xyyyF   { align16 NoDDClr };
+dp2(8)          g4<1>.zF        g1<0>.xyyyF     g1.4<0>.zwwwF   { align16 NoDDClr,NoDDChk };
+dp2(8)          g4<1>.wF        g1<0>.xyyyF     g2<0>.xyyyF     { align16 NoDDChk };

diff --git a/src/intel/tools/tests/gen4/dp2.expected b/src/intel/tools/tests/gen4/dp2.expected
new file mode 100644 (file)
index 0000000..491895d
--- /dev/null
+++ b/src/intel/tools/tests/gen4/dp2.expected
@@ -0,0 +1,7 @@
+57 01 60 00 bd 77 e1 20 e4 00 65 00 e4 00 65 00
+57 01 60 00 be 77 a1 20 25 00 05 00 25 00 05 00
+57 05 60 00 be 77 a6 20 20 00 00 00 2e 00 0f 00
+57 09 60 00 be 77 a8 20 2d 00 0f 00 27 00 05 00
+57 05 60 00 bd 77 82 20 24 00 05 00 34 00 05 00
+57 0d 60 00 bd 77 84 20 24 00 05 00 3e 00 0f 00
+57 09 60 00 bd 77 88 20 24 00 05 00 44 00 05 00

diff --git a/src/intel/tools/tests/gen4/dp3.asm b/src/intel/tools/tests/gen4/dp3.asm
new file mode 100644 (file)
index 0000000..bdde400
--- /dev/null
+++ b/src/intel/tools/tests/gen4/dp3.asm
@@ -0,0 +1,10 @@
+dp3(8)          g5<1>.xF        g5<4>.xyzzF     g5<4>.xyzzF     { align16 };
+dp3(8)          m5<1>.xF        g3<0>.xyzzF     g6<4>.xyzzF     { align16 NoDDClr };
+dp3(8)          m5<1>.yF        g3.4<0>.xyzzF   g6<4>.xyzzF     { align16 NoDDClr,NoDDChk };
+dp3(8)          g19<1>.xF       g3<0>.xyzzF     g3.4<0>.xyzzF   { align16 NoDDClr };
+dp3(8)          g19<1>.yF       g3<0>.xyzzF     g4<0>.xyzzF     { align16 NoDDClr,NoDDChk };
+dp3(8)          g19<1>.zF       g3<0>.xyzzF     g4.4<0>.xyzzF   { align16 NoDDChk };
+dp3(8)          m5<1>.xF        g4<4>.xyzzF     g5<4>.xyzzF     { align16 };
+dp3.le.f0.0(8)  g18<1>.xF       g17<4>.xyzzF    g3.4<0>.xyzzF   { align16 };
+dp3.sat(8)      g4<1>.xF        g4<4>.xyzzF     g5<4>.xyzzF     { align16 };
+dp3.sat(8)      m5<1>F          g3<4>.xyzzF     g3<4>.xyzzF     { align16 };

diff --git a/src/intel/tools/tests/gen4/dp3.expected b/src/intel/tools/tests/gen4/dp3.expected
new file mode 100644 (file)
index 0000000..108ce15
--- /dev/null
+++ b/src/intel/tools/tests/gen4/dp3.expected
@@ -0,0 +1,10 @@
+56 01 60 00 bd 77 a1 20 a4 00 6a 00 a4 00 6a 00
+56 05 60 00 be 77 a1 20 64 00 0a 00 c4 00 6a 00
+56 0d 60 00 be 77 a2 20 74 00 0a 00 c4 00 6a 00
+56 05 60 00 bd 77 61 22 64 00 0a 00 74 00 0a 00
+56 0d 60 00 bd 77 62 22 64 00 0a 00 84 00 0a 00
+56 09 60 00 bd 77 64 22 64 00 0a 00 94 00 0a 00
+56 01 60 00 be 77 a1 20 84 00 6a 00 a4 00 6a 00
+56 01 60 06 bd 77 41 22 24 02 6a 00 74 00 0a 00
+56 01 60 80 bd 77 81 20 84 00 6a 00 a4 00 6a 00
+56 01 60 80 be 77 af 20 64 00 6a 00 64 00 6a 00

diff --git a/src/intel/tools/tests/gen4/dp4.asm b/src/intel/tools/tests/gen4/dp4.asm
new file mode 100644 (file)
index 0000000..3ea82da
--- /dev/null
+++ b/src/intel/tools/tests/gen4/dp4.asm
@@ -0,0 +1,6 @@
+dp4(8)          g6<1>.xF        g3<4>F          g1<0>F          { align16 };
+dp4(8)          g4<1>.xF        g5<4>F          g1<0>F          { align16 NoDDClr };
+dp4(8)          g4<1>.yF        g5<4>F          g1.4<0>F        { align16 NoDDClr,NoDDChk };
+dp4(8)          g4<1>.wF        g5<4>F          g2.4<0>F        { align16 NoDDChk };
+dp4(8)          m5<1>.xF        g4<4>F          g5<4>F          { align16 };
+dp4.sat(8)      m5<1>F          g3<4>.xF        g3<4>F          { align16 };

diff --git a/src/intel/tools/tests/gen4/dp4.expected b/src/intel/tools/tests/gen4/dp4.expected
new file mode 100644 (file)
index 0000000..cae5f76
--- /dev/null
+++ b/src/intel/tools/tests/gen4/dp4.expected
@@ -0,0 +1,6 @@
+54 01 60 00 bd 77 c1 20 64 00 6e 00 24 00 0e 00
+54 05 60 00 bd 77 81 20 a4 00 6e 00 24 00 0e 00
+54 0d 60 00 bd 77 82 20 a4 00 6e 00 34 00 0e 00
+54 09 60 00 bd 77 88 20 a4 00 6e 00 54 00 0e 00
+54 01 60 00 be 77 a1 20 84 00 6e 00 a4 00 6e 00
+54 01 60 80 be 77 af 20 60 00 60 00 64 00 6e 00

diff --git a/src/intel/tools/tests/gen4/dph.asm b/src/intel/tools/tests/gen4/dph.asm
new file mode 100644 (file)
index 0000000..16c9d52
--- /dev/null
+++ b/src/intel/tools/tests/gen4/dph.asm
@@ -0,0 +1,5 @@
+dph(8)          m5<1>.xF        g4<4>.xyzxF     g5<4>F          { align16 };
+dph.sat(8)      m5<1>F          g1<0>.xyzxF     g3<4>F          { align16 };
+dph(8)          g5<1>.xF        g4<4>.xyzxF     g1<0>F          { align16 NoDDClr };
+dph(8)          g5<1>.yF        g4<4>.xyzxF     g1.4<0>F        { align16 NoDDClr,NoDDChk };
+dph(8)          g6<1>.wF        g5<4>.xyzxF     g2.4<0>F        { align16 NoDDChk };

diff --git a/src/intel/tools/tests/gen4/dph.expected b/src/intel/tools/tests/gen4/dph.expected
new file mode 100644 (file)
index 0000000..aed1eae
--- /dev/null
+++ b/src/intel/tools/tests/gen4/dph.expected
@@ -0,0 +1,5 @@
+55 01 60 00 be 77 a1 20 84 00 62 00 a4 00 6e 00
+55 01 60 80 be 77 af 20 24 00 02 00 64 00 6e 00
+55 05 60 00 bd 77 a1 20 84 00 62 00 24 00 0e 00
+55 0d 60 00 bd 77 a2 20 84 00 62 00 34 00 0e 00
+55 09 60 00 bd 77 c8 20 a4 00 62 00 54 00 0e 00

diff --git a/src/intel/tools/tests/gen4/else.asm b/src/intel/tools/tests/gen4/else.asm
new file mode 100644 (file)
index 0000000..7ce3494
--- /dev/null
+++ b/src/intel/tools/tests/gen4/else.asm
@@ -0,0 +1,2 @@
+else(16)        Jump: 7         Pop: 1                          { align1 switch };
+else(8)         Jump: 3         Pop: 1                          { align16 switch };

diff --git a/src/intel/tools/tests/gen4/else.expected b/src/intel/tools/tests/gen4/else.expected
new file mode 100644 (file)
index 0000000..c56d124
--- /dev/null
+++ b/src/intel/tools/tests/gen4/else.expected
@@ -0,0 +1,2 @@
+24 80 80 00 00 1c 00 34 00 14 60 00 07 00 01 00
+24 81 60 00 00 1c 0f 34 04 14 6e 00 03 00 01 00

diff --git a/src/intel/tools/tests/gen4/endif.asm b/src/intel/tools/tests/gen4/endif.asm
new file mode 100644 (file)
index 0000000..6c71e4a
--- /dev/null
+++ b/src/intel/tools/tests/gen4/endif.asm
@@ -0,0 +1,2 @@
+endif(16)       Pop: 1                                          { align1 switch };
+endif(8)        Pop: 1                                          { align16 switch };

diff --git a/src/intel/tools/tests/gen4/endif.expected b/src/intel/tools/tests/gen4/endif.expected
new file mode 100644 (file)
index 0000000..99daf4c
--- /dev/null
+++ b/src/intel/tools/tests/gen4/endif.expected
@@ -0,0 +1,2 @@
+25 80 80 00 84 1c 00 20 00 00 8d 00 00 00 01 00
+25 81 60 00 84 1c 0f 20 04 00 6e 00 00 00 01 00

diff --git a/src/intel/tools/tests/gen4/frc.asm b/src/intel/tools/tests/gen4/frc.asm
new file mode 100644 (file)
index 0000000..4a13a53
--- /dev/null
+++ b/src/intel/tools/tests/gen4/frc.asm
@@ -0,0 +1,3 @@
+frc.sat(8)      m5<1>F          g3<4>F                          { align16 };
+frc(8)          g7<1>.xF        (abs)g1<0>.xF                   { align16 };
+frc(16)         g4<1>F          g2<0,1,0>F                      { align1 compr };

diff --git a/src/intel/tools/tests/gen4/frc.expected b/src/intel/tools/tests/gen4/frc.expected
new file mode 100644 (file)
index 0000000..52c9c7b
--- /dev/null
+++ b/src/intel/tools/tests/gen4/frc.expected
@@ -0,0 +1,3 @@
+43 01 60 80 be 03 af 20 64 00 6e 00 00 00 00 00
+43 01 60 00 bd 03 e1 20 20 20 00 00 00 00 00 00
+43 20 80 00 bd 03 80 20 40 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen4/if.asm b/src/intel/tools/tests/gen4/if.asm
new file mode 100644 (file)
index 0000000..db56aca
--- /dev/null
+++ b/src/intel/tools/tests/gen4/if.asm
@@ -0,0 +1,2 @@
+(+f0.0) if(16)  Jump: 15                                        { align1 switch };
+(+f0.0.x) if(8) Jump: 7                                         { align16 switch };

diff --git a/src/intel/tools/tests/gen4/if.expected b/src/intel/tools/tests/gen4/if.expected
new file mode 100644 (file)
index 0000000..cef4838
--- /dev/null
+++ b/src/intel/tools/tests/gen4/if.expected
@@ -0,0 +1,2 @@
+22 80 81 00 00 1c 00 34 00 14 60 00 0f 00 00 00
+22 81 62 00 00 1c 0f 34 04 14 6e 00 07 00 00 00

diff --git a/src/intel/tools/tests/gen4/iff.asm b/src/intel/tools/tests/gen4/iff.asm
new file mode 100644 (file)
index 0000000..1ff0b17
--- /dev/null
+++ b/src/intel/tools/tests/gen4/iff.asm
@@ -0,0 +1,3 @@
+(-f0.0) iff(16) Jump: 5                                         { align1 switch };
+(+f0.0.x) iff(8) Jump: 11                                       { align16 switch };
+(+f0.0) iff(16) Jump: 7                                         { align1 switch };

diff --git a/src/intel/tools/tests/gen4/iff.expected b/src/intel/tools/tests/gen4/iff.expected
new file mode 100644 (file)
index 0000000..4ed2705
--- /dev/null
+++ b/src/intel/tools/tests/gen4/iff.expected
@@ -0,0 +1,3 @@
+23 80 91 00 00 1c 00 34 00 14 60 00 05 00 00 00
+23 81 62 00 00 1c 0f 34 04 14 6e 00 0b 00 00 00
+23 80 81 00 00 1c 00 34 00 14 60 00 07 00 00 00

diff --git a/src/intel/tools/tests/gen4/jmpi.asm b/src/intel/tools/tests/gen4/jmpi.asm
new file mode 100644 (file)
index 0000000..65d0d53
--- /dev/null
+++ b/src/intel/tools/tests/gen4/jmpi.asm
@@ -0,0 +1 @@
+(+f0.0) jmpi(1) 0x00000002UD                                    { align1 nomask };

diff --git a/src/intel/tools/tests/gen4/jmpi.expected b/src/intel/tools/tests/gen4/jmpi.expected
new file mode 100644 (file)
index 0000000..682e0a7
--- /dev/null
+++ b/src/intel/tools/tests/gen4/jmpi.expected
@@ -0,0 +1 @@
+20 02 01 00 00 0c 00 34 00 14 00 00 02 00 00 00

diff --git a/src/intel/tools/tests/gen4/line.asm b/src/intel/tools/tests/gen4/line.asm
new file mode 100644 (file)
index 0000000..026d610
--- /dev/null
+++ b/src/intel/tools/tests/gen4/line.asm
@@ -0,0 +1,2 @@
+line(16)        null<1>F        g3.4<0,1,0>F    g6<8,8,1>F      { align1 compr };
+line(8)         null<1>F        g4.4<0,1,0>F    g37<8,8,1>F     { align1 };

diff --git a/src/intel/tools/tests/gen4/line.expected b/src/intel/tools/tests/gen4/line.expected
new file mode 100644 (file)
index 0000000..681b350
--- /dev/null
+++ b/src/intel/tools/tests/gen4/line.expected
@@ -0,0 +1,2 @@
+59 20 80 00 bc 77 00 20 70 00 00 00 c0 00 8d 00
+59 00 60 00 bc 77 00 20 90 00 00 00 a0 04 8d 00

diff --git a/src/intel/tools/tests/gen4/mac.asm b/src/intel/tools/tests/gen4/mac.asm
new file mode 100644 (file)
index 0000000..064198d
--- /dev/null
+++ b/src/intel/tools/tests/gen4/mac.asm
@@ -0,0 +1,3 @@
+mac(16)         g10<1>F         g3.5<0,1,0>F    g8<8,8,1>F      { align1 compr };
+mac(8)          g39<1>F         g4.5<0,1,0>F    g38<8,8,1>F     { align1 };
+mac(16)         m11<1>F         g7.1<0,1,0>F    g10<8,8,1>F     { align1 compr };

diff --git a/src/intel/tools/tests/gen4/mac.expected b/src/intel/tools/tests/gen4/mac.expected
new file mode 100644 (file)
index 0000000..45e7842
--- /dev/null
+++ b/src/intel/tools/tests/gen4/mac.expected
@@ -0,0 +1,3 @@
+48 20 80 00 bd 77 40 21 74 00 00 00 00 01 8d 00
+48 00 60 00 bd 77 e0 24 94 00 00 00 c0 04 8d 00
+48 20 80 00 be 77 60 21 e4 00 00 00 40 01 8d 00

diff --git a/src/intel/tools/tests/gen4/mach.asm b/src/intel/tools/tests/gen4/mach.asm
new file mode 100644 (file)
index 0000000..5e0ccc5
--- /dev/null
+++ b/src/intel/tools/tests/gen4/mach.asm
@@ -0,0 +1 @@
+mach(8)         null<1>D        g1<0>.xD        g1<0>.yD        { align16 };

diff --git a/src/intel/tools/tests/gen4/mach.expected b/src/intel/tools/tests/gen4/mach.expected
new file mode 100644 (file)
index 0000000..90d1371
--- /dev/null
+++ b/src/intel/tools/tests/gen4/mach.expected
@@ -0,0 +1 @@
+49 01 60 00 a4 14 0f 20 20 00 00 00 25 00 05 00

diff --git a/src/intel/tools/tests/gen4/mov.asm b/src/intel/tools/tests/gen4/mov.asm
new file mode 100644 (file)
index 0000000..f8c4ad6
--- /dev/null
+++ b/src/intel/tools/tests/gen4/mov.asm
@@ -0,0 +1,102 @@
+mov(8)          m3<1>F          g16<8,8,1>F                     { align1 };
+mov(8)          m7<1>F          g17<8,8,1>F                     { align1 sechalf };
+mov(8)          m2<1>UD         g1<8,8,1>UD                     { align1 nomask };
+mov(8)          g9<1>.xyzUD     0x00000000UD                    { align16 };
+mov.sat(8)      m5<1>F          g4<4>F                          { align16 };
+mov(8)          m4<1>F          g6<4>F                          { align16 };
+(+f0.0) mov(8)  g8<1>F          0x0F             /* 0F */       { align16 };
+mov(8)          m2<1>UD         g9<4>UD                         { align16 };
+mov(16)         g6<1>D          1065353216D                     { align1 compr };
+mov.nz.f0.0(16) null<1>D        g2<0,1,0>D                      { align1 compr };
+mov(8)          m3<1>F          0x0F             /* 0F */       { align1 };
+mov(8)          m7<1>F          0x0F             /* 0F */       { align1 sechalf };
+mov(8)          g8<1>F          0x30003000VF    /* [0F, 1F, 0F, 1F]VF */ { align16 };
+mov(8)          g7<1>.xD        0D                              { align16 };
+(+f0.0.any4h) mov(8) g7<1>.xD   -1D                             { align16 };
+mov(16)         g8<1>F          g4<8,8,1>D                      { align1 compr };
+mov(1)          m14<1>D         0D                              { align1 nomask };
+mov(8)          m15<1>D         g3<0>D                          { align16 };
+mov(1)          m14<1>D         g8<0,1,0>D                      { align1 nomask };
+mov(16)         m6<1>F          g9.3<0,1,0>F                    { align1 compr };
+mov(16)         g12<1>F         g4<8,8,1>UW                     { align1 compr };
+mov(16)         g4<1>D          g12<8,8,1>F                     { align1 compr };
+mov(8)          null<1>F        g7<8,8,1>F                      { align1 sechalf };
+mov(8)          null<1>F        g8<8,8,1>F                      { align1 };
+mov(8)          m15<1>D         g2<4>.xUD                       { align16 };
+mov(8)          g7<1>.xD        g4<0>.yD                        { align16 };
+mov(8)          g7<1>.xD        g10<4>.xD                       { align16 NoDDClr };
+mov(8)          g7<1>.yD        g4<0>.yD                        { align16 NoDDChk };
+mov(16)         m2<1>UD         0x00000000UD                    { align1 compr };
+mov(16)         m6<1>D          g9.3<0,1,0>D                    { align1 compr };
+mov(16)         m8<1>UD         0D                              { align1 compr };
+mov(16)         m2<1>D          g4<8,8,1>F                      { align1 compr };
+mov(8)          m5<1>.xF        g3<4>.xD                        { align16 NoDDClr };
+mov(8)          m5<1>.yzwD      0D                              { align16 NoDDChk };
+mov.sat(16)     g6<1>F          g2<0,1,0>F                      { align1 compr };
+mov(8)          m6<1>F          0x50484030VF    /* [1F, 2F, 3F, 4F]VF */ { align16 };
+mov(8)          m5<1>.wD        g8<4>.wD                        { align16 NoDDChk };
+mov(8)          g6<1>.xD        g6<4>.xF                        { align16 };
+mov(8)          g20<1>.yD       -1070881309D                    { align16 NoDDClr };
+mov(8)          g20<1>.zD       1091044167D                     { align16 NoDDChk };
+mov(8)          g28<1>.zD       -1102236248D                    { align16 NoDDClr,NoDDChk };
+mov(8)          g5<1>.xD        acc0<4>D                        { align16 };
+mov(8)          m13<1>.wD       1107296256D                     { align16 NoDDClr };
+mov(8)          g11<1>.yzwD     0x48403000VF    /* [0F, 1F, 2F, 3F]VF */ { align16 };
+mov(8)          m13<1>.xyzF     0x7f7e7dVF      /* [29F, 30F, 31F, 0F]VF */ { align16 NoDDChk };
+mov(8)          m3<1>UD         g4<8,8,1>UD                     { align1 };
+mov(8)          m7<1>UD         g4<8,8,1>UD                     { align1 sechalf };
+mov(8)          m6<1>.xF        0x0F             /* 0F */       { align16 };
+mov(16)         m8<1>F          0x40400000F      /* 3F */       { align1 compr };
+(+f0.0.all4h) mov(8) g3<1>.xD   -1D                             { align16 };
+mov(8)          g3<1>F          g2<0,1,0>D                      { align1 };
+mov(8)          m3<1>F          g2<8,8,1>D                      { align1 };
+mov(8)          m5<1>.yF        g3<4>.xD                        { align16 NoDDClr,NoDDChk };
+mov(8)          m5<1>.wF        g3<4>.xD                        { align16 NoDDChk };
+mov(8)          g3<1>.xF        g3<4>.xD                        { align16 NoDDClr };
+mov(8)          g3<1>.yF        g4<4>.xD                        { align16 NoDDClr,NoDDChk };
+mov(8)          g3<1>.wF        g4<4>.xD                        { align16 NoDDChk };
+mov(8)          g8<1>UD         g2<4>UD                         { align16 };
+mov(8)          g7<1>.xF        g3<0>.xD                        { align16 };
+mov(8)          g6<1>.xF        -g5<4>.yF                       { align16 NoDDClr };
+mov.nz.f0.0(16) g4<1>F          -(abs)g2<0,1,0>F                { align1 compr };
+(+f0.0) mov(16) g4<1>F          0xbf800000F      /* -1F */      { align1 compr };
+mov(16)         g24<1>D         g42<8,8,1>D                     { align1 compr };
+mov(8)          g8<1>F          g[a0]<VxH,1,0>F                 { align1 };
+mov(8)          g9<1>F          g[a0]<VxH,1,0>F                 { align1 sechalf };
+mov(8)          g3<1>.xyzF      0x0F             /* 0F */       { align16 };
+mov(8)          m3<1>D          g2<0,1,0>D                      { align1 };
+mov(8)          m3<1>D          g2<0,1,0>D                      { align1 sechalf };
+mov(1)          m14.2<1>UD      0x00000000UD                    { align1 nomask };
+mov(8)          null<1>F        g4<8,8,1>F                      { align1 nomask };
+mov(8)          g5<1>.zD        g1.4<0>.xD                      { align16 NoDDClr,NoDDChk };
+mov.sat(8)      m5<1>.wF        g20<4>.wF                       { align16 NoDDChk };
+mov(8)          g26<1>.xyzUD    0x00000000UD                    { align16 NoDDClr };
+mov(8)          m9<1>.xyD       g4<0>.yzzzD                     { align16 NoDDClr };
+mov(8)          m5<1>F          g3<4>D                          { align16 };
+mov(8)          m3<1>F          g4<8,8,1>F                      { align1 nomask };
+mov.sat(8)      m5<1>.zF        0x3eaaaaabF      /* 0.333333F */ { align16 };
+mov.sat(8)      m5<1>.wF        0x3dcccccdF      /* 0.1F */     { align16 NoDDClr };
+mov(8)          m5<1>.zD        g3<4>.zD                        { align16 NoDDClr,NoDDChk };
+mov(8)          m13<1>.yD       1107820544D                     { align16 NoDDClr,NoDDChk };
+mov.sat(8)      m5<1>F          g4<4>D                          { align16 };
+mov.sat(8)      m5<1>.wF        0x3f800000F      /* 1F */       { align16 NoDDChk };
+mov(16)         g8<1>F          g4.3<0,1,0>F                    { align1 compr };
+mov.sat(8)      m5<1>.zF        0x3f666660F      /* 0.9F */     { align16 NoDDClr,NoDDChk };
+mov(16)         g8<1>F          0x3f800000F      /* 1F */       { align1 compr };
+mov(8)          m15<1>D         0D                              { align16 };
+mov(8)          m2<1>UD         0x00000000UD                    { align16 };
+mov(8)          g2<1>.xyzF      g2<4>.wF                        { align16 };
+mov(8)          g5<1>.xyzF      0x7f7e7dVF      /* [29F, 30F, 31F, 0F]VF */ { align16 NoDDChk };
+mov.sat(8)      m5<1>.xF        g4<4>.xF                        { align16 NoDDClr };
+mov.sat(8)      m5<1>.yzF       g5<4>.xxyyF                     { align16 NoDDClr,NoDDChk };
+mov(1)          f0.1<1>UW       g0<0,1,0>UW                     { align1 nomask };
+mov(1)          g0<1>UW         f0.1<0,1,0>UW                   { align1 nomask };
+mov.sat(8)      m5<1>.xF        g5<4>.xD                        { align16 NoDDClr };
+mov.sat(8)      m5<1>.yF        g5<4>.xD                        { align16 NoDDClr,NoDDChk };
+mov.sat(8)      m5<1>.wF        g5<4>.xD                        { align16 NoDDChk };
+mov(8)          g6<1>.yzD       0xf7c000VF      /* [0F, -2F, -23F, 0F]VF */ { align16 NoDDChk };
+mov(8)          g5<1>F          g3<4>UD                         { align16 };
+mov(8)          m5<1>.xyzF      0x3000VF        /* [0F, 1F, 0F, 0F]VF */ { align16 NoDDClr };
+mov.nz.f0.0(8)  null<1>.xD      g8<4>.xD                        { align16 };
+mov.nz.f0.0(8)  g8<1>F          -(abs)g1<0>F                    { align16 };
+mov(16)         m2<1>F          g8<8,8,1>D                      { align1 compr };

diff --git a/src/intel/tools/tests/gen4/mov.expected b/src/intel/tools/tests/gen4/mov.expected
new file mode 100644 (file)
index 0000000..a0fca33
--- /dev/null
+++ b/src/intel/tools/tests/gen4/mov.expected
@@ -0,0 +1,102 @@
+01 00 60 00 be 03 60 20 00 02 8d 00 00 00 00 00
+01 10 60 00 be 03 e0 20 20 02 8d 00 00 00 00 00
+01 02 60 00 22 00 40 20 20 00 8d 00 00 00 00 00
+01 01 60 00 61 00 27 21 00 00 00 00 00 00 00 00
+01 01 60 80 be 03 af 20 84 00 6e 00 00 00 00 00
+01 01 60 00 be 03 8f 20 c4 00 6e 00 00 00 00 00
+01 01 61 00 fd 73 0f 21 00 00 00 00 00 00 00 00
+01 01 60 00 22 00 4f 20 24 01 6e 00 00 00 00 00
+01 20 80 00 e5 10 c0 20 00 00 00 00 00 00 80 3f
+01 20 80 02 a4 00 00 20 40 00 00 00 00 00 00 00
+01 00 60 00 fe 73 60 20 00 00 00 00 00 00 00 00
+01 10 60 00 fe 73 e0 20 00 00 00 00 00 00 00 00
+01 01 60 00 fd 52 0f 21 00 00 00 00 00 30 00 30
+01 01 60 00 e5 10 e1 20 00 00 00 00 00 00 00 00
+01 01 66 00 e5 10 e1 20 00 00 00 00 ff ff ff ff
+01 20 80 00 bd 00 00 21 80 00 8d 00 00 00 00 00
+01 02 00 00 e6 10 c0 21 00 00 00 00 00 00 00 00
+01 01 60 00 a6 00 ef 21 64 00 0e 00 00 00 00 00
+01 02 00 00 a6 00 c0 21 00 01 00 00 00 00 00 00
+01 20 80 00 be 03 c0 20 2c 01 00 00 00 00 00 00
+01 20 80 00 3d 01 80 21 80 00 8d 00 00 00 00 00
+01 20 80 00 a5 03 80 20 80 01 8d 00 00 00 00 00
+01 10 60 00 bc 03 00 20 e0 00 8d 00 00 00 00 00
+01 00 60 00 bc 03 00 20 00 01 8d 00 00 00 00 00
+01 01 60 00 26 00 ef 21 40 00 60 00 00 00 00 00
+01 01 60 00 a5 00 e1 20 85 00 05 00 00 00 00 00
+01 05 60 00 a5 00 e1 20 40 01 60 00 00 00 00 00
+01 09 60 00 a5 00 e2 20 85 00 05 00 00 00 00 00
+01 20 80 00 62 00 40 20 00 00 00 00 00 00 00 00
+01 20 80 00 a6 00 c0 20 2c 01 00 00 00 00 00 00
+01 20 80 00 e2 10 00 21 00 00 00 00 00 00 00 00
+01 20 80 00 a6 03 40 20 80 00 8d 00 00 00 00 00
+01 05 60 00 be 00 a1 20 60 00 60 00 00 00 00 00
+01 09 60 00 e6 10 ae 20 00 00 00 00 00 00 00 00
+01 20 80 80 bd 03 c0 20 40 00 00 00 00 00 00 00
+01 01 60 00 fe 52 cf 20 00 00 00 00 30 40 48 50
+01 09 60 00 a6 00 a8 20 0f 01 6f 00 00 00 00 00
+01 01 60 00 a5 03 c1 20 c0 00 60 00 00 00 00 00
+01 05 60 00 e5 10 82 22 00 00 00 00 e3 a5 2b c0
+01 09 60 00 e5 10 84 22 00 00 00 00 47 03 08 41
+01 0d 60 00 e5 10 84 23 00 00 00 00 a8 35 4d be
+01 01 60 00 85 00 a1 20 04 04 6e 00 00 00 00 00
+01 05 60 00 e6 10 a8 21 00 00 00 00 00 00 00 42
+01 01 60 00 e5 52 6e 21 00 00 00 00 00 30 40 48
+01 09 60 00 fe 52 a7 21 00 00 00 00 7d 7e 7f 00
+01 00 60 00 22 00 60 20 80 00 8d 00 00 00 00 00
+01 10 60 00 22 00 e0 20 80 00 8d 00 00 00 00 00
+01 01 60 00 fe 73 c1 20 00 00 00 00 00 00 00 00
+01 20 80 00 fe 73 00 21 00 00 00 00 00 00 40 40
+01 01 67 00 e5 10 61 20 00 00 00 00 ff ff ff ff
+01 00 60 00 bd 00 60 20 40 00 00 00 00 00 00 00
+01 00 60 00 be 00 60 20 40 00 8d 00 00 00 00 00
+01 0d 60 00 be 00 a2 20 60 00 60 00 00 00 00 00
+01 09 60 00 be 00 a8 20 60 00 60 00 00 00 00 00
+01 05 60 00 bd 00 61 20 60 00 60 00 00 00 00 00
+01 0d 60 00 bd 00 62 20 80 00 60 00 00 00 00 00
+01 09 60 00 bd 00 68 20 80 00 60 00 00 00 00 00
+01 01 60 00 21 00 0f 21 44 00 6e 00 00 00 00 00
+01 01 60 00 bd 00 e1 20 60 00 00 00 00 00 00 00
+01 05 60 00 bd 03 c1 20 a5 40 65 00 00 00 00 00
+01 20 80 02 bd 03 80 20 40 60 00 00 00 00 00 00
+01 20 81 00 fd 73 80 20 00 00 00 00 00 00 80 bf
+01 20 80 00 a5 00 00 23 40 05 8d 00 00 00 00 00
+01 00 60 00 bd 03 00 21 00 80 e0 01 00 00 00 00
+01 10 60 00 bd 03 20 21 00 80 e0 01 00 00 00 00
+01 01 60 00 fd 73 67 20 00 00 00 00 00 00 00 00
+01 00 60 00 a6 00 60 20 40 00 00 00 00 00 00 00
+01 10 60 00 a6 00 60 20 40 00 00 00 00 00 00 00
+01 02 00 00 62 00 c8 21 00 00 00 00 00 00 00 00
+01 02 60 00 bc 03 00 20 80 00 8d 00 00 00 00 00
+01 0d 60 00 a5 00 a4 20 30 00 00 00 00 00 00 00
+01 09 60 80 be 03 a8 20 8f 02 6f 00 00 00 00 00
+01 05 60 00 61 00 47 23 00 00 00 00 00 00 00 00
+01 05 60 00 a6 00 23 21 89 00 0a 00 00 00 00 00
+01 01 60 00 be 00 af 20 64 00 6e 00 00 00 00 00
+01 02 60 00 be 03 60 20 80 00 8d 00 00 00 00 00
+01 01 60 80 fe 73 a4 20 00 00 00 00 ab aa aa 3e
+01 05 60 80 fe 73 a8 20 00 00 00 00 cd cc cc 3d
+01 0d 60 00 a6 00 a4 20 6a 00 6a 00 00 00 00 00
+01 0d 60 00 e6 10 a2 21 00 00 00 00 00 00 08 42
+01 01 60 80 be 00 af 20 84 00 6e 00 00 00 00 00
+01 09 60 80 fe 73 a8 20 00 00 00 00 00 00 80 3f
+01 20 80 00 bd 03 00 21 8c 00 00 00 00 00 00 00
+01 0d 60 80 fe 73 a4 20 00 00 00 00 60 66 66 3f
+01 20 80 00 fd 73 00 21 00 00 00 00 00 00 80 3f
+01 01 60 00 e6 10 ef 21 00 00 00 00 00 00 00 00
+01 01 60 00 62 00 4f 20 00 00 00 00 00 00 00 00
+01 01 60 00 bd 03 47 20 4f 00 6f 00 00 00 00 00
+01 09 60 00 fd 52 a7 20 00 00 00 00 7d 7e 7f 00
+01 05 60 80 be 03 a1 20 80 00 60 00 00 00 00 00
+01 0d 60 80 be 03 a6 20 a0 00 65 00 00 00 00 00
+01 02 00 00 28 01 02 26 00 00 00 00 00 00 00 00
+01 02 00 00 09 01 00 20 02 06 00 00 00 00 00 00
+01 05 60 80 be 00 a1 20 a0 00 60 00 00 00 00 00
+01 0d 60 80 be 00 a2 20 a0 00 60 00 00 00 00 00
+01 09 60 80 be 00 a8 20 a0 00 60 00 00 00 00 00
+01 09 60 00 e5 52 c6 20 00 00 00 00 00 c0 f7 00
+01 01 60 00 3d 00 af 20 64 00 6e 00 00 00 00 00
+01 05 60 00 fe 52 a7 20 00 00 00 00 00 30 00 00
+01 01 60 02 a4 00 01 20 00 01 60 00 00 00 00 00
+01 01 60 02 bd 03 0f 21 24 60 0e 00 00 00 00 00
+01 20 80 00 be 00 40 20 00 01 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen4/mul.asm b/src/intel/tools/tests/gen4/mul.asm
new file mode 100644 (file)
index 0000000..82629fa
--- /dev/null
+++ b/src/intel/tools/tests/gen4/mul.asm
@@ -0,0 +1,37 @@
+mul(16)         g16<1>F         g14<8,8,1>F     g12<8,8,1>F     { align1 compr };
+mul(8)          g8<1>.xyzF      g6<4>.xyzzF     g8<4>.wF        { align16 };
+mul(8)          g9<1>.wUD       g7<4>.wF        0x45000000F  /* 2048F */ { align16 };
+mul(8)          g8<1>.xD        g8<4>.xD        g5<0>.xD        { align16 };
+mul(8)          g8<1>.xD        g8<4>.xD        32D             { align16 };
+mul(16)         m2<1>F          g4<8,8,1>F      g8.3<0,1,0>F    { align1 compr };
+mul(16)         g22<1>F         g16<8,8,1>F     0x41800000F  /* 16F */ { align1 compr };
+mul(8)          m5<1>.xyF       g3<4>.xyyyF     0x3f000000F  /* 0.5F */ { align16 NoDDClr };
+mul(8)          g5<1>F          g3<4>F          0x37800000F  /* 1.52588e-05F */ { align16 };
+mul.sat(16)     m2<1>F          g16<8,8,1>F     g6<8,8,1>F      { align1 compr };
+mul(8)          acc0<1>D        g1<0>.xD        g1<0>.yD        { align16 };
+mul(8)          m5<1>F          g3<4>F          0x3f000000F  /* 0.5F */ { align16 };
+mul(16)         g4<1>D          g6<8,8,1>D      g2<0,1,0>D      { align1 compr };
+mul.sat(16)     g18<1>F         g16<8,8,1>F     g14<8,8,1>F     { align1 compr };
+mul(8)          g4<1>F          g4<8,8,1>F      g55<8,8,1>F     { align1 };
+mul(8)          g26<1>.wUD      g29<4>.wF       0x45000000F  /* 2048F */ { align16 NoDDChk };
+mul(8)          g2<1>.xyzF      g2<4>.wF        0x40404830VF /* [1F, 3F, 2F, 2F]VF */ { align16 };
+mul(16)         g4<1>D          g2<0,1,0>UW     g2.2<0,1,0>D    { align1 compr };
+mul(16)         m8<1>F          g24<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 compr };
+mul.sat(8)      g6<1>.xyzF      g6<4>.xyzzF     g7<4>.xF        { align16 };
+mul.sat(8)      m5<1>F          g6<4>F          0x3b800000F  /* 0.00390625F */ { align16 };
+mul.sat(8)      m5<1>.xyzF      g3<4>.xyzzF     0x3f000000F  /* 0.5F */ { align16 NoDDClr };
+mul.g.f0.0(16)  null<1>F        g18<8,8,1>F     g12<8,8,1>F     { align1 compr };
+mul.sat(8)      m5<1>F          g3<4>F          g3<4>F          { align16 };
+mul.l.f0.0(8)   null<1>.xF      g1<0>.zF        g1<0>.yF        { align16 };
+mul.l.f0.0(16)  null<1>F        g2.2<0,1,0>F    g2.1<0,1,0>F    { align1 compr };
+mul.l.f0.0(16)  g16<1>F         g14<8,8,1>F     g12<8,8,1>F     { align1 compr };
+mul.nz.f0.0(16) g18<1>F         g16<8,8,1>F     g12<8,8,1>F     { align1 compr };
+mul.sat(8)      m6<1>.xyzF      g32<4>.xF       g30<4>.xyzzF    { align16 NoDDClr };
+mul.nz.f0.0(16) g6<1>F          g4<8,8,1>F      0x3f808000F  /* 1.00391F */ { align1 compr };
+mul.sat(8)      m5<1>F          g4<4>F          0x20303030VF /* [1F, 1F, 1F, 0.5F]VF */ { align16 };
+mul(8)          m5<1>F          g3<4>F          0x20305454VF /* [5F, 5F, 1F, 0.5F]VF */ { align16 };
+mul(8)          m6<1>.xyzF      g12<4>.xyzzF    g13<4>.xF       { align16 NoDDClr };
+mul(8)          m5<1>.xyzF      g3<4>.xyzzF     0x30302020VF /* [0.5F, 0.5F, 1F, 1F]VF */ { align16 NoDDClr };
+mul(8)          m5<1>.zF        g3<4>.zF        0x3f000000F  /* 0.5F */ { align16 NoDDClr,NoDDChk };
+mul(8)          m5<1>F          g3<4>F          g1<0>.xF        { align16 };
+mul.sat(8)      m5<1>.xyzF      g7<4>.xF        0x3030VF /* [1F, 1F, 0F, 0F]VF */ { align16 NoDDClr };

diff --git a/src/intel/tools/tests/gen4/mul.expected b/src/intel/tools/tests/gen4/mul.expected
new file mode 100644 (file)
index 0000000..c67cda0
--- /dev/null
+++ b/src/intel/tools/tests/gen4/mul.expected
@@ -0,0 +1,37 @@
+41 20 80 00 bd 77 00 22 c0 01 8d 00 80 01 8d 00
+41 01 60 00 bd 77 07 21 c4 00 6a 00 0f 01 6f 00
+41 01 60 00 a1 7f 28 21 ef 00 6f 00 00 00 00 45
+41 01 60 00 a5 14 01 21 00 01 60 00 a0 00 00 00
+41 01 60 00 a5 1c 01 21 00 01 60 00 20 00 00 00
+41 20 80 00 be 77 40 20 80 00 8d 00 0c 01 00 00
+41 20 80 00 bd 7f c0 22 00 02 8d 00 00 00 80 41
+41 05 60 00 be 7f a3 20 64 00 65 00 00 00 00 3f
+41 01 60 00 bd 7f af 20 64 00 6e 00 00 00 80 37
+41 20 80 80 be 77 40 20 00 02 8d 00 c0 00 8d 00
+41 01 60 00 a4 14 0f 24 20 00 00 00 25 00 05 00
+41 01 60 00 be 7f af 20 64 00 6e 00 00 00 00 3f
+41 20 80 00 a5 14 80 20 c0 00 8d 00 40 00 00 00
+41 20 80 80 bd 77 40 22 00 02 8d 00 c0 01 8d 00
+41 00 60 00 bd 77 80 20 80 00 8d 00 e0 06 8d 00
+41 09 60 00 a1 7f 48 23 af 03 6f 00 00 00 00 45
+41 01 60 00 bd 5f 47 20 4f 00 6f 00 30 48 40 40
+41 20 80 00 25 15 80 20 40 00 00 00 48 00 00 00
+41 20 80 00 be 7f 00 21 00 03 8d 00 00 00 00 3f
+41 01 60 80 bd 77 c7 20 c4 00 6a 00 e0 00 60 00
+41 01 60 80 be 7f af 20 c4 00 6e 00 00 00 80 3b
+41 05 60 80 be 7f a7 20 64 00 6a 00 00 00 00 3f
+41 20 80 03 bc 77 00 20 40 02 8d 00 80 01 8d 00
+41 01 60 80 be 77 af 20 64 00 6e 00 64 00 6e 00
+41 01 60 05 bc 77 01 20 2a 00 0a 00 25 00 05 00
+41 20 80 05 bc 77 00 20 48 00 00 00 44 00 00 00
+41 20 80 05 bd 77 00 22 c0 01 8d 00 80 01 8d 00
+41 20 80 02 bd 77 40 22 00 02 8d 00 80 01 8d 00
+41 05 60 80 be 77 c7 20 00 04 60 00 c4 03 6a 00
+41 20 80 02 bd 7f c0 20 80 00 8d 00 00 80 80 3f
+41 01 60 80 be 5f af 20 84 00 6e 00 30 30 30 20
+41 01 60 00 be 5f af 20 64 00 6e 00 54 54 30 20
+41 05 60 00 be 77 c7 20 84 01 6a 00 a0 01 60 00
+41 05 60 00 be 5f a7 20 64 00 6a 00 20 20 30 30
+41 0d 60 00 be 7f a4 20 6a 00 6a 00 00 00 00 3f
+41 01 60 00 be 77 af 20 64 00 6e 00 20 00 00 00
+41 05 60 80 be 5f a7 20 e0 00 60 00 30 30 00 00

diff --git a/src/intel/tools/tests/gen4/not.asm b/src/intel/tools/tests/gen4/not.asm
new file mode 100644 (file)
index 0000000..e245cb4
--- /dev/null
+++ b/src/intel/tools/tests/gen4/not.asm
@@ -0,0 +1,3 @@
+not(16)         g6<1>D          -g4<8,8,1>D                     { align1 compr };
+not(8)          g2<1>D          -g2<8,8,1>D                     { align1 };
+not(8)          g5<1>.xD        g5<4>.xD                        { align16 };

diff --git a/src/intel/tools/tests/gen4/not.expected b/src/intel/tools/tests/gen4/not.expected
new file mode 100644 (file)
index 0000000..9349818
--- /dev/null
+++ b/src/intel/tools/tests/gen4/not.expected
@@ -0,0 +1,3 @@
+04 20 80 00 a5 00 c0 20 80 40 8d 00 00 00 00 00
+04 00 60 00 a5 00 40 20 40 40 8d 00 00 00 00 00
+04 01 60 00 a5 00 a1 20 a0 00 60 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen4/or.asm b/src/intel/tools/tests/gen4/or.asm
new file mode 100644 (file)
index 0000000..48ecdd9
--- /dev/null
+++ b/src/intel/tools/tests/gen4/or.asm
@@ -0,0 +1,6 @@
+(+f0.0) or(8)   g9<1>.wUD       g9<4>.wUD       0x00000040UD    { align16 };
+or(8)           g13<1>.xUD      g13<4>.xUD      g14<4>.xUD      { align16 };
+or(8)           g3<1>UD         g3<8,8,1>UD     g5<8,8,1>UD     { align1 };
+or(16)          g12<1>UD        g14<8,8,1>UD    g20<8,8,1>UD    { align1 compr };
+(+f0.0) or(16)  g12<1>UD        g12<8,8,1>UD    0x3f800000UD    { align1 compr };
+or(8)           g8<1>.wUD       g11<4>.xUD      g12<4>.xUD      { align16 NoDDChk };

diff --git a/src/intel/tools/tests/gen4/or.expected b/src/intel/tools/tests/gen4/or.expected
new file mode 100644 (file)
index 0000000..62758bf
--- /dev/null
+++ b/src/intel/tools/tests/gen4/or.expected
@@ -0,0 +1,6 @@
+06 01 61 00 21 0c 28 21 2f 01 6f 00 40 00 00 00
+06 01 60 00 21 04 a1 21 a0 01 60 00 c0 01 60 00
+06 00 60 00 21 04 60 20 60 00 8d 00 a0 00 8d 00
+06 20 80 00 21 04 80 21 c0 01 8d 00 80 02 8d 00
+06 20 81 00 21 0c 80 21 80 01 8d 00 00 00 80 3f
+06 09 60 00 21 04 08 21 60 01 60 00 80 01 60 00

diff --git a/src/intel/tools/tests/gen4/rndd.asm b/src/intel/tools/tests/gen4/rndd.asm
new file mode 100644 (file)
index 0000000..bdacb26
--- /dev/null
+++ b/src/intel/tools/tests/gen4/rndd.asm
@@ -0,0 +1,5 @@
+rndd(16)        g16<1>F         g26<8,8,1>F                     { align1 compr };
+rndd(8)         g6<1>.xF        g1<0>.xF                        { align16 };
+rndd(8)         g6<1>.xF        (abs)g1<0>.xF                   { align16 NoDDClr };
+rndd(8)         g6<1>.yF        g7<4>.xF                        { align16 NoDDClr,NoDDChk };
+rndd.sat(8)     m5<1>F          g4<4>F                          { align16 };

diff --git a/src/intel/tools/tests/gen4/rndd.expected b/src/intel/tools/tests/gen4/rndd.expected
new file mode 100644 (file)
index 0000000..8cd4c86
--- /dev/null
+++ b/src/intel/tools/tests/gen4/rndd.expected
@@ -0,0 +1,5 @@
+45 20 80 00 bd 03 00 22 40 03 8d 00 00 00 00 00
+45 01 60 00 bd 03 c1 20 20 00 00 00 00 00 00 00
+45 05 60 00 bd 03 c1 20 20 20 00 00 00 00 00 00
+45 0d 60 00 bd 03 c2 20 e0 00 60 00 00 00 00 00
+45 01 60 80 be 03 af 20 84 00 6e 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen4/sel.asm b/src/intel/tools/tests/gen4/sel.asm
new file mode 100644 (file)
index 0000000..2461334
--- /dev/null
+++ b/src/intel/tools/tests/gen4/sel.asm
@@ -0,0 +1,27 @@
+(+f0.0.any4h) sel(8) g7<1>UD    g9<4>UD         g8<4>UD         { align16 };
+(+f0.0) sel(8)  g10<1>.xyUD     g7<4>.xyyyUD    g3<0>.zwwwUD    { align16 };
+(+f0.0.all4h) sel(8) g6<1>UD    g6<4>UD         g7<4>UD         { align16 };
+(+f0.0) sel(16) g6<1>UD         g40<8,8,1>UD    g46<8,8,1>UD    { align1 compr };
+(+f0.0) sel(16) g6<1>UD         g30<8,8,1>UD    0x3f800000UD    { align1 compr };
+(+f0.0) sel(16) g10<1>F         g6<8,8,1>F      0x0F  /* 0F */  { align1 compr };
+(-f0.0) sel(16) g4<1>UD         g6<8,8,1>UD     0x00000000UD    { align1 compr };
+(+f0.0) sel(8)  g4<1>.yF        g5<4>.xF        0x0F  /* 0F */  { align16 };
+(-f0.0.z) sel(8) g4<1>.zUD      g6<4>.xUD       0x00000000UD    { align16 };
+(+f0.0.x) sel(8) g6<1>.xUD      g6<4>.yUD       0x41a80000UD    { align16 };
+(-f0.0.x) sel(8) g6<1>.xUD      g6<4>.xUD       0x41b80000UD    { align16 };
+(+f0.0) sel(16) g4<1>F          (abs)g14<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
+(+f0.0.x) sel(8) g10<1>.xUD     g9<4>.yUD       g9<4>.xUD       { align16 };
+(+f0.0) sel.sat(8) m5<1>F       g3<4>F          0x3f000000F  /* 0.5F */ { align16 };
+(+f0.0) sel(16) m11<1>UD        g6<8,8,1>UD     0x3f000000UD    { align1 compr };
+(+f0.0) sel.sat(8) m5<1>F       g1<0>F          g3<4>F          { align16 };
+(-f0.0) sel(16) g8<1>F          (abs)g6<8,8,1>F 0x3f800000F  /* 1F */ { align1 compr };
+(-f0.0.y) sel(8) g3<1>.yUD      g4<4>.xUD       0x00000000UD    { align16 };
+(+f0.0) sel(8)  g5<1>UD         g3<4>UD         0x00000000UD    { align16 };
+(+f0.0.y) sel(8) g3<1>.yUD      g1<0>.wUD       g1<0>.zUD       { align16 };
+(+f0.0) sel(8)  g5<1>.xyF       g1<0>.xyyyF     g1<0>.zF        { align16 };
+(+f0.0.x) sel(8) g5<1>.xF       g1<0>.xF        -g1<0>.xF       { align16 };
+(-f0.0) sel(8)  g5<1>.wUD       g5<4>.wUD       0x3f800000UD    { align16 };
+(-f0.0) sel(8)  g4<1>.xyzF      (abs)g4<4>.xyzzF 0x3f800000F  /* 1F */ { align16 };
+(+f0.0.x) sel(8) g4<1>.xD       -g4<4>.xD       0D              { align16 };
+(+f0.0) sel(16) g4<1>D          -g6<8,8,1>D     -1D             { align1 compr };
+(-f0.0.x) sel(8) g3<1>.xF       (abs)g3<4>.xF   0x3f800000F  /* 1F */ { align16 };

diff --git a/src/intel/tools/tests/gen4/sel.expected b/src/intel/tools/tests/gen4/sel.expected
new file mode 100644 (file)
index 0000000..606b085
--- /dev/null
+++ b/src/intel/tools/tests/gen4/sel.expected
@@ -0,0 +1,27 @@
+02 01 66 00 21 04 ef 20 24 01 6e 00 04 01 6e 00
+02 01 61 00 21 04 43 21 e4 00 65 00 6e 00 0f 00
+02 01 67 00 21 04 cf 20 c4 00 6e 00 e4 00 6e 00
+02 20 81 00 21 04 c0 20 00 05 8d 00 c0 05 8d 00
+02 20 81 00 21 0c c0 20 c0 03 8d 00 00 00 80 3f
+02 20 81 00 bd 7f 40 21 c0 00 8d 00 00 00 00 00
+02 20 91 00 21 0c 80 20 c0 00 8d 00 00 00 00 00
+02 01 61 00 bd 7f 82 20 a0 00 60 00 00 00 00 00
+02 01 74 00 21 0c 84 20 c0 00 60 00 00 00 00 00
+02 01 62 00 21 0c c1 20 c5 00 65 00 00 00 a8 41
+02 01 72 00 21 0c c1 20 c0 00 60 00 00 00 b8 41
+02 20 81 00 bd 77 80 20 c0 21 8d 00 00 21 8d 00
+02 01 62 00 21 04 41 21 25 01 65 00 20 01 60 00
+02 01 61 80 be 7f af 20 64 00 6e 00 00 00 00 3f
+02 20 81 00 22 0c 60 21 c0 00 8d 00 00 00 00 3f
+02 01 61 80 be 77 af 20 24 00 0e 00 64 00 6e 00
+02 20 91 00 bd 7f 00 21 c0 20 8d 00 00 00 80 3f
+02 01 73 00 21 0c 62 20 80 00 60 00 00 00 00 00
+02 01 61 00 21 0c af 20 64 00 6e 00 00 00 00 00
+02 01 63 00 21 04 62 20 2f 00 0f 00 2a 00 0a 00
+02 01 61 00 bd 77 a3 20 24 00 05 00 2a 00 0a 00
+02 01 62 00 bd 77 a1 20 20 00 00 00 20 40 00 00
+02 01 71 00 21 0c a8 20 af 00 6f 00 00 00 80 3f
+02 01 71 00 bd 7f 87 20 84 20 6a 00 00 00 80 3f
+02 01 62 00 a5 1c 81 20 80 40 60 00 00 00 00 00
+02 20 81 00 a5 1c 80 20 c0 40 8d 00 ff ff ff ff
+02 01 72 00 bd 7f 61 20 60 20 60 00 00 00 80 3f

diff --git a/src/intel/tools/tests/gen4/send.asm b/src/intel/tools/tests/gen4/send.asm
new file mode 100644 (file)
index 0000000..2731d03
--- /dev/null
+++ b/src/intel/tools/tests/gen4/send.asm
@@ -0,0 +1,214 @@
+send(8) 2       g12<1>F         g10<8,8,1>F     0x01110001
+                            math MsgDesc: inv mlen 1 rlen 1                 { align1 };
+send(8) 2       g13<1>F         g11<8,8,1>F     0x01110001
+                            math MsgDesc: inv mlen 1 rlen 1                 { align1 sechalf };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 EOT };
+send(8) 1       null<1>F        g0<4>F          0x8650c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 5 rlen 0 { align16 EOT };
+send(8) 1       null<1>F        g0<4>F          0x8640c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 4 rlen 0 { align16 EOT };
+send(8) 13      g0<1>F          g0<4>F          0x053190ff
+                            write MsgDesc: OWord dual block write MsgCtrl = 0x0 Surface = 255 mlen 3 rlen 1 { align16 };
+send(8) 14      g10<1>F         g0<4>F          0x042150ff
+                            read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 255 mlen 2 rlen 1 { align16 };
+send(8) 1       null<1>F        g0<4>F          0x8680c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 8 rlen 0 { align16 EOT };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02780001
+                            sampler MsgDesc: (1, 0, 0, F) mlen 7 rlen 8     { align1 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02580001
+                            sampler MsgDesc: (1, 0, 0, F) mlen 5 rlen 8     { align1 };
+send(8) 14      g3<1>UD         g0<4>F          0x04211000
+                            read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 0 mlen 2 rlen 1 { align16 };
+send(8) 1       g6<1>.xF        g6<4>.xF        0x01110004
+                            math MsgDesc: sqrt mlen 1 rlen 1                { align16 };
+send(16) 1      g26<1>UW        g0<8,8,1>UW     0x0238a001
+                            sampler MsgDesc: (1, 0, 2, UD) mlen 3 rlen 8    { align1 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x0298c001
+                            sampler MsgDesc: (1, 0, 3, F) mlen 9 rlen 8     { align1 };
+send(8) 1       null<1>F        g0<4>F          0x06d04400
+                            urb MsgDesc: 0 urb_write interleave used mlen 13 rlen 0 { align16 };
+send(8) 1       null<1>F        g0<4>F          0x8650c460
+                            urb MsgDesc: 6 urb_write interleave used complete mlen 5 rlen 0 { align16 EOT };
+send(8) 1       null<1>F        g0<4>F          0x8660c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 6 rlen 0 { align16 EOT };
+send(8) 2       g6<1>F          g4<8,8,1>F      0x0121000a
+                            math MsgDesc: pow mlen 2 rlen 1                 { align1 };
+send(16) 1      g16<1>UW        g0<8,8,1>UW     0x02380001
+                            sampler MsgDesc: (1, 0, 0, F) mlen 3 rlen 8     { align1 };
+send(8) 2       g6<1>F          g4<8,8,1>F      0x01110007
+                            math MsgDesc: cos mlen 1 rlen 1                 { align1 };
+send(16) 13     g8<1>UW         g0<8,8,1>F      0x0238c001
+                            sampler MsgDesc: (1, 0, 3, F) mlen 3 rlen 8     { align1 };
+send(8) 2       g4<1>F          g2.4<0,1,0>F    0x01110081
+                            math MsgDesc: inv scalar mlen 1 rlen 1          { align1 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02980001
+                            sampler MsgDesc: (1, 0, 0, F) mlen 9 rlen 8     { align1 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x0298e001
+                            sampler MsgDesc: (1, 0, 3, UD) mlen 9 rlen 8    { align1 };
+send(8) 1       null<1>F        g0<4>F          0x8670c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 7 rlen 0 { align16 EOT };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x85604c00
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 EOT };
+send(8) 1       null<1>F        g0<4>F          0x8680c460
+                            urb MsgDesc: 6 urb_write interleave used complete mlen 8 rlen 0 { align16 EOT };
+send(8) 1       g5<1>.yF        g6<4>.xF        0x01110006
+                            math MsgDesc: sin mlen 1 rlen 1                 { align16 };
+send(8) 1       g7<1>.xD        g1<0>.zD        0x0121001c
+                            math MsgDesc: intdiv signed mlen 2 rlen 1       { align16 };
+send(8) 1       null<1>F        g0<4>F          0x8640c460
+                            urb MsgDesc: 6 urb_write interleave used complete mlen 4 rlen 0 { align16 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85e04800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 14 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85c04800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 12 rlen 0 { align1 EOT };
+send(8) 1       null<1>F        g0<4>F          0x86b0c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 11 rlen 0 { align16 EOT };
+send(8) 2       g6<1>F          g4<8,8,1>F      0x01110003
+                            math MsgDesc: exp mlen 1 rlen 1                 { align1 };
+send(8) 2       g4<1>D          g2.4<0,1,0>D    0x0121009c
+                            math MsgDesc: intdiv signed scalar mlen 2 rlen 1 { align1 };
+send(16) 14     g8<1>UW         null<8,8,1>F    0x04120301
+                            read MsgDesc: OWord Block Read MsgCtrl = 0x3 Surface = 1 mlen 1 rlen 2 { align1 nomask };
+send(8) 1       g30<1>.xF       (abs)g30<4>.xF  0x01110005
+                            math MsgDesc: rsq mlen 1 rlen 1                 { align16 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02984001
+                            sampler MsgDesc: (1, 0, 1, F) mlen 9 rlen 8     { align1 };
+send(8) 2       g4<1>F          g2<0,1,0>F      0x01110086
+                            math MsgDesc: sin scalar mlen 1 rlen 1          { align1 };
+send(8) 2       g6<1>F          g2<0,1,0>F      0x01110087
+                            math MsgDesc: cos scalar mlen 1 rlen 1          { align1 };
+send(8) 2       g6<1>F          g2.1<0,1,0>F    0x01110085
+                            math MsgDesc: rsq scalar mlen 1 rlen 1          { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85f04800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 15 rlen 0 { align1 EOT };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02988001
+                            sampler MsgDesc: (1, 0, 2, F) mlen 9 rlen 8     { align1 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02580304
+                            sampler MsgDesc: (4, 3, 0, F) mlen 5 rlen 8     { align1 };
+send(8) 1       g5<1>.xF        g1<0>.xF        0x01110002
+                            math MsgDesc: log mlen 1 rlen 1                 { align16 };
+send(8) 1       g6<1>UW         g0<8,8,1>UW     0x02640001
+                            sampler MsgDesc: (1, 0, 0, F) mlen 6 rlen 4     { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04000
+                            write MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04001
+                            write MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04002
+                            write MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04803
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 EOT };
+send(8) 1       g8<1>UW         g0<8,8,1>UW     0x02644001
+                            sampler MsgDesc: (1, 0, 1, F) mlen 6 rlen 4     { align1 };
+send(8) 2       g4<1>F          g2<0,1,0>F      0x012100ca
+                            math MsgDesc: pow sat scalar mlen 2 rlen 1      { align1 };
+send(16) 1      g16<1>UW        g0<8,8,1>UW     0x02988102
+                            sampler MsgDesc: (2, 1, 2, F) mlen 9 rlen 8     { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04801
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 EOT };
+send(8) 1       null<1>F        g0<4>F          0x8690c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 9 rlen 0 { align16 EOT };
+send(8) 1       null<1>F        g0<4>F          0x86c0c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 12 rlen 0 { align16 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04802
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 EOT };
+send(16) 1      g20<1>UW        g0<8,8,1>UW     0x02580102
+                            sampler MsgDesc: (2, 1, 0, F) mlen 5 rlen 8     { align1 };
+send(8) 1       null<1>F        g0<4>F          0x86a0c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 10 rlen 0 { align16 EOT };
+send(8) 2       g4<1>F          g2<0,1,0>F      0x01110082
+                            math MsgDesc: log scalar mlen 1 rlen 1          { align1 };
+send(16) 1      g14<1>UW        g0<8,8,1>UW     0x0238a102
+                            sampler MsgDesc: (2, 1, 2, UD) mlen 3 rlen 8    { align1 };
+send(16) 1      g26<1>UW        g0<8,8,1>UW     0x0238a203
+                            sampler MsgDesc: (3, 2, 2, UD) mlen 3 rlen 8    { align1 };
+send(16) 1      g26<1>UW        g0<8,8,1>UW     0x02580203
+                            sampler MsgDesc: (3, 2, 0, F) mlen 5 rlen 8     { align1 };
+send(16) 1      g34<1>UW        g0<8,8,1>UW     0x0238a304
+                            sampler MsgDesc: (4, 3, 2, UD) mlen 3 rlen 8    { align1 };
+send(16) 1      g42<1>UW        g0<8,8,1>UW     0x0238a405
+                            sampler MsgDesc: (5, 4, 2, UD) mlen 3 rlen 8    { align1 };
+send(16) 1      g42<1>UW        g0<8,8,1>UW     0x02580405
+                            sampler MsgDesc: (5, 4, 0, F) mlen 5 rlen 8     { align1 };
+send(16) 1      g50<1>UW        g0<8,8,1>UW     0x0238a506
+                            sampler MsgDesc: (6, 5, 2, UD) mlen 3 rlen 8    { align1 };
+send(16) 1      g50<1>UW        g0<8,8,1>UW     0x02580506
+                            sampler MsgDesc: (6, 5, 0, F) mlen 5 rlen 8     { align1 };
+send(16) 1      g58<1>UW        g0<8,8,1>UW     0x0238a607
+                            sampler MsgDesc: (7, 6, 2, UD) mlen 3 rlen 8    { align1 };
+send(16) 1      g58<1>UW        g0<8,8,1>UW     0x02580607
+                            sampler MsgDesc: (7, 6, 0, F) mlen 5 rlen 8     { align1 };
+send(16) 1      g66<1>UW        g0<8,8,1>UW     0x0238a708
+                            sampler MsgDesc: (8, 7, 2, UD) mlen 3 rlen 8    { align1 };
+send(16) 1      g66<1>UW        g0<8,8,1>UW     0x02580708
+                            sampler MsgDesc: (8, 7, 0, F) mlen 5 rlen 8     { align1 };
+send(8) 1       null<1>F        g0<4>F          0x86d0c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 13 rlen 0 { align16 EOT };
+send(8) 1       g10<1>UW        g0<8,8,1>UW     0x02644102
+                            sampler MsgDesc: (2, 1, 1, F) mlen 6 rlen 4     { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85b04800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 11 rlen 0 { align1 EOT };
+send(8) 2       g3<1>F          g0<4>F          0x02214505
+                            sampler MsgDesc: (5, 5, 1, F) mlen 2 rlen 1     { align16 };
+send(8) 2       g4<1>F          g2<0,1,0>F      0x011100c4
+                            math MsgDesc: sqrt sat scalar mlen 1 rlen 1     { align1 };
+send(8) 2       g4<1>F          g2<0,1,0>F      0x011100c3
+                            math MsgDesc: exp sat scalar mlen 1 rlen 1      { align1 };
+send(8) 2       g3<1>F          g0<4>F          0x02214000
+                            sampler MsgDesc: (0, 0, 1, F) mlen 2 rlen 1     { align16 };
+send(16) 13     g24<1>UW        g0<8,8,1>F      0x0238c002
+                            sampler MsgDesc: (2, 0, 3, F) mlen 3 rlen 8     { align1 };
+send(8) 1       g3<1>F          g1<0>F          0x01110044
+                            math MsgDesc: sqrt sat mlen 1 rlen 1            { align16 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04003
+                            write MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04804
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04004
+                            write MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04805
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04005
+                            write MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04806
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x05a04006
+                            write MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x85a04807
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 EOT };
+send(8) 1       g8<1>UW         g0<8,8,1>UW     0x02748001
+                            sampler MsgDesc: (1, 0, 2, F) mlen 7 rlen 4     { align1 };
+send(16) 1      g12<1>UW        g0<8,8,1>UW     0x02780102
+                            sampler MsgDesc: (2, 1, 0, F) mlen 7 rlen 8     { align1 };
+send(8) 1       null<1>F        g0<4>F          0x8620c460
+                            urb MsgDesc: 6 urb_write interleave used complete mlen 2 rlen 0 { align16 EOT };
+send(8) 2       g6<1>F          g2<0,1,0>F      0x01110084
+                            math MsgDesc: sqrt scalar mlen 1 rlen 1         { align1 };
+send(8) 1       g3<1>F          g1<0>F          0x01110043
+                            math MsgDesc: exp sat mlen 1 rlen 1             { align16 };
+send(8) 2       g4<1>F          g2<0,1,0>F      0x0121008a
+                            math MsgDesc: pow scalar mlen 2 rlen 1          { align1 };
+send(8) 1       g8<1>UW         g0<8,8,1>UW     0x02640102
+                            sampler MsgDesc: (2, 1, 0, F) mlen 6 rlen 4     { align1 };
+send(8) 2       g4<1>F          g2<0,1,0>F      0x01110083
+                            math MsgDesc: exp scalar mlen 1 rlen 1          { align1 };
+send(8) 1       g8<1>UW         g0<8,8,1>UW     0x02a48001
+                            sampler MsgDesc: (1, 0, 2, F) mlen 10 rlen 4    { align1 };
+send(16) 1      g14<1>UW        g0<8,8,1>UW     0x02580003
+                            sampler MsgDesc: (3, 0, 0, F) mlen 5 rlen 8     { align1 };
+send(16) 1      g22<1>UW        g0<8,8,1>UW     0x02580004
+                            sampler MsgDesc: (4, 0, 0, F) mlen 5 rlen 8     { align1 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02580f10
+                            sampler MsgDesc: (16, 15, 0, F) mlen 5 rlen 8   { align1 };
+send(8) 2       g3<1>F          g0<4>F          0x02214303
+                            sampler MsgDesc: (3, 3, 1, F) mlen 2 rlen 1     { align16 };
+send(8) 1       g3<1>F          g1<0>F          0x0121004a
+                            math MsgDesc: pow sat mlen 2 rlen 1             { align16 };
+send(16) 1      g10<1>UW        g0<8,8,1>UW     0x0238a004
+                            sampler MsgDesc: (4, 0, 2, UD) mlen 3 rlen 8    { align1 };
+send(16) 1      g10<1>UW        g0<8,8,1>UW     0x0238a003
+                            sampler MsgDesc: (3, 0, 2, UD) mlen 3 rlen 8    { align1 };
+send(16) 1      g10<1>UW        g0<8,8,1>UW     0x0238a002
+                            sampler MsgDesc: (2, 0, 2, UD) mlen 3 rlen 8    { align1 };
+send(16) 1      g4<1>UW         g0<8,8,1>UW     0x02580002
+                            sampler MsgDesc: (2, 0, 0, F) mlen 5 rlen 8     { align1 };

diff --git a/src/intel/tools/tests/gen4/send.expected b/src/intel/tools/tests/gen4/send.expected
new file mode 100644 (file)
index 0000000..e0c11f4
--- /dev/null
+++ b/src/intel/tools/tests/gen4/send.expected
@@ -0,0 +1,107 @@
+31 00 60 02 bd 0f 80 21 40 01 8d 00 01 00 11 01
+31 10 60 02 bd 0f a0 21 60 01 8d 00 01 00 11 01
+31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 a0 85
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 50 86
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 40 86
+31 01 60 0d bd 0f 0f 20 04 00 6e 00 ff 90 31 05
+31 01 60 0e bd 0f 4f 21 04 00 6e 00 ff 50 21 04
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 80 86
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 00 78 02
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 00 58 02
+31 01 60 0e a1 0f 6f 20 04 00 6e 00 00 10 21 04
+31 01 60 01 bd 0f c1 20 c0 00 60 00 04 00 11 01
+31 00 80 01 29 0d 40 23 00 00 8d 00 01 a0 38 02
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 c0 98 02
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 44 d0 06
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 60 c4 50 86
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 60 86
+31 00 60 02 bd 0f c0 20 80 00 8d 00 0a 00 21 01
+31 00 80 01 29 0d 00 22 00 00 8d 00 01 00 38 02
+31 00 60 02 bd 0f c0 20 80 00 8d 00 07 00 11 01
+31 00 80 0d a9 0f 00 21 00 00 8d 00 01 c0 38 02
+31 00 60 02 bd 0f 80 20 50 00 00 00 81 00 11 01
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 00 98 02
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 e0 98 02
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 70 86
+31 00 60 01 28 0d 00 20 00 00 8d 00 00 4c 60 85
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 60 c4 80 86
+31 01 60 01 bd 0f a2 20 c0 00 60 00 06 00 11 01
+31 01 60 01 a5 0c e1 20 2a 00 0a 00 1c 00 21 01
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 60 c4 40 86
+31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 e0 85
+31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 c0 85
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 b0 86
+31 00 60 02 bd 0f c0 20 80 00 8d 00 03 00 11 01
+31 00 60 02 a5 0c 80 20 50 00 00 00 9c 00 21 01
+31 02 80 0e 89 0f 00 21 00 00 8d 00 01 03 12 04
+31 01 60 01 bd 0f c1 23 c0 23 60 00 05 00 11 01
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 40 98 02
+31 00 60 02 bd 0f 80 20 40 00 00 00 86 00 11 01
+31 00 60 02 bd 0f c0 20 40 00 00 00 87 00 11 01
+31 00 60 02 bd 0f c0 20 44 00 00 00 85 00 11 01
+31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 f0 85
+31 00 80 01 29 0d 80 20 00 00 8d 00 01 80 98 02
+31 00 80 01 29 0d 80 20 00 00 8d 00 04 03 58 02
+31 01 60 01 bd 0f a1 20 20 00 00 00 02 00 11 01
+31 00 60 01 29 0d c0 20 00 00 8d 00 01 00 64 02
+31 00 80 01 28 0d 00 20 00 00 8d 00 00 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 01 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 02 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 03 48 a0 85
+31 00 60 01 29 0d 00 21 00 00 8d 00 01 40 64 02
+31 00 60 02 bd 0f 80 20 40 00 00 00 ca 00 21 01
+31 00 80 01 29 0d 00 22 00 00 8d 00 02 81 98 02
+31 00 80 01 28 0d 00 20 00 00 8d 00 01 48 a0 85
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 90 86
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 c0 86
+31 00 80 01 28 0d 00 20 00 00 8d 00 02 48 a0 85
+31 00 80 01 29 0d 80 22 00 00 8d 00 02 01 58 02
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 a0 86
+31 00 60 02 bd 0f 80 20 40 00 00 00 82 00 11 01
+31 00 80 01 29 0d c0 21 00 00 8d 00 02 a1 38 02
+31 00 80 01 29 0d 40 23 00 00 8d 00 03 a2 38 02
+31 00 80 01 29 0d 40 23 00 00 8d 00 03 02 58 02
+31 00 80 01 29 0d 40 24 00 00 8d 00 04 a3 38 02
+31 00 80 01 29 0d 40 25 00 00 8d 00 05 a4 38 02
+31 00 80 01 29 0d 40 25 00 00 8d 00 05 04 58 02
+31 00 80 01 29 0d 40 26 00 00 8d 00 06 a5 38 02
+31 00 80 01 29 0d 40 26 00 00 8d 00 06 05 58 02
+31 00 80 01 29 0d 40 27 00 00 8d 00 07 a6 38 02
+31 00 80 01 29 0d 40 27 00 00 8d 00 07 06 58 02
+31 00 80 01 29 0d 40 28 00 00 8d 00 08 a7 38 02
+31 00 80 01 29 0d 40 28 00 00 8d 00 08 07 58 02
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 00 c4 d0 86
+31 00 60 01 29 0d 40 21 00 00 8d 00 02 41 64 02
+31 00 80 01 28 0d 00 20 00 00 8d 00 00 48 b0 85
+31 01 60 02 bd 0f 6f 20 04 00 6e 00 05 45 21 02
+31 00 60 02 bd 0f 80 20 40 00 00 00 c4 00 11 01
+31 00 60 02 bd 0f 80 20 40 00 00 00 c3 00 11 01
+31 01 60 02 bd 0f 6f 20 04 00 6e 00 00 40 21 02
+31 00 80 0d a9 0f 00 23 00 00 8d 00 02 c0 38 02
+31 01 60 01 bd 0f 6f 20 24 00 0e 00 44 00 11 01
+31 00 80 01 28 0d 00 20 00 00 8d 00 03 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 04 48 a0 85
+31 00 80 01 28 0d 00 20 00 00 8d 00 04 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 05 48 a0 85
+31 00 80 01 28 0d 00 20 00 00 8d 00 05 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 06 48 a0 85
+31 00 80 01 28 0d 00 20 00 00 8d 00 06 40 a0 05
+31 00 80 01 28 0d 00 20 00 00 8d 00 07 48 a0 85
+31 00 60 01 29 0d 00 21 00 00 8d 00 01 80 74 02
+31 00 80 01 29 0d 80 21 00 00 8d 00 02 01 78 02
+31 01 60 01 bc 0f 0f 20 04 00 6e 00 60 c4 20 86
+31 00 60 02 bd 0f c0 20 40 00 00 00 84 00 11 01
+31 01 60 01 bd 0f 6f 20 24 00 0e 00 43 00 11 01
+31 00 60 02 bd 0f 80 20 40 00 00 00 8a 00 21 01
+31 00 60 01 29 0d 00 21 00 00 8d 00 02 01 64 02
+31 00 60 02 bd 0f 80 20 40 00 00 00 83 00 11 01
+31 00 60 01 29 0d 00 21 00 00 8d 00 01 80 a4 02
+31 00 80 01 29 0d c0 21 00 00 8d 00 03 00 58 02
+31 00 80 01 29 0d c0 22 00 00 8d 00 04 00 58 02
+31 00 80 01 29 0d 80 20 00 00 8d 00 10 0f 58 02
+31 01 60 02 bd 0f 6f 20 04 00 6e 00 03 43 21 02
+31 01 60 01 bd 0f 6f 20 24 00 0e 00 4a 00 21 01
+31 00 80 01 29 0d 40 21 00 00 8d 00 04 a0 38 02
+31 00 80 01 29 0d 40 21 00 00 8d 00 03 a0 38 02
+31 00 80 01 29 0d 40 21 00 00 8d 00 02 a0 38 02
+31 00 80 01 29 0d 80 20 00 00 8d 00 02 00 58 02

diff --git a/src/intel/tools/tests/gen4/shl.asm b/src/intel/tools/tests/gen4/shl.asm
new file mode 100644 (file)
index 0000000..533acb4
--- /dev/null
+++ b/src/intel/tools/tests/gen4/shl.asm
@@ -0,0 +1,5 @@
+shl(8)          g4<1>.xD        g1<0>.yD        0x00000004UD    { align16 };
+shl(16)         g4<1>D          g2.4<0,1,0>D    0x00000004UD    { align1 compr };
+shl(16)         m14<1>D         g2<0,1,0>D      0x00000004UD    { align1 compr };
+shl(8)          g13<1>.xUD      g13<4>.xUD      4D              { align16 };
+shl(8)          g5<1>D          g3<4>D          g4<4>UD         { align16 };

diff --git a/src/intel/tools/tests/gen4/shl.expected b/src/intel/tools/tests/gen4/shl.expected
new file mode 100644 (file)
index 0000000..ce814be
--- /dev/null
+++ b/src/intel/tools/tests/gen4/shl.expected
@@ -0,0 +1,5 @@
+09 01 60 00 a5 0c 81 20 25 00 05 00 04 00 00 00
+09 20 80 00 a5 0c 80 20 50 00 00 00 04 00 00 00
+09 20 80 00 a6 0c c0 21 40 00 00 00 04 00 00 00
+09 01 60 00 21 1c a1 21 a0 01 60 00 04 00 00 00
+09 01 60 00 a5 04 af 20 64 00 6e 00 84 00 6e 00

diff --git a/src/intel/tools/tests/gen4/shr.asm b/src/intel/tools/tests/gen4/shr.asm
new file mode 100644 (file)
index 0000000..e857805
--- /dev/null
+++ b/src/intel/tools/tests/gen4/shr.asm
@@ -0,0 +1 @@
+shr(1)          g12.4<1>UD      g12.4<0,1,0>UD  0x00000004UD    { align1 nomask };

diff --git a/src/intel/tools/tests/gen4/shr.expected b/src/intel/tools/tests/gen4/shr.expected
new file mode 100644 (file)
index 0000000..be1a8a0
--- /dev/null
+++ b/src/intel/tools/tests/gen4/shr.expected
@@ -0,0 +1 @@
+08 02 00 00 21 0c 90 21 90 01 00 00 04 00 00 00

diff --git a/src/intel/tools/tests/gen4/while.asm b/src/intel/tools/tests/gen4/while.asm
new file mode 100644 (file)
index 0000000..9f9645f
--- /dev/null
+++ b/src/intel/tools/tests/gen4/while.asm
@@ -0,0 +1,4 @@
+while(16)       Jump: -10                                       { align1 };
+while(8)        Jump: -16                                       { align16 };
+(-f0.0) while(16) Jump: -11                                     { align1 };
+(-f0.0.x) while(8) Jump: -11                                    { align16 };

diff --git a/src/intel/tools/tests/gen4/while.expected b/src/intel/tools/tests/gen4/while.expected
new file mode 100644 (file)
index 0000000..9707936
--- /dev/null
+++ b/src/intel/tools/tests/gen4/while.expected
@@ -0,0 +1,4 @@
+27 00 80 00 00 1c 00 34 00 14 60 00 f6 ff 00 00
+27 01 60 00 00 1c 0f 34 04 14 6e 00 f0 ff 00 00
+27 00 91 00 00 1c 00 34 00 14 60 00 f5 ff 00 00
+27 01 72 00 00 1c 0f 34 04 14 6e 00 f5 ff 00 00

diff --git a/src/intel/tools/tests/gen4/xor.asm b/src/intel/tools/tests/gen4/xor.asm
new file mode 100644 (file)
index 0000000..bcaaea8
--- /dev/null
+++ b/src/intel/tools/tests/gen4/xor.asm
@@ -0,0 +1,2 @@
+xor(16)         g4<1>UD         g2<0,1,0>UD     g2.1<0,1,0>UD   { align1 compr };
+xor(8)          g5<1>.xUD       g1<0>.xUD       g1<0>.yUD       { align16 };

diff --git a/src/intel/tools/tests/gen4/xor.expected b/src/intel/tools/tests/gen4/xor.expected
new file mode 100644 (file)
index 0000000..f5d2ef3
--- /dev/null
+++ b/src/intel/tools/tests/gen4/xor.expected
@@ -0,0 +1,2 @@
+07 20 80 00 21 04 80 20 40 00 00 00 44 00 00 00
+07 01 60 00 21 04 a1 20 20 00 00 00 25 00 05 00

diff --git a/src/intel/tools/tests/gen5/add.asm b/src/intel/tools/tests/gen5/add.asm
new file mode 100644 (file)
index 0000000..eff22ad
--- /dev/null
+++ b/src/intel/tools/tests/gen5/add.asm
@@ -0,0 +1,49 @@
+add(8)          g2<1>UW         g1.4<2,4,0>UW   0x10101010V     { align1 };
+add(8)          g8<1>F          g2<8,8,1>UW     -g1<0,1,0>F     { align1 };
+add(16)         g10<1>UW        g1.4<2,4,0>UW   0x10101010V     { align1 };
+add(8)          g8<1>F          g10.8<8,8,1>UW  -g1<0,1,0>F     { align1 sechalf };
+add(8)          g2<1>F          g2<8,8,1>F      g6.7<0,1,0>F    { align1 };
+add(16)         g4<1>F          g10<8,8,1>F     g6.7<0,1,0>F    { align1 compr };
+add(8)          g5<1>.xD        g2<4>.xD        64D             { align16 };
+add(8)          g4<1>.xD        g5<4>.xD        g4<4>.xD        { align16 };
+add(8)          g3<1>F          g3<4>F          g5<4>F          { align16 };
+add(8)          g14<1>F         g6<8,8,1>F      0x3f800000F  /* 1F */ { align1 };
+add(8)          g12<1>D         g12<8,8,1>D     1D              { align1 };
+add(16)         g24<1>F         g20<8,8,1>F     0x3f800000F  /* 1F */ { align1 compr };
+add(16)         g14<1>D         g14<8,8,1>D     1D              { align1 compr };
+add(8)          m3<1>F          g4<8,8,1>F      g2.1<0,1,0>F    { align1 };
+add(16)         m3<1>F          g6<8,8,1>F      g2.1<0,1,0>F    { align1 compr4 };
+add(8)          m5<1>.xyzF      g10<4>.xyzzF    g8<4>.xyzzF     { align16 NoDDClr };
+add.le.f0.0(8)  g3<1>F          g3<8,8,1>F      g4<8,8,1>F      { align1 };
+add.le.f0.0(16) g6<1>F          g8<8,8,1>F      g4<8,8,1>F      { align1 compr };
+add(8)          g3<1>.xyF       g2<4>.xyyyF     0x3f800000F  /* 1F */ { align16 };
+add(8)          m4<1>F          -g2<8,8,1>F     0x3f800000F  /* 1F */ { align1 };
+add(16)         m4<1>F          -g6<8,8,1>F     0x3f800000F  /* 1F */ { align1 compr4 };
+add.sat(8)      g3<1>F          g3<8,8,1>F      g2.1<0,1,0>F    { align1 };
+add.sat(16)     g6<1>F          g4<8,8,1>F      g2.1<0,1,0>F    { align1 compr };
+add(8)          g2<1>D          g2<8,8,1>D      -g9.3<0,1,0>D   { align1 };
+add(16)         g12<1>D         g4<8,8,1>D      -g9.3<0,1,0>D   { align1 compr };
+add(8)          m5<1>.xF        g3<4>.xF        0x3f000000F  /* 0.5F */ { align16 };
+add(8)          g31<1>.xyzF     g28<4>.xyzzF    0x30300000VF /* [0F, 0F, 1F, 1F]VF */ { align16 };
+add.sat(8)      m5<1>.xyzF      g25<4>.xyzzF    g26<4>.xyzzF    { align16 NoDDClr };
+add(8)          g3.1<2>UW       g3.1<16,8,2>UW  g4<16,8,2>UW    { align1 };
+add(16)         g4.1<2>UW       g4.1<16,8,2>UW  g6<16,8,2>UW    { align1 compr };
+add(8)          g4<1>.xyF       g4<4>.xyyyF     0xbf800000F  /* -1F */ { align16 NoDDClr };
+add.sat(8)      m5<1>F          g3<4>.yzxwF     -g3<4>F         { align16 };
+add(8)          m5<1>.zwF       g8<4>.xxxyF     g9<4>.xxxyF     { align16 NoDDChk };
+add(8)          m8<1>.xyF       g8<4>.xyyyF     g9<4>.xyyyF     { align16 };
+add(1)          m15.4<1>D       g5.4<0,1,0>D    16D             { align1 nomask };
+add.sat(8)      m3<1>F          g6<8,8,1>F      g12<8,8,1>F     { align1 };
+add.sat(16)     m3<1>F          g16<8,8,1>F     g12<8,8,1>F     { align1 compr4 };
+add.sat(8)      m5<1>.xF        -g8<4>.xF       0x3f800000F  /* 1F */ { align16 };
+add(16)         g4<1>F          -g8<4>.xyxyF    g8<4>.zwzwF     { align16 compr };
+add(8)          m14<1>D         g3<8,8,1>D      12D             { align1 };
+add(16)         m14<1>D         g4<8,8,1>D      12D             { align1 compr };
+add.sat(8)      m5<1>.yF        g6<4>.xF        g7<4>.xF        { align16 NoDDClr,NoDDChk };
+add.sat(8)      m5<1>.wF        g6<4>.xF        g7<4>.xF        { align16 NoDDChk };
+add.ge.f0.0(8)  g8<1>F          g8<8,8,1>F      g9<8,8,1>F      { align1 };
+add.ge.f0.0(16) g16<1>F         g18<8,8,1>F     g10<8,8,1>F     { align1 compr };
+add(8)          g5<1>.zF        g4<4>.xF        0xbf800000F  /* -1F */ { align16 NoDDClr,NoDDChk };
+add(8)          m5<1>.xyF       g12<4>.xyyyF    0x3f000000F  /* 0.5F */ { align16 NoDDClr };
+add(8)          g5<1>.xUD       g7<4>.xUD       0x00000080UD    { align16 };
+add(8)          m5<1>.yF        -g5<4>.xF       0x3f800000F  /* 1F */ { align16 NoDDClr,NoDDChk };

diff --git a/src/intel/tools/tests/gen5/add.expected b/src/intel/tools/tests/gen5/add.expected
new file mode 100644 (file)
index 0000000..7b40131
--- /dev/null
+++ b/src/intel/tools/tests/gen5/add.expected
@@ -0,0 +1,49 @@
+40 00 60 00 29 6d 40 20 28 00 48 00 10 10 10 10
+40 00 60 00 3d 75 00 21 40 00 8d 00 20 40 00 00
+40 00 80 00 29 6d 40 21 28 00 48 00 10 10 10 10
+40 10 60 00 3d 75 00 21 50 01 8d 00 20 40 00 00
+40 00 60 00 bd 77 40 20 40 00 8d 00 dc 00 00 00
+40 20 80 00 bd 77 80 20 40 01 8d 00 dc 00 00 00
+40 01 60 00 a5 1c a1 20 40 00 60 00 40 00 00 00
+40 01 60 00 a5 14 81 20 a0 00 60 00 80 00 60 00
+40 01 60 00 bd 77 6f 20 64 00 6e 00 a4 00 6e 00
+40 00 60 00 bd 7f c0 21 c0 00 8d 00 00 00 80 3f
+40 00 60 00 a5 1c 80 21 80 01 8d 00 01 00 00 00
+40 20 80 00 bd 7f 00 23 80 02 8d 00 00 00 80 3f
+40 20 80 00 a5 1c c0 21 c0 01 8d 00 01 00 00 00
+40 00 60 00 be 77 60 20 80 00 8d 00 44 00 00 00
+40 20 80 00 be 77 60 30 c0 00 8d 00 44 00 00 00
+40 05 60 00 be 77 a7 20 44 01 6a 00 04 01 6a 00
+40 00 60 06 bd 77 60 20 60 00 8d 00 80 00 8d 00
+40 20 80 06 bd 77 c0 20 00 01 8d 00 80 00 8d 00
+40 01 60 00 bd 7f 63 20 44 00 65 00 00 00 80 3f
+40 00 60 00 be 7f 80 20 40 40 8d 00 00 00 80 3f
+40 20 80 00 be 7f 80 30 c0 40 8d 00 00 00 80 3f
+40 00 60 80 bd 77 60 20 60 00 8d 00 44 00 00 00
+40 20 80 80 bd 77 c0 20 80 00 8d 00 44 00 00 00
+40 00 60 00 a5 14 40 20 40 00 8d 00 2c 41 00 00
+40 20 80 00 a5 14 80 21 80 00 8d 00 2c 41 00 00
+40 01 60 00 be 7f a1 20 60 00 60 00 00 00 00 3f
+40 01 60 00 bd 5f e7 23 84 03 6a 00 00 00 30 30
+40 05 60 80 be 77 a7 20 24 03 6a 00 44 03 6a 00
+40 00 60 00 29 25 62 40 62 00 ae 00 80 00 ae 00
+40 20 80 00 29 25 82 40 82 00 ae 00 c0 00 ae 00
+40 05 60 00 bd 7f 83 20 84 00 65 00 00 00 80 bf
+40 01 60 80 be 77 af 20 69 00 6c 00 64 40 6e 00
+40 09 60 00 be 77 ac 20 00 01 64 00 20 01 64 00
+40 01 60 00 be 77 03 21 04 01 65 00 24 01 65 00
+40 02 00 00 a6 1c f0 21 b0 00 00 00 10 00 00 00
+40 00 60 80 be 77 60 20 c0 00 8d 00 80 01 8d 00
+40 20 80 80 be 77 60 30 00 02 8d 00 80 01 8d 00
+40 01 60 80 be 7f a1 20 00 41 60 00 00 00 80 3f
+40 21 80 00 bd 77 8f 20 04 41 64 00 0e 01 6e 00
+40 00 60 00 a6 1c c0 21 60 00 8d 00 0c 00 00 00
+40 20 80 00 a6 1c c0 21 80 00 8d 00 0c 00 00 00
+40 0d 60 80 be 77 a2 20 c0 00 60 00 e0 00 60 00
+40 09 60 80 be 77 a8 20 c0 00 60 00 e0 00 60 00
+40 00 60 04 bd 77 00 21 00 01 8d 00 20 01 8d 00
+40 20 80 04 bd 77 00 22 40 02 8d 00 40 01 8d 00
+40 0d 60 00 bd 7f a4 20 80 00 60 00 00 00 80 bf
+40 05 60 00 be 7f a3 20 84 01 65 00 00 00 00 3f
+40 01 60 00 21 0c a1 20 e0 00 60 00 80 00 00 00
+40 0d 60 00 be 7f a2 20 a0 40 60 00 00 00 80 3f

diff --git a/src/intel/tools/tests/gen5/and.asm b/src/intel/tools/tests/gen5/and.asm
new file mode 100644 (file)
index 0000000..cc2f760
--- /dev/null
+++ b/src/intel/tools/tests/gen5/and.asm
@@ -0,0 +1,20 @@
+and(8)          g9<1>.wUD       g9<4>.wUD       524032D         { align16 };
+and(8)          g5<1>.xD        g5<4>.xD        1D              { align16 };
+and(8)          g5<1>D          g6<8,8,1>D      1D              { align1 };
+and(16)         g14<1>D         g12<8,8,1>D     1D              { align1 compr };
+and(8)          g2<1>D          g2<8,8,1>UD     1D              { align1 };
+and.nz.f0.0(8)  null<1>.xD      g9<4>.xUD       1D              { align16 };
+and.nz.f0.0(8)  null<1>D        g8<8,8,1>UD     1D              { align1 };
+and(8)          g8<1>UD         g2.4<0,1,0>UD   0x80000000UD    { align1 };
+and.nz.f0.0(16) null<1>D        g12<8,8,1>UD    1D              { align1 compr };
+and(16)         g12<1>UD        g2.4<0,1,0>UD   0x80000000UD    { align1 compr };
+and(16)         g6<1>D          g4<8,8,1>UD     1D              { align1 compr };
+and(8)          g2<1>UD         g4<8,8,1>UD     g3<8,8,1>UD     { align1 };
+and(16)         g6<1>UD         g8<8,8,1>UD     g4<8,8,1>UD     { align1 compr };
+and(8)          g17<1>.xUD      g1<0>.xUD       0x80000000UD    { align16 };
+and(8)          g47<1>.xUD      g48<4>.xUD      g47<4>.xUD      { align16 };
+and(1)          g8<1>UD         f0<0,1,0>UW     0x0000000fUD    { align1 nomask };
+and.nz.f0.0(8)  g7<1>D          g7<8,8,1>D      1D              { align1 };
+and.nz.f0.0(16) g14<1>D         g8<8,8,1>D      1D              { align1 compr };
+and(8)          g3<1>.xD        g3<4>.xUD       1D              { align16 };
+and.nz.f0.0(1)  null<1>UD       g1.6<0,1,0>UD   0x04000000UD    { align1 };

diff --git a/src/intel/tools/tests/gen5/and.expected b/src/intel/tools/tests/gen5/and.expected
new file mode 100644 (file)
index 0000000..7d12dd5
--- /dev/null
+++ b/src/intel/tools/tests/gen5/and.expected
@@ -0,0 +1,20 @@
+05 01 60 00 21 1c 28 21 2f 01 6f 00 00 ff 07 00
+05 01 60 00 a5 1c a1 20 a0 00 60 00 01 00 00 00
+05 00 60 00 a5 1c a0 20 c0 00 8d 00 01 00 00 00
+05 20 80 00 a5 1c c0 21 80 01 8d 00 01 00 00 00
+05 00 60 00 25 1c 40 20 40 00 8d 00 01 00 00 00
+05 01 60 02 24 1c 01 20 20 01 60 00 01 00 00 00
+05 00 60 02 24 1c 00 20 00 01 8d 00 01 00 00 00
+05 00 60 00 21 0c 00 21 50 00 00 00 00 00 00 80
+05 20 80 02 24 1c 00 20 80 01 8d 00 01 00 00 00
+05 20 80 00 21 0c 80 21 50 00 00 00 00 00 00 80
+05 20 80 00 25 1c c0 20 80 00 8d 00 01 00 00 00
+05 00 60 00 21 04 40 20 80 00 8d 00 60 00 8d 00
+05 20 80 00 21 04 c0 20 00 01 8d 00 80 00 8d 00
+05 01 60 00 21 0c 21 22 20 00 00 00 00 00 00 80
+05 01 60 00 21 04 e1 25 00 06 60 00 e0 05 60 00
+05 02 00 00 01 0d 00 21 00 06 00 00 0f 00 00 00
+05 00 60 02 a5 1c e0 20 e0 00 8d 00 01 00 00 00
+05 20 80 02 a5 1c c0 21 00 01 8d 00 01 00 00 00
+05 01 60 00 25 1c 61 20 60 00 60 00 01 00 00 00
+05 00 00 02 20 0c 00 20 38 00 00 00 00 00 00 04

diff --git a/src/intel/tools/tests/gen5/asr.asm b/src/intel/tools/tests/gen5/asr.asm
new file mode 100644 (file)
index 0000000..4374a80
--- /dev/null
+++ b/src/intel/tools/tests/gen5/asr.asm
@@ -0,0 +1,6 @@
+asr.nz.f0.0(8)  null<1>D        -g1.6<0,1,0>D   31D             { align1 };
+asr.nz.f0.0(16) null<1>D        -g1.6<0,1,0>D   31D             { align1 compr };
+asr(8)          g4<1>D          g5<4>D          g4<4>UD         { align16 };
+asr(8)          g11<1>.xD       g5<4>.xD        0x00000002UD    { align16 };
+asr(8)          g5<1>D          g3<8,8,1>D      0x00000002UD    { align1 };
+asr(16)         g10<1>D         g6<8,8,1>D      0x00000002UD    { align1 compr };

diff --git a/src/intel/tools/tests/gen5/asr.expected b/src/intel/tools/tests/gen5/asr.expected
new file mode 100644 (file)
index 0000000..8da3c86
--- /dev/null
+++ b/src/intel/tools/tests/gen5/asr.expected
@@ -0,0 +1,6 @@
+0c 00 60 02 a4 1c 00 20 38 40 00 00 1f 00 00 00
+0c 20 80 02 a4 1c 00 20 38 40 00 00 1f 00 00 00
+0c 01 60 00 a5 04 8f 20 a4 00 6e 00 84 00 6e 00
+0c 01 60 00 a5 0c 61 21 a0 00 60 00 02 00 00 00
+0c 00 60 00 a5 0c a0 20 60 00 8d 00 02 00 00 00
+0c 20 80 00 a5 0c 40 21 c0 00 8d 00 02 00 00 00

diff --git a/src/intel/tools/tests/gen5/break.asm b/src/intel/tools/tests/gen5/break.asm
new file mode 100644 (file)
index 0000000..26ab881
--- /dev/null
+++ b/src/intel/tools/tests/gen5/break.asm
@@ -0,0 +1,4 @@
+(+f0.0) break(8) Jump: 282      Pop: 0                          { align1 };
+(+f0.0) break(16) Jump: 282     Pop: 0                          { align1 };
+(+f0.0.x) break(8) Jump: 32     Pop: 0                          { align16 };
+break(8)        Jump: 12        Pop: 2                          { align16 };

diff --git a/src/intel/tools/tests/gen5/break.expected b/src/intel/tools/tests/gen5/break.expected
new file mode 100644 (file)
index 0000000..1ccb911
--- /dev/null
+++ b/src/intel/tools/tests/gen5/break.expected
@@ -0,0 +1,4 @@
+28 00 61 00 00 1c 00 34 00 14 60 00 1a 01 00 00
+28 00 81 00 00 1c 00 34 00 14 60 00 1a 01 00 00
+28 01 62 00 00 1c 0f 34 04 14 6e 00 20 00 00 00
+28 01 60 00 00 1c 0f 34 04 14 6e 00 0c 00 02 00

diff --git a/src/intel/tools/tests/gen5/cmp.asm b/src/intel/tools/tests/gen5/cmp.asm
new file mode 100644 (file)
index 0000000..d2cbcf0
--- /dev/null
+++ b/src/intel/tools/tests/gen5/cmp.asm
@@ -0,0 +1,91 @@
+cmp.ge.f0.0(8)  null<1>D        g12<8,8,1>D     16D             { align1 };
+cmp.ge.f0.0(16) null<1>D        g14<8,8,1>D     16D             { align1 compr };
+cmp.ge.f0.0(8)  null<1>F        g3<8,8,1>F      0x0F  /* 0F */  { align1 };
+cmp.ge.f0.0(16) null<1>F        g6<8,8,1>F      0x0F  /* 0F */  { align1 compr };
+cmp.ge.f0.0(8)  null<1>F        g5<4>.xF        0x0F  /* 0F */  { align16 };
+cmp.l.f0.0(8)   null<1>F        g5<4>.wF        0x43000000F  /* 128F */ { align16 };
+cmp.le.f0.0(8)  g5<1>.xF        g5<4>.xF        0x0F  /* 0F */  { align16 };
+cmp.nz.f0.0(8)  null<1>.zD      -g5<4>.xD       0D              { align16 };
+cmp.ge.f0.0(8)  g6<1>F          g4<8,8,1>F      0x26901d7dF  /* 1e-15F */ { align1 };
+cmp.ge.f0.0(16) g12<1>F         g8<8,8,1>F      0x26901d7dF  /* 1e-15F */ { align1 compr };
+cmp.ge.f0.0(8)  null<1>F        (abs)g4<8,8,1>F (abs)g3<8,8,1>F { align1 };
+cmp.ge.f0.0(16) null<1>F        (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
+cmp.z.f0.0(8)   null<1>D        g3<8,8,1>D      1D              { align1 };
+cmp.z.f0.0(16)  null<1>D        g8<8,8,1>D      1D              { align1 compr };
+cmp.nz.f0.0(8)  g5<1>F          g5<8,8,1>F      g38<8,8,1>F     { align1 };
+cmp.ge.f0.0(8)  null<1>.xD      g5<4>.xD        4D              { align16 };
+cmp.z.f0.0(8)   g9<1>.xD        g4<4>.xD        g1<0>.xD        { align16 };
+cmp.z.f0.0(8)   g10<1>.xD       g1<0>.xD        1D              { align16 };
+cmp.nz.f0.0(8)  null<1>F        g2.4<0,1,0>F    0x0F  /* 0F */  { align1 };
+cmp.nz.f0.0(16) g20<1>F         g6<8,8,1>F      -g14<8,8,1>F    { align1 compr };
+cmp.nz.f0.0(16) null<1>F        g2.4<0,1,0>F    0x0F  /* 0F */  { align1 compr };
+cmp.z.f0.0(8)   null<1>F        g4.1<0,1,0>F    0x3f800000F  /* 1F */ { align1 };
+cmp.z.f0.0(16)  null<1>F        g4.1<0,1,0>F    0x3f800000F  /* 1F */ { align1 compr };
+cmp.l.f0.0(8)   g31<1>.xyzF     g8<0>.wF        g30<4>.xF       { align16 };
+cmp.z.f0.0(8)   g3<1>D          g3<8,8,1>D      g2.5<0,1,0>D    { align1 };
+cmp.z.f0.0(16)  g4<1>D          g8<8,8,1>D      g2.5<0,1,0>D    { align1 compr };
+cmp.nz.f0.0(8)  null<1>F        g1<0>.xF        0x0F  /* 0F */  { align16 };
+cmp.nz.f0.0(8)  g17<1>.xF       g17<4>.xF       g1<0>.zF        { align16 };
+cmp.le.f0.0(8)  g5<1>.xD        g1<0>.xD        0D              { align16 };
+cmp.le.f0.0(8)  null<1>F        g2<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 };
+cmp.le.f0.0(8)  g10<1>F         g2<8,8,1>F      0x461c3f9aF  /* 9999.9F */ { align1 };
+cmp.ge.f0.0(8)  g9<1>F          -g3<8,8,1>F     g9<8,8,1>F      { align1 };
+cmp.nz.f0.0(8)  null<1>D        g20<8,8,1>D     0D              { align1 };
+cmp.nz.f0.0(8)  g24<1>D         g20<8,8,1>D     2D              { align1 };
+cmp.z.f0.0(8)   g25<1>D         g20<8,8,1>D     2D              { align1 };
+cmp.le.f0.0(16) null<1>F        g4<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 compr };
+cmp.le.f0.0(16) g20<1>F         g4<8,8,1>F      0x461c3f9aF  /* 9999.9F */ { align1 compr };
+cmp.ge.f0.0(16) g24<1>F         -g6<8,8,1>F     g12<8,8,1>F     { align1 compr };
+cmp.nz.f0.0(16) null<1>D        g40<8,8,1>D     0D              { align1 compr };
+cmp.nz.f0.0(16) g48<1>D         g40<8,8,1>D     2D              { align1 compr };
+cmp.z.f0.0(16)  g52<1>D         g40<8,8,1>D     2D              { align1 compr };
+cmp.g.f0.0(8)   g4<1>F          g3<4>F          0x3f000000F  /* 0.5F */ { align16 };
+cmp.l.f0.0(8)   null<1>F        g1<0>F          g3<4>F          { align16 };
+cmp.z.f0.0(8)   null<1>.xD      g1<0>.xD        1D              { align16 };
+cmp.ge.f0.0(8)  g3<1>F          g1<0>F          g1.4<0>F        { align16 };
+cmp.g.f0.0(8)   g3<1>F          (abs)g2<8,8,1>F 0x3a83126fF  /* 0.001F */ { align1 };
+cmp.g.f0.0(16)  g6<1>F          (abs)g4<8,8,1>F 0x3a83126fF  /* 0.001F */ { align1 compr };
+cmp.le.f0.0(8)  null<1>.xF      g8<4>.xF        0x3f000000F  /* 0.5F */ { align16 };
+cmp.ge.f0.0(8)  g48<1>.xF       g8<4>.xF        0x3727c5acF  /* 1e-05F */ { align16 };
+cmp.ge.f0.0(8)  null<1>.xF      g22<4>.xF       g10<4>.xF       { align16 };
+cmp.l.f0.0(8)   null<1>F        g2<0,1,0>F      0x3eb33333F  /* 0.35F */ { align1 };
+cmp.l.f0.0(8)   null<1>F        g3<8,8,1>F      g4<8,8,1>F      { align1 };
+cmp.l.f0.0(16)  null<1>F        g2<0,1,0>F      0x3eb33333F  /* 0.35F */ { align1 compr };
+cmp.l.f0.0(16)  null<1>F        g4<8,8,1>F      g6<8,8,1>F      { align1 compr };
+cmp.l.f0.0(8)   g2<1>F          g2<8,8,1>F      0x3b800000F  /* 0.00390625F */ { align1 };
+cmp.l.f0.0(16)  g4<1>F          g6<8,8,1>F      0x3b800000F  /* 0.00390625F */ { align1 compr };
+cmp.z.f0.0(8)   null<1>D        g3<8,8,1>D      g2<0,1,0>D      { align1 };
+cmp.nz.f0.0(8)  g4<1>D          g3<8,8,1>D      g2.1<0,1,0>D    { align1 };
+cmp.z.f0.0(16)  null<1>D        g6<8,8,1>D      g2<0,1,0>D      { align1 compr };
+cmp.nz.f0.0(16) g4<1>D          g6<8,8,1>D      g2.1<0,1,0>D    { align1 compr };
+cmp.nz.f0.0(8)  g3<1>F          g3<8,8,1>F      0x0F  /* 0F */  { align1 };
+(+f0.1) cmp.z.f0.1(8) null<1>D  g3<8,8,1>D      0D              { align1 };
+cmp.nz.f0.0(16) g8<1>F          g6<8,8,1>F      0x0F  /* 0F */  { align1 compr };
+(+f0.1) cmp.z.f0.1(16) null<1>D g6<8,8,1>D      0D              { align1 compr };
+cmp.ge.f0.0(8)  null<1>D        g4<8,8,1>D      g2<0,1,0>D      { align1 };
+cmp.ge.f0.0(16) null<1>D        g6<8,8,1>D      g2<0,1,0>D      { align1 compr };
+cmp.nz.f0.0(8)  null<1>F        g4<4>.xyyyF     g3<4>.xyyyF     { align16 };
+cmp.z.f0.0(8)   g3<1>F          g3<4>F          0x0F  /* 0F */  { align16 };
+cmp.nz.f0.0(8)  g11<1>.xD       g4<4>.xD        10D             { align16 };
+cmp.nz.f0.0(8)  null<1>.xD      g6<4>.xD        g3<4>.xD        { align16 };
+cmp.z.f0.0(8)   g3<1>F          g3<8,8,1>F      g2.2<0,1,0>F    { align1 };
+cmp.z.f0.0(16)  g8<1>F          g6<8,8,1>F      g2.2<0,1,0>F    { align1 compr };
+cmp.nz.f0.0(8)  g3<1>F          g3<4>F          0x0F  /* 0F */  { align16 };
+cmp.l.f0.0(8)   g5<1>F          g2<0,1,0>F      g7<8,8,1>F      { align1 };
+cmp.l.f0.0(16)  g4<1>F          g2<0,1,0>F      g16<8,8,1>F     { align1 compr };
+cmp.le.f0.0(8)  g3<1>D          g2<0,1,0>D      0D              { align1 };
+cmp.le.f0.0(16) g4<1>D          g2<0,1,0>D      0D              { align1 compr };
+cmp.l.f0.0(8)   g5<1>.xF        g3<0>.zF        0x3f000000F  /* 0.5F */ { align16 };
+cmp.ge.f0.0(8)  null<1>.xD      g5<4>.xD        g1<0>.xD        { align16 };
+cmp.l.f0.0(8)   null<1>.xD      g6<4>.xD        g5<4>.xD        { align16 };
+cmp.ge.f0.0(8)  g10<1>.xD       g5<4>.xD        2D              { align16 };
+cmp.z.f0.0(8)   g3<1>F          g3<8,8,1>F      0x40a00000F  /* 5F */ { align1 };
+cmp.z.f0.0(16)  g8<1>F          g4<8,8,1>F      0x40a00000F  /* 5F */ { align1 compr };
+cmp.g.f0.0(8)   null<1>.xF      g2<4>.zF        0x3f400000F  /* 0.75F */ { align16 };
+cmp.le.f0.0(8)  g3<1>.xUD       g1<0>.xUD       0x00000001UD    { align16 };
+cmp.z.f0.0(8)   null<1>F        g8<4>.xyzzF     g3<0>.yzwwF     { align16 };
+cmp.z.f0.0(8)   g8<1>.xF        g8<4>.xF        g3<0>.yF        { align16 };
+cmp.g.f0.0(8)   null<1>.xD      g1<0>.xD        0D              { align16 };
+cmp.g.f0.0(8)   g8<1>.xD        g1<0>.xD        2D              { align16 };
+cmp.nz.f0.0(8)  null<1>F        g27<8,8,1>F     g2.6<0,1,0>F    { align1 };
+cmp.nz.f0.0(16) null<1>F        g16<8,8,1>F     g2.6<0,1,0>F    { align1 compr };

diff --git a/src/intel/tools/tests/gen5/cmp.expected b/src/intel/tools/tests/gen5/cmp.expected
new file mode 100644 (file)
index 0000000..c8ba629
--- /dev/null
+++ b/src/intel/tools/tests/gen5/cmp.expected
@@ -0,0 +1,91 @@
+10 00 60 04 a4 1c 00 20 80 01 8d 00 10 00 00 00
+10 20 80 04 a4 1c 00 20 c0 01 8d 00 10 00 00 00
+10 00 60 04 bc 7f 00 20 60 00 8d 00 00 00 00 00
+10 20 80 04 bc 7f 00 20 c0 00 8d 00 00 00 00 00
+10 01 60 04 bc 7f 0f 20 a0 00 60 00 00 00 00 00
+10 01 60 05 bc 7f 0f 20 af 00 6f 00 00 00 00 43
+10 01 60 06 bd 7f a1 20 a0 00 60 00 00 00 00 00
+10 01 60 02 a4 1c 04 20 a0 40 60 00 00 00 00 00
+10 00 60 04 bd 7f c0 20 80 00 8d 00 7d 1d 90 26
+10 20 80 04 bd 7f 80 21 00 01 8d 00 7d 1d 90 26
+10 00 60 04 bc 77 00 20 80 20 8d 00 60 20 8d 00
+10 20 80 04 bc 77 00 20 00 22 8d 00 00 21 8d 00
+10 00 60 01 a4 1c 00 20 60 00 8d 00 01 00 00 00
+10 20 80 01 a4 1c 00 20 00 01 8d 00 01 00 00 00
+10 00 60 02 bd 77 a0 20 a0 00 8d 00 c0 04 8d 00
+10 01 60 04 a4 1c 01 20 a0 00 60 00 04 00 00 00
+10 01 60 01 a5 14 21 21 80 00 60 00 20 00 00 00
+10 01 60 01 a5 1c 41 21 20 00 00 00 01 00 00 00
+10 00 60 02 bc 7f 00 20 50 00 00 00 00 00 00 00
+10 20 80 02 bd 77 80 22 c0 00 8d 00 c0 41 8d 00
+10 20 80 02 bc 7f 00 20 50 00 00 00 00 00 00 00
+10 00 60 01 bc 7f 00 20 84 00 00 00 00 00 80 3f
+10 20 80 01 bc 7f 00 20 84 00 00 00 00 00 80 3f
+10 01 60 05 bd 77 e7 23 0f 01 0f 00 c0 03 60 00
+10 00 60 01 a5 14 60 20 60 00 8d 00 54 00 00 00
+10 20 80 01 a5 14 80 20 00 01 8d 00 54 00 00 00
+10 01 60 02 bc 7f 0f 20 20 00 00 00 00 00 00 00
+10 01 60 02 bd 77 21 22 20 02 60 00 2a 00 0a 00
+10 01 60 06 a5 1c a1 20 20 00 00 00 00 00 00 00
+10 00 60 06 bc 7f 00 20 40 00 8d 00 00 00 00 3f
+10 00 60 06 bd 7f 40 21 40 00 8d 00 9a 3f 1c 46
+10 00 60 04 bd 77 20 21 60 40 8d 00 20 01 8d 00
+10 00 60 02 a4 1c 00 20 80 02 8d 00 00 00 00 00
+10 00 60 02 a5 1c 00 23 80 02 8d 00 02 00 00 00
+10 00 60 01 a5 1c 20 23 80 02 8d 00 02 00 00 00
+10 20 80 06 bc 7f 00 20 80 00 8d 00 00 00 00 3f
+10 20 80 06 bd 7f 80 22 80 00 8d 00 9a 3f 1c 46
+10 20 80 04 bd 77 00 23 c0 40 8d 00 80 01 8d 00
+10 20 80 02 a4 1c 00 20 00 05 8d 00 00 00 00 00
+10 20 80 02 a5 1c 00 26 00 05 8d 00 02 00 00 00
+10 20 80 01 a5 1c 80 26 00 05 8d 00 02 00 00 00
+10 01 60 03 bd 7f 8f 20 64 00 6e 00 00 00 00 3f
+10 01 60 05 bc 77 0f 20 24 00 0e 00 64 00 6e 00
+10 01 60 01 a4 1c 01 20 20 00 00 00 01 00 00 00
+10 01 60 04 bd 77 6f 20 24 00 0e 00 34 00 0e 00
+10 00 60 03 bd 7f 60 20 40 20 8d 00 6f 12 83 3a
+10 20 80 03 bd 7f c0 20 80 20 8d 00 6f 12 83 3a
+10 01 60 06 bc 7f 01 20 00 01 60 00 00 00 00 3f
+10 01 60 04 bd 7f 01 26 00 01 60 00 ac c5 27 37
+10 01 60 04 bc 77 01 20 c0 02 60 00 40 01 60 00
+10 00 60 05 bc 7f 00 20 40 00 00 00 33 33 b3 3e
+10 00 60 05 bc 77 00 20 60 00 8d 00 80 00 8d 00
+10 20 80 05 bc 7f 00 20 40 00 00 00 33 33 b3 3e
+10 20 80 05 bc 77 00 20 80 00 8d 00 c0 00 8d 00
+10 00 60 05 bd 7f 40 20 40 00 8d 00 00 00 80 3b
+10 20 80 05 bd 7f 80 20 c0 00 8d 00 00 00 80 3b
+10 00 60 01 a4 14 00 20 60 00 8d 00 40 00 00 00
+10 00 60 02 a5 14 80 20 60 00 8d 00 44 00 00 00
+10 20 80 01 a4 14 00 20 c0 00 8d 00 40 00 00 00
+10 20 80 02 a5 14 80 20 c0 00 8d 00 44 00 00 00
+10 00 60 02 bd 7f 60 20 60 00 8d 00 00 00 00 00
+10 00 61 01 a4 1c 00 20 60 00 8d 02 00 00 00 00
+10 20 80 02 bd 7f 00 21 c0 00 8d 00 00 00 00 00
+10 20 81 01 a4 1c 00 20 c0 00 8d 02 00 00 00 00
+10 00 60 04 a4 14 00 20 80 00 8d 00 40 00 00 00
+10 20 80 04 a4 14 00 20 c0 00 8d 00 40 00 00 00
+10 01 60 02 bc 77 0f 20 84 00 65 00 64 00 65 00
+10 01 60 01 bd 7f 6f 20 64 00 6e 00 00 00 00 00
+10 01 60 02 a5 1c 61 21 80 00 60 00 0a 00 00 00
+10 01 60 02 a4 14 01 20 c0 00 60 00 60 00 60 00
+10 00 60 01 bd 77 60 20 60 00 8d 00 48 00 00 00
+10 20 80 01 bd 77 00 21 c0 00 8d 00 48 00 00 00
+10 01 60 02 bd 7f 6f 20 64 00 6e 00 00 00 00 00
+10 00 60 05 bd 77 a0 20 40 00 00 00 e0 00 8d 00
+10 20 80 05 bd 77 80 20 40 00 00 00 00 02 8d 00
+10 00 60 06 a5 1c 60 20 40 00 00 00 00 00 00 00
+10 20 80 06 a5 1c 80 20 40 00 00 00 00 00 00 00
+10 01 60 05 bd 7f a1 20 6a 00 0a 00 00 00 00 3f
+10 01 60 04 a4 14 01 20 a0 00 60 00 20 00 00 00
+10 01 60 05 a4 14 01 20 c0 00 60 00 a0 00 60 00
+10 01 60 04 a5 1c 41 21 a0 00 60 00 02 00 00 00
+10 00 60 01 bd 7f 60 20 60 00 8d 00 00 00 a0 40
+10 20 80 01 bd 7f 00 21 80 00 8d 00 00 00 a0 40
+10 01 60 03 bc 7f 01 20 4a 00 6a 00 00 00 40 3f
+10 01 60 06 21 0c 61 20 20 00 00 00 01 00 00 00
+10 01 60 01 bc 77 0f 20 04 01 6a 00 69 00 0f 00
+10 01 60 01 bd 77 01 21 00 01 60 00 65 00 05 00
+10 01 60 03 a4 1c 01 20 20 00 00 00 00 00 00 00
+10 01 60 03 a5 1c 01 21 20 00 00 00 02 00 00 00
+10 00 60 02 bc 77 00 20 60 03 8d 00 58 00 00 00
+10 20 80 02 bc 77 00 20 00 02 8d 00 58 00 00 00

diff --git a/src/intel/tools/tests/gen5/do.asm b/src/intel/tools/tests/gen5/do.asm
new file mode 100644 (file)
index 0000000..945fdc1
--- /dev/null
+++ b/src/intel/tools/tests/gen5/do.asm
@@ -0,0 +1,3 @@
+do(8)                                                           { align1 };
+do(16)                                                          { align1 };
+do(8)                                                           { align16 };

diff --git a/src/intel/tools/tests/gen5/do.expected b/src/intel/tools/tests/gen5/do.expected
new file mode 100644 (file)
index 0000000..7dac5f7
--- /dev/null
+++ b/src/intel/tools/tests/gen5/do.expected
@@ -0,0 +1,3 @@
+26 00 60 00 9c 73 00 20 00 00 8d 00 00 00 8d 00
+26 00 80 00 9c 73 00 20 00 00 8d 00 00 00 8d 00
+26 01 60 00 9c 73 0f 20 04 00 6e 00 04 00 6e 00

diff --git a/src/intel/tools/tests/gen5/dp3.asm b/src/intel/tools/tests/gen5/dp3.asm
new file mode 100644 (file)
index 0000000..4af3bc9
--- /dev/null
+++ b/src/intel/tools/tests/gen5/dp3.asm
@@ -0,0 +1,10 @@
+dp3(8)          m5<1>.xF        g3<0>.xyzzF     g6<4>.xyzzF     { align16 NoDDClr };
+dp3(8)          m5<1>.yF        g3.4<0>.xyzzF   g6<4>.xyzzF     { align16 NoDDClr,NoDDChk };
+dp3(8)          g25<1>.xF       g17<4>.xyzzF    g3<0>.xyzzF     { align16 };
+dp3(8)          g19<1>.xF       g3<0>.xyzzF     g3.4<0>.xyzzF   { align16 NoDDClr };
+dp3(8)          g19<1>.yF       g3<0>.xyzzF     g4<0>.xyzzF     { align16 NoDDClr,NoDDChk };
+dp3(8)          g19<1>.zF       g3<0>.xyzzF     g4.4<0>.xyzzF   { align16 NoDDChk };
+dp3(8)          m5<1>.xF        g4<4>.xyzzF     g5<4>.xyzzF     { align16 };
+dp3.le.f0.0(8)  g18<1>.xF       g17<4>.xyzzF    g3.4<0>.xyzzF   { align16 };
+dp3.sat(8)      g4<1>.xF        g4<4>.xyzzF     g5<4>.xyzzF     { align16 };
+dp3.sat(8)      m5<1>F          g3<4>.xyzzF     g3<4>.xyzzF     { align16 };

diff --git a/src/intel/tools/tests/gen5/dp3.expected b/src/intel/tools/tests/gen5/dp3.expected
new file mode 100644 (file)
index 0000000..01365ea
--- /dev/null
+++ b/src/intel/tools/tests/gen5/dp3.expected
@@ -0,0 +1,10 @@
+56 05 60 00 be 77 a1 20 64 00 0a 00 c4 00 6a 00
+56 0d 60 00 be 77 a2 20 74 00 0a 00 c4 00 6a 00
+56 01 60 00 bd 77 21 23 24 02 6a 00 64 00 0a 00
+56 05 60 00 bd 77 61 22 64 00 0a 00 74 00 0a 00
+56 0d 60 00 bd 77 62 22 64 00 0a 00 84 00 0a 00
+56 09 60 00 bd 77 64 22 64 00 0a 00 94 00 0a 00
+56 01 60 00 be 77 a1 20 84 00 6a 00 a4 00 6a 00
+56 01 60 06 bd 77 41 22 24 02 6a 00 74 00 0a 00
+56 01 60 80 bd 77 81 20 84 00 6a 00 a4 00 6a 00
+56 01 60 80 be 77 af 20 64 00 6a 00 64 00 6a 00

diff --git a/src/intel/tools/tests/gen5/dp4.asm b/src/intel/tools/tests/gen5/dp4.asm
new file mode 100644 (file)
index 0000000..3ea82da
--- /dev/null
+++ b/src/intel/tools/tests/gen5/dp4.asm
@@ -0,0 +1,6 @@
+dp4(8)          g6<1>.xF        g3<4>F          g1<0>F          { align16 };
+dp4(8)          g4<1>.xF        g5<4>F          g1<0>F          { align16 NoDDClr };
+dp4(8)          g4<1>.yF        g5<4>F          g1.4<0>F        { align16 NoDDClr,NoDDChk };
+dp4(8)          g4<1>.wF        g5<4>F          g2.4<0>F        { align16 NoDDChk };
+dp4(8)          m5<1>.xF        g4<4>F          g5<4>F          { align16 };
+dp4.sat(8)      m5<1>F          g3<4>.xF        g3<4>F          { align16 };

diff --git a/src/intel/tools/tests/gen5/dp4.expected b/src/intel/tools/tests/gen5/dp4.expected
new file mode 100644 (file)
index 0000000..cae5f76
--- /dev/null
+++ b/src/intel/tools/tests/gen5/dp4.expected
@@ -0,0 +1,6 @@
+54 01 60 00 bd 77 c1 20 64 00 6e 00 24 00 0e 00
+54 05 60 00 bd 77 81 20 a4 00 6e 00 24 00 0e 00
+54 0d 60 00 bd 77 82 20 a4 00 6e 00 34 00 0e 00
+54 09 60 00 bd 77 88 20 a4 00 6e 00 54 00 0e 00
+54 01 60 00 be 77 a1 20 84 00 6e 00 a4 00 6e 00
+54 01 60 80 be 77 af 20 60 00 60 00 64 00 6e 00

diff --git a/src/intel/tools/tests/gen5/dph.asm b/src/intel/tools/tests/gen5/dph.asm
new file mode 100644 (file)
index 0000000..2992b28
--- /dev/null
+++ b/src/intel/tools/tests/gen5/dph.asm
@@ -0,0 +1,4 @@
+dph(8)          m5<1>.xF        g4<4>.xyzxF     g5<4>F          { align16 };
+dph.sat(8)      m5<1>F          g1<0>.xyzxF     g3<4>F          { align16 };
+dph(8)          g5<1>.xF        g4<4>.xyzxF     g1<0>F          { align16 NoDDClr };
+dph(8)          g5<1>.yF        g4<4>.xyzxF     g1.4<0>F        { align16 NoDDClr,NoDDChk };

diff --git a/src/intel/tools/tests/gen5/dph.expected b/src/intel/tools/tests/gen5/dph.expected
new file mode 100644 (file)
index 0000000..c540092
--- /dev/null
+++ b/src/intel/tools/tests/gen5/dph.expected
@@ -0,0 +1,4 @@
+55 01 60 00 be 77 a1 20 84 00 62 00 a4 00 6e 00
+55 01 60 80 be 77 af 20 24 00 02 00 64 00 6e 00
+55 05 60 00 bd 77 a1 20 84 00 62 00 24 00 0e 00
+55 0d 60 00 bd 77 a2 20 84 00 62 00 34 00 0e 00

diff --git a/src/intel/tools/tests/gen5/else.asm b/src/intel/tools/tests/gen5/else.asm
new file mode 100644 (file)
index 0000000..114c607
--- /dev/null
+++ b/src/intel/tools/tests/gen5/else.asm
@@ -0,0 +1,3 @@
+else(8)         Jump: 86        Pop: 1                          { align1 switch };
+else(16)        Jump: 86        Pop: 1                          { align1 switch };
+else(8)         Jump: 14        Pop: 1                          { align16 switch };

diff --git a/src/intel/tools/tests/gen5/else.expected b/src/intel/tools/tests/gen5/else.expected
new file mode 100644 (file)
index 0000000..1ef88bc
--- /dev/null
+++ b/src/intel/tools/tests/gen5/else.expected
@@ -0,0 +1,3 @@
+24 80 60 00 00 1c 00 34 00 14 60 00 56 00 01 00
+24 80 80 00 00 1c 00 34 00 14 60 00 56 00 01 00
+24 81 60 00 00 1c 0f 34 04 14 6e 00 0e 00 01 00

diff --git a/src/intel/tools/tests/gen5/endif.asm b/src/intel/tools/tests/gen5/endif.asm
new file mode 100644 (file)
index 0000000..48994f7
--- /dev/null
+++ b/src/intel/tools/tests/gen5/endif.asm
@@ -0,0 +1,3 @@
+endif(8)        Pop: 1                                          { align16 switch };
+endif(8)        Pop: 1                                          { align1 switch };
+endif(16)       Pop: 1                                          { align1 switch };

diff --git a/src/intel/tools/tests/gen5/endif.expected b/src/intel/tools/tests/gen5/endif.expected
new file mode 100644 (file)
index 0000000..67335a7
--- /dev/null
+++ b/src/intel/tools/tests/gen5/endif.expected
@@ -0,0 +1,3 @@
+25 81 60 00 84 1c 0f 20 04 00 6e 00 00 00 01 00
+25 80 60 00 84 1c 00 20 00 00 8d 00 00 00 01 00
+25 80 80 00 84 1c 00 20 00 00 8d 00 00 00 01 00

diff --git a/src/intel/tools/tests/gen5/frc.asm b/src/intel/tools/tests/gen5/frc.asm
new file mode 100644 (file)
index 0000000..102fba1
--- /dev/null
+++ b/src/intel/tools/tests/gen5/frc.asm
@@ -0,0 +1,4 @@
+frc.sat(8)      m5<1>F          g3<4>F                          { align16 };
+frc(8)          g7<1>.xF        (abs)g1<0>.xF                   { align16 };
+frc(8)          g4<1>F          g3<8,8,1>F                      { align1 };
+frc(16)         g4<1>F          g6<8,8,1>F                      { align1 compr };

diff --git a/src/intel/tools/tests/gen5/frc.expected b/src/intel/tools/tests/gen5/frc.expected
new file mode 100644 (file)
index 0000000..4bd4f50
--- /dev/null
+++ b/src/intel/tools/tests/gen5/frc.expected
@@ -0,0 +1,4 @@
+43 01 60 80 be 03 af 20 64 00 6e 00 00 00 00 00
+43 01 60 00 bd 03 e1 20 20 20 00 00 00 00 00 00
+43 00 60 00 bd 03 80 20 60 00 8d 00 00 00 00 00
+43 20 80 00 bd 03 80 20 c0 00 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen5/if.asm b/src/intel/tools/tests/gen5/if.asm
new file mode 100644 (file)
index 0000000..e6f832e
--- /dev/null
+++ b/src/intel/tools/tests/gen5/if.asm
@@ -0,0 +1,3 @@
+(+f0.0) if(8)   Jump: 10                                        { align1 switch };
+(+f0.0) if(16)  Jump: 10                                        { align1 switch };
+(+f0.0.x) if(8) Jump: 26                                        { align16 switch };

diff --git a/src/intel/tools/tests/gen5/if.expected b/src/intel/tools/tests/gen5/if.expected
new file mode 100644 (file)
index 0000000..d619976
--- /dev/null
+++ b/src/intel/tools/tests/gen5/if.expected
@@ -0,0 +1,3 @@
+22 80 61 00 00 1c 00 34 00 14 60 00 0a 00 00 00
+22 80 81 00 00 1c 00 34 00 14 60 00 0a 00 00 00
+22 81 62 00 00 1c 0f 34 04 14 6e 00 1a 00 00 00

diff --git a/src/intel/tools/tests/gen5/iff.asm b/src/intel/tools/tests/gen5/iff.asm
new file mode 100644 (file)
index 0000000..6ccc9c4
--- /dev/null
+++ b/src/intel/tools/tests/gen5/iff.asm
@@ -0,0 +1,3 @@
+(+f0.0.x) iff(8) Jump: 22                                       { align16 switch };
+(+f0.0) iff(8)  Jump: 44                                        { align1 switch };
+(+f0.0) iff(16) Jump: 44                                        { align1 switch };

diff --git a/src/intel/tools/tests/gen5/iff.expected b/src/intel/tools/tests/gen5/iff.expected
new file mode 100644 (file)
index 0000000..75a81c3
--- /dev/null
+++ b/src/intel/tools/tests/gen5/iff.expected
@@ -0,0 +1,3 @@
+23 81 62 00 00 1c 0f 34 04 14 6e 00 16 00 00 00
+23 80 61 00 00 1c 00 34 00 14 60 00 2c 00 00 00
+23 80 81 00 00 1c 00 34 00 14 60 00 2c 00 00 00

diff --git a/src/intel/tools/tests/gen5/jmpi.asm b/src/intel/tools/tests/gen5/jmpi.asm
new file mode 100644 (file)
index 0000000..e3dc605
--- /dev/null
+++ b/src/intel/tools/tests/gen5/jmpi.asm
@@ -0,0 +1 @@
+(+f0.0) jmpi(1) 0x00000004UD                                    { align1 nomask };

diff --git a/src/intel/tools/tests/gen5/jmpi.expected b/src/intel/tools/tests/gen5/jmpi.expected
new file mode 100644 (file)
index 0000000..9c2dfcf
--- /dev/null
+++ b/src/intel/tools/tests/gen5/jmpi.expected
@@ -0,0 +1 @@
+20 02 01 00 00 0c 00 34 00 14 00 00 04 00 00 00

diff --git a/src/intel/tools/tests/gen5/mach.asm b/src/intel/tools/tests/gen5/mach.asm
new file mode 100644 (file)
index 0000000..4854911
--- /dev/null
+++ b/src/intel/tools/tests/gen5/mach.asm
@@ -0,0 +1,4 @@
+mach(8)         g3<1>UD         g2<8,8,1>UD     0xaaaaaaabUD    { align1 };
+mach(8)         g2<1>D          g2<8,8,1>D      1431655766D     { align1 };
+mach(16)        g4<1>UD         g12<8,8,1>UD    0xaaaaaaabUD    { align1 compr };
+mach(16)        g4<1>D          g12<8,8,1>D     1431655766D     { align1 compr };

diff --git a/src/intel/tools/tests/gen5/mach.expected b/src/intel/tools/tests/gen5/mach.expected
new file mode 100644 (file)
index 0000000..472d8b0
--- /dev/null
+++ b/src/intel/tools/tests/gen5/mach.expected
@@ -0,0 +1,4 @@
+49 00 60 00 21 0c 60 20 40 00 8d 00 ab aa aa aa
+49 00 60 00 a5 1c 40 20 40 00 8d 00 56 55 55 55
+49 20 80 00 21 0c 80 20 80 01 8d 00 ab aa aa aa
+49 20 80 00 a5 1c 80 20 80 01 8d 00 56 55 55 55

diff --git a/src/intel/tools/tests/gen5/mov.asm b/src/intel/tools/tests/gen5/mov.asm
new file mode 100644 (file)
index 0000000..d441898
--- /dev/null
+++ b/src/intel/tools/tests/gen5/mov.asm
@@ -0,0 +1,103 @@
+mov(8)          m2<1>UD         g1<8,8,1>UD                     { align1 nomask };
+mov(8)          g9<1>.xyzUD     0x00000000UD                    { align16 };
+mov.sat(8)      m5<1>F          g4<4>F                          { align16 };
+mov(8)          m4<1>F          g6<4>F                          { align16 };
+mov(8)          m2<1>UD         g9<4>UD                         { align16 };
+mov(8)          m3<1>F          g4.3<0,1,0>F                    { align1 };
+mov(16)         m3<1>F          g4.3<0,1,0>F                    { align1 compr4 };
+mov(8)          g2<1>F          g2<8,8,1>UW                     { align1 };
+mov(8)          g2<1>D          g2<8,8,1>F                      { align1 };
+mov(8)          g2<1>F          g2<8,8,1>D                      { align1 };
+mov(16)         g12<1>F         g4<8,8,1>UW                     { align1 compr };
+mov(16)         g4<1>D          g12<8,8,1>F                     { align1 compr };
+mov(16)         g12<1>F         g4<8,8,1>D                      { align1 compr };
+mov(8)          m2<1>UD         0x00000000UD                    { align16 };
+mov(8)          m4<1>F          0x0F             /* 0F */       { align1 };
+mov(16)         m3<1>F          0x0F             /* 0F */       { align1 compr4 };
+mov(8)          g2<1>.xD        224D                            { align16 };
+mov(8)          m15<1>D         g2<4>.xUD                       { align16 };
+mov(8)          g12<1>D         0D                              { align1 };
+mov(8)          m2<1>UD         0x00000000UD                    { align1 };
+mov(16)         g14<1>D         0D                              { align1 compr };
+mov(16)         m2<1>UD         0x00000000UD                    { align1 compr };
+mov(8)          g5<1>.xyF       0x3000VF        /* [0F, 1F, 0F, 0F]VF */ { align16 };
+mov(8)          g4<1>.xyD       g2<4>.xyyyD                     { align16 };
+mov(8)          m4<1>D          g9.3<0,1,0>D                    { align1 };
+mov(8)          m5<1>UD         0D                              { align1 };
+mov(8)          m2<1>D          g2<8,8,1>F                      { align1 };
+mov(16)         m6<1>D          g9.3<0,1,0>D                    { align1 compr };
+mov(16)         m8<1>UD         0D                              { align1 compr };
+mov(16)         m2<1>D          g4<8,8,1>F                      { align1 compr };
+mov.sat(8)      m3<1>F          g2<0,1,0>F                      { align1 };
+mov.sat(16)     m3<1>F          g2<0,1,0>F                      { align1 compr4 };
+mov(8)          m5<1>.wD        0D                              { align16 NoDDChk };
+mov(8)          m3<1>F          0x42fc6666F      /* 126.2F */   { align1 sechalf };
+mov(8)          m5<1>.wD        g8<4>.wD                        { align16 NoDDChk };
+mov(8)          g6<1>.xD        g6<4>.xF                        { align16 };
+mov(8)          m3<1>UD         g2<8,8,1>UD                     { align1 };
+mov(16)         m3<1>UD         g4<8,8,1>UD                     { align1 compr4 };
+mov(8)          m5<1>F          0x28000030VF    /* [1F, 0F, 0F, 0.75F]VF */ { align16 };
+mov(8)          m6<1>.xF        0x0F             /* 0F */       { align16 };
+mov(8)          m3<1>F          g2<8,8,1>D                      { align1 };
+mov(8)          m5<1>.xF        g1<0>.xD                        { align16 NoDDClr };
+mov(8)          m5<1>.yF        g3<4>.xD                        { align16 NoDDClr,NoDDChk };
+mov(8)          m5<1>.wF        g3<4>.xD                        { align16 NoDDChk };
+mov(8)          g3<1>.xF        g3<4>.xD                        { align16 NoDDClr };
+mov(8)          g3<1>.yF        g4<4>.xD                        { align16 NoDDClr,NoDDChk };
+mov(8)          g3<1>.wF        g4<4>.xD                        { align16 NoDDChk };
+mov(8)          g8<1>UD         g2<4>UD                         { align16 };
+mov(8)          g7<1>.xF        g3<0>.xD                        { align16 };
+mov(8)          g6<1>.xF        -g5<4>.yF                       { align16 NoDDClr };
+mov(8)          g6<1>.yD        g5<4>.xD                        { align16 NoDDChk };
+mov(8)          m2<1>D          g3<0>.xD                        { align16 };
+mov.nz.f0.0(8)  g4<1>F          -(abs)g2<0,1,0>F                { align1 };
+(+f0.0) mov(8)  g4<1>F          0xbf800000F      /* -1F */      { align1 };
+mov.nz.f0.0(16) g4<1>F          -(abs)g2<0,1,0>F                { align1 compr };
+(+f0.0) mov(16) g4<1>F          0xbf800000F      /* -1F */      { align1 compr };
+mov(8)          g3<1>.xyzF      0x0F             /* 0F */       { align16 };
+mov(8)          g3<1>.xyD       g2<4>.xyyyD                     { align16 NoDDClr };
+mov.sat(8)      m5<1>.wF        g20<4>.wF                       { align16 NoDDChk };
+mov(8)          g26<1>.xyzUD    0x00000000UD                    { align16 NoDDClr };
+mov(8)          g21<1>.xD       1065353216D                     { align16 NoDDClr };
+mov(8)          g5<1>.zwD       0D                              { align16 NoDDChk };
+mov(16)         m4<1>F          g4<8,8,1>D                      { align1 compr4 };
+mov(8)          g3<1>D          g2<8,8,1>D                      { align1 };
+mov(16)         g6<1>D          g4<8,8,1>D                      { align1 compr };
+mov(8)          m3<1>F          g4<8,8,1>F                      { align1 nomask };
+mov(8)          m15<1>F         g6<8,8,1>F                      { align1 sechalf };
+mov.sat(8)      m5<1>.zF        0x3eaaaaabF      /* 0.333333F */ { align16 };
+mov.sat(8)      m5<1>.wF        0x3dcccccdF      /* 0.1F */     { align16 NoDDClr };
+mov(8)          m5<1>.xyF       0x2030VF        /* [1F, 0.5F, 0F, 0F]VF */ { align16 NoDDChk };
+mov.sat(8)      m5<1>F          g4<4>D                          { align16 };
+mov(8)          g10<1>F         g10<8,8,1>F                     { align1 };
+mov(8)          g11<1>F         g4<8,8,1>F                      { align1 sechalf };
+mov.sat(8)      m5<1>.zF        0x3f666660F      /* 0.9F */     { align16 NoDDClr,NoDDChk };
+mov.sat(8)      m5<1>.wF        0x3e4cccc0F      /* 0.2F */     { align16 NoDDChk };
+mov(16)         g10<1>F         g2<0,1,0>F                      { align1 compr };
+mov(8)          g5<1>F          0x3f800000F      /* 1F */       { align1 };
+mov(16)         g10<1>F         0x3f800000F      /* 1F */       { align1 compr };
+mov(8)          g3<1>.zD        g1<0>.xD                        { align16 NoDDClr,NoDDChk };
+mov(1)          m14<1>D         96D                             { align1 nomask };
+mov(1)          m15<1>D         g5<0,1,0>D                      { align1 nomask };
+mov(8)          g33<1>.zD       1053609165D                     { align16 NoDDClr,NoDDChk };
+mov(8)          g2<1>.xyzF      g2<4>.wF                        { align16 };
+mov.nz.f0.0(8)  null<1>D        g2<8,8,1>D                      { align1 };
+mov.nz.f0.0(16) null<1>D        g4<8,8,1>D                      { align1 compr };
+mov(8)          m2<1>.zwF       0D                              { align16 };
+mov(8)          m5<1>.xD        1036831949D                     { align16 };
+mov(8)          m5<1>.yD        1045220557D                     { align16 NoDDClr };
+mov(8)          m5<1>.zD        1050253722D                     { align16 NoDDClr,NoDDChk };
+mov(1)          f0.1<1>UW       g0<0,1,0>UW                     { align1 nomask };
+mov(1)          g0<1>UW         f0.1<0,1,0>UW                   { align1 nomask };
+(+f0.0.any4h) mov(8) g3<1>.xD   -1D                             { align16 };
+mov.sat(8)      m5<1>.yzF       g1<0>.xxzzF                     { align16 NoDDClr };
+mov(8)          m5<1>F          g3<4>D                          { align16 };
+mov.sat(8)      m5<1>.xF        g5<4>.xD                        { align16 NoDDClr };
+mov.sat(8)      m5<1>.yF        g5<4>.xD                        { align16 NoDDClr,NoDDChk };
+mov.sat(8)      m5<1>.wF        g5<4>.xD                        { align16 NoDDChk };
+mov(8)          g4<1>D          0x7e767676VF    /* [22F, 22F, 22F, 30F]VF */ { align16 };
+mov(8)          g5<1>F          g3<4>UD                         { align16 };
+mov(8)          m5<1>.xyzF      0x3000VF        /* [0F, 1F, 0F, 0F]VF */ { align16 NoDDClr };
+mov.nz.f0.0(8)  null<1>.xD      g8<4>.xD                        { align16 };
+mov.nz.f0.0(8)  g8<1>F          -(abs)g1<0>F                    { align16 };
+(+f0.0) mov(8)  g8<1>F          0xbf800000F      /* -1F */      { align16 };

diff --git a/src/intel/tools/tests/gen5/mov.expected b/src/intel/tools/tests/gen5/mov.expected
new file mode 100644 (file)
index 0000000..ab3947c
--- /dev/null
+++ b/src/intel/tools/tests/gen5/mov.expected
@@ -0,0 +1,103 @@
+01 02 60 00 22 00 40 20 20 00 8d 00 00 00 00 00
+01 01 60 00 61 00 27 21 00 00 00 00 00 00 00 00
+01 01 60 80 be 03 af 20 84 00 6e 00 00 00 00 00
+01 01 60 00 be 03 8f 20 c4 00 6e 00 00 00 00 00
+01 01 60 00 22 00 4f 20 24 01 6e 00 00 00 00 00
+01 00 60 00 be 03 60 20 8c 00 00 00 00 00 00 00
+01 20 80 00 be 03 60 30 8c 00 00 00 00 00 00 00
+01 00 60 00 3d 01 40 20 40 00 8d 00 00 00 00 00
+01 00 60 00 a5 03 40 20 40 00 8d 00 00 00 00 00
+01 00 60 00 bd 00 40 20 40 00 8d 00 00 00 00 00
+01 20 80 00 3d 01 80 21 80 00 8d 00 00 00 00 00
+01 20 80 00 a5 03 80 20 80 01 8d 00 00 00 00 00
+01 20 80 00 bd 00 80 21 80 00 8d 00 00 00 00 00
+01 01 60 00 62 00 4f 20 00 00 00 00 00 00 00 00
+01 00 60 00 fe 73 80 20 00 00 00 00 00 00 00 00
+01 20 80 00 fe 73 60 30 00 00 00 00 00 00 00 00
+01 01 60 00 e5 10 41 20 00 00 00 00 e0 00 00 00
+01 01 60 00 26 00 ef 21 40 00 60 00 00 00 00 00
+01 00 60 00 e5 10 80 21 00 00 00 00 00 00 00 00
+01 00 60 00 62 00 40 20 00 00 00 00 00 00 00 00
+01 20 80 00 e5 10 c0 21 00 00 00 00 00 00 00 00
+01 20 80 00 62 00 40 20 00 00 00 00 00 00 00 00
+01 01 60 00 fd 52 a3 20 00 00 00 00 00 30 00 00
+01 01 60 00 a5 00 83 20 44 00 65 00 00 00 00 00
+01 00 60 00 a6 00 80 20 2c 01 00 00 00 00 00 00
+01 00 60 00 e2 10 a0 20 00 00 00 00 00 00 00 00
+01 00 60 00 a6 03 40 20 40 00 8d 00 00 00 00 00
+01 20 80 00 a6 00 c0 20 2c 01 00 00 00 00 00 00
+01 20 80 00 e2 10 00 21 00 00 00 00 00 00 00 00
+01 20 80 00 a6 03 40 20 80 00 8d 00 00 00 00 00
+01 00 60 80 be 03 60 20 40 00 00 00 00 00 00 00
+01 20 80 80 be 03 60 30 40 00 00 00 00 00 00 00
+01 09 60 00 e6 10 a8 20 00 00 00 00 00 00 00 00
+01 10 60 00 fe 73 60 20 00 00 00 00 66 66 fc 42
+01 09 60 00 a6 00 a8 20 0f 01 6f 00 00 00 00 00
+01 01 60 00 a5 03 c1 20 c0 00 60 00 00 00 00 00
+01 00 60 00 22 00 60 20 40 00 8d 00 00 00 00 00
+01 20 80 00 22 00 60 30 80 00 8d 00 00 00 00 00
+01 01 60 00 fe 52 af 20 00 00 00 00 30 00 00 28
+01 01 60 00 fe 73 c1 20 00 00 00 00 00 00 00 00
+01 00 60 00 be 00 60 20 40 00 8d 00 00 00 00 00
+01 05 60 00 be 00 a1 20 20 00 00 00 00 00 00 00
+01 0d 60 00 be 00 a2 20 60 00 60 00 00 00 00 00
+01 09 60 00 be 00 a8 20 60 00 60 00 00 00 00 00
+01 05 60 00 bd 00 61 20 60 00 60 00 00 00 00 00
+01 0d 60 00 bd 00 62 20 80 00 60 00 00 00 00 00
+01 09 60 00 bd 00 68 20 80 00 60 00 00 00 00 00
+01 01 60 00 21 00 0f 21 44 00 6e 00 00 00 00 00
+01 01 60 00 bd 00 e1 20 60 00 00 00 00 00 00 00
+01 05 60 00 bd 03 c1 20 a5 40 65 00 00 00 00 00
+01 09 60 00 a5 00 c2 20 a0 00 60 00 00 00 00 00
+01 01 60 00 a6 00 4f 20 60 00 00 00 00 00 00 00
+01 00 60 02 bd 03 80 20 40 60 00 00 00 00 00 00
+01 00 61 00 fd 73 80 20 00 00 00 00 00 00 80 bf
+01 20 80 02 bd 03 80 20 40 60 00 00 00 00 00 00
+01 20 81 00 fd 73 80 20 00 00 00 00 00 00 80 bf
+01 01 60 00 fd 73 67 20 00 00 00 00 00 00 00 00
+01 05 60 00 a5 00 63 20 44 00 65 00 00 00 00 00
+01 09 60 80 be 03 a8 20 8f 02 6f 00 00 00 00 00
+01 05 60 00 61 00 47 23 00 00 00 00 00 00 00 00
+01 05 60 00 e5 10 a1 22 00 00 00 00 00 00 80 3f
+01 09 60 00 e5 10 ac 20 00 00 00 00 00 00 00 00
+01 20 80 00 be 00 80 30 80 00 8d 00 00 00 00 00
+01 00 60 00 a5 00 60 20 40 00 8d 00 00 00 00 00
+01 20 80 00 a5 00 c0 20 80 00 8d 00 00 00 00 00
+01 02 60 00 be 03 60 20 80 00 8d 00 00 00 00 00
+01 10 60 00 be 03 e0 21 c0 00 8d 00 00 00 00 00
+01 01 60 80 fe 73 a4 20 00 00 00 00 ab aa aa 3e
+01 05 60 80 fe 73 a8 20 00 00 00 00 cd cc cc 3d
+01 09 60 00 fe 52 a3 20 00 00 00 00 30 20 00 00
+01 01 60 80 be 00 af 20 84 00 6e 00 00 00 00 00
+01 00 60 00 bd 03 40 21 40 01 8d 00 00 00 00 00
+01 10 60 00 bd 03 60 21 80 00 8d 00 00 00 00 00
+01 0d 60 80 fe 73 a4 20 00 00 00 00 60 66 66 3f
+01 09 60 80 fe 73 a8 20 00 00 00 00 c0 cc 4c 3e
+01 20 80 00 bd 03 40 21 40 00 00 00 00 00 00 00
+01 00 60 00 fd 73 a0 20 00 00 00 00 00 00 80 3f
+01 20 80 00 fd 73 40 21 00 00 00 00 00 00 80 3f
+01 0d 60 00 a5 00 64 20 20 00 00 00 00 00 00 00
+01 02 00 00 e6 10 c0 21 00 00 00 00 60 00 00 00
+01 02 00 00 a6 00 e0 21 a0 00 00 00 00 00 00 00
+01 0d 60 00 e5 10 24 24 00 00 00 00 cd cc cc 3e
+01 01 60 00 bd 03 47 20 4f 00 6f 00 00 00 00 00
+01 00 60 02 a4 00 00 20 40 00 8d 00 00 00 00 00
+01 20 80 02 a4 00 00 20 80 00 8d 00 00 00 00 00
+01 01 60 00 fe 10 4c 20 00 00 00 00 00 00 00 00
+01 01 60 00 e6 10 a1 20 00 00 00 00 cd cc cc 3d
+01 05 60 00 e6 10 a2 20 00 00 00 00 cd cc 4c 3e
+01 0d 60 00 e6 10 a4 20 00 00 00 00 9a 99 99 3e
+01 02 00 00 28 01 02 26 00 00 00 00 00 00 00 00
+01 02 00 00 09 01 00 20 02 06 00 00 00 00 00 00
+01 01 66 00 e5 10 61 20 00 00 00 00 ff ff ff ff
+01 05 60 80 be 03 a6 20 20 00 0a 00 00 00 00 00
+01 01 60 00 be 00 af 20 64 00 6e 00 00 00 00 00
+01 05 60 80 be 00 a1 20 a0 00 60 00 00 00 00 00
+01 0d 60 80 be 00 a2 20 a0 00 60 00 00 00 00 00
+01 09 60 80 be 00 a8 20 a0 00 60 00 00 00 00 00
+01 01 60 00 e5 52 8f 20 00 00 00 00 76 76 76 7e
+01 01 60 00 3d 00 af 20 64 00 6e 00 00 00 00 00
+01 05 60 00 fe 52 a7 20 00 00 00 00 00 30 00 00
+01 01 60 02 a4 00 01 20 00 01 60 00 00 00 00 00
+01 01 60 02 bd 03 0f 21 24 60 0e 00 00 00 00 00
+01 01 61 00 fd 73 0f 21 00 00 00 00 00 00 80 bf

diff --git a/src/intel/tools/tests/gen5/mul.asm b/src/intel/tools/tests/gen5/mul.asm
new file mode 100644 (file)
index 0000000..06998c2
--- /dev/null
+++ b/src/intel/tools/tests/gen5/mul.asm
@@ -0,0 +1,35 @@
+mul(8)          m3<1>F          g3<8,8,1>F      g2<8,8,1>F      { align1 };
+mul(16)         m3<1>F          g10<8,8,1>F     g12<8,8,1>F     { align1 compr4 };
+mul(8)          g8<1>.xyzF      g6<4>.xyzzF     g8<4>.wF        { align16 };
+mul(8)          g9<1>.wUD       g7<4>.wF        0x45000000F  /* 2048F */ { align16 };
+mul(8)          g2<1>F          g2<8,8,1>F      g6.3<0,1,0>F    { align1 };
+mul(16)         g10<1>F         g12<8,8,1>F     g6.3<0,1,0>F    { align1 compr };
+mul(8)          g2<1>.xD        g2<4>.xD        g1<0>.xD        { align16 };
+mul(8)          g5<1>F          g3<8,8,1>F      0x41800000F  /* 16F */ { align1 };
+mul(8)          m3<1>F          g8<8,8,1>F      0x3b800000F  /* 0.00390625F */ { align1 };
+mul(16)         g22<1>F         g16<8,8,1>F     0x41800000F  /* 16F */ { align1 compr };
+mul(16)         m3<1>F          g6<8,8,1>F      0x3b800000F  /* 0.00390625F */ { align1 compr4 };
+mul(8)          m5<1>.xyF       g3<4>.xyyyF     0x3f000000F  /* 0.5F */ { align16 NoDDClr };
+mul(8)          g5<1>F          g3<4>F          0x37800000F  /* 1.52588e-05F */ { align16 };
+mul.sat(8)      m2<1>F          g6<8,8,1>F      g2<8,8,1>F      { align1 };
+mul.sat(16)     m2<1>F          g14<8,8,1>F     g6<8,8,1>F      { align1 compr };
+mul.sat(8)      g8<1>F          g7<8,8,1>F      g3<8,8,1>F      { align1 };
+mul.sat(16)     g18<1>F         g16<8,8,1>F     g14<8,8,1>F     { align1 compr };
+mul(8)          acc0<1>UD       g2<8,8,1>UD     0xaaaaaaabUD    { align1 };
+mul(8)          g3<1>D          g4<8,8,1>D      g3<8,8,1>D      { align1 };
+mul(8)          acc0<1>D        g2<8,8,1>D      1431655766D     { align1 };
+mul(16)         acc0<1>UD       g12<8,8,1>UD    0xaaaaaaabUD    { align1 compr };
+mul(16)         g4<1>D          g16<8,8,1>D     g8<8,8,1>D      { align1 compr };
+mul(16)         acc0<1>D        g12<8,8,1>D     1431655766D     { align1 compr };
+mul(8)          g26<1>.wUD      g29<4>.wF       0x45000000F  /* 2048F */ { align16 NoDDChk };
+mul(8)          g2<1>.xyzF      g2<4>.wF        0x40404830VF /* [1F, 3F, 2F, 2F]VF */ { align16 };
+mul(8)          g3<1>D          g2<0,1,0>UW     g2.2<0,1,0>D    { align1 };
+mul(16)         g4<1>D          g2<0,1,0>UW     g2.2<0,1,0>D    { align1 compr };
+mul(8)          m5<1>F          g3<4>F          0x3f000000F  /* 0.5F */ { align16 };
+mul.sat(8)      m5<1>F          g6<4>F          0x3b800000F  /* 0.00390625F */ { align16 };
+mul(8)          g5<1>.xD        g5<4>.xD        32D             { align16 };
+mul.sat(8)      m5<1>F          g3<4>F          g3<4>F          { align16 };
+mul.sat(8)      m6<1>.xyzF      g32<4>.xF       g30<4>.xyzzF    { align16 NoDDClr };
+mul.sat(8)      m5<1>F          g4<4>F          0x20303030VF /* [1F, 1F, 1F, 0.5F]VF */ { align16 };
+mul(8)          m6<1>.xyzF      g12<4>.xyzzF    g13<4>.xF       { align16 NoDDClr };
+mul.sat(8)      m5<1>.xyzF      g7<4>.xF        0x3030VF /* [1F, 1F, 0F, 0F]VF */ { align16 NoDDClr };

diff --git a/src/intel/tools/tests/gen5/mul.expected b/src/intel/tools/tests/gen5/mul.expected
new file mode 100644 (file)
index 0000000..d2a3e29
--- /dev/null
+++ b/src/intel/tools/tests/gen5/mul.expected
@@ -0,0 +1,35 @@
+41 00 60 00 be 77 60 20 60 00 8d 00 40 00 8d 00
+41 20 80 00 be 77 60 30 40 01 8d 00 80 01 8d 00
+41 01 60 00 bd 77 07 21 c4 00 6a 00 0f 01 6f 00
+41 01 60 00 a1 7f 28 21 ef 00 6f 00 00 00 00 45
+41 00 60 00 bd 77 40 20 40 00 8d 00 cc 00 00 00
+41 20 80 00 bd 77 40 21 80 01 8d 00 cc 00 00 00
+41 01 60 00 a5 14 41 20 40 00 60 00 20 00 00 00
+41 00 60 00 bd 7f a0 20 60 00 8d 00 00 00 80 41
+41 00 60 00 be 7f 60 20 00 01 8d 00 00 00 80 3b
+41 20 80 00 bd 7f c0 22 00 02 8d 00 00 00 80 41
+41 20 80 00 be 7f 60 30 c0 00 8d 00 00 00 80 3b
+41 05 60 00 be 7f a3 20 64 00 65 00 00 00 00 3f
+41 01 60 00 bd 7f af 20 64 00 6e 00 00 00 80 37
+41 00 60 80 be 77 40 20 c0 00 8d 00 40 00 8d 00
+41 20 80 80 be 77 40 20 c0 01 8d 00 c0 00 8d 00
+41 00 60 80 bd 77 00 21 e0 00 8d 00 60 00 8d 00
+41 20 80 80 bd 77 40 22 00 02 8d 00 c0 01 8d 00
+41 00 60 00 20 0c 00 24 40 00 8d 00 ab aa aa aa
+41 00 60 00 a5 14 60 20 80 00 8d 00 60 00 8d 00
+41 00 60 00 a4 1c 00 24 40 00 8d 00 56 55 55 55
+41 20 80 00 20 0c 00 24 80 01 8d 00 ab aa aa aa
+41 20 80 00 a5 14 80 20 00 02 8d 00 00 01 8d 00
+41 20 80 00 a4 1c 00 24 80 01 8d 00 56 55 55 55
+41 09 60 00 a1 7f 48 23 af 03 6f 00 00 00 00 45
+41 01 60 00 bd 5f 47 20 4f 00 6f 00 30 48 40 40
+41 00 60 00 25 15 60 20 40 00 00 00 48 00 00 00
+41 20 80 00 25 15 80 20 40 00 00 00 48 00 00 00
+41 01 60 00 be 7f af 20 64 00 6e 00 00 00 00 3f
+41 01 60 80 be 7f af 20 c4 00 6e 00 00 00 80 3b
+41 01 60 00 a5 1c a1 20 a0 00 60 00 20 00 00 00
+41 01 60 80 be 77 af 20 64 00 6e 00 64 00 6e 00
+41 05 60 80 be 77 c7 20 00 04 60 00 c4 03 6a 00
+41 01 60 80 be 5f af 20 84 00 6e 00 30 30 30 20
+41 05 60 00 be 77 c7 20 84 01 6a 00 a0 01 60 00
+41 05 60 80 be 5f a7 20 e0 00 60 00 30 30 00 00

diff --git a/src/intel/tools/tests/gen5/not.asm b/src/intel/tools/tests/gen5/not.asm
new file mode 100644 (file)
index 0000000..699da8b
--- /dev/null
+++ b/src/intel/tools/tests/gen5/not.asm
@@ -0,0 +1,2 @@
+not(8)          g2<1>D          -g2<8,8,1>D                     { align1 };
+not(16)         g4<1>D          -g6<8,8,1>D                     { align1 compr };

diff --git a/src/intel/tools/tests/gen5/not.expected b/src/intel/tools/tests/gen5/not.expected
new file mode 100644 (file)
index 0000000..dae1423
--- /dev/null
+++ b/src/intel/tools/tests/gen5/not.expected
@@ -0,0 +1,2 @@
+04 00 60 00 a5 00 40 20 40 40 8d 00 00 00 00 00
+04 20 80 00 a5 00 80 20 c0 40 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen5/or.asm b/src/intel/tools/tests/gen5/or.asm
new file mode 100644 (file)
index 0000000..aa482dc
--- /dev/null
+++ b/src/intel/tools/tests/gen5/or.asm
@@ -0,0 +1,7 @@
+or(8)           g3<1>UD         g3<8,8,1>UD     g5<8,8,1>UD     { align1 };
+or(8)           g9<1>.xUD       g10<4>.xUD      g9<4>.xUD       { align16 };
+(+f0.0) or(8)   g8<1>UD         g8<8,8,1>UD     0x3f800000UD    { align1 };
+or(16)          g12<1>UD        g14<8,8,1>UD    g20<8,8,1>UD    { align1 compr };
+(+f0.0) or(16)  g12<1>UD        g12<8,8,1>UD    0x3f800000UD    { align1 compr };
+(+f0.0) or(8)   g17<1>.xUD      g17<4>.xUD      0x3f800000UD    { align16 };
+or(8)           m2<1>.wUD       g8<4>.xUD       g11<4>.xUD      { align16 };

diff --git a/src/intel/tools/tests/gen5/or.expected b/src/intel/tools/tests/gen5/or.expected
new file mode 100644 (file)
index 0000000..4d56bda
--- /dev/null
+++ b/src/intel/tools/tests/gen5/or.expected
@@ -0,0 +1,7 @@
+06 00 60 00 21 04 60 20 60 00 8d 00 a0 00 8d 00
+06 01 60 00 21 04 21 21 40 01 60 00 20 01 60 00
+06 00 61 00 21 0c 00 21 00 01 8d 00 00 00 80 3f
+06 20 80 00 21 04 80 21 c0 01 8d 00 80 02 8d 00
+06 20 81 00 21 0c 80 21 80 01 8d 00 00 00 80 3f
+06 01 61 00 21 0c 21 22 20 02 60 00 00 00 80 3f
+06 01 60 00 22 04 48 20 00 01 60 00 60 01 60 00

diff --git a/src/intel/tools/tests/gen5/pln.asm b/src/intel/tools/tests/gen5/pln.asm
new file mode 100644 (file)
index 0000000..e730b2d
--- /dev/null
+++ b/src/intel/tools/tests/gen5/pln.asm
@@ -0,0 +1,4 @@
+pln(8)          g2<1>F          g3.4<0,1,0>F    g8<8,8,1>F      { align1 };
+pln(16)         g10<1>F         g3.4<0,1,0>F    g6<8,8,1>F      { align1 compr };
+pln(8)          m4<1>F          g5.4<0,1,0>F    g6<8,8,1>F      { align1 };
+pln(16)         m4<1>F          g5.4<0,1,0>F    g6<8,8,1>F      { align1 compr4 };

diff --git a/src/intel/tools/tests/gen5/pln.expected b/src/intel/tools/tests/gen5/pln.expected
new file mode 100644 (file)
index 0000000..7f4987f
--- /dev/null
+++ b/src/intel/tools/tests/gen5/pln.expected
@@ -0,0 +1,4 @@
+5a 00 60 00 bd 77 40 20 70 00 00 00 00 01 8d 00
+5a 20 80 00 bd 77 40 21 70 00 00 00 c0 00 8d 00
+5a 00 60 00 be 77 80 20 b0 00 00 00 c0 00 8d 00
+5a 20 80 00 be 77 80 30 b0 00 00 00 c0 00 8d 00

diff --git a/src/intel/tools/tests/gen5/rndd.asm b/src/intel/tools/tests/gen5/rndd.asm
new file mode 100644 (file)
index 0000000..4dff954
--- /dev/null
+++ b/src/intel/tools/tests/gen5/rndd.asm
@@ -0,0 +1,6 @@
+rndd(8)         g3<1>F          g5<8,8,1>F                      { align1 };
+rndd(16)        g16<1>F         g24<8,8,1>F                     { align1 compr };
+rndd(8)         g6<1>.xF        g1<0>.xF                        { align16 };
+rndd(8)         g6<1>.xF        (abs)g1<0>.xF                   { align16 NoDDClr };
+rndd(8)         g6<1>.yF        g7<4>.xF                        { align16 NoDDClr,NoDDChk };
+rndd.sat(8)     m5<1>F          g4<4>F                          { align16 };

diff --git a/src/intel/tools/tests/gen5/rndd.expected b/src/intel/tools/tests/gen5/rndd.expected
new file mode 100644 (file)
index 0000000..ad38448
--- /dev/null
+++ b/src/intel/tools/tests/gen5/rndd.expected
@@ -0,0 +1,6 @@
+45 00 60 00 bd 03 60 20 a0 00 8d 00 00 00 00 00
+45 20 80 00 bd 03 00 22 00 03 8d 00 00 00 00 00
+45 01 60 00 bd 03 c1 20 20 00 00 00 00 00 00 00
+45 05 60 00 bd 03 c1 20 20 20 00 00 00 00 00 00
+45 0d 60 00 bd 03 c2 20 e0 00 60 00 00 00 00 00
+45 01 60 80 be 03 af 20 84 00 6e 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen5/sel.asm b/src/intel/tools/tests/gen5/sel.asm
new file mode 100644 (file)
index 0000000..a97923f
--- /dev/null
+++ b/src/intel/tools/tests/gen5/sel.asm
@@ -0,0 +1,34 @@
+(+f0.0) sel(8)  g6<1>F          g3<8,8,1>F      0x0F  /* 0F */  { align1 };
+(-f0.0) sel(8)  g2<1>UD         g2<8,8,1>UD     0x00000000UD    { align1 };
+(+f0.0) sel(16) g10<1>F         g6<8,8,1>F      0x0F  /* 0F */  { align1 compr };
+(-f0.0) sel(16) g4<1>UD         g6<8,8,1>UD     0x00000000UD    { align1 compr };
+(+f0.0) sel(8)  g4<1>.yF        g5<4>.xF        0x0F  /* 0F */  { align16 };
+(-f0.0.z) sel(8) g4<1>.zUD      g6<4>.xUD       0x00000000UD    { align16 };
+(+f0.0) sel(8)  g2<1>F          (abs)g4<8,8,1>F (abs)g3<8,8,1>F { align1 };
+(+f0.0) sel(16) g4<1>F          (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
+(+f0.0) sel(8)  g2<1>UD         g5<8,8,1>UD     g6<8,8,1>UD     { align1 };
+(+f0.0) sel(8)  m3<1>UD         g4<8,8,1>UD     g2<8,8,1>UD     { align1 };
+(+f0.0) sel(16) g4<1>UD         g12<8,8,1>UD    g14<8,8,1>UD    { align1 compr };
+(+f0.0) sel(16) m3<1>UD         g10<8,8,1>UD    g4<8,8,1>UD     { align1 compr4 };
+(+f0.0) sel.sat(8) m5<1>F       g3<4>F          0x3f000000F  /* 0.5F */ { align16 };
+(+f0.0) sel(8)  m7<1>UD         g2<8,8,1>UD     0x3f000000UD    { align1 };
+(+f0.0) sel(16) m11<1>UD        g4<8,8,1>UD     0x3f000000UD    { align1 compr };
+(+f0.0) sel(8)  g15<1>UD        g16<4>UD        g15<4>UD        { align16 };
+(+f0.0) sel.sat(8) m5<1>F       g1<0>F          g3<4>F          { align16 };
+(-f0.0.x) sel(8) g17<1>.xUD     g17<4>.xUD      0x00000000UD    { align16 };
+(+f0.0) sel(8)  m4<1>F          g3<8,8,1>F      g4<8,8,1>F      { align1 };
+(+f0.0) sel(16) m4<1>F          g4<8,8,1>F      g6<8,8,1>F      { align1 compr4 };
+(-f0.0) sel(8)  m5<1>UD         g2<8,8,1>UD     0x00000000UD    { align1 };
+(-f0.0) sel(16) m5<1>UD         g6<8,8,1>UD     0x00000000UD    { align1 compr4 };
+(+f0.0.any4h) sel(8) g4<1>UD    g4<4>UD         g5<4>UD         { align16 };
+(+f0.0) sel(8)  g3<1>.xyUD      g3<4>.xyyyUD    0x3e4ccccdUD    { align16 };
+(+f0.0.x) sel(8) g4<1>.xD       -g4<4>.xD       0D              { align16 };
+(+f0.0) sel(8)  g2<1>D          -g2<8,8,1>D     -1D             { align1 };
+(+f0.0) sel(16) g4<1>D          -g6<8,8,1>D     -1D             { align1 compr };
+(+f0.0) sel(8)  m3<1>F          g2<8,8,1>F      0x3f800000F  /* 1F */ { align1 };
+(+f0.0) sel(16) m3<1>F          g4<8,8,1>F      0x3f800000F  /* 1F */ { align1 compr4 };
+(+f0.0.x) sel(8) g3<1>.xUD      g3<4>.xUD       0x3e4ccccdUD    { align16 };
+(+f0.0) sel(8)  g3<1>UD         g2.1<0,1,0>UD   0x40800000UD    { align1 };
+(+f0.0) sel(16) g4<1>UD         g2.1<0,1,0>UD   0x40800000UD    { align1 compr };
+(+f0.0.all4h) sel(8) g6<1>UD    g6<4>UD         g7<4>UD         { align16 };
+(+f0.0.x) sel(8) g8<1>.xUD      g3<0>.wUD       g3<0>.zUD       { align16 };

diff --git a/src/intel/tools/tests/gen5/sel.expected b/src/intel/tools/tests/gen5/sel.expected
new file mode 100644 (file)
index 0000000..8d4449a
--- /dev/null
+++ b/src/intel/tools/tests/gen5/sel.expected
@@ -0,0 +1,34 @@
+02 00 61 00 bd 7f c0 20 60 00 8d 00 00 00 00 00
+02 00 71 00 21 0c 40 20 40 00 8d 00 00 00 00 00
+02 20 81 00 bd 7f 40 21 c0 00 8d 00 00 00 00 00
+02 20 91 00 21 0c 80 20 c0 00 8d 00 00 00 00 00
+02 01 61 00 bd 7f 82 20 a0 00 60 00 00 00 00 00
+02 01 74 00 21 0c 84 20 c0 00 60 00 00 00 00 00
+02 00 61 00 bd 77 40 20 80 20 8d 00 60 20 8d 00
+02 20 81 00 bd 77 80 20 00 22 8d 00 00 21 8d 00
+02 00 61 00 21 04 40 20 a0 00 8d 00 c0 00 8d 00
+02 00 61 00 22 04 60 20 80 00 8d 00 40 00 8d 00
+02 20 81 00 21 04 80 20 80 01 8d 00 c0 01 8d 00
+02 20 81 00 22 04 60 30 40 01 8d 00 80 00 8d 00
+02 01 61 80 be 7f af 20 64 00 6e 00 00 00 00 3f
+02 00 61 00 22 0c e0 20 40 00 8d 00 00 00 00 3f
+02 20 81 00 22 0c 60 21 80 00 8d 00 00 00 00 3f
+02 01 61 00 21 04 ef 21 04 02 6e 00 e4 01 6e 00
+02 01 61 80 be 77 af 20 24 00 0e 00 64 00 6e 00
+02 01 72 00 21 0c 21 22 20 02 60 00 00 00 00 00
+02 00 61 00 be 77 80 20 60 00 8d 00 80 00 8d 00
+02 20 81 00 be 77 80 30 80 00 8d 00 c0 00 8d 00
+02 00 71 00 22 0c a0 20 40 00 8d 00 00 00 00 00
+02 20 91 00 22 0c a0 30 c0 00 8d 00 00 00 00 00
+02 01 66 00 21 04 8f 20 84 00 6e 00 a4 00 6e 00
+02 01 61 00 21 0c 63 20 64 00 65 00 cd cc 4c 3e
+02 01 62 00 a5 1c 81 20 80 40 60 00 00 00 00 00
+02 00 61 00 a5 1c 40 20 40 40 8d 00 ff ff ff ff
+02 20 81 00 a5 1c 80 20 c0 40 8d 00 ff ff ff ff
+02 00 61 00 be 7f 60 20 40 00 8d 00 00 00 80 3f
+02 20 81 00 be 7f 60 30 80 00 8d 00 00 00 80 3f
+02 01 62 00 21 0c 61 20 60 00 60 00 cd cc 4c 3e
+02 00 61 00 21 0c 60 20 44 00 00 00 00 00 80 40
+02 20 81 00 21 0c 80 20 44 00 00 00 00 00 80 40
+02 01 67 00 21 04 cf 20 c4 00 6e 00 e4 00 6e 00
+02 01 62 00 21 04 01 21 6f 00 0f 00 6a 00 0a 00

diff --git a/src/intel/tools/tests/gen5/send.asm b/src/intel/tools/tests/gen5/send.asm
new file mode 100644 (file)
index 0000000..4500f06
--- /dev/null
+++ b/src/intel/tools/tests/gen5/send.asm
@@ -0,0 +1,300 @@
+send(8) 2       g2<1>F          g2<8,8,1>F      0x02100001
+                            math MsgDesc: inv mlen 1 rlen 1                 { align1 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x8c084c00
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 EOT };
+send(16) 2      g12<1>F         g10<8,8,1>F     0x02100001
+                            math MsgDesc: inv mlen 1 rlen 1                 { align1 compr };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x94084800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 EOT };
+send(8) 1       null<1>F        g0<4>F          0x8a08c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 5 rlen 0 { align16 EOT };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x06410001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 };
+send(16) 2      g4<1>UW         null<8,8,1>F    0x0c820001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x04410001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 };
+send(16) 2      g4<1>UW         null<8,8,1>F    0x08820001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 };
+send(8) 14      g3<1>UD         g0<4>F          0x04181000
+                            read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 0 mlen 2 rlen 1 { align16 };
+send(8) 1       null<1>F        g0<4>F          0x8808c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 4 rlen 0 { align16 EOT };
+send(8) 2       g13<1>UW        null<8,8,1>F    0x0241a001
+                            sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 };
+send(16) 2      g26<1>UW        null<8,8,1>F    0x0482a001
+                            sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x08417001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 };
+send(16) 2      g4<1>UW         null<8,8,1>F    0x10827001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 };
+send(8) 1       null<1>F        g0<4>F          0x8c08c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 6 rlen 0 { align16 EOT };
+send(8) 2       g2<1>F          g2<8,8,1>F      0x0410000a
+                            math MsgDesc: pow mlen 2 rlen 1                 { align1 };
+send(8) 2       g12<1>UW        null<8,8,1>F    0x02410001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 };
+send(16) 2      g16<1>UW        null<8,8,1>F    0x04820001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 };
+send(8) 2       g2<1>F          g2<8,8,1>F      0x02100007
+                            math MsgDesc: cos mlen 1 rlen 1                 { align1 };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x0a411001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 };
+send(16) 2      g4<1>UW         null<8,8,1>F    0x14821001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x90084c00
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 8 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x9c084800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 14 rlen 0 { align1 EOT };
+send(8) 1       null<1>F        g0<4>F          0x1a084400
+                            urb MsgDesc: 0 urb_write interleave used mlen 13 rlen 0 { align16 };
+send(8) 1       null<1>F        g0<4>F          0x9008c460
+                            urb MsgDesc: 6 urb_write interleave used complete mlen 8 rlen 0 { align16 EOT };
+send(8) 1       g5<1>.yF        g6<4>.xF        0x02100006
+                            math MsgDesc: sin mlen 1 rlen 1                 { align16 };
+send(8) 1       g7<1>.xD        g1<0>.zD        0x0410001c
+                            math MsgDesc: intdiv signed mlen 2 rlen 1       { align16 };
+send(8) 2       g3<1>F          g2.3<0,1,0>F    0x02100081
+                            math MsgDesc: inv scalar mlen 1 rlen 1          { align1 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x8e084c00
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 7 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x98084800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 12 rlen 0 { align1 EOT };
+send(8) 1       g30<1>.xF       (abs)g30<4>.xF  0x02100005
+                            math MsgDesc: rsq mlen 1 rlen 1                 { align16 };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x0a412001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 };
+send(16) 2      g4<1>UW         null<8,8,1>F    0x14822001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 };
+send(8) 2       g2<1>F          g2<8,8,1>F      0x02100004
+                            math MsgDesc: sqrt mlen 1 rlen 1                { align1 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x92084c00
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 9 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x9e084800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 15 rlen 0 { align1 EOT };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x04410304
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 4 { align1 };
+send(16) 2      g4<1>UW         null<8,8,1>F    0x08820304
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 8 { align1 };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x0a413001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 };
+send(16) 2      g4<1>UW         null<8,8,1>F    0x14823001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 };
+send(8) 1       null<1>F        g0<4>F          0x9008c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 8 rlen 0 { align16 EOT };
+send(8) 1       null<1>F        g0<4>F          0x9608c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 11 rlen 0 { align16 EOT };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x0c084400
+                            write MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x0c084401
+                            write MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x0c084402
+                            write MsgDesc: RT write SIMD8 Surface = 2 mlen 6 rlen 0 { align1 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x8c084c03
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 6 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x14084000
+                            write MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x14084001
+                            write MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x14084002
+                            write MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x94084803
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 EOT };
+send(8) 2       g2<1>F          g2<8,8,1>F      0x02100002
+                            math MsgDesc: log mlen 1 rlen 1                 { align1 };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x0c416001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 };
+send(8) 2       g3<1>F          g2<0,1,0>F      0x041000ca
+                            math MsgDesc: pow sat scalar mlen 2 rlen 1      { align1 };
+send(8) 2       g7<1>UW         null<8,8,1>F    0x0a413102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 };
+send(16) 2      g14<1>UW        null<8,8,1>F    0x14823102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x8c084c01
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x94084801
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 EOT };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x8c084c02
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 6 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x94084802
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 EOT };
+send(8) 2       g9<1>UW         null<8,8,1>F    0x04410102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 };
+send(16) 2      g20<1>UW        null<8,8,1>F    0x08820102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 };
+send(8) 1       null<1>F        g0<4>F          0x8e08c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 7 rlen 0 { align16 EOT };
+send(8) 13      g0<1>F          g0<4>F          0x061890ff
+                            write MsgDesc: OWord dual block write MsgCtrl = 0x0 Surface = 255 mlen 3 rlen 1 { align16 };
+send(8) 14      g6<1>F          g0<4>F          0x041850ff
+                            read MsgDesc: OWord Dual Block Read MsgCtrl = 0x0 Surface = 255 mlen 2 rlen 1 { align16 };
+send(8) 2       g17<1>UW        null<8,8,1>F    0x0241a102
+                            sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 };
+send(8) 2       g30<1>UW        null<8,8,1>F    0x0241a203
+                            sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 };
+send(8) 2       g30<1>UW        null<8,8,1>F    0x04410203
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 4 { align1 };
+send(8) 2       g13<1>UW        null<8,8,1>F    0x0241a304
+                            sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 4 { align1 };
+send(8) 2       g34<1>UW        null<8,8,1>F    0x0241a405
+                            sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 4 { align1 };
+send(8) 2       g34<1>UW        null<8,8,1>F    0x04410405
+                            sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 };
+send(8) 2       g38<1>UW        null<8,8,1>F    0x0241a506
+                            sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 4 { align1 };
+send(8) 2       g9<1>UW         null<8,8,1>F    0x04410506
+                            sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 2 rlen 4 { align1 };
+send(8) 2       g38<1>UW        null<8,8,1>F    0x0241a607
+                            sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 6 mlen 1 rlen 4 { align1 };
+send(8) 2       g38<1>UW        null<8,8,1>F    0x04410607
+                            sampler MsgDesc: sample SIMD8 Surface = 7 Sampler = 6 mlen 2 rlen 4 { align1 };
+send(8) 2       g42<1>UW        null<8,8,1>F    0x0241a708
+                            sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 7 mlen 1 rlen 4 { align1 };
+send(8) 2       g42<1>UW        null<8,8,1>F    0x04410708
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 2 rlen 4 { align1 };
+send(16) 2      g14<1>UW        null<8,8,1>F    0x0482a102
+                            sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 };
+send(16) 2      g26<1>UW        null<8,8,1>F    0x0482a203
+                            sampler MsgDesc: resinfo SIMD16 Surface = 3 Sampler = 2 mlen 2 rlen 8 { align1 };
+send(16) 2      g26<1>UW        null<8,8,1>F    0x08820203
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 8 { align1 };
+send(16) 2      g34<1>UW        null<8,8,1>F    0x0482a304
+                            sampler MsgDesc: resinfo SIMD16 Surface = 4 Sampler = 3 mlen 2 rlen 8 { align1 };
+send(16) 2      g42<1>UW        null<8,8,1>F    0x0482a405
+                            sampler MsgDesc: resinfo SIMD16 Surface = 5 Sampler = 4 mlen 2 rlen 8 { align1 };
+send(16) 2      g42<1>UW        null<8,8,1>F    0x08820405
+                            sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 8 { align1 };
+send(16) 2      g50<1>UW        null<8,8,1>F    0x0482a506
+                            sampler MsgDesc: resinfo SIMD16 Surface = 6 Sampler = 5 mlen 2 rlen 8 { align1 };
+send(16) 2      g50<1>UW        null<8,8,1>F    0x08820506
+                            sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 4 rlen 8 { align1 };
+send(16) 2      g58<1>UW        null<8,8,1>F    0x0482a607
+                            sampler MsgDesc: resinfo SIMD16 Surface = 7 Sampler = 6 mlen 2 rlen 8 { align1 };
+send(16) 2      g58<1>UW        null<8,8,1>F    0x08820607
+                            sampler MsgDesc: sample SIMD16 Surface = 7 Sampler = 6 mlen 4 rlen 8 { align1 };
+send(16) 2      g66<1>UW        null<8,8,1>F    0x0482a708
+                            sampler MsgDesc: resinfo SIMD16 Surface = 8 Sampler = 7 mlen 2 rlen 8 { align1 };
+send(16) 2      g66<1>UW        null<8,8,1>F    0x08820708
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 4 rlen 8 { align1 };
+send(8) 1       null<1>F        g0<4>F          0x9a08c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 13 rlen 0 { align16 EOT };
+send(8) 1       null<1>F        g0<4>F          0x9808c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 12 rlen 0 { align16 EOT };
+send(8) 2       g8<1>UW         null<8,8,1>F    0x0c416102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x96084800
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 11 rlen 0 { align1 EOT };
+send(8) 2       g3<1>F          null<4>UD       0x04102505
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 5 Sampler = 5 mlen 2 rlen 1 { align16 };
+send(8) 2       g3<1>F          g2<0,1,0>F      0x021000c4
+                            math MsgDesc: sqrt sat scalar mlen 1 rlen 1     { align1 };
+send(8) 2       g3<1>F          g2<0,1,0>F      0x021000c3
+                            math MsgDesc: exp sat scalar mlen 1 rlen 1      { align1 };
+send(8) 2       g3<1>F          null<4>UD       0x04102000
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 0 Sampler = 0 mlen 2 rlen 1 { align16 };
+send(8) 1       g3<1>F          g1<0>F          0x02100044
+                            math MsgDesc: sqrt sat mlen 1 rlen 1            { align16 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x0c084403
+                            write MsgDesc: RT write SIMD8 Surface = 3 mlen 6 rlen 0 { align1 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x8c084c04
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 4 mlen 6 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x14084003
+                            write MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x94084804
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 EOT };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x0c084404
+                            write MsgDesc: RT write SIMD8 Surface = 4 mlen 6 rlen 0 { align1 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x8c084c05
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 5 mlen 6 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x14084004
+                            write MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x94084805
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 EOT };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x0c084405
+                            write MsgDesc: RT write SIMD8 Surface = 5 mlen 6 rlen 0 { align1 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x8c084c06
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 6 mlen 6 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x14084005
+                            write MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x94084806
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 EOT };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x0c084406
+                            write MsgDesc: RT write SIMD8 Surface = 6 mlen 6 rlen 0 { align1 };
+send(8) 1       null<1>UW       g0<8,8,1>UW     0x8c084c07
+                            write MsgDesc: RT write SIMD8 LastRT Surface = 7 mlen 6 rlen 0 { align1 EOT };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x14084006
+                            write MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 };
+send(16) 1      null<1>UW       g0<8,8,1>UW     0x94084807
+                            write MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 EOT };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x10414001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 };
+send(8) 2       g6<1>UW         null<8,8,1>F    0x06410102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 };
+send(16) 2      g12<1>UW        null<8,8,1>F    0x0c820102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 };
+send(8) 13      g11<1>UW        g0<8,8,1>F      0x04497001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 };
+send(16) 13     g4<1>UW         g0<8,8,1>F      0x068a7001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 8 { align1 };
+send(8) 1       null<1>F        g0<4>F          0x9408c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 10 rlen 0 { align16 EOT };
+send(8) 1       null<1>F        g0<4>F          0x8408c460
+                            urb MsgDesc: 6 urb_write interleave used complete mlen 2 rlen 0 { align16 EOT };
+send(8) 2       g4<1>F          g2<0,1,0>F      0x02100084
+                            math MsgDesc: sqrt scalar mlen 1 rlen 1         { align1 };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x0c414001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 };
+send(8) 1       g3<1>F          g1<0>F          0x02100043
+                            math MsgDesc: exp sat mlen 1 rlen 1             { align16 };
+send(8) 1       null<1>F        g0<4>F          0x9208c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 9 rlen 0 { align16 EOT };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x0c415001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 };
+send(8) 2       g5<1>F          g2<0,1,0>F      0x02100087
+                            math MsgDesc: cos scalar mlen 1 rlen 1          { align1 };
+send(8) 1       g4<1>.xF        g3<4>.xF        0x02100003
+                            math MsgDesc: exp mlen 1 rlen 1                 { align16 };
+send(8) 2       g7<1>UW         null<8,8,1>F    0x0c415102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x14414001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 };
+send(8) 2       g3<1>F          g2<0,1,0>F      0x02100083
+                            math MsgDesc: exp scalar mlen 1 rlen 1          { align1 };
+send(8) 2       g6<1>UW         null<8,8,1>F    0x04410003
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 4 { align1 };
+send(8) 2       g10<1>UW        null<8,8,1>F    0x04410004
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 0 mlen 2 rlen 4 { align1 };
+send(16) 2      g14<1>UW        null<8,8,1>F    0x08820003
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 8 { align1 };
+send(16) 2      g22<1>UW        null<8,8,1>F    0x08820004
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 0 mlen 4 rlen 8 { align1 };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x04419001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 };
+send(16) 2      g4<1>UW         null<8,8,1>F    0x08829001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x04410f10
+                            sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 2 rlen 4 { align1 };
+send(16) 2      g4<1>UW         null<8,8,1>F    0x08820f10
+                            sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 4 rlen 8 { align1 };
+send(8) 2       g3<1>F          null<4>UD       0x04102303
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 3 Sampler = 3 mlen 2 rlen 1 { align16 };
+send(8) 1       g3<1>F          g1<0>F          0x0410004a
+                            math MsgDesc: pow sat mlen 2 rlen 1             { align16 };
+send(8) 2       g4<1>UW         null<8,8,1>F    0x0241a004
+                            sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 0 mlen 1 rlen 4 { align1 };
+send(16) 2      g10<1>UW        null<8,8,1>F    0x0482a004
+                            sampler MsgDesc: resinfo SIMD16 Surface = 4 Sampler = 0 mlen 2 rlen 8 { align1 };
+send(8) 2       g4<1>UW         null<8,8,1>F    0x0241a003
+                            sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 0 mlen 1 rlen 4 { align1 };
+send(16) 2      g10<1>UW        null<8,8,1>F    0x0482a003
+                            sampler MsgDesc: resinfo SIMD16 Surface = 3 Sampler = 0 mlen 2 rlen 8 { align1 };
+send(8) 2       g4<1>UW         null<8,8,1>F    0x0241a002
+                            sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 0 mlen 1 rlen 4 { align1 };
+send(8) 2       g2<1>UW         null<8,8,1>F    0x04410002
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 };
+send(16) 2      g10<1>UW        null<8,8,1>F    0x0482a002
+                            sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 0 mlen 2 rlen 8 { align1 };
+send(16) 2      g4<1>UW         null<8,8,1>F    0x08820002
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 };
+send(8) 2       g5<1>F          g2<0,1,0>F      0x02100086
+                            math MsgDesc: sin scalar mlen 1 rlen 1          { align1 };

diff --git a/src/intel/tools/tests/gen5/send.expected b/src/intel/tools/tests/gen5/send.expected
new file mode 100644 (file)
index 0000000..30aa147
--- /dev/null
+++ b/src/intel/tools/tests/gen5/send.expected
@@ -0,0 +1,150 @@
+31 00 60 02 bd 0f 40 20 40 00 8d 10 01 00 10 02
+31 00 60 01 28 0d 00 20 00 00 8d 50 00 4c 08 8c
+31 20 80 02 bd 0f 80 21 40 01 8d 10 01 00 10 02
+31 00 80 01 28 0d 00 20 00 00 8d 50 00 48 08 94
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 8a
+31 00 60 02 89 0f 40 20 00 00 8d 20 01 00 41 06
+31 00 80 02 89 0f 80 20 00 00 8d 20 01 00 82 0c
+31 00 60 02 89 0f 40 20 00 00 8d 20 01 00 41 04
+31 00 80 02 89 0f 80 20 00 00 8d 20 01 00 82 08
+31 01 60 0e a1 0f 6f 20 04 00 6e 40 00 10 18 04
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 88
+31 00 60 02 89 0f a0 21 00 00 8d 20 01 a0 41 02
+31 00 80 02 89 0f 40 23 00 00 8d 20 01 a0 82 04
+31 00 60 02 89 0f 40 20 00 00 8d 20 01 70 41 08
+31 00 80 02 89 0f 80 20 00 00 8d 20 01 70 82 10
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 8c
+31 00 60 02 bd 0f 40 20 40 00 8d 10 0a 00 10 04
+31 00 60 02 89 0f 80 21 00 00 8d 20 01 00 41 02
+31 00 80 02 89 0f 00 22 00 00 8d 20 01 00 82 04
+31 00 60 02 bd 0f 40 20 40 00 8d 10 07 00 10 02
+31 00 60 02 89 0f 40 20 00 00 8d 20 01 10 41 0a
+31 00 80 02 89 0f 80 20 00 00 8d 20 01 10 82 14
+31 00 60 01 28 0d 00 20 00 00 8d 50 00 4c 08 90
+31 00 80 01 28 0d 00 20 00 00 8d 50 00 48 08 9c
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 44 08 1a
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 60 c4 08 90
+31 01 60 01 bd 0f a2 20 c0 00 60 10 06 00 10 02
+31 01 60 01 a5 0c e1 20 2a 00 0a 10 1c 00 10 04
+31 00 60 02 bd 0f 60 20 4c 00 00 10 81 00 10 02
+31 00 60 01 28 0d 00 20 00 00 8d 50 00 4c 08 8e
+31 00 80 01 28 0d 00 20 00 00 8d 50 00 48 08 98
+31 01 60 01 bd 0f c1 23 c0 23 60 10 05 00 10 02
+31 00 60 02 89 0f 40 20 00 00 8d 20 01 20 41 0a
+31 00 80 02 89 0f 80 20 00 00 8d 20 01 20 82 14
+31 00 60 02 bd 0f 40 20 40 00 8d 10 04 00 10 02
+31 00 60 01 28 0d 00 20 00 00 8d 50 00 4c 08 92
+31 00 80 01 28 0d 00 20 00 00 8d 50 00 48 08 9e
+31 00 60 02 89 0f 40 20 00 00 8d 20 04 03 41 04
+31 00 80 02 89 0f 80 20 00 00 8d 20 04 03 82 08
+31 00 60 02 89 0f 40 20 00 00 8d 20 01 30 41 0a
+31 00 80 02 89 0f 80 20 00 00 8d 20 01 30 82 14
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 90
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 96
+31 00 60 01 28 0d 00 20 00 00 8d 50 00 44 08 0c
+31 00 60 01 28 0d 00 20 00 00 8d 50 01 44 08 0c
+31 00 60 01 28 0d 00 20 00 00 8d 50 02 44 08 0c
+31 00 60 01 28 0d 00 20 00 00 8d 50 03 4c 08 8c
+31 00 80 01 28 0d 00 20 00 00 8d 50 00 40 08 14
+31 00 80 01 28 0d 00 20 00 00 8d 50 01 40 08 14
+31 00 80 01 28 0d 00 20 00 00 8d 50 02 40 08 14
+31 00 80 01 28 0d 00 20 00 00 8d 50 03 48 08 94
+31 00 60 02 bd 0f 40 20 40 00 8d 10 02 00 10 02
+31 00 60 02 89 0f 40 20 00 00 8d 20 01 60 41 0c
+31 00 60 02 bd 0f 60 20 40 00 00 10 ca 00 10 04
+31 00 60 02 89 0f e0 20 00 00 8d 20 02 31 41 0a
+31 00 80 02 89 0f c0 21 00 00 8d 20 02 31 82 14
+31 00 60 01 28 0d 00 20 00 00 8d 50 01 4c 08 8c
+31 00 80 01 28 0d 00 20 00 00 8d 50 01 48 08 94
+31 00 60 01 28 0d 00 20 00 00 8d 50 02 4c 08 8c
+31 00 80 01 28 0d 00 20 00 00 8d 50 02 48 08 94
+31 00 60 02 89 0f 20 21 00 00 8d 20 02 01 41 04
+31 00 80 02 89 0f 80 22 00 00 8d 20 02 01 82 08
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 8e
+31 01 60 0d bd 0f 0f 20 04 00 6e 50 ff 90 18 06
+31 01 60 0e bd 0f cf 20 04 00 6e 40 ff 50 18 04
+31 00 60 02 89 0f 20 22 00 00 8d 20 02 a1 41 02
+31 00 60 02 89 0f c0 23 00 00 8d 20 03 a2 41 02
+31 00 60 02 89 0f c0 23 00 00 8d 20 03 02 41 04
+31 00 60 02 89 0f a0 21 00 00 8d 20 04 a3 41 02
+31 00 60 02 89 0f 40 24 00 00 8d 20 05 a4 41 02
+31 00 60 02 89 0f 40 24 00 00 8d 20 05 04 41 04
+31 00 60 02 89 0f c0 24 00 00 8d 20 06 a5 41 02
+31 00 60 02 89 0f 20 21 00 00 8d 20 06 05 41 04
+31 00 60 02 89 0f c0 24 00 00 8d 20 07 a6 41 02
+31 00 60 02 89 0f c0 24 00 00 8d 20 07 06 41 04
+31 00 60 02 89 0f 40 25 00 00 8d 20 08 a7 41 02
+31 00 60 02 89 0f 40 25 00 00 8d 20 08 07 41 04
+31 00 80 02 89 0f c0 21 00 00 8d 20 02 a1 82 04
+31 00 80 02 89 0f 40 23 00 00 8d 20 03 a2 82 04
+31 00 80 02 89 0f 40 23 00 00 8d 20 03 02 82 08
+31 00 80 02 89 0f 40 24 00 00 8d 20 04 a3 82 04
+31 00 80 02 89 0f 40 25 00 00 8d 20 05 a4 82 04
+31 00 80 02 89 0f 40 25 00 00 8d 20 05 04 82 08
+31 00 80 02 89 0f 40 26 00 00 8d 20 06 a5 82 04
+31 00 80 02 89 0f 40 26 00 00 8d 20 06 05 82 08
+31 00 80 02 89 0f 40 27 00 00 8d 20 07 a6 82 04
+31 00 80 02 89 0f 40 27 00 00 8d 20 07 06 82 08
+31 00 80 02 89 0f 40 28 00 00 8d 20 08 a7 82 04
+31 00 80 02 89 0f 40 28 00 00 8d 20 08 07 82 08
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 9a
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 98
+31 00 60 02 89 0f 00 21 00 00 8d 20 02 61 41 0c
+31 00 80 01 28 0d 00 20 00 00 8d 50 00 48 08 96
+31 01 60 02 1d 0c 6f 20 04 00 6e 20 05 25 10 04
+31 00 60 02 bd 0f 60 20 40 00 00 10 c4 00 10 02
+31 00 60 02 bd 0f 60 20 40 00 00 10 c3 00 10 02
+31 01 60 02 1d 0c 6f 20 04 00 6e 20 00 20 10 04
+31 01 60 01 bd 0f 6f 20 24 00 0e 10 44 00 10 02
+31 00 60 01 28 0d 00 20 00 00 8d 50 03 44 08 0c
+31 00 60 01 28 0d 00 20 00 00 8d 50 04 4c 08 8c
+31 00 80 01 28 0d 00 20 00 00 8d 50 03 40 08 14
+31 00 80 01 28 0d 00 20 00 00 8d 50 04 48 08 94
+31 00 60 01 28 0d 00 20 00 00 8d 50 04 44 08 0c
+31 00 60 01 28 0d 00 20 00 00 8d 50 05 4c 08 8c
+31 00 80 01 28 0d 00 20 00 00 8d 50 04 40 08 14
+31 00 80 01 28 0d 00 20 00 00 8d 50 05 48 08 94
+31 00 60 01 28 0d 00 20 00 00 8d 50 05 44 08 0c
+31 00 60 01 28 0d 00 20 00 00 8d 50 06 4c 08 8c
+31 00 80 01 28 0d 00 20 00 00 8d 50 05 40 08 14
+31 00 80 01 28 0d 00 20 00 00 8d 50 06 48 08 94
+31 00 60 01 28 0d 00 20 00 00 8d 50 06 44 08 0c
+31 00 60 01 28 0d 00 20 00 00 8d 50 07 4c 08 8c
+31 00 80 01 28 0d 00 20 00 00 8d 50 06 40 08 14
+31 00 80 01 28 0d 00 20 00 00 8d 50 07 48 08 94
+31 00 60 02 89 0f 40 20 00 00 8d 20 01 40 41 10
+31 00 60 02 89 0f c0 20 00 00 8d 20 02 01 41 06
+31 00 80 02 89 0f 80 21 00 00 8d 20 02 01 82 0c
+31 00 60 0d a9 0f 60 21 00 00 8d 20 01 70 49 04
+31 00 80 0d a9 0f 80 20 00 00 8d 20 01 70 8a 06
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 94
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 60 c4 08 84
+31 00 60 02 bd 0f 80 20 40 00 00 10 84 00 10 02
+31 00 60 02 89 0f 40 20 00 00 8d 20 01 40 41 0c
+31 01 60 01 bd 0f 6f 20 24 00 0e 10 43 00 10 02
+31 01 60 01 bc 0f 0f 20 04 00 6e 60 00 c4 08 92
+31 00 60 02 89 0f 40 20 00 00 8d 20 01 50 41 0c
+31 00 60 02 bd 0f a0 20 40 00 00 10 87 00 10 02
+31 01 60 01 bd 0f 81 20 60 00 60 10 03 00 10 02
+31 00 60 02 89 0f e0 20 00 00 8d 20 02 51 41 0c
+31 00 60 02 89 0f 40 20 00 00 8d 20 01 40 41 14
+31 00 60 02 bd 0f 60 20 40 00 00 10 83 00 10 02
+31 00 60 02 89 0f c0 20 00 00 8d 20 03 00 41 04
+31 00 60 02 89 0f 40 21 00 00 8d 20 04 00 41 04
+31 00 80 02 89 0f c0 21 00 00 8d 20 03 00 82 08
+31 00 80 02 89 0f c0 22 00 00 8d 20 04 00 82 08
+31 00 60 02 89 0f 40 20 00 00 8d 20 01 90 41 04
+31 00 80 02 89 0f 80 20 00 00 8d 20 01 90 82 08
+31 00 60 02 89 0f 40 20 00 00 8d 20 10 0f 41 04
+31 00 80 02 89 0f 80 20 00 00 8d 20 10 0f 82 08
+31 01 60 02 1d 0c 6f 20 04 00 6e 20 03 23 10 04
+31 01 60 01 bd 0f 6f 20 24 00 0e 10 4a 00 10 04
+31 00 60 02 89 0f 80 20 00 00 8d 20 04 a0 41 02
+31 00 80 02 89 0f 40 21 00 00 8d 20 04 a0 82 04
+31 00 60 02 89 0f 80 20 00 00 8d 20 03 a0 41 02
+31 00 80 02 89 0f 40 21 00 00 8d 20 03 a0 82 04
+31 00 60 02 89 0f 80 20 00 00 8d 20 02 a0 41 02
+31 00 60 02 89 0f 40 20 00 00 8d 20 02 00 41 04
+31 00 80 02 89 0f 40 21 00 00 8d 20 02 a0 82 04
+31 00 80 02 89 0f 80 20 00 00 8d 20 02 00 82 08
+31 00 60 02 bd 0f a0 20 40 00 00 10 86 00 10 02

diff --git a/src/intel/tools/tests/gen5/shl.asm b/src/intel/tools/tests/gen5/shl.asm
new file mode 100644 (file)
index 0000000..a02bfff
--- /dev/null
+++ b/src/intel/tools/tests/gen5/shl.asm
@@ -0,0 +1,7 @@
+shl(8)          g4<1>.xD        g1<0>.yD        0x00000004UD    { align16 };
+shl(8)          g4<1>D          g3<8,8,1>D      0x00000001UD    { align1 };
+shl(16)         g6<1>D          g4<8,8,1>D      0x00000001UD    { align1 compr };
+shl(8)          g11<1>.xUD      g11<4>.xUD      4D              { align16 };
+shl(8)          m14<1>D         g4<0,1,0>D      0x00000004UD    { align1 };
+shl(16)         m14<1>D         g4<0,1,0>D      0x00000004UD    { align1 compr };
+shl(8)          g5<1>D          g3<4>D          g4<4>UD         { align16 };

diff --git a/src/intel/tools/tests/gen5/shl.expected b/src/intel/tools/tests/gen5/shl.expected
new file mode 100644 (file)
index 0000000..f9c9cef
--- /dev/null
+++ b/src/intel/tools/tests/gen5/shl.expected
@@ -0,0 +1,7 @@
+09 01 60 00 a5 0c 81 20 25 00 05 00 04 00 00 00
+09 00 60 00 a5 0c 80 20 60 00 8d 00 01 00 00 00
+09 20 80 00 a5 0c c0 20 80 00 8d 00 01 00 00 00
+09 01 60 00 21 1c 61 21 60 01 60 00 04 00 00 00
+09 00 60 00 a6 0c c0 21 80 00 00 00 04 00 00 00
+09 20 80 00 a6 0c c0 21 80 00 00 00 04 00 00 00
+09 01 60 00 a5 04 af 20 64 00 6e 00 84 00 6e 00

diff --git a/src/intel/tools/tests/gen5/shr.asm b/src/intel/tools/tests/gen5/shr.asm
new file mode 100644 (file)
index 0000000..51db89d
--- /dev/null
+++ b/src/intel/tools/tests/gen5/shr.asm
@@ -0,0 +1,3 @@
+shr(8)          g3<1>UD         g3<8,8,1>UD     0x00000001UD    { align1 };
+shr(16)         g8<1>UD         g4<8,8,1>UD     0x00000001UD    { align1 compr };
+shr(1)          g8.4<1>UD       g8.4<0,1,0>UD   0x00000004UD    { align1 nomask };

diff --git a/src/intel/tools/tests/gen5/shr.expected b/src/intel/tools/tests/gen5/shr.expected
new file mode 100644 (file)
index 0000000..fe61e45
--- /dev/null
+++ b/src/intel/tools/tests/gen5/shr.expected
@@ -0,0 +1,3 @@
+08 00 60 00 21 0c 60 20 60 00 8d 00 01 00 00 00
+08 20 80 00 21 0c 00 21 80 00 8d 00 01 00 00 00
+08 02 00 00 21 0c 10 21 10 01 00 00 04 00 00 00

diff --git a/src/intel/tools/tests/gen5/while.asm b/src/intel/tools/tests/gen5/while.asm
new file mode 100644 (file)
index 0000000..a5985d9
--- /dev/null
+++ b/src/intel/tools/tests/gen5/while.asm
@@ -0,0 +1,3 @@
+while(8)        Jump: -282                                      { align1 };
+while(16)       Jump: -282                                      { align1 };
+while(8)        Jump: -32                                       { align16 };

diff --git a/src/intel/tools/tests/gen5/while.expected b/src/intel/tools/tests/gen5/while.expected
new file mode 100644 (file)
index 0000000..290e75f
--- /dev/null
+++ b/src/intel/tools/tests/gen5/while.expected
@@ -0,0 +1,3 @@
+27 00 60 00 00 1c 00 34 00 14 60 00 e6 fe 00 00
+27 00 80 00 00 1c 00 34 00 14 60 00 e6 fe 00 00
+27 01 60 00 00 1c 0f 34 04 14 6e 00 e0 ff 00 00

diff --git a/src/intel/tools/tests/gen6/add.asm b/src/intel/tools/tests/gen6/add.asm
new file mode 100644 (file)
index 0000000..37b2e5d
--- /dev/null
+++ b/src/intel/tools/tests/gen6/add.asm
@@ -0,0 +1,79 @@
+add(16)         g6<1>UW         g1.4<1,4,0>UW   0x11001010V     { align1 WE_all 1H };
+add(16)         g4<1>UW         g1.4<2,4,0>UW   0x10101010V     { align1 1H };
+add(8)          g30<1>F         g26<8,8,1>F     -g4.4<0,1,0>F   { align1 1Q };
+add(16)         g18<1>F         g8<8,8,1>F      -g6.4<0,1,0>F   { align1 1H };
+add(1)          m22.4<1>D       g39.4<0,1,0>D   1D              { align1 WE_all 1N };
+add(8)          m1<1>D          g3.3<0,1,0>D    g2<0,1,0>D      { align1 1Q };
+add(16)         m1<1>D          g3.3<0,1,0>D    g2<0,1,0>D      { align1 1H };
+add(8)          g11<1>.xyF      g1<0>.xyyyF     g2<0>.xF        { align16 1Q };
+add(8)          m6<1>F          g4<8,8,1>F      0xbd4ccccdF  /* -0.05F */ { align1 1Q };
+add(8)          g2<1>F          g4<8,8,1>F      0x3d4ccccdF  /* 0.05F */ { align1 1Q };
+add(16)         g2<1>F          g11<8,8,1>F     0xbd4ccccdF  /* -0.05F */ { align1 1H };
+add(8)          g6<1>.xUD       g6<4>.xUD       0x00000001UD    { align16 1Q };
+add(8)          g19<1>.xUD      g6<4>.xUD       3D              { align16 1Q };
+add(8)          m3<1>F          g2<4>F          g1<0>F          { align16 1Q };
+add(8)          g67<1>.xD       g38<4>.xD       g40<4>.xD       { align16 1Q };
+add(8)          g21<1>.xD       g19<4>.xD       -1D             { align16 1Q };
+add(8)          a0<1>UW         g3<16,8,2>UW    0x0040UW        { align1 1Q };
+add(8)          a0<1>UW         g4<16,8,2>UW    0x0040UW        { align1 2Q };
+add(8)          m2<1>.xD        g3.4<0>.xD      7D              { align16 NoDDClr 1Q };
+add(8)          g6<1>.xyF       g1<4>.xyyyF     0x3f800000F  /* 1F */ { align16 1Q };
+add(16)         m3<1>F          -g39<8,8,1>F    0x3f800000F  /* 1F */ { align1 1H };
+add(8)          m4<1>F          g10<8,8,1>F     g2.7<0,1,0>F    { align1 1Q };
+add(16)         m7<1>F          g35<8,8,1>F     g2.7<0,1,0>F    { align1 1H };
+add(8)          m3<1>.xyF       g10<4>.xyyyF    0x3f000000F  /* 0.5F */ { align16 NoDDClr 1Q };
+add(8)          g26<1>UD        g26<4>UD        g28<4>UD        { align16 1Q };
+add(8)          m6<1>.xD        g5<4>.zD        g5<4>.xD        { align16 1Q };
+add(8)          g4<1>D          g2<0,1,0>D      g2.4<0,1,0>D    { align1 1Q };
+add(16)         g4<1>D          g2<0,1,0>D      g2.4<0,1,0>D    { align1 1H };
+add(8)          m2<1>.xyzD      g3.4<0>.xyzzD   g11<4>.xyzzD    { align16 NoDDClr 1Q };
+add(8)          g70<1>D         g4<0,1,0>D      1D              { align1 1Q };
+add(8)          m2<1>F          g4<8,8,1>D      1D              { align1 1Q };
+add(16)         g75<1>D         g6<0,1,0>D      1D              { align1 1H };
+add(16)         m3<1>F          g89<8,8,1>D     1D              { align1 1H };
+add(8)          g37<1>F         g34<8,8,1>D     1D              { align1 1Q };
+add(16)         g68<1>F         g62<8,8,1>D     1D              { align1 1H };
+add(8)          g11<1>F         g10<4>.xF       0x48403000VF /* [0F, 1F, 2F, 3F]VF */ { align16 1Q };
+add(8)          m4<1>.zD        g1<0>.xD        2D              { align16 NoDDClr,NoDDChk 1Q };
+add(8)          g15<1>.yD       g1<0>.xD        49D             { align16 NoDDClr 1Q };
+add(8)          g15<1>.zD       g1<0>.xD        50D             { align16 NoDDClr,NoDDChk 1Q };
+add(8)          m5<1>.wD        g1<0>.xD        7D              { align16 NoDDChk 1Q };
+add(8)          g15<1>.wD       g1<0>.xD        51D             { align16 NoDDChk 1Q };
+add(8)          g3<1>.yF        g5<4>.xF        -g1<0>.xF       { align16 NoDDClr 1Q };
+add(8)          g3<1>.yF        g13<4>.xF       -g1<0>.xF       { align16 NoDDClr,NoDDChk 1Q };
+add(8)          g42<1>.wF       g2<0>.xF        0x40400000F  /* 3F */ { align16 NoDDClr 1Q };
+add(8)          g43<1>.wF       g2<0>.xF        0x40e00000F  /* 7F */ { align16 NoDDChk 1Q };
+add(8)          m5<1>.zF        g1<0>.xF        0x40000000F  /* 2F */ { align16 NoDDClr,NoDDChk 1Q };
+add(8)          m14<1>.zF       g1<0>.xF        0x42180000F  /* 38F */ { align16 NoDDChk 1Q };
+add(8)          m3<1>F          g1<4>.xF        0x48403000VF /* [0F, 1F, 2F, 3F]VF */ { align16 1Q };
+add(8)          g99<1>.xD       g8<4>.xUD       32D             { align16 1Q };
+add(8)          m4<1>.xF        g1<4>.xF        0x42c80000F  /* 100F */ { align16 1Q };
+add(8)          g3.1<2>UW       g3.1<16,8,2>UW  g13<16,8,2>UW   { align1 1Q };
+add(16)         g3.1<2>UW       g3.1<16,8,2>UW  g5<16,8,2>UW    { align1 1H };
+add.sat(8)      m4<1>F          g2<4>.yzxwF     -g2<4>F         { align16 1Q };
+add(8)          g15<1>.wF       g2<0>.xF        0x40400000F  /* 3F */ { align16 NoDDClr,NoDDChk 1Q };
+add(8)          g2<1>UD         g22<0,1,0>UD    g12<1,4,0>UW    { align1 1Q };
+add(8)          g3<1>UD         g22<0,1,0>UD    g12.2<1,4,0>UW  { align1 2Q };
+add(8)          m3<1>.xyF       g2<4>.xyyyF     g1<0>.xyyyF     { align16 NoDDChk 1Q };
+add.sat(8)      m4<1>F          g2<0,1,0>F      g2.4<0,1,0>F    { align1 1Q };
+add.sat(8)      g3<1>F          g2.3<0,1,0>F    g2.4<0,1,0>F    { align1 1Q };
+add.sat(16)     m7<1>F          g2<0,1,0>F      g2.4<0,1,0>F    { align1 1H };
+add.sat(16)     g3<1>F          g2.3<0,1,0>F    g2.4<0,1,0>F    { align1 1H };
+add(8)          m17<1>D         g3<8,8,1>D      12D             { align1 1Q };
+add(16)         m17<1>D         g3<8,8,1>D      12D             { align1 1H };
+add(8)          m3<1>.yF        g1<4>.yF        -g9<4>.xF       { align16 NoDDClr,NoDDChk 1Q };
+add(8)          m5<1>.xyD       g6<4>.xyyyD     g12<4>.xD       { align16 NoDDClr,NoDDChk 1Q };
+add(8)          m5<1>.xD        g11<4>.xD       1D              { align16 1Q };
+add.sat(8)      m4<1>.xF        -g15<4>.xF      0x3f800000F  /* 1F */ { align16 NoDDClr 1Q };
+add(8)          m10<1>UD        g13<0,1,0>UD    g10<1,4,0>UW    { align1 1Q };
+add(8)          m11<1>UD        g13<0,1,0>UD    g10.2<1,4,0>UW  { align1 2Q };
+add(8)          m17<1>UD        g6<8,8,1>UD     0x00000110UD    { align1 1Q };
+add(16)         m17<1>UD        g9<8,8,1>UD     0x00000110UD    { align1 1H };
+add.sat(8)      g22<1>.xUD      g20<4>.xUD      g10<4>.xUD      { align16 1Q };
+add.l.f0.0(8)   g14<1>.xD       g12<4>.xD       -g12<4>.yD      { align16 1Q };
+add(8)          g18<1>F         -g16<4>.xyxyF   g16<4>.zwzwF    { align16 2Q };
+add.sat(8)      m4<1>F          g7<4>.xF        0xbf800000F  /* -1F */ { align16 1Q };
+add.sat(8)      m4<1>.yF        -g1<0>.xF       0x3f000000F  /* 0.5F */ { align16 NoDDClr,NoDDChk 1Q };
+add.sat(8)      m4<1>.wF        g3<4>.yF        0xc0000000F  /* -2F */ { align16 NoDDChk 1Q };
+add(8)          m5<1>.xF        g25<4>.xF       -g3<4>.yF       { align16 NoDDClr 1Q };
+add(8)          g18<1>.yF       g21<4>.xF       g27<4>.xF       { align16 NoDDChk 1Q };

diff --git a/src/intel/tools/tests/gen6/add.expected b/src/intel/tools/tests/gen6/add.expected
new file mode 100644 (file)
index 0000000..7419dca
--- /dev/null
+++ b/src/intel/tools/tests/gen6/add.expected
@@ -0,0 +1,79 @@
+40 02 80 00 29 6d c0 20 28 00 28 00 10 10 00 11
+40 00 80 00 29 6d 80 20 28 00 48 00 10 10 10 10
+40 00 60 00 bd 77 c0 23 40 03 8d 00 90 40 00 00
+40 00 80 00 bd 77 40 22 00 01 8d 00 d0 40 00 00
+40 02 00 00 a6 1c d0 22 f0 04 00 00 01 00 00 00
+40 00 60 00 a6 14 20 20 6c 00 00 00 40 00 00 00
+40 00 80 00 a6 14 20 20 6c 00 00 00 40 00 00 00
+40 01 60 00 bd 77 63 21 24 00 05 00 40 00 00 00
+40 00 60 00 be 7f c0 20 80 00 8d 00 cd cc 4c bd
+40 00 60 00 bd 7f 40 20 80 00 8d 00 cd cc 4c 3d
+40 00 80 00 bd 7f 40 20 60 01 8d 00 cd cc 4c bd
+40 01 60 00 21 0c c1 20 c0 00 60 00 01 00 00 00
+40 01 60 00 21 1c 61 22 c0 00 60 00 03 00 00 00
+40 01 60 00 be 77 6f 20 44 00 6e 00 24 00 0e 00
+40 01 60 00 a5 14 61 28 c0 04 60 00 00 05 60 00
+40 01 60 00 a5 1c a1 22 60 02 60 00 ff ff ff ff
+40 00 60 00 28 2d 00 22 60 00 ae 00 40 00 40 00
+40 10 60 00 28 2d 00 22 80 00 ae 00 40 00 40 00
+40 05 60 00 a6 1c 41 20 70 00 00 00 07 00 00 00
+40 01 60 00 bd 7f c3 20 24 00 65 00 00 00 80 3f
+40 00 80 00 be 7f 60 20 e0 44 8d 00 00 00 80 3f
+40 00 60 00 be 77 80 20 40 01 8d 00 5c 00 00 00
+40 00 80 00 be 77 e0 20 60 04 8d 00 5c 00 00 00
+40 05 60 00 be 7f 63 20 44 01 65 00 00 00 00 3f
+40 01 60 00 21 04 4f 23 44 03 6e 00 84 03 6e 00
+40 01 60 00 a6 14 c1 20 aa 00 6a 00 a0 00 60 00
+40 00 60 00 a5 14 80 20 40 00 00 00 50 00 00 00
+40 00 80 00 a5 14 80 20 40 00 00 00 50 00 00 00
+40 05 60 00 a6 14 47 20 74 00 0a 00 64 01 6a 00
+40 00 60 00 a5 1c c0 28 80 00 00 00 01 00 00 00
+40 00 60 00 be 1c 40 20 80 00 8d 00 01 00 00 00
+40 00 80 00 a5 1c 60 29 c0 00 00 00 01 00 00 00
+40 00 80 00 be 1c 60 20 20 0b 8d 00 01 00 00 00
+40 00 60 00 bd 1c a0 24 40 04 8d 00 01 00 00 00
+40 00 80 00 bd 1c 80 28 c0 07 8d 00 01 00 00 00
+40 01 60 00 bd 5f 6f 21 40 01 60 00 00 30 40 48
+40 0d 60 00 a6 1c 84 20 20 00 00 00 02 00 00 00
+40 05 60 00 a5 1c e2 21 20 00 00 00 31 00 00 00
+40 0d 60 00 a5 1c e4 21 20 00 00 00 32 00 00 00
+40 09 60 00 a6 1c a8 20 20 00 00 00 07 00 00 00
+40 09 60 00 a5 1c e8 21 20 00 00 00 33 00 00 00
+40 05 60 00 bd 77 62 20 a0 00 60 00 20 40 00 00
+40 0d 60 00 bd 77 62 20 a0 01 60 00 20 40 00 00
+40 05 60 00 bd 7f 48 25 40 00 00 00 00 00 40 40
+40 09 60 00 bd 7f 68 25 40 00 00 00 00 00 e0 40
+40 0d 60 00 be 7f a4 20 20 00 00 00 00 00 00 40
+40 09 60 00 be 7f c4 21 20 00 00 00 00 00 18 42
+40 01 60 00 be 5f 6f 20 20 00 60 00 00 30 40 48
+40 01 60 00 25 1c 61 2c 00 01 60 00 20 00 00 00
+40 01 60 00 be 7f 81 20 20 00 60 00 00 00 c8 42
+40 00 60 00 29 25 62 40 62 00 ae 00 a0 01 ae 00
+40 00 80 00 29 25 62 40 62 00 ae 00 a0 00 ae 00
+40 01 60 80 be 77 8f 20 49 00 6c 00 44 40 6e 00
+40 0d 60 00 bd 7f e8 21 40 00 00 00 00 00 40 40
+40 00 60 00 21 24 40 20 c0 02 00 00 80 01 28 00
+40 10 60 00 21 24 60 20 c0 02 00 00 84 01 28 00
+40 09 60 00 be 77 63 20 44 00 65 00 24 00 05 00
+40 00 60 80 be 77 80 20 40 00 00 00 50 00 00 00
+40 00 60 80 bd 77 60 20 4c 00 00 00 50 00 00 00
+40 00 80 80 be 77 e0 20 40 00 00 00 50 00 00 00
+40 00 80 80 bd 77 60 20 4c 00 00 00 50 00 00 00
+40 00 60 00 a6 1c 20 22 60 00 8d 00 0c 00 00 00
+40 00 80 00 a6 1c 20 22 60 00 8d 00 0c 00 00 00
+40 0d 60 00 be 77 62 20 25 00 65 00 20 41 60 00
+40 0d 60 00 a6 14 a3 20 c4 00 65 00 80 01 60 00
+40 01 60 00 a6 1c a1 20 60 01 60 00 01 00 00 00
+40 05 60 80 be 7f 81 20 e0 41 60 00 00 00 80 3f
+40 00 60 00 22 24 40 21 a0 01 00 00 40 01 28 00
+40 10 60 00 22 24 60 21 a0 01 00 00 44 01 28 00
+40 00 60 00 22 0c 20 22 c0 00 8d 00 10 01 00 00
+40 00 80 00 22 0c 20 22 20 01 8d 00 10 01 00 00
+40 01 60 80 21 04 c1 22 80 02 60 00 40 01 60 00
+40 01 60 05 a5 14 c1 21 80 01 60 00 85 41 65 00
+40 11 60 00 bd 77 4f 22 04 42 64 00 0e 02 6e 00
+40 01 60 80 be 7f 8f 20 e0 00 60 00 00 00 80 bf
+40 0d 60 80 be 7f 82 20 20 40 00 00 00 00 00 3f
+40 09 60 80 be 7f 88 20 65 00 65 00 00 00 00 c0
+40 05 60 00 be 77 a1 20 20 03 60 00 65 40 65 00
+40 09 60 00 bd 77 42 22 a0 02 60 00 60 03 60 00

diff --git a/src/intel/tools/tests/gen6/and.asm b/src/intel/tools/tests/gen6/and.asm
new file mode 100644 (file)
index 0000000..72f35e5
--- /dev/null
+++ b/src/intel/tools/tests/gen6/and.asm
@@ -0,0 +1,19 @@
+and(8)          g22<1>UD        g21<8,8,1>UD    g20<8,8,1>UD    { align1 1Q };
+and.nz.f0.0(8)  null<1>UD       g24<8,8,1>UD    g25<8,8,1>UD    { align1 1Q };
+and(16)         g41<1>UD        g39<8,8,1>UD    g37<8,8,1>UD    { align1 1H };
+and.nz.f0.0(16) null<1>UD       g45<8,8,1>UD    g47<8,8,1>UD    { align1 1H };
+and(1)          g28<1>UD        g55<0,1,0>UD    0x0000ffffUD    { align1 1N };
+and(8)          g64<1>.xUD      g27<4>.xUD      0x0000ffffUD    { align16 1Q };
+and(8)          g12<1>UD        g11<8,8,1>UD    0x00000001UD    { align1 1Q };
+and(16)         g19<1>UD        g17<8,8,1>UD    0x00000001UD    { align1 1H };
+and(8)          g16<1>.xUD      g4<4>.yUD       g3<4>.xUD       { align16 1Q };
+and(8)          g5<1>D          g2.4<0,1,0>D    -g2.4<0,1,0>D   { align1 1Q };
+and(16)         g6<1>D          g2.4<0,1,0>D    -g2.4<0,1,0>D   { align1 1H };
+and(1)          g22<1>UD        g0<0,1,0>UD     0x000000c0UD    { align1 WE_all 1N };
+and(8)          g12<1>D         g1.4<0>D        -g1.4<0>D       { align16 1Q };
+and.nz.f0.0(8)  null<1>.xUD     g90<4>.xUD      g89<4>.xUD      { align16 1Q };
+and.nz.f0.0(8)  null<1>UD       g4<0,1,0>UD     0x00000001UD    { align1 1Q };
+and.nz.f0.0(16) null<1>UD       g6<0,1,0>UD     0x00000001UD    { align1 1H };
+and.z.f0.0(8)   null<1>UD       g20<8,8,1>UD    0x00000001UD    { align1 1Q };
+and.z.f0.0(16)  null<1>UD       g33<8,8,1>UD    0x00000001UD    { align1 1H };
+and.z.f0.0(8)   null<1>.xUD     g3<4>.xUD       0x00000001UD    { align16 1Q };

diff --git a/src/intel/tools/tests/gen6/and.expected b/src/intel/tools/tests/gen6/and.expected
new file mode 100644 (file)
index 0000000..c8926d0
--- /dev/null
+++ b/src/intel/tools/tests/gen6/and.expected
@@ -0,0 +1,19 @@
+05 00 60 00 21 04 c0 22 a0 02 8d 00 80 02 8d 00
+05 00 60 02 20 04 00 20 00 03 8d 00 20 03 8d 00
+05 00 80 00 21 04 20 25 e0 04 8d 00 a0 04 8d 00
+05 00 80 02 20 04 00 20 a0 05 8d 00 e0 05 8d 00
+05 00 00 00 21 0c 80 23 e0 06 00 00 ff ff 00 00
+05 01 60 00 21 0c 01 28 60 03 60 00 ff ff 00 00
+05 00 60 00 21 0c 80 21 60 01 8d 00 01 00 00 00
+05 00 80 00 21 0c 60 22 20 02 8d 00 01 00 00 00
+05 01 60 00 21 04 01 22 85 00 65 00 60 00 60 00
+05 00 60 00 a5 14 a0 20 50 00 00 00 50 40 00 00
+05 00 80 00 a5 14 c0 20 50 00 00 00 50 40 00 00
+05 02 00 00 21 0c c0 22 00 00 00 00 c0 00 00 00
+05 01 60 00 a5 14 8f 21 34 00 0e 00 34 40 0e 00
+05 01 60 02 20 04 01 20 40 0b 60 00 20 0b 60 00
+05 00 60 02 20 0c 00 20 80 00 00 00 01 00 00 00
+05 00 80 02 20 0c 00 20 c0 00 00 00 01 00 00 00
+05 00 60 01 20 0c 00 20 80 02 8d 00 01 00 00 00
+05 00 80 01 20 0c 00 20 20 04 8d 00 01 00 00 00
+05 01 60 01 20 0c 01 20 60 00 60 00 01 00 00 00

diff --git a/src/intel/tools/tests/gen6/asr.asm b/src/intel/tools/tests/gen6/asr.asm
new file mode 100644 (file)
index 0000000..65cb48e
--- /dev/null
+++ b/src/intel/tools/tests/gen6/asr.asm
@@ -0,0 +1,13 @@
+asr(8)          g11<1>D         g11<4>D         16D             { align16 1Q };
+asr(8)          g2<1>D          g2<8,8,1>D      16D             { align1 1Q };
+asr(16)         g2<1>D          g2<8,8,1>D      16D             { align1 1H };
+asr(8)          g6<1>D          g5<8,8,1>D      0x00000001UD    { align1 1Q };
+asr(16)         g8<1>D          g6<8,8,1>D      0x00000001UD    { align1 1H };
+asr.nz.f0.0(8)  null<1>D        -g0<0,1,0>W     15D             { align1 1Q };
+asr.nz.f0.0(16) null<1>D        -g0<0,1,0>W     15D             { align1 1H };
+asr(8)          g2<1>D          -g0<0,1,0>W     15D             { align1 1Q };
+asr(16)         g2<1>D          -g0<0,1,0>W     15D             { align1 1H };
+asr(8)          g26<1>D         g25<4>D         g20<4>UD        { align16 1Q };
+asr(8)          g16<1>D         g15<4>D         0x00000017UD    { align16 1Q };
+asr(8)          g14<1>D         g10<8,8,1>D     g8<8,8,1>UD     { align1 1Q };
+asr(16)         g21<1>D         g13<8,8,1>D     g9<8,8,1>UD     { align1 1H };

diff --git a/src/intel/tools/tests/gen6/asr.expected b/src/intel/tools/tests/gen6/asr.expected
new file mode 100644 (file)
index 0000000..da7461d
--- /dev/null
+++ b/src/intel/tools/tests/gen6/asr.expected
@@ -0,0 +1,13 @@
+0c 01 60 00 a5 1c 6f 21 64 01 6e 00 10 00 00 00
+0c 00 60 00 a5 1c 40 20 40 00 8d 00 10 00 00 00
+0c 00 80 00 a5 1c 40 20 40 00 8d 00 10 00 00 00
+0c 00 60 00 a5 0c c0 20 a0 00 8d 00 01 00 00 00
+0c 00 80 00 a5 0c 00 21 c0 00 8d 00 01 00 00 00
+0c 00 60 02 a4 1d 00 20 00 40 00 00 0f 00 00 00
+0c 00 80 02 a4 1d 00 20 00 40 00 00 0f 00 00 00
+0c 00 60 00 a5 1d 40 20 00 40 00 00 0f 00 00 00
+0c 00 80 00 a5 1d 40 20 00 40 00 00 0f 00 00 00
+0c 01 60 00 a5 04 4f 23 24 03 6e 00 84 02 6e 00
+0c 01 60 00 a5 0c 0f 22 e4 01 6e 00 17 00 00 00
+0c 00 60 00 a5 04 c0 21 40 01 8d 00 00 01 8d 00
+0c 00 80 00 a5 04 a0 22 a0 01 8d 00 20 01 8d 00

diff --git a/src/intel/tools/tests/gen6/break.asm b/src/intel/tools/tests/gen6/break.asm
new file mode 100644 (file)
index 0000000..4b8afa9
--- /dev/null
+++ b/src/intel/tools/tests/gen6/break.asm
@@ -0,0 +1,6 @@
+break(8)        JIP: 2          UIP: 12                         { align16 1Q };
+break(8)        JIP: 2          UIP: 104                        { align1 1Q };
+break(16)       JIP: 2          UIP: 104                        { align1 1H };
+(+f0.0) break(8) JIP: 4         UIP: 12                         { align1 1Q };
+(+f0.0) break(16) JIP: 4        UIP: 12                         { align1 1H };
+(+f0.0.x) break(8) JIP: 122     UIP: 124                        { align16 1Q };

diff --git a/src/intel/tools/tests/gen6/break.expected b/src/intel/tools/tests/gen6/break.expected
new file mode 100644 (file)
index 0000000..9ab35ec
--- /dev/null
+++ b/src/intel/tools/tests/gen6/break.expected
@@ -0,0 +1,6 @@
+28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 0c 00
+28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 68 00
+28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 68 00
+28 00 61 00 84 1c 00 20 00 00 8d 00 04 00 0c 00
+28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 0c 00
+28 01 62 00 84 1c 0f 20 04 00 6e 00 7a 00 7c 00

diff --git a/src/intel/tools/tests/gen6/cmp.asm b/src/intel/tools/tests/gen6/cmp.asm
new file mode 100644 (file)
index 0000000..9ac10dd
--- /dev/null
+++ b/src/intel/tools/tests/gen6/cmp.asm
@@ -0,0 +1,135 @@
+cmp.ge.f0.0(8)  g38<1>F         g37<8,8,1>F     0x3189705fF  /* 4e-09F */ { align1 1Q };
+cmp.l.f0.0(8)   g39<1>F         g37<8,8,1>F     0x3189705fF  /* 4e-09F */ { align1 1Q };
+cmp.ge.f0.0(16) g6<1>F          g4<8,8,1>F      0x3189705fF  /* 4e-09F */ { align1 1H };
+cmp.l.f0.0(16)  g8<1>F          g4<8,8,1>F      0x3189705fF  /* 4e-09F */ { align1 1H };
+cmp.ge.f0.0(8)  null<1>F        g38<4>.xF       g36<4>.xF       { align16 1Q };
+cmp.g.f0.0(8)   null<1>UD       g17<4>.xUD      0x00000000UD    { align16 1Q };
+cmp.ge.f0.0(8)  null<1>UD       g18<4>.xUD      g17<4>.xUD      { align16 1Q };
+cmp.l.f0.0(8)   null<1>F        g4.4<0,1,0>F    0x0F  /* 0F */  { align1 1Q };
+cmp.l.f0.0(16)  null<1>F        g6.4<0,1,0>F    0x0F  /* 0F */  { align1 1H };
+cmp.z.f0.0(8)   null<1>UD       g9<4>.xUD       0x00000000UD    { align16 1Q };
+cmp.l.f0.0(8)   null<1>UD       g20<4>.xUD      0x00000004UD    { align16 1Q };
+(+f0.0) cmp.nz.f0.0(8) null<1>UD g20<4>.xUD     0x00000000UD    { align16 1Q };
+cmp.l.f0.0(8)   null<1>D        g4<0,1,0>D      1D              { align1 1Q };
+cmp.z.f0.0(8)   g20<1>F         g3<8,8,1>F      g4.3<0,1,0>F    { align1 1Q };
+cmp.l.f0.0(16)  null<1>D        g6<0,1,0>D      1D              { align1 1H };
+cmp.z.f0.0(16)  g37<1>F         g4<8,8,1>F      g6.3<0,1,0>F    { align1 1H };
+cmp.z.f0.0(8)   null<1>F        g66<4>F         g3.4<0>F        { align16 1Q };
+cmp.l.f0.0(8)   g22<1>F         g21<8,8,1>F     g20<8,8,1>F     { align1 1Q };
+cmp.ge.f0.0(8)  g23<1>F         g21<8,8,1>F     g20<8,8,1>F     { align1 1Q };
+cmp.l.f0.0(16)  g25<1>F         g23<8,8,1>F     g2<8,8,1>F      { align1 1H };
+cmp.ge.f0.0(16) g27<1>F         g23<8,8,1>F     g2<8,8,1>F      { align1 1H };
+cmp.le.f0.0(8)  null<1>.zF      g7<4>.xF        0x0F  /* 0F */  { align16 1Q };
+cmp.le.f0.0(8)  null<1>UD       g60<4>UD        g29<4>UD        { align16 1Q };
+cmp.l.f0.0(8)   null<1>UD       g60<4>UD        g55<4>.xUD      { align16 1Q };
+cmp.z.f0.0(8)   null<1>D        g4<0,1,0>D      1D              { align1 1Q };
+cmp.z.f0.0(8)   null<1>F        g11<8,8,1>F     g4.1<0,1,0>F    { align1 1Q };
+cmp.z.f0.0(16)  null<1>D        g6<0,1,0>D      1D              { align1 1H };
+cmp.z.f0.0(16)  null<1>F        g17<8,8,1>F     g6.1<0,1,0>F    { align1 1H };
+cmp.z.f0.0(8)   g31<1>.yzwD     g3<0>.xD        g19<4>.yyzwD    { align16 1Q };
+cmp.nz.f0.0(8)  null<1>.xD      g31<4>.yD       0D              { align16 1Q };
+cmp.nz.f0.0(8)  g8<1>D          g5<8,8,1>D      g3.1<0,1,0>D    { align1 1Q };
+cmp.nz.f0.0(16) g12<1>D         g6<8,8,1>D      g3.1<0,1,0>D    { align1 1H };
+cmp.nz.f0.0(8)  null<1>D        g4<0,1,0>D      0D              { align1 1Q };
+cmp.nz.f0.0(16) null<1>D        g6<0,1,0>D      0D              { align1 1H };
+cmp.nz.f0.0(8)  g72<1>F         g74<8,8,1>F     g71<8,8,1>F     { align1 1Q };
+cmp.nz.f0.0(16) g77<1>F         g75<8,8,1>F     g71<8,8,1>F     { align1 1H };
+cmp.ge.f0.0(8)  null<1>.xD      g5<4>.xD        4D              { align16 1Q };
+cmp.z.f0.0(8)   g17<1>.xD       g1<0>.xD        1D              { align16 1Q };
+cmp.z.f0.0(8)   null<1>D        g2<4>.zD        g17<4>.xD       { align16 1Q };
+cmp.nz.f0.0(8)  null<1>F        g2.4<0,1,0>F    0x0F  /* 0F */  { align1 1Q };
+cmp.nz.f0.0(16) null<1>F        g2.4<0,1,0>F    0x0F  /* 0F */  { align1 1H };
+cmp.z.f0.0(8)   null<1>D        g4.4<0>.xD      0D              { align16 1Q };
+cmp.z.f0.0(8)   null<1>.xF      (abs)g13<4>.xF  0x7f800000F  /* infF */ { align16 1Q };
+cmp.nz.f0.0(8)  null<1>.xF      g13<4>.xF       g13<4>.xF       { align16 1Q };
+cmp.nz.f0.0(8)  null<1>F        g13<4>.xF       0x0F  /* 0F */  { align16 1Q };
+cmp.l.f0.0(8)   null<1>.xF      g5<4>.xF        g13<4>.xF       { align16 1Q };
+cmp.l.f0.0(8)   g10<1>UD        g9<4>UD         g1<0>UD         { align16 1Q };
+cmp.nz.f0.0(8)  null<1>D        -g10<4>D        g2<0>D          { align16 1Q };
+cmp.g.f0.0(8)   g34<1>F         g33<8,8,1>F     0x3727c5acF  /* 1e-05F */ { align1 1Q };
+cmp.le.f0.0(8)  g35<1>F         g33<8,8,1>F     0x3727c5acF  /* 1e-05F */ { align1 1Q };
+cmp.g.f0.0(16)  g8<1>F          g6<8,8,1>F      0x3727c5acF  /* 1e-05F */ { align1 1H };
+cmp.le.f0.0(16) g10<1>F         g6<8,8,1>F      0x3727c5acF  /* 1e-05F */ { align1 1H };
+cmp.z.f0.0(8)   g11<1>F         g9<4>.xF        g2<4>F          { align16 1Q };
+cmp.z.f0.0(8)   g3<1>D          g2.3<0,1,0>D    0D              { align1 1Q };
+cmp.nz.f0.0(8)  g4<1>D          g2.3<0,1,0>D    0D              { align1 1Q };
+cmp.z.f0.0(16)  g3<1>D          g2.3<0,1,0>D    0D              { align1 1H };
+cmp.nz.f0.0(16) g5<1>D          g2.3<0,1,0>D    0D              { align1 1H };
+cmp.le.f0.0(8)  g50<1>.xF       g44<4>.xF       0x3727c5acF  /* 1e-05F */ { align16 1Q };
+cmp.g.f0.0(8)   null<1>.xF      g49<4>.xF       0x3727c5acF  /* 1e-05F */ { align16 1Q };
+cmp.l.f0.0(8)   null<1>F        g39<4>.xF       0x3189705fF  /* 4e-09F */ { align16 1Q };
+cmp.nz.f0.0(8)  null<1>F        g4.4<0>F        0x48403000VF /* [0F, 1F, 2F, 3F]VF */ { align16 1Q };
+cmp.ge.f0.0(8)  g5<1>D          g2<0,1,0>D      1D              { align1 1Q };
+cmp.ge.f0.0(16) g7<1>D          g2<0,1,0>D      1D              { align1 1H };
+cmp.z.f0.0(8)   null<1>F        (abs)g10<8,8,1>F 0x7f800000F  /* infF */ { align1 1Q };
+cmp.nz.f0.0(8)  null<1>F        g10<8,8,1>F     g10<8,8,1>F     { align1 1Q };
+cmp.g.f0.0(8)   null<1>F        g10<8,8,1>F     0x0F  /* 0F */  { align1 1Q };
+cmp.z.f0.0(16)  null<1>F        (abs)g15<8,8,1>F 0x7f800000F  /* infF */ { align1 1H };
+cmp.nz.f0.0(16) null<1>F        g15<8,8,1>F     g15<8,8,1>F     { align1 1H };
+cmp.g.f0.0(16)  null<1>F        g15<8,8,1>F     0x0F  /* 0F */  { align1 1H };
+cmp.z.f0.0(8)   g3<1>F          g2.1<0,1,0>F    0x40800000F  /* 4F */ { align1 1Q };
+cmp.z.f0.0(16)  g3<1>F          g2.1<0,1,0>F    0x40800000F  /* 4F */ { align1 1H };
+cmp.ge.f0.0(8)  g77<1>.xD       g2<0>.xD        16D             { align16 1Q };
+cmp.l.f0.0(8)   g76<1>.xyzF     g8<0>.wF        g75<4>.xF       { align16 1Q };
+cmp.z.f0.0(8)   g6<1>D          g5<8,8,1>D      g2.5<0,1,0>D    { align1 1Q };
+cmp.z.f0.0(16)  g9<1>D          g7<8,8,1>D      g2.5<0,1,0>D    { align1 1H };
+cmp.le.f0.0(8)  null<1>D        g1<0>.xD        0D              { align16 1Q };
+cmp.l.f0.0(8)   g76<1>.xD       g74<4>.xD       7D              { align16 1Q };
+cmp.l.f0.0(8)   null<1>.xD      g74<4>.xD       3D              { align16 1Q };
+cmp.le.f0.0(8)  g4<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1Q };
+cmp.g.f0.0(8)   g5<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1Q };
+cmp.le.f0.0(16) g5<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1H };
+cmp.g.f0.0(16)  g7<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1H };
+cmp.le.f0.0(8)  null<1>F        g68<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
+cmp.le.f0.0(16) null<1>F        g2<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 1H };
+cmp.z.f0.0(8)   null<1>F        g3<0>.xyzzF     0x6e6e6c6aVF /* [13F, 14F, 15F, 15F]VF */ { align16 1Q };
+cmp.ge.f0.0(8)  g31<1>UD        g30<8,8,1>UD    g5.7<0,1,0>UD   { align1 1Q };
+cmp.l.f0.0(8)   g32<1>UD        g30<8,8,1>UD    g5.3<0,1,0>UD   { align1 1Q };
+(+f0.1) cmp.z.f0.1(8) null<1>D  g37<8,8,1>D     0D              { align1 1Q };
+cmp.ge.f0.0(16) g49<1>UD        g47<8,8,1>UD    g7.7<0,1,0>UD   { align1 1H };
+cmp.l.f0.0(16)  g51<1>UD        g47<8,8,1>UD    g7.3<0,1,0>UD   { align1 1H };
+(+f0.1) cmp.z.f0.1(16) null<1>D g80<8,8,1>D     0D              { align1 1H };
+cmp.ge.f0.0(8)  null<1>F        g13<8,8,1>F     0x38d1b717F  /* 0.0001F */ { align1 1Q };
+cmp.ge.f0.0(16) null<1>F        g21<8,8,1>F     0x38d1b717F  /* 0.0001F */ { align1 1H };
+cmp.g.f0.0(8)   g6<1>F          g2<4>F          0x3f000000F  /* 0.5F */ { align16 1Q };
+cmp.nz.f0.0(8)  g4<1>F          g2.2<0,1,0>F    0x0F  /* 0F */  { align1 1Q };
+cmp.nz.f0.0(16) g5<1>F          g2.2<0,1,0>F    0x0F  /* 0F */  { align1 1H };
+cmp.ge.f0.0(8)  null<1>D        g6<8,8,1>D      4D              { align1 1Q };
+cmp.nz.f0.0(8)  null<1>D        g8<8,8,1>D      g6<8,8,1>D      { align1 1Q };
+cmp.ge.f0.0(16) null<1>D        g10<8,8,1>D     4D              { align1 1H };
+cmp.nz.f0.0(16) null<1>D        g14<8,8,1>D     g10<8,8,1>D     { align1 1H };
+cmp.ge.f0.0(8)  g8<1>F          g1<0>F          g1.4<0>F        { align16 1Q };
+cmp.l.f0.0(8)   g54<1>D         g5<0,1,0>D      1D              { align1 1Q };
+cmp.l.f0.0(16)  g52<1>D         g7<0,1,0>D      1D              { align1 1H };
+cmp.nz.f0.0(8)  g13<1>.xyF      g12<4>.xyyyF    g12<4>.xyyyF    { align16 1Q };
+cmp.ge.f0.0(8)  null<1>F        g3<4>.xF        0x41f00000F  /* 30F */ { align16 1Q };
+cmp.g.f0.0(8)   null<1>D        g2.1<0,1,0>D    0D              { align1 1Q };
+cmp.ge.f0.0(8)  null<1>D        g3<8,8,1>D      g2.1<0,1,0>D    { align1 1Q };
+cmp.g.f0.0(16)  null<1>D        g2.1<0,1,0>D    0D              { align1 1H };
+cmp.ge.f0.0(16) null<1>D        g3<8,8,1>D      g2.1<0,1,0>D    { align1 1H };
+cmp.ge.f0.0(8)  g88<1>.xF       g8<4>.xF        0x3727c5acF  /* 1e-05F */ { align16 1Q };
+cmp.ge.f0.0(8)  null<1>.xD      g6<4>.xD        g3<0>.yD        { align16 1Q };
+cmp.g.f0.0(8)   null<1>.xD      g1<0>.xD        0D              { align16 1Q };
+cmp.z.f0.0(8)   null<1>D        g4<8,8,1>D      g2<0,1,0>D      { align1 1Q };
+cmp.z.f0.0(16)  null<1>D        g5<8,8,1>D      g2<0,1,0>D      { align1 1H };
+cmp.ge.f0.0(8)  null<1>F        g2<8,8,1>F      g8<8,8,1>F      { align1 1Q };
+cmp.ge.f0.0(16) null<1>F        g2<8,8,1>F      g11<8,8,1>F     { align1 1H };
+cmp.z.f0.0(8)   g8<1>.xF        g7<4>.xF        0x40533333F  /* 3.3F */ { align16 1Q };
+cmp.nz.f0.0(8)  g40<1>.xD       g7<4>.xD        g39<4>.xD       { align16 1Q };
+(+f0.1) cmp.nz.f0.1(8) null<1>UW g0<8,8,1>UW    g0<8,8,1>UW     { align1 1Q };
+(+f0.1) cmp.nz.f0.1(16) null<1>UW g0<8,8,1>UW   g0<8,8,1>UW     { align1 1H };
+cmp.nz.f0.0(8)  g20<1>.xD       g19<4>.xD       0D              { align16 1Q };
+cmp.nz.f0.0(8)  g8<1>F          g7<4>F          0x0F  /* 0F */  { align16 1Q };
+cmp.le.f0.0(8)  g3<1>D          g2<0,1,0>D      0D              { align1 1Q };
+cmp.le.f0.0(16) g3<1>D          g2<0,1,0>D      0D              { align1 1H };
+cmp.l.f0.0(8)   g12<1>.xF       g3<0>.zF        0x3f000000F  /* 0.5F */ { align16 1Q };
+cmp.l.f0.0(8)   null<1>.xD      g9<4>.xD        g5<4>.xD        { align16 1Q };
+cmp.ge.f0.0(8)  null<1>UD       g4<8,8,1>UD     g2.3<0,1,0>UD   { align1 1Q };
+cmp.ge.f0.0(16) null<1>UD       g5<8,8,1>UD     g2.3<0,1,0>UD   { align1 1H };
+cmp.l.f0.0(8)   null<1>D        g2.1<0,1,0>D    g3<8,8,1>D      { align1 1Q };
+cmp.l.f0.0(16)  null<1>D        g2.1<0,1,0>D    g3<8,8,1>D      { align1 1H };
+cmp.le.f0.0(8)  g9<1>.xUD       g1<0>.xUD       0x00000001UD    { align16 1Q };
+cmp.l.f0.0(8)   null<1>UD       g2<8,8,1>UD     g3<8,8,1>UD     { align1 1Q };
+cmp.l.f0.0(16)  null<1>UD       g2<8,8,1>UD     g4<8,8,1>UD     { align1 1H };
+cmp.l.f0.0(8)   null<1>F        (abs)g7<8,8,1>F (abs)g16<8,8,1>F { align1 1Q };
+cmp.l.f0.0(16)  null<1>F        (abs)g31<8,8,1>F (abs)g33<8,8,1>F { align1 1H };

diff --git a/src/intel/tools/tests/gen6/cmp.expected b/src/intel/tools/tests/gen6/cmp.expected
new file mode 100644 (file)
index 0000000..3a4d096
--- /dev/null
+++ b/src/intel/tools/tests/gen6/cmp.expected
@@ -0,0 +1,135 @@
+10 00 60 04 bd 7f c0 24 a0 04 8d 00 5f 70 89 31
+10 00 60 05 bd 7f e0 24 a0 04 8d 00 5f 70 89 31
+10 00 80 04 bd 7f c0 20 80 00 8d 00 5f 70 89 31
+10 00 80 05 bd 7f 00 21 80 00 8d 00 5f 70 89 31
+10 01 60 04 bc 77 0f 20 c0 04 60 00 80 04 60 00
+10 01 60 03 20 0c 0f 20 20 02 60 00 00 00 00 00
+10 01 60 04 20 04 0f 20 40 02 60 00 20 02 60 00
+10 00 60 05 bc 7f 00 20 90 00 00 00 00 00 00 00
+10 00 80 05 bc 7f 00 20 d0 00 00 00 00 00 00 00
+10 01 60 01 20 0c 0f 20 20 01 60 00 00 00 00 00
+10 01 60 05 20 0c 0f 20 80 02 60 00 04 00 00 00
+10 01 61 02 20 0c 0f 20 80 02 60 00 00 00 00 00
+10 00 60 05 a4 1c 00 20 80 00 00 00 01 00 00 00
+10 00 60 01 bd 77 80 22 60 00 8d 00 8c 00 00 00
+10 00 80 05 a4 1c 00 20 c0 00 00 00 01 00 00 00
+10 00 80 01 bd 77 a0 24 80 00 8d 00 cc 00 00 00
+10 01 60 01 bc 77 0f 20 44 08 6e 00 74 00 0e 00
+10 00 60 05 bd 77 c0 22 a0 02 8d 00 80 02 8d 00
+10 00 60 04 bd 77 e0 22 a0 02 8d 00 80 02 8d 00
+10 00 80 05 bd 77 20 23 e0 02 8d 00 40 00 8d 00
+10 00 80 04 bd 77 60 23 e0 02 8d 00 40 00 8d 00
+10 01 60 06 bc 7f 04 20 e0 00 60 00 00 00 00 00
+10 01 60 06 20 04 0f 20 84 07 6e 00 a4 03 6e 00
+10 01 60 05 20 04 0f 20 84 07 6e 00 e0 06 60 00
+10 00 60 01 a4 1c 00 20 80 00 00 00 01 00 00 00
+10 00 60 01 bc 77 00 20 60 01 8d 00 84 00 00 00
+10 00 80 01 a4 1c 00 20 c0 00 00 00 01 00 00 00
+10 00 80 01 bc 77 00 20 20 02 8d 00 c4 00 00 00
+10 01 60 01 a5 14 ee 23 60 00 00 00 65 02 6e 00
+10 01 60 02 a4 1c 01 20 e5 03 65 00 00 00 00 00
+10 00 60 02 a5 14 00 21 a0 00 8d 00 64 00 00 00
+10 00 80 02 a5 14 80 21 c0 00 8d 00 64 00 00 00
+10 00 60 02 a4 1c 00 20 80 00 00 00 00 00 00 00
+10 00 80 02 a4 1c 00 20 c0 00 00 00 00 00 00 00
+10 00 60 02 bd 77 00 29 40 09 8d 00 e0 08 8d 00
+10 00 80 02 bd 77 a0 29 60 09 8d 00 e0 08 8d 00
+10 01 60 04 a4 1c 01 20 a0 00 60 00 04 00 00 00
+10 01 60 01 a5 1c 21 22 20 00 00 00 01 00 00 00
+10 01 60 01 a4 14 0f 20 4a 00 6a 00 20 02 60 00
+10 00 60 02 bc 7f 00 20 50 00 00 00 00 00 00 00
+10 00 80 02 bc 7f 00 20 50 00 00 00 00 00 00 00
+10 01 60 01 a4 1c 0f 20 90 00 00 00 00 00 00 00
+10 01 60 01 bc 7f 01 20 a0 21 60 00 00 00 80 7f
+10 01 60 02 bc 77 01 20 a0 01 60 00 a0 01 60 00
+10 01 60 02 bc 7f 0f 20 a0 01 60 00 00 00 00 00
+10 01 60 05 bc 77 01 20 a0 00 60 00 a0 01 60 00
+10 01 60 05 21 04 4f 21 24 01 6e 00 24 00 0e 00
+10 01 60 02 a4 14 0f 20 44 41 6e 00 44 00 0e 00
+10 00 60 03 bd 7f 40 24 20 04 8d 00 ac c5 27 37
+10 00 60 06 bd 7f 60 24 20 04 8d 00 ac c5 27 37
+10 00 80 03 bd 7f 00 21 c0 00 8d 00 ac c5 27 37
+10 00 80 06 bd 7f 40 21 c0 00 8d 00 ac c5 27 37
+10 01 60 01 bd 77 6f 21 20 01 60 00 44 00 6e 00
+10 00 60 01 a5 1c 60 20 4c 00 00 00 00 00 00 00
+10 00 60 02 a5 1c 80 20 4c 00 00 00 00 00 00 00
+10 00 80 01 a5 1c 60 20 4c 00 00 00 00 00 00 00
+10 00 80 02 a5 1c a0 20 4c 00 00 00 00 00 00 00
+10 01 60 06 bd 7f 41 26 80 05 60 00 ac c5 27 37
+10 01 60 03 bc 7f 01 20 20 06 60 00 ac c5 27 37
+10 01 60 05 bc 7f 0f 20 e0 04 60 00 5f 70 89 31
+10 01 60 02 bc 5f 0f 20 94 00 0e 00 00 30 40 48
+10 00 60 04 a5 1c a0 20 40 00 00 00 01 00 00 00
+10 00 80 04 a5 1c e0 20 40 00 00 00 01 00 00 00
+10 00 60 01 bc 7f 00 20 40 21 8d 00 00 00 80 7f
+10 00 60 02 bc 77 00 20 40 01 8d 00 40 01 8d 00
+10 00 60 03 bc 7f 00 20 40 01 8d 00 00 00 00 00
+10 00 80 01 bc 7f 00 20 e0 21 8d 00 00 00 80 7f
+10 00 80 02 bc 77 00 20 e0 01 8d 00 e0 01 8d 00
+10 00 80 03 bc 7f 00 20 e0 01 8d 00 00 00 00 00
+10 00 60 01 bd 7f 60 20 44 00 00 00 00 00 80 40
+10 00 80 01 bd 7f 60 20 44 00 00 00 00 00 80 40
+10 01 60 04 a5 1c a1 29 40 00 00 00 10 00 00 00
+10 01 60 05 bd 77 87 29 0f 01 0f 00 60 09 60 00
+10 00 60 01 a5 14 c0 20 a0 00 8d 00 54 00 00 00
+10 00 80 01 a5 14 20 21 e0 00 8d 00 54 00 00 00
+10 01 60 06 a4 1c 0f 20 20 00 00 00 00 00 00 00
+10 01 60 05 a5 1c 81 29 40 09 60 00 07 00 00 00
+10 01 60 05 a4 1c 01 20 40 09 60 00 03 00 00 00
+10 00 60 06 21 0c 80 20 40 00 00 00 01 00 00 00
+10 00 60 03 21 0c a0 20 40 00 00 00 01 00 00 00
+10 00 80 06 21 0c a0 20 40 00 00 00 01 00 00 00
+10 00 80 03 21 0c e0 20 40 00 00 00 01 00 00 00
+10 00 60 06 bc 7f 00 20 80 08 8d 00 00 00 00 3f
+10 00 80 06 bc 7f 00 20 40 00 8d 00 00 00 00 3f
+10 01 60 01 bc 5f 0f 20 64 00 0a 00 6a 6c 6e 6e
+10 00 60 04 21 04 e0 23 c0 03 8d 00 bc 00 00 00
+10 00 60 05 21 04 00 24 c0 03 8d 00 ac 00 00 00
+10 00 61 01 a4 1c 00 20 a0 04 8d 02 00 00 00 00
+10 00 80 04 21 04 20 26 e0 05 8d 00 fc 00 00 00
+10 00 80 05 21 04 60 26 e0 05 8d 00 ec 00 00 00
+10 00 81 01 a4 1c 00 20 00 0a 8d 02 00 00 00 00
+10 00 60 04 bc 7f 00 20 a0 01 8d 00 17 b7 d1 38
+10 00 80 04 bc 7f 00 20 a0 02 8d 00 17 b7 d1 38
+10 01 60 03 bd 7f cf 20 44 00 6e 00 00 00 00 3f
+10 00 60 02 bd 7f 80 20 48 00 00 00 00 00 00 00
+10 00 80 02 bd 7f a0 20 48 00 00 00 00 00 00 00
+10 00 60 04 a4 1c 00 20 c0 00 8d 00 04 00 00 00
+10 00 60 02 a4 14 00 20 00 01 8d 00 c0 00 8d 00
+10 00 80 04 a4 1c 00 20 40 01 8d 00 04 00 00 00
+10 00 80 02 a4 14 00 20 c0 01 8d 00 40 01 8d 00
+10 01 60 04 bd 77 0f 21 24 00 0e 00 34 00 0e 00
+10 00 60 05 a5 1c c0 26 a0 00 00 00 01 00 00 00
+10 00 80 05 a5 1c 80 26 e0 00 00 00 01 00 00 00
+10 01 60 02 bd 77 a3 21 84 01 65 00 84 01 65 00
+10 01 60 04 bc 7f 0f 20 60 00 60 00 00 00 f0 41
+10 00 60 03 a4 1c 00 20 44 00 00 00 00 00 00 00
+10 00 60 04 a4 14 00 20 60 00 8d 00 44 00 00 00
+10 00 80 03 a4 1c 00 20 44 00 00 00 00 00 00 00
+10 00 80 04 a4 14 00 20 60 00 8d 00 44 00 00 00
+10 01 60 04 bd 7f 01 2b 00 01 60 00 ac c5 27 37
+10 01 60 04 a4 14 01 20 c0 00 60 00 65 00 05 00
+10 01 60 03 a4 1c 01 20 20 00 00 00 00 00 00 00
+10 00 60 01 a4 14 00 20 80 00 8d 00 40 00 00 00
+10 00 80 01 a4 14 00 20 a0 00 8d 00 40 00 00 00
+10 00 60 04 bc 77 00 20 40 00 8d 00 00 01 8d 00
+10 00 80 04 bc 77 00 20 40 00 8d 00 60 01 8d 00
+10 01 60 01 bd 7f 01 21 e0 00 60 00 33 33 53 40
+10 01 60 02 a5 14 01 25 e0 00 60 00 e0 04 60 00
+10 00 61 02 28 25 00 20 00 00 8d 02 00 00 8d 00
+10 00 81 02 28 25 00 20 00 00 8d 02 00 00 8d 00
+10 01 60 02 a5 1c 81 22 60 02 60 00 00 00 00 00
+10 01 60 02 bd 7f 0f 21 e4 00 6e 00 00 00 00 00
+10 00 60 06 a5 1c 60 20 40 00 00 00 00 00 00 00
+10 00 80 06 a5 1c 60 20 40 00 00 00 00 00 00 00
+10 01 60 05 bd 7f 81 21 6a 00 0a 00 00 00 00 3f
+10 01 60 05 a4 14 01 20 20 01 60 00 a0 00 60 00
+10 00 60 04 20 04 00 20 80 00 8d 00 4c 00 00 00
+10 00 80 04 20 04 00 20 a0 00 8d 00 4c 00 00 00
+10 00 60 05 a4 14 00 20 44 00 00 00 60 00 8d 00
+10 00 80 05 a4 14 00 20 44 00 00 00 60 00 8d 00
+10 01 60 06 21 0c 21 21 20 00 00 00 01 00 00 00
+10 00 60 05 20 04 00 20 40 00 8d 00 60 00 8d 00
+10 00 80 05 20 04 00 20 40 00 8d 00 80 00 8d 00
+10 00 60 05 bc 77 00 20 e0 20 8d 00 00 22 8d 00
+10 00 80 05 bc 77 00 20 e0 23 8d 00 20 24 8d 00

diff --git a/src/intel/tools/tests/gen6/cont.asm b/src/intel/tools/tests/gen6/cont.asm
new file mode 100644 (file)
index 0000000..7f7a9c4
--- /dev/null
+++ b/src/intel/tools/tests/gen6/cont.asm
@@ -0,0 +1,3 @@
+cont(8)         JIP: 2          UIP: 8                          { align1 1Q };
+cont(16)        JIP: 2          UIP: 8                          { align1 1H };
+cont(8)         JIP: 2          UIP: 8                          { align16 1Q };

diff --git a/src/intel/tools/tests/gen6/cont.expected b/src/intel/tools/tests/gen6/cont.expected
new file mode 100644 (file)
index 0000000..a8376c2
--- /dev/null
+++ b/src/intel/tools/tests/gen6/cont.expected
@@ -0,0 +1,3 @@
+29 00 60 00 00 1c 00 34 00 14 60 00 02 00 08 00
+29 00 80 00 00 1c 00 34 00 14 60 00 02 00 08 00
+29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 08 00

diff --git a/src/intel/tools/tests/gen6/dp2.asm b/src/intel/tools/tests/gen6/dp2.asm
new file mode 100644 (file)
index 0000000..dd2b52c
--- /dev/null
+++ b/src/intel/tools/tests/gen6/dp2.asm
@@ -0,0 +1,7 @@
+dp2(8)          g91<1>F         g88<4>.xyyyF    g88<4>.xyyyF    { align16 1Q };
+dp2(8)          m4<1>.xF        g1<0>.yF        g1<0>.yF        { align16 NoDDClr 1Q };
+dp2(8)          m4<1>.yzF       g1<0>.xF        g1<0>.zwwwF     { align16 NoDDClr,NoDDChk 1Q };
+dp2(8)          m4<1>.wF        g1<0>.ywwwF     g1<0>.wyyyF     { align16 NoDDChk 1Q };
+dp2(8)          g4<1>.yF        g1<0>.xyyyF     g1.4<0>.xyyyF   { align16 NoDDClr 1Q };
+dp2(8)          g4<1>.zF        g1<0>.xyyyF     g1.4<0>.zwwwF   { align16 NoDDClr,NoDDChk 1Q };
+dp2(8)          g4<1>.wF        g1<0>.xyyyF     g2<0>.xyyyF     { align16 NoDDChk 1Q };

diff --git a/src/intel/tools/tests/gen6/dp2.expected b/src/intel/tools/tests/gen6/dp2.expected
new file mode 100644 (file)
index 0000000..9aa7928
--- /dev/null
+++ b/src/intel/tools/tests/gen6/dp2.expected
@@ -0,0 +1,7 @@
+57 01 60 00 bd 77 6f 2b 04 0b 65 00 04 0b 65 00
+57 05 60 00 be 77 81 20 25 00 05 00 25 00 05 00
+57 0d 60 00 be 77 86 20 20 00 00 00 2e 00 0f 00
+57 09 60 00 be 77 88 20 2d 00 0f 00 27 00 05 00
+57 05 60 00 bd 77 82 20 24 00 05 00 34 00 05 00
+57 0d 60 00 bd 77 84 20 24 00 05 00 3e 00 0f 00
+57 09 60 00 bd 77 88 20 24 00 05 00 44 00 05 00

diff --git a/src/intel/tools/tests/gen6/dp3.asm b/src/intel/tools/tests/gen6/dp3.asm
new file mode 100644 (file)
index 0000000..c51880a
--- /dev/null
+++ b/src/intel/tools/tests/gen6/dp3.asm
@@ -0,0 +1,10 @@
+dp3(8)          m4<1>.xF        g3<0>.xyzzF     g6<4>.xyzzF     { align16 NoDDClr 1Q };
+dp3(8)          m4<1>.yF        g3.4<0>.xyzzF   g6<4>.xyzzF     { align16 NoDDClr,NoDDChk 1Q };
+dp3(8)          g70<1>F         g67<4>.xyzzF    g67<4>.xyzzF    { align16 1Q };
+dp3(8)          m4<1>.xF        g4<4>.xyzzF     g5<4>.xyzzF     { align16 1Q };
+dp3.le.f0.0(8)  g42<1>.xF       g33<4>.xyzzF    g3.4<0>.xyzzF   { align16 1Q };
+dp3(8)          g21<1>.xF       g20<4>.xyzzF    g1<0>.xyzzF     { align16 NoDDClr 1Q };
+dp3(8)          g21<1>.yF       g20<4>.xyzzF    g1.4<0>.xyzzF   { align16 NoDDClr,NoDDChk 1Q };
+dp3(8)          g21<1>.zF       g20<4>.xyzzF    g2<0>.xyzzF     { align16 NoDDChk 1Q };
+dp3.sat(8)      g49<1>F         g38<4>.xyzzF    g43<4>.xyzzF    { align16 1Q };
+dp3.sat(8)      m4<1>F          g2<4>.xyzzF     g2<4>.xyzzF     { align16 1Q };

diff --git a/src/intel/tools/tests/gen6/dp3.expected b/src/intel/tools/tests/gen6/dp3.expected
new file mode 100644 (file)
index 0000000..2d71488
--- /dev/null
+++ b/src/intel/tools/tests/gen6/dp3.expected
@@ -0,0 +1,10 @@
+56 05 60 00 be 77 81 20 64 00 0a 00 c4 00 6a 00
+56 0d 60 00 be 77 82 20 74 00 0a 00 c4 00 6a 00
+56 01 60 00 bd 77 cf 28 64 08 6a 00 64 08 6a 00
+56 01 60 00 be 77 81 20 84 00 6a 00 a4 00 6a 00
+56 01 60 06 bd 77 41 25 24 04 6a 00 74 00 0a 00
+56 05 60 00 bd 77 a1 22 84 02 6a 00 24 00 0a 00
+56 0d 60 00 bd 77 a2 22 84 02 6a 00 34 00 0a 00
+56 09 60 00 bd 77 a4 22 84 02 6a 00 44 00 0a 00
+56 01 60 80 bd 77 2f 26 c4 04 6a 00 64 05 6a 00
+56 01 60 80 be 77 8f 20 44 00 6a 00 44 00 6a 00

diff --git a/src/intel/tools/tests/gen6/dp4.asm b/src/intel/tools/tests/gen6/dp4.asm
new file mode 100644 (file)
index 0000000..c873b54
--- /dev/null
+++ b/src/intel/tools/tests/gen6/dp4.asm
@@ -0,0 +1,9 @@
+dp4(8)          m3<1>.xF        g3<4>F          g1<0>F          { align16 NoDDClr 1Q };
+dp4(8)          m3<1>.yF        g3<4>F          g1.4<0>F        { align16 NoDDClr,NoDDChk 1Q };
+dp4(8)          m3<1>.wF        g3<4>F          g2.4<0>F        { align16 NoDDChk 1Q };
+dp4(8)          g6<1>.xF        g3<4>F          g1<0>F          { align16 1Q };
+dp4(8)          m3<1>.wF        g4<4>F          g2.4<0>F        { align16 1Q };
+dp4(8)          g26<1>.xF       g24<4>F         g5<0>F          { align16 NoDDClr 1Q };
+dp4(8)          g26<1>.yF       g24<4>F         g5.4<0>F        { align16 NoDDChk 1Q };
+dp4.sat(8)      m4<1>F          g2<4>.xF        g2<4>F          { align16 1Q };
+dp4(8)          g18<1>.xF       g2.4<0>F        0x3f800000F  /* 1F */ { align16 1Q };

diff --git a/src/intel/tools/tests/gen6/dp4.expected b/src/intel/tools/tests/gen6/dp4.expected
new file mode 100644 (file)
index 0000000..4de7901
--- /dev/null
+++ b/src/intel/tools/tests/gen6/dp4.expected
@@ -0,0 +1,9 @@
+54 05 60 00 be 77 61 20 64 00 6e 00 24 00 0e 00
+54 0d 60 00 be 77 62 20 64 00 6e 00 34 00 0e 00
+54 09 60 00 be 77 68 20 64 00 6e 00 54 00 0e 00
+54 01 60 00 bd 77 c1 20 64 00 6e 00 24 00 0e 00
+54 01 60 00 be 77 68 20 84 00 6e 00 54 00 0e 00
+54 05 60 00 bd 77 41 23 04 03 6e 00 a4 00 0e 00
+54 09 60 00 bd 77 42 23 04 03 6e 00 b4 00 0e 00
+54 01 60 80 be 77 8f 20 40 00 60 00 44 00 6e 00
+54 01 60 00 bd 7f 41 22 54 00 0e 00 00 00 80 3f

diff --git a/src/intel/tools/tests/gen6/dph.asm b/src/intel/tools/tests/gen6/dph.asm
new file mode 100644 (file)
index 0000000..e0fe694
--- /dev/null
+++ b/src/intel/tools/tests/gen6/dph.asm
@@ -0,0 +1,5 @@
+dph(8)          m4<1>.xF        g4<4>.xyzxF     g5<4>F          { align16 1Q };
+dph.sat(8)      m4<1>F          g1<0>.xyzxF     g3<4>F          { align16 1Q };
+dph(8)          m3<1>.xF        g5<4>.xyzxF     g1<0>F          { align16 NoDDClr 1Q };
+dph(8)          m3<1>.yF        g5<4>.xyzxF     g1.4<0>F        { align16 NoDDClr,NoDDChk 1Q };
+dph(8)          m3<1>.wF        g5<4>.xyzxF     g2.4<0>F        { align16 NoDDChk 1Q };

diff --git a/src/intel/tools/tests/gen6/dph.expected b/src/intel/tools/tests/gen6/dph.expected
new file mode 100644 (file)
index 0000000..2ef78a0
--- /dev/null
+++ b/src/intel/tools/tests/gen6/dph.expected
@@ -0,0 +1,5 @@
+55 01 60 00 be 77 81 20 84 00 62 00 a4 00 6e 00
+55 01 60 80 be 77 8f 20 24 00 02 00 64 00 6e 00
+55 05 60 00 be 77 61 20 a4 00 62 00 24 00 0e 00
+55 0d 60 00 be 77 62 20 a4 00 62 00 34 00 0e 00
+55 09 60 00 be 77 68 20 a4 00 62 00 54 00 0e 00

diff --git a/src/intel/tools/tests/gen6/else.asm b/src/intel/tools/tests/gen6/else.asm
new file mode 100644 (file)
index 0000000..71a09a3
--- /dev/null
+++ b/src/intel/tools/tests/gen6/else.asm
@@ -0,0 +1,3 @@
+else(8)         JIP: 12                                         { align1 1Q };
+else(16)        JIP: 12                                         { align1 1H };
+else(8)         JIP: 18                                         { align16 1Q };

diff --git a/src/intel/tools/tests/gen6/else.expected b/src/intel/tools/tests/gen6/else.expected
new file mode 100644 (file)
index 0000000..9e1b70e
--- /dev/null
+++ b/src/intel/tools/tests/gen6/else.expected
@@ -0,0 +1,3 @@
+24 00 60 00 8f 10 0c 00 00 00 8d 00 00 00 8d 00
+24 00 80 00 8f 10 0c 00 00 00 8d 00 00 00 8d 00
+24 01 60 00 8f 10 12 00 04 00 6e 00 04 00 6e 00

diff --git a/src/intel/tools/tests/gen6/endif.asm b/src/intel/tools/tests/gen6/endif.asm
new file mode 100644 (file)
index 0000000..b3a5066
--- /dev/null
+++ b/src/intel/tools/tests/gen6/endif.asm
@@ -0,0 +1,3 @@
+endif(8)        JIP: 2                                          { align16 1Q };
+endif(8)        JIP: 2                                          { align1 1Q };
+endif(16)       JIP: 2                                          { align1 1H };

diff --git a/src/intel/tools/tests/gen6/endif.expected b/src/intel/tools/tests/gen6/endif.expected
new file mode 100644 (file)
index 0000000..8bfc53e
--- /dev/null
+++ b/src/intel/tools/tests/gen6/endif.expected
@@ -0,0 +1,3 @@
+25 01 60 00 8f 10 02 00 04 00 6e 00 04 00 6e 00
+25 00 60 00 8f 10 02 00 00 00 8d 00 00 00 8d 00
+25 00 80 00 8f 10 02 00 00 00 8d 00 00 00 8d 00

diff --git a/src/intel/tools/tests/gen6/frc.asm b/src/intel/tools/tests/gen6/frc.asm
new file mode 100644 (file)
index 0000000..7639a63
--- /dev/null
+++ b/src/intel/tools/tests/gen6/frc.asm
@@ -0,0 +1,6 @@
+frc.sat(8)      m4<1>F          g3<4>F                          { align16 1Q };
+frc(8)          g19<1>.xF       (abs)g1<0>.xF                   { align16 1Q };
+frc(8)          g12<1>F         g6<8,8,1>F                      { align1 1Q };
+frc(16)         g18<1>F         g9<8,8,1>F                      { align1 1H };
+frc(8)          m1<1>F          g9<8,8,1>F                      { align1 1Q };
+frc(16)         m1<1>F          g11<8,8,1>F                     { align1 1H };

diff --git a/src/intel/tools/tests/gen6/frc.expected b/src/intel/tools/tests/gen6/frc.expected
new file mode 100644 (file)
index 0000000..c643a28
--- /dev/null
+++ b/src/intel/tools/tests/gen6/frc.expected
@@ -0,0 +1,6 @@
+43 01 60 80 be 03 8f 20 64 00 6e 00 00 00 00 00
+43 01 60 00 bd 03 61 22 20 20 00 00 00 00 00 00
+43 00 60 00 bd 03 80 21 c0 00 8d 00 00 00 00 00
+43 00 80 00 bd 03 40 22 20 01 8d 00 00 00 00 00
+43 00 60 00 be 03 20 20 20 01 8d 00 00 00 00 00
+43 00 80 00 be 03 20 20 60 01 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen6/halt.asm b/src/intel/tools/tests/gen6/halt.asm
new file mode 100644 (file)
index 0000000..3674b30
--- /dev/null
+++ b/src/intel/tools/tests/gen6/halt.asm
@@ -0,0 +1,4 @@
+(-f0.1.any4h) halt(8) JIP: 96   UIP: 98                         { align1 1Q };
+halt(8)         JIP: 2          UIP: 2                          { align1 1Q };
+(-f0.1.any4h) halt(16) JIP: 100 UIP: 102                        { align1 1H };
+halt(16)        JIP: 2          UIP: 2                          { align1 1H };

diff --git a/src/intel/tools/tests/gen6/halt.expected b/src/intel/tools/tests/gen6/halt.expected
new file mode 100644 (file)
index 0000000..b5b612a
--- /dev/null
+++ b/src/intel/tools/tests/gen6/halt.expected
@@ -0,0 +1,4 @@
+2a 00 76 00 84 1c 00 20 00 00 8d 02 60 00 62 00
+2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
+2a 00 96 00 84 1c 00 20 00 00 8d 02 64 00 66 00
+2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen6/if.asm b/src/intel/tools/tests/gen6/if.asm
new file mode 100644 (file)
index 0000000..532dbda
--- /dev/null
+++ b/src/intel/tools/tests/gen6/if.asm
@@ -0,0 +1,6 @@
+(+f0.0) if(8)   JIP: 84                                         { align16 1Q };
+(+f0.0) if(8)   JIP: 32                                         { align1 1Q };
+(+f0.0) if(16)  JIP: 32                                         { align1 1H };
+(+f0.0.x) if(8) JIP: 18                                         { align16 1Q };
+(-f0.0) if(8)   JIP: 12                                         { align1 1Q };
+(-f0.0) if(16)  JIP: 12                                         { align1 1H };

diff --git a/src/intel/tools/tests/gen6/if.expected b/src/intel/tools/tests/gen6/if.expected
new file mode 100644 (file)
index 0000000..e5a2666
--- /dev/null
+++ b/src/intel/tools/tests/gen6/if.expected
@@ -0,0 +1,6 @@
+22 01 61 00 8f 10 54 00 04 00 0e 00 04 00 0e 00
+22 00 61 00 8f 10 20 00 00 00 00 00 00 00 00 00
+22 00 81 00 8f 10 20 00 00 00 00 00 00 00 00 00
+22 01 62 00 8f 10 12 00 04 00 0e 00 04 00 0e 00
+22 00 71 00 8f 10 0c 00 00 00 00 00 00 00 00 00
+22 00 91 00 8f 10 0c 00 00 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen6/lrp.asm b/src/intel/tools/tests/gen6/lrp.asm
new file mode 100644 (file)
index 0000000..eaae1db
--- /dev/null
+++ b/src/intel/tools/tests/gen6/lrp.asm
@@ -0,0 +1,8 @@
+lrp(8)          g10<1>.xF       g2.2<0,1,0>F    g2.1<0,1,0>F    g2.0<0,1,0>F { align16 1Q };
+lrp(8)          m1<1>F          g34<4,4,1>F     g4<4,4,1>F      g64<4,4,1>F { align16 1Q };
+lrp(8)          m2<1>F          g2<4,4,1>F      g6<4,4,1>F      g13<4,4,1>F { align16 2Q };
+lrp.sat(8)      g7<1>F          g12<4,4,1>F     g15<4,4,1>F     g18<4,4,1>F { align16 1Q };
+lrp.sat(8)      g18<1>F         g26<4,4,1>F     g13<4,4,1>F     g38<4,4,1>F { align16 2Q };
+lrp(8)          g2<1>F          g18<4,4,1>F     g2<4,4,1>F      g8<4,4,1>F { align16 2Q };
+lrp.sat(8)      m1<1>F          g6<4,4,1>F      g13<4,4,1>F     g4<4,4,1>F { align16 1Q };
+lrp.sat(8)      m2<1>F          g9<4,4,1>F      g27<4,4,1>F     g17<4,4,1>F { align16 2Q };

diff --git a/src/intel/tools/tests/gen6/lrp.expected b/src/intel/tools/tests/gen6/lrp.expected
new file mode 100644 (file)
index 0000000..deb5789
--- /dev/null
+++ b/src/intel/tools/tests/gen6/lrp.expected
@@ -0,0 +1,8 @@
+5c 01 60 00 00 00 02 0a 01 24 20 40 04 04 80 00
+5c 01 60 00 01 00 1e 01 c8 21 02 39 08 20 07 10
+5c 11 60 00 01 00 1e 02 c8 21 00 39 0c 20 47 03
+5c 01 60 80 00 00 1e 07 c8 c1 00 39 1e 20 87 04
+5c 11 60 80 00 00 1e 12 c8 a1 01 39 1a 20 87 09
+5c 11 60 00 00 00 1e 02 c8 21 01 39 04 20 07 02
+5c 01 60 80 01 00 1e 01 c8 61 00 39 1a 20 07 01
+5c 11 60 80 01 00 1e 02 c8 91 00 39 36 20 47 04

diff --git a/src/intel/tools/tests/gen6/lzd.asm b/src/intel/tools/tests/gen6/lzd.asm
new file mode 100644 (file)
index 0000000..d9ba856
--- /dev/null
+++ b/src/intel/tools/tests/gen6/lzd.asm
@@ -0,0 +1,3 @@
+lzd(8)          g16<1>UD        g17<4>UD                        { align16 1Q };
+lzd(8)          g4<1>UD         g5<8,8,1>UD                     { align1 1Q };
+lzd(16)         g4<1>UD         g6<8,8,1>UD                     { align1 1H };

diff --git a/src/intel/tools/tests/gen6/lzd.expected b/src/intel/tools/tests/gen6/lzd.expected
new file mode 100644 (file)
index 0000000..18c1fec
--- /dev/null
+++ b/src/intel/tools/tests/gen6/lzd.expected
@@ -0,0 +1,3 @@
+4a 01 60 00 21 00 0f 22 24 02 6e 00 00 00 00 00
+4a 00 60 00 21 00 80 20 a0 00 8d 00 00 00 00 00
+4a 00 80 00 21 00 80 20 c0 00 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen6/mach.asm b/src/intel/tools/tests/gen6/mach.asm
new file mode 100644 (file)
index 0000000..45eb5a3
--- /dev/null
+++ b/src/intel/tools/tests/gen6/mach.asm
@@ -0,0 +1,13 @@
+mach(8)         g12<1>UD        g10<8,8,1>UD    0xaaaaaaabUD    { align1 1Q AccWrEnable };
+mach(8)         g16<1>D         g10<8,8,1>D     1431655766D     { align1 1Q AccWrEnable };
+mach(16)        g17<1>UD        g14<8,8,1>UD    0xaaaaaaabUD    { align1 1H AccWrEnable };
+mach(16)        g25<1>D         g14<8,8,1>D     1431655766D     { align1 1H AccWrEnable };
+mach(8)         g9<1>D          g1<0>D          g1.4<0>D        { align16 1Q AccWrEnable };
+mach(8)         null<1>D        g1<4>.xD        741092396D      { align16 1Q AccWrEnable };
+mach(8)         g12<1>UD        g4<8,8,1>UD     g8<8,8,1>UD     { align1 1Q AccWrEnable };
+mach(16)        g20<1>UD        g4<8,8,1>UD     g12<8,8,1>UD    { align1 1H AccWrEnable };
+mach(8)         g13<1>D         g5<8,8,1>D      g9<8,8,1>D      { align1 1Q AccWrEnable };
+mach(16)        g21<1>D         g5<8,8,1>D      g13<8,8,1>D     { align1 1H AccWrEnable };
+mach(8)         null<1>D        g9<4>D          g11<4>D         { align16 1Q AccWrEnable };
+mach(8)         g24<1>.xUD      g22<4>.xUD      0x80000001UD    { align16 1Q AccWrEnable };
+mach(8)         g12<1>UD        g9<4>UD         g11<4>UD        { align16 1Q AccWrEnable };

diff --git a/src/intel/tools/tests/gen6/mach.expected b/src/intel/tools/tests/gen6/mach.expected
new file mode 100644 (file)
index 0000000..9799450
--- /dev/null
+++ b/src/intel/tools/tests/gen6/mach.expected
@@ -0,0 +1,13 @@
+49 00 60 10 21 0c 80 21 40 01 8d 00 ab aa aa aa
+49 00 60 10 a5 1c 00 22 40 01 8d 00 56 55 55 55
+49 00 80 10 21 0c 20 22 c0 01 8d 00 ab aa aa aa
+49 00 80 10 a5 1c 20 23 c0 01 8d 00 56 55 55 55
+49 01 60 10 a5 14 2f 21 24 00 0e 00 34 00 0e 00
+49 01 60 10 a4 1c 0f 20 20 00 60 00 2c 2c 2c 2c
+49 00 60 10 21 04 80 21 80 00 8d 00 00 01 8d 00
+49 00 80 10 21 04 80 22 80 00 8d 00 80 01 8d 00
+49 00 60 10 a5 14 a0 21 a0 00 8d 00 20 01 8d 00
+49 00 80 10 a5 14 a0 22 a0 00 8d 00 a0 01 8d 00
+49 01 60 10 a4 14 0f 20 24 01 6e 00 64 01 6e 00
+49 01 60 10 21 0c 01 23 c0 02 60 00 01 00 00 80
+49 01 60 10 21 04 8f 21 24 01 6e 00 64 01 6e 00

diff --git a/src/intel/tools/tests/gen6/mad.asm b/src/intel/tools/tests/gen6/mad.asm
new file mode 100644 (file)
index 0000000..164bfca
--- /dev/null
+++ b/src/intel/tools/tests/gen6/mad.asm
@@ -0,0 +1,41 @@
+mad(8)          g11<1>F         g4.7<0,1,0>F    g4.3<0,1,0>F    g9<4,4,1>F { align16 1Q };
+mad(8)          g17<1>F         g6.7<0,1,0>F    g6.3<0,1,0>F    g13<4,4,1>F { align16 2Q };
+mad(8)          m4<1>.xyzF      g9<4,4,1>.xyzzF g6<4,4,1>.xyzzF g30<4,4,1>.xyzzF { align16 NoDDClr 1Q };
+mad(8)          m3<1>F          g20<4,4,1>F     g5<4,4,1>.wF    g22<4,4,1>F { align16 1Q };
+mad.le.f0.0(8)  g5<1>F          g3<4,4,1>F      g4.2<0,1,0>F    g21<4,4,1>F { align16 1Q };
+mad.le.f0.0(8)  g4<1>F          g2<4,4,1>F      g6.2<0,1,0>F    g24<4,4,1>F { align16 2Q };
+mad(8)          m2<1>F          g26<4,4,1>F     g10<4,4,1>F     g18<4,4,1>F { align16 2Q };
+mad(8)          g5<1>F          -g3.0<0,1,0>F   g2.3<0,1,0>F    g2.0<0,1,0>F { align16 1Q };
+mad(8)          g5<1>F          -g3.0<0,1,0>F   g2.3<0,1,0>F    g2.0<0,1,0>F { align16 2Q };
+mad.sat(8)      m4<1>F          g26<4,4,1>F     g4.7<0,1,0>F    g10<4,4,1>F { align16 1Q };
+mad.sat(8)      m4<1>.xyzF      g109<4,4,1>.xyzzF g100<4,4,1>.xyzzF g107<4,4,1>.zF { align16 NoDDClr 1Q };
+mad(8)          g42<1>F         g41<4,4,1>F     g4.2<0,1,0>F    -g64.0<0,1,0>F { align16 1Q };
+mad(8)          g58<1>F         -g57<4,4,1>F    g53<4,4,1>F     -g53<4,4,1>F { align16 1Q };
+mad(8)          g76<1>F         -g56<4,4,1>F    -g64.1<0,1,0>F  -g53<4,4,1>F { align16 1Q };
+mad.sat(8)      g44<1>F         g43<4,4,1>F     g41<4,4,1>F     g26<4,4,1>F { align16 1Q };
+mad(8)          g4<1>F          g2<4,4,1>F      g6.2<0,1,0>F    -g12.0<0,1,0>F { align16 2Q };
+mad(8)          g2<1>F          -g22<4,4,1>F    g14<4,4,1>F     -g14<4,4,1>F { align16 2Q };
+mad(8)          g43<1>F         -g20<4,4,1>F    -g12.1<0,1,0>F  -g14<4,4,1>F { align16 2Q };
+mad.sat(8)      g12<1>F         g4<4,4,1>F      g68<4,4,1>F     g14<4,4,1>F { align16 2Q };
+mad(8)          m2<1>F          g11<4,4,1>F     g9<4,4,1>F      -g18.1<0,1,0>F { align16 1Q };
+mad(8)          m4<1>F          g2<4,4,1>F      g15<4,4,1>F     -g64.1<0,1,0>F { align16 2Q };
+mad(8)          m3<1>F          -g11.1<0,1,0>F  g2<4,4,1>F      g9<4,4,1>F { align16 1Q };
+mad(8)          m3<1>.xF        g1<4,4,1>.xF    g9<4,4,1>.xF    g2<4,4,1>.xF { align16 NoDDChk 1Q };
+mad(8)          g30<1>F         g44.4<0,1,0>F   -g44.5<0,1,0>F  g27<4,4,1>F { align16 1Q };
+mad(8)          g2<1>F          g45.4<0,1,0>F   -g45.5<0,1,0>F  g5<4,4,1>F { align16 2Q };
+mad.sat(8)      m4<1>.xyzF      -g9<4,4,1>.xyzzF g8<4,4,1>.zxyyF g6<4,4,1>.yzxxF { align16 NoDDClr 1Q };
+mad(8)          g3<1>.yF        g17<4,4,1>.yF   g6<4,4,1>.xF    g19<4,4,1>.xF { align16 NoDDClr 1Q };
+mad(8)          g2<1>F          -g2<4,4,1>F     (abs)g8<4,4,1>F g17.0<0,1,0>F { align16 1Q };
+mad(8)          g13<1>F         -g5<4,4,1>F     (abs)g3<4,4,1>F g17.0<0,1,0>F { align16 2Q };
+mad(8)          m2<1>F          -g64.0<0,1,0>F  g64.1<0,1,0>F   g10<4,4,1>F { align16 2Q };
+mad(8)          g5<1>F          -g20.0<0,1,0>F  g11<4,4,1>F     (abs)g6<4,4,1>F { align16 1Q };
+mad(8)          g13<1>F         g20.1<0,1,0>F   g5<4,4,1>F      (abs)g6<4,4,1>F { align16 1Q };
+mad(8)          g3<1>F          -g25.0<0,1,0>F  g6<4,4,1>F      (abs)g10<4,4,1>F { align16 2Q };
+mad(8)          g4<1>F          g25.1<0,1,0>F   g3<4,4,1>F      (abs)g10<4,4,1>F { align16 2Q };
+mad(8)          g7<1>.zF        g79<4,4,1>.xF   g36<4,4,1>.xF   g1.3<0,1,0>F { align16 NoDDClr,NoDDChk 1Q };
+mad(8)          g8<1>.wF        g92<4,4,1>.xF   g52<4,4,1>.xF   g1.3<0,1,0>F { align16 NoDDChk 1Q };
+mad(8)          g5<1>.xF        -g16<4,4,1>.xF  g2.2<0,1,0>F    g1.5<0,1,0>F { align16 NoDDClr 1Q };
+mad(8)          g6<1>.yF        -g23<4,4,1>.xF  g2.2<0,1,0>F    g1.0<0,1,0>F { align16 NoDDClr,NoDDChk 1Q };
+mad(8)          g5<1>.zF        -g26<4,4,1>.xF  g1.6<0,1,0>F    g1.1<0,1,0>F { align16 NoDDChk 1Q };
+mad.nz.f0.0(8)  g13<1>F         -g23.0<0,1,0>F  g9<4,4,1>F      g12<4,4,1>F { align16 1Q };
+mad.nz.f0.0(8)  g19<1>F         -g30.0<0,1,0>F  g10<4,4,1>F     g17<4,4,1>F { align16 2Q };

diff --git a/src/intel/tools/tests/gen6/mad.expected b/src/intel/tools/tests/gen6/mad.expected
new file mode 100644 (file)
index 0000000..217141e
--- /dev/null
+++ b/src/intel/tools/tests/gen6/mad.expected
@@ -0,0 +1,41 @@
+5b 01 60 00 00 00 1e 0b 01 4e 20 c0 08 20 47 02
+5b 11 60 00 00 00 1e 11 01 6e 20 c0 0c 20 47 03
+5b 05 60 00 01 00 0e 04 48 91 00 29 0c 20 85 07
+5b 01 60 00 01 00 1e 03 c8 41 c1 3f 0a 20 87 05
+5b 01 60 06 00 00 1e 05 c8 31 20 80 08 20 47 05
+5b 11 60 06 00 00 1e 04 c8 21 20 80 0c 20 07 06
+5b 11 60 00 01 00 1e 02 c8 a1 01 39 14 20 87 04
+5b 01 60 00 20 00 1e 05 01 30 20 c0 04 04 80 00
+5b 11 60 00 20 00 1e 05 01 30 20 c0 04 04 80 00
+5b 01 60 80 01 00 1e 04 c8 a1 21 c0 09 20 87 02
+5b 05 60 80 01 00 0e 04 48 d1 06 29 c8 50 c5 1a
+5b 01 60 00 00 02 1e 2a c8 91 22 80 08 04 00 10
+5b 01 60 00 20 02 1e 3a c8 91 03 39 6a 20 47 0d
+5b 01 60 00 a0 02 1e 4c c8 81 23 40 80 20 47 0d
+5b 01 60 80 00 00 1e 2c c8 b1 02 39 52 20 87 06
+5b 11 60 00 00 02 1e 04 c8 21 20 80 0c 04 00 03
+5b 11 60 00 20 02 1e 02 c8 61 01 39 1c 20 87 03
+5b 11 60 00 a0 02 1e 2b c8 41 21 40 18 20 87 03
+5b 11 60 80 00 00 1e 0c c8 41 00 39 88 20 87 03
+5b 01 60 00 01 02 1e 02 c8 b1 00 39 12 04 88 04
+5b 11 60 00 01 02 1e 04 c8 21 00 39 1e 04 08 10
+5b 01 60 00 21 00 1e 03 01 b2 00 39 04 20 47 02
+5b 09 60 00 01 00 02 03 00 10 00 00 12 00 80 00
+5b 01 60 00 80 00 1e 1e 01 c8 22 40 59 20 c7 06
+5b 11 60 00 80 00 1e 02 01 d8 22 40 5b 20 47 01
+5b 05 60 80 21 00 0e 04 48 91 80 14 10 48 80 01
+5b 05 60 00 00 00 04 03 aa 10 01 00 0c 00 c0 04
+5b 01 60 00 60 00 1e 02 c8 21 00 39 10 04 40 04
+5b 11 60 00 60 00 1e 0d c8 51 00 39 06 04 40 04
+5b 11 60 00 21 00 1e 02 01 00 24 40 80 20 87 02
+5b 01 60 00 20 01 1e 05 01 40 01 39 16 20 87 01
+5b 01 60 00 00 01 1e 0d 01 42 01 39 0a 20 87 01
+5b 11 60 00 20 01 1e 03 01 90 01 39 0c 20 87 02
+5b 11 60 00 00 01 1e 04 01 92 01 39 06 20 87 02
+5b 0d 60 00 00 00 08 07 00 f0 04 00 48 04 58 00
+5b 09 60 00 00 00 10 08 00 c0 05 00 68 04 58 00
+5b 05 60 00 20 00 02 05 00 00 21 80 04 04 68 00
+5b 0d 60 00 20 00 04 06 00 70 21 80 04 04 40 00
+5b 09 60 00 20 00 08 05 00 a0 21 80 03 04 48 00
+5b 01 60 02 20 00 1e 0d 01 70 01 39 12 20 07 03
+5b 11 60 02 20 00 1e 13 01 e0 01 39 14 20 47 04

diff --git a/src/intel/tools/tests/gen6/math.asm b/src/intel/tools/tests/gen6/math.asm
new file mode 100644 (file)
index 0000000..e970850
--- /dev/null
+++ b/src/intel/tools/tests/gen6/math.asm
@@ -0,0 +1,26 @@
+math inv(8)     g7<1>F          g10<8,8,1>F     null<8,8,1>F    { align1 1Q };
+math inv(8)     g13<1>F         g18<8,8,1>F     null<8,8,1>F    { align1 2Q };
+math pow(8)     g16<1>F         g15<8,8,1>F     g14<8,8,1>F     { align1 1Q };
+math pow(8)     g24<1>F         g22<8,8,1>F     g20<8,8,1>F     { align1 2Q };
+math cos(8)     g3<1>F          g2<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math cos(8)     g5<1>F          g3<8,8,1>F      null<8,8,1>F    { align1 2Q };
+math sqrt(8)    g16<1>F         g15<8,8,1>F     null<8,8,1>F    { align1 1Q };
+math log(8)     g21<1>F         g20<8,8,1>F     null<8,8,1>F    { align1 1Q };
+math sqrt(8)    g11<1>F         g3<8,8,1>F      null<8,8,1>F    { align1 2Q };
+math log(8)     g2<1>F          g13<8,8,1>F     null<8,8,1>F    { align1 2Q };
+math sin(8)     g23<1>F         g22<4,4,1>F     null<8,8,1>F    { align1 1Q };
+math exp(8)     g18<1>F         g17<4,4,1>F     null<8,8,1>F    { align1 1Q };
+math exp(8)     g19<1>F         g8<8,8,1>F      null<8,8,1>F    { align1 2Q };
+math rsq(8)     g71<1>F         g70<4,4,1>F     null<8,8,1>F    { align1 1Q };
+math sin(8)     g6<1>F          g4<8,8,1>F      null<8,8,1>F    { align1 2Q };
+math rsq(8)     g3<1>F          g5<8,8,1>F      null<8,8,1>F    { align1 2Q };
+math.sat pow(8) g4<1>F          g7<8,8,1>F      g13<8,8,1>F     { align1 1Q };
+math.sat pow(8) g2<1>F          g8<8,8,1>F      g14<8,8,1>F     { align1 2Q };
+math.sat sqrt(8) g4<1>F         g9<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math.sat sqrt(8) g2<1>F         g6<8,8,1>F      null<8,8,1>F    { align1 2Q };
+math.sat exp(8) g2<1>F          g5<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math.sat exp(8) g3<1>F          g8<8,8,1>F      null<8,8,1>F    { align1 2Q };
+math intmod(8)  g45<1>UD        g44<8,8,1>UD    g13<8,8,1>UD    { align1 1Q };
+math intdiv(8)  g52<1>D         g51<8,8,1>D     g12<8,8,1>D     { align1 1Q };
+math intmod(8)  g75<1>UD        g73<8,8,1>UD    g15<8,8,1>UD    { align1 2Q };
+math intdiv(8)  g87<1>D         g85<8,8,1>D     g13<8,8,1>D     { align1 2Q };

diff --git a/src/intel/tools/tests/gen6/math.expected b/src/intel/tools/tests/gen6/math.expected
new file mode 100644 (file)
index 0000000..a431308
--- /dev/null
+++ b/src/intel/tools/tests/gen6/math.expected
@@ -0,0 +1,26 @@
+38 00 60 01 bd 73 e0 20 40 01 8d 00 00 00 8d 00
+38 10 60 01 bd 73 a0 21 40 02 8d 00 00 00 8d 00
+38 00 60 0a bd 77 00 22 e0 01 8d 00 c0 01 8d 00
+38 10 60 0a bd 77 00 23 c0 02 8d 00 80 02 8d 00
+38 00 60 07 bd 73 60 20 40 00 8d 00 00 00 8d 00
+38 10 60 07 bd 73 a0 20 60 00 8d 00 00 00 8d 00
+38 00 60 04 bd 73 00 22 e0 01 8d 00 00 00 8d 00
+38 00 60 02 bd 73 a0 22 80 02 8d 00 00 00 8d 00
+38 10 60 04 bd 73 60 21 60 00 8d 00 00 00 8d 00
+38 10 60 02 bd 73 40 20 a0 01 8d 00 00 00 8d 00
+38 00 60 06 bd 73 e0 22 c0 02 69 00 00 00 8d 00
+38 00 60 03 bd 73 40 22 20 02 69 00 00 00 8d 00
+38 10 60 03 bd 73 60 22 00 01 8d 00 00 00 8d 00
+38 00 60 05 bd 73 e0 28 c0 08 69 00 00 00 8d 00
+38 10 60 06 bd 73 c0 20 80 00 8d 00 00 00 8d 00
+38 10 60 05 bd 73 60 20 a0 00 8d 00 00 00 8d 00
+38 00 60 8a bd 77 80 20 e0 00 8d 00 a0 01 8d 00
+38 10 60 8a bd 77 40 20 00 01 8d 00 c0 01 8d 00
+38 00 60 84 bd 73 80 20 20 01 8d 00 00 00 8d 00
+38 10 60 84 bd 73 40 20 c0 00 8d 00 00 00 8d 00
+38 00 60 83 bd 73 40 20 a0 00 8d 00 00 00 8d 00
+38 10 60 83 bd 73 60 20 00 01 8d 00 00 00 8d 00
+38 00 60 0d 21 04 a0 25 80 05 8d 00 a0 01 8d 00
+38 00 60 0c a5 14 80 26 60 06 8d 00 80 01 8d 00
+38 10 60 0d 21 04 60 29 20 09 8d 00 e0 01 8d 00
+38 10 60 0c a5 14 e0 2a a0 0a 8d 00 a0 01 8d 00

diff --git a/src/intel/tools/tests/gen6/mov.asm b/src/intel/tools/tests/gen6/mov.asm
new file mode 100644 (file)
index 0000000..7978500
--- /dev/null
+++ b/src/intel/tools/tests/gen6/mov.asm
@@ -0,0 +1,164 @@
+mov(8)          g7<1>F          g4<8,8,1>D                      { align1 1Q };
+mov(8)          m1<1>F          g7<8,8,1>F                      { align1 1Q };
+mov(16)         g7<1>F          g5<8,8,1>D                      { align1 1H };
+mov(16)         m1<1>F          g7<8,8,1>F                      { align1 1H };
+mov(8)          m2<1>D          0D                              { align16 1Q };
+mov(8)          m3<1>F          0x41880000F      /* 17F */      { align16 1Q };
+mov(8)          m1<1>UD         g0<4>UD                         { align16 WE_all 1Q };
+mov.sat(8)      m4<1>F          g4<4>F                          { align16 1Q };
+mov(8)          m2<1>.wF        g5<4>.xF                        { align16 1Q };
+mov(4)          m2<1>F          g2.3<8,2,4>F                    { align1 WE_all 1N };
+mov(8)          m2<1>D          g3.3<0,1,0>D                    { align1 1Q };
+mov(8)          m5<1>UD         g4.7<0,1,0>D                    { align1 1Q };
+mov(8)          g10<1>F         g2<0,1,0>F                      { align1 1Q };
+mov(8)          m2<1>F          0x0F             /* 0F */       { align1 1Q };
+mov(16)         m2<1>D          g3.3<0,1,0>D                    { align1 1H };
+mov(16)         m8<1>UD         g4.7<0,1,0>D                    { align1 1H };
+mov(16)         g17<1>F         g2<0,1,0>F                      { align1 1H };
+mov(16)         m3<1>F          0x0F             /* 0F */       { align1 1H };
+mov(8)          m5<1>UD         0D                              { align1 1Q };
+mov(8)          g2<1>F          g6<8,4,1>UW                     { align1 1Q };
+mov(8)          g7<1>D          g2<8,8,1>F                      { align1 1Q };
+mov(8)          m2<1>D          g11<8,8,1>F                     { align1 1Q };
+mov(16)         m8<1>UD         0D                              { align1 1H };
+mov(16)         g2<1>F          g4<8,8,1>UW                     { align1 1H };
+mov(16)         g8<1>D          g2<8,8,1>F                      { align1 1H };
+mov(16)         m2<1>D          g16<8,8,1>F                     { align1 1H };
+mov(8)          m1<1>F          -g38<8,8,1>D                    { align1 1Q };
+mov(16)         m1<1>F          -g6<8,8,1>D                     { align1 1H };
+mov(1)          m22<1>D         0D                              { align1 WE_all 1N };
+mov(8)          m23<1>D         g3<0>D                          { align16 1Q };
+mov(8)          g28<1>.xD       1D                              { align16 1Q };
+mov(1)          m22<1>D         g39<0,1,0>D                     { align1 WE_all 1N };
+mov(8)          m4<1>.xD        1059749626D                     { align16 NoDDClr 1Q };
+mov(8)          m4<1>.yD        1143373824D                     { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          m5<1>.yD        -1093874483D                    { align16 NoDDChk 1Q };
+mov(8)          m5<1>.xzF       0x7e0020VF      /* [0.5F, 0F, 30F, 0F]VF */ { align16 NoDDChk 1Q };
+mov(8)          m1<1>F          g0<8,8,1>F                      { align1 WE_all 1Q };
+mov(1)          m1.2<1>UD       0x000003f2UD                    { align1 WE_all 1N };
+mov(8)          m2<1>F          g16<8,8,1>F                     { align1 2Q };
+mov(8)          g5<1>F          0x30003000VF    /* [0F, 1F, 0F, 1F]VF */ { align16 1Q };
+mov(8)          m4<1>F          0x30003000VF    /* [0F, 1F, 0F, 1F]VF */ { align16 1Q };
+mov(8)          g21<1>F         g11<8,8,1>F                     { align1 2Q };
+mov(1)          g0.2<1>UD       0x00000000UD                    { align1 WE_all 1N };
+mov(8)          g6<1>.xUD       0x00000000UD                    { align16 1Q };
+mov(8)          g20<1>.xD       0x00000000UD                    { align16 1Q };
+mov(8)          g21<1>UD        0x00000000UD                    { align16 WE_all 1Q };
+mov(8)          m2<1>.xyzD      g3.4<0>.xyzzD                   { align16 NoDDClr 1Q };
+mov(8)          g22<1>.xD       g6<4>.xUD                       { align16 1Q };
+mov(8)          g27<1>UD        7D                              { align16 1Q };
+mov(1)          m1.1<1>UD       g9<0,1,0>UD                     { align1 WE_all 1N };
+mov(8)          m2<1>F          g30<4>F                         { align16 WE_all 1Q };
+mov(8)          g13<1>D         0D                              { align1 1Q };
+mov(16)         g9<1>D          0D                              { align1 1H };
+mov.sat(8)      m1<1>F          g2<0,1,0>F                      { align1 1Q };
+mov.sat(16)     m1<1>F          g2<0,1,0>F                      { align1 1H };
+mov(8)          g16<1>UD        g1.4<0>UD                       { align16 1Q };
+mov(8)          m4<1>.wD        g9<4>.wD                        { align16 NoDDChk 1Q };
+mov(8)          g19<1>.xD       g18<4>.xF                       { align16 1Q };
+mov(8)          m4<1>F          g[a0]<VxH,1,0>F                 { align1 1Q switch };
+mov(8)          m8<1>F          g[a0]<VxH,1,0>F                 { align1 2Q switch };
+mov(8)          m2<1>UD         0x00000000UD                    { align1 1Q };
+mov(16)         m2<1>UD         0x00000000UD                    { align1 1H };
+mov(8)          m3<1>F          g14<4>.xD                       { align16 1Q };
+mov.sat(8)      m4<1>.xF        0x3f800000F      /* 1F */       { align16 NoDDClr 1Q };
+mov.sat(8)      m4<1>.yF        0x3f666666F      /* 0.9F */     { align16 NoDDClr,NoDDChk 1Q };
+mov.sat(8)      m4<1>.wF        0x3f333333F      /* 0.7F */     { align16 NoDDChk 1Q };
+mov(1)          g32<1>F         0x40000000F      /* 2F */       { align1 WE_all 1N };
+mov(8)          m17<1>UD        g0<8,8,1>UD                     { align1 WE_all 1Q };
+mov(8)          g12<1>F         g11<4>D                         { align16 1Q };
+mov(8)          g30<1>.xyD      g3.4<0>.xyyyD                   { align16 NoDDClr 1Q };
+mov(8)          g30<1>.wD       0D                              { align16 NoDDChk 1Q };
+mov(4)          g28<1>F         g23.1<4,4,1>F                   { align1 WE_all 1N };
+mov(8)          g26<1>UD        0x403000VF      /* [0F, 1F, 2F, 0F]VF */ { align16 WE_all 1Q };
+mov(4)          m2<1>UD         g101<4>UD                       { align16 1N };
+mov(8)          g19<1>.yzwD     0x48403000VF    /* [0F, 1F, 2F, 3F]VF */ { align16 1Q };
+mov(8)          g11<1>UD        g11<4>F                         { align16 1Q };
+mov(8)          g12<1>F         g11<4>UD                        { align16 1Q };
+mov(8)          m1<1>UD         g3<8,8,1>UD                     { align1 1Q };
+mov(16)         m1<1>UD         g3<8,8,1>UD                     { align1 1H };
+mov(16)         g8<1>UD         g0<8,8,1>UD                     { align1 WE_all 1H };
+mov(8)          m1<1>F          g4<8,8,1>UD                     { align1 1Q };
+mov(16)         m1<1>F          g4<8,8,1>UD                     { align1 1H };
+mov(8)          m4<1>.xF        g1<0>.xD                        { align16 NoDDClr 1Q };
+mov(8)          m4<1>.yF        g40<4>.xD                       { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g15<1>.xF       g87<4>.xD                       { align16 NoDDClr 1Q };
+mov(8)          g15<1>.yF       g88<4>.xD                       { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          m4<1>.wF        g42<4>.xD                       { align16 NoDDChk 1Q };
+mov(8)          g15<1>.wF       g90<4>.xD                       { align16 NoDDChk 1Q };
+mov(8)          g7<1>F          g4<8,8,1>UD                     { align1 1Q };
+mov(16)         g7<1>F          g5<8,8,1>UD                     { align1 1H };
+mov(8)          g3<1>D          g11<4>D                         { align16 1Q };
+mov(8)          g20<1>F         g14<4>.xF                       { align16 1Q };
+mov(8)          g5<1>.yF        g21<4>.yF                       { align16 NoDDClr 1Q };
+mov(8)          g5<1>.zF        g23<4>.zF                       { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g6<1>.xzwD      g5<4>.wwywD                     { align16 NoDDChk 1Q };
+mov(8)          m3<1>.zwF       0x30000000VF    /* [0F, 0F, 0F, 1F]VF */ { align16 NoDDClr 1Q };
+mov.nz.f0.0(8)  g4<1>F          -(abs)g2<0,1,0>F                { align1 1Q };
+(+f0.0) mov(8)  g4<1>F          0xbf800000F      /* -1F */      { align1 1Q };
+mov.nz.f0.0(16) g4<1>F          -(abs)g2<0,1,0>F                { align1 1H };
+(+f0.0) mov(16) g4<1>F          0xbf800000F      /* -1F */      { align1 1H };
+mov(8)          g21<1>.xzwD     0D                              { align16 NoDDClr 1Q };
+mov(8)          g3<1>.yzwF      0x30000000VF    /* [0F, 0F, 0F, 1F]VF */ { align16 NoDDChk 1Q };
+mov(8)          g3<1>.xD        g6<4>.xD                        { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g3<1>.xF        -g18<4>.xF                      { align16 NoDDChk 1Q };
+mov.sat(8)      g12<1>.xF       g1<0>.zF                        { align16 1Q };
+(+f0.0.any4h) mov(8) g4<1>.xD   -1D                             { align16 1Q };
+mov(8)          m2<1>.zD        g2<4>.zD                        { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g3<1>.xyzF      g1.4<0>.xyzzUD                  { align16 NoDDClr 1Q };
+mov(8)          g3<1>.wF        g1<0>.xUD                       { align16 NoDDChk 1Q };
+mov(8)          g3<1>D          -g2<0,1,0>D                     { align1 1Q };
+mov(16)         g3<1>D          -g2<0,1,0>D                     { align1 1H };
+mov.nz.f0.0(8)  null<1>.xD      g1<0>.xD                        { align16 1Q };
+mov(8)          g2<1>UD         g2<8,8,1>F                      { align1 1Q };
+mov(16)         g2<1>UD         g2<8,8,1>F                      { align1 1H };
+mov.sat(8)      g10<1>F         g2.2<0,1,0>F                    { align1 1Q };
+mov.sat(16)     g15<1>F         g2.2<0,1,0>F                    { align1 1H };
+mov(8)          m3<1>.zwF       0D                              { align16 NoDDChk 1Q };
+mov.nz.f0.0(8)  null<1>D        g2<8,8,1>D                      { align1 1Q };
+mov.nz.f0.0(16) null<1>D        g87<8,8,1>D                     { align1 1H };
+mov(8)          m2<1>D          0D                              { align1 1Q };
+mov(16)         m2<1>D          0D                              { align1 1H };
+mov.sat(8)      m4<1>.wF        g20<4>.wF                       { align16 NoDDChk 1Q };
+mov(8)          g55<1>.zD       1045220557D                     { align16 NoDDClr,NoDDChk 1Q };
+(+f0.0.all4h) mov(8) g60<1>.xD  -1D                             { align16 1Q };
+mov(8)          m7<1>F          0x0F             /* 0F */       { align1 2Q };
+mov.sat(8)      m4<1>F          0x3f800000F      /* 1F */       { align16 1Q };
+mov(8)          g33<1>.xF       0x3e8F           /* 1.4013e-42F */ { align16 1Q };
+mov(1)          f0<1>UW         g1.14<0,1,0>UW                  { align1 WE_all 1N };
+(-f0.0) mov(8)  g4<1>F          g2<8,8,1>F                      { align1 1Q };
+(-f0.0) mov(8)  g8<1>F          g4<8,8,1>F                      { align1 2Q };
+mov(8)          m4<1>.xF        g8<4>.xF                        { align16 NoDDClr 1Q };
+mov(8)          m4<1>.yF        g8<4>.xF                        { align16 NoDDChk 1Q };
+mov(1)          g1<1>UD         g0.1<0,1,0>UD                   { align1 WE_all 1N };
+mov(1)          g7.14<1>UW      f0.1<0,1,0>UW                   { align1 WE_all 1N };
+mov(8)          g12<1>UW        0x32103210V                     { align1 WE_all 1Q };
+mov.sat(8)      m4<1>F          -g6<4>D                         { align16 1Q };
+mov(8)          m5<1>.yF        g4<4>.yF                        { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g12<1>.xD       acc0<4>D                        { align16 1Q };
+mov(8)          m8<1>.xyzD      0x737271VF      /* [17F, 18F, 19F, 0F]VF */ { align16 1Q };
+mov(8)          m7<1>.zwD       0x706e0000VF    /* [0F, 0F, 15F, 16F]VF */ { align16 NoDDChk 1Q };
+mov.sat(8)      m4<1>.xyzF      -g13<4>.xyzzD                   { align16 NoDDClr 1Q };
+mov(8)          m2<1>UD         0x0F             /* 0F */       { align1 1Q };
+mov(16)         m2<1>UD         0x0F             /* 0F */       { align1 1H };
+mov(8)          m1<1>UD         g4<8,8,1>UD                     { align1 WE_all 2Q };
+mov(8)          m4<1>.yF        0x40a00000F      /* 5F */       { align16 NoDDChk 1Q };
+mov(8)          g6<1>UD         0D                              { align1 1Q };
+mov(16)         g8<1>UD         0D                              { align1 1H };
+mov(8)          m4<1>.yzF       0x484000VF      /* [0F, 2F, 3F, 0F]VF */ { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          m4<1>F          g10<4>UD                        { align16 1Q };
+mov(8)          g20<1>.yzD      0x404800VF      /* [0F, 3F, 2F, 0F]VF */ { align16 NoDDChk 1Q };
+mov.sat(8)      m4<1>.yzF       g1<0>.xxzzF                     { align16 NoDDClr,NoDDChk 1Q };
+mov.sat(8)      m4<1>.xF        -g1<0>.wF                       { align16 NoDDClr 1Q };
+mov.sat(8)      m4<1>.yF        -g11<4>.xD                      { align16 NoDDClr,NoDDChk 1Q };
+mov.sat(8)      m4<1>.wF        -g13<4>.xD                      { align16 NoDDChk 1Q };
+mov(8)          m1<1>UD         g9<8,8,1>F                      { align1 1Q };
+mov(16)         m1<1>UD         g11<8,8,1>F                     { align1 1H };
+mov(8)          g84<1>UD        g80.1<16,8,2>UW                 { align1 1Q };
+mov(16)         g45<1>UD        g37.1<16,8,2>UW                 { align1 1H };
+mov(8)          g48<1>UD        g44.3<32,8,4>UB                 { align1 1Q };
+mov(16)         g99<1>UD        g91.3<32,8,4>UB                 { align1 1H };
+mov.z.f0.0(8)   null<1>D        g22<8,8,1>F                     { align1 1Q };
+mov.z.f0.0(16)  null<1>D        g28<8,8,1>F                     { align1 1H };
+mov.nz.f0.0(8)  g11<1>F         -(abs)g1<0>F                    { align16 1Q };
+(+f0.0) mov(8)  g11<1>F         0xbf800000F      /* -1F */      { align16 1Q };

diff --git a/src/intel/tools/tests/gen6/mov.expected b/src/intel/tools/tests/gen6/mov.expected
new file mode 100644 (file)
index 0000000..634f0d8
--- /dev/null
+++ b/src/intel/tools/tests/gen6/mov.expected
@@ -0,0 +1,164 @@
+01 00 60 00 bd 00 e0 20 80 00 8d 00 00 00 00 00
+01 00 60 00 be 03 20 20 e0 00 8d 00 00 00 00 00
+01 00 80 00 bd 00 e0 20 a0 00 8d 00 00 00 00 00
+01 00 80 00 be 03 20 20 e0 00 8d 00 00 00 00 00
+01 01 60 00 e6 10 4f 20 00 00 00 00 00 00 00 00
+01 01 60 00 fe 73 6f 20 00 00 00 00 00 00 88 41
+01 03 60 00 22 00 2f 20 04 00 6e 00 00 00 00 00
+01 01 60 80 be 03 8f 20 84 00 6e 00 00 00 00 00
+01 01 60 00 be 03 48 20 a0 00 60 00 00 00 00 00
+01 02 40 00 be 03 40 20 4c 00 87 00 00 00 00 00
+01 00 60 00 a6 00 40 20 6c 00 00 00 00 00 00 00
+01 00 60 00 a2 00 a0 20 9c 00 00 00 00 00 00 00
+01 00 60 00 bd 03 40 21 40 00 00 00 00 00 00 00
+01 00 60 00 fe 73 40 20 00 00 00 00 00 00 00 00
+01 00 80 00 a6 00 40 20 6c 00 00 00 00 00 00 00
+01 00 80 00 a2 00 00 21 9c 00 00 00 00 00 00 00
+01 00 80 00 bd 03 20 22 40 00 00 00 00 00 00 00
+01 00 80 00 fe 73 60 20 00 00 00 00 00 00 00 00
+01 00 60 00 e2 10 a0 20 00 00 00 00 00 00 00 00
+01 00 60 00 3d 01 40 20 c0 00 89 00 00 00 00 00
+01 00 60 00 a5 03 e0 20 40 00 8d 00 00 00 00 00
+01 00 60 00 a6 03 40 20 60 01 8d 00 00 00 00 00
+01 00 80 00 e2 10 00 21 00 00 00 00 00 00 00 00
+01 00 80 00 3d 01 40 20 80 00 8d 00 00 00 00 00
+01 00 80 00 a5 03 00 21 40 00 8d 00 00 00 00 00
+01 00 80 00 a6 03 40 20 00 02 8d 00 00 00 00 00
+01 00 60 00 be 00 20 20 c0 44 8d 00 00 00 00 00
+01 00 80 00 be 00 20 20 c0 40 8d 00 00 00 00 00
+01 02 00 00 e6 10 c0 22 00 00 00 00 00 00 00 00
+01 01 60 00 a6 00 ef 22 64 00 0e 00 00 00 00 00
+01 01 60 00 e5 10 81 23 00 00 00 00 01 00 00 00
+01 02 00 00 a6 00 c0 22 e0 04 00 00 00 00 00 00
+01 05 60 00 e6 10 81 20 00 00 00 00 fa 7e 2a 3f
+01 0d 60 00 e6 10 82 20 00 00 00 00 00 80 26 44
+01 09 60 00 e6 10 a2 20 00 00 00 00 cd cc cc be
+01 09 60 00 fe 52 a5 20 00 00 00 00 20 00 7e 00
+01 02 60 00 be 03 20 20 00 00 8d 00 00 00 00 00
+01 02 00 00 62 00 28 20 00 00 00 00 f2 03 00 00
+01 10 60 00 be 03 40 20 00 02 8d 00 00 00 00 00
+01 01 60 00 fd 52 af 20 00 00 00 00 00 30 00 30
+01 01 60 00 fe 52 8f 20 00 00 00 00 00 30 00 30
+01 10 60 00 bd 03 a0 22 60 01 8d 00 00 00 00 00
+01 02 00 00 61 00 08 20 00 00 00 00 00 00 00 00
+01 01 60 00 61 00 c1 20 00 00 00 00 00 00 00 00
+01 01 60 00 65 00 81 22 00 00 00 00 00 00 00 00
+01 03 60 00 61 00 af 22 00 00 00 00 00 00 00 00
+01 05 60 00 a6 00 47 20 74 00 0a 00 00 00 00 00
+01 01 60 00 25 00 c1 22 c0 00 60 00 00 00 00 00
+01 01 60 00 e1 10 6f 23 00 00 00 00 07 00 00 00
+01 02 00 00 22 00 24 20 20 01 00 00 00 00 00 00
+01 03 60 00 be 03 4f 20 c4 03 6e 00 00 00 00 00
+01 00 60 00 e5 10 a0 21 00 00 00 00 00 00 00 00
+01 00 80 00 e5 10 20 21 00 00 00 00 00 00 00 00
+01 00 60 80 be 03 20 20 40 00 00 00 00 00 00 00
+01 00 80 80 be 03 20 20 40 00 00 00 00 00 00 00
+01 01 60 00 21 00 0f 22 34 00 0e 00 00 00 00 00
+01 09 60 00 a6 00 88 20 2f 01 6f 00 00 00 00 00
+01 01 60 00 a5 03 61 22 40 02 60 00 00 00 00 00
+01 80 60 00 be 03 80 20 00 80 e0 01 00 00 00 00
+01 90 60 00 be 03 00 21 00 80 e0 01 00 00 00 00
+01 00 60 00 62 00 40 20 00 00 00 00 00 00 00 00
+01 00 80 00 62 00 40 20 00 00 00 00 00 00 00 00
+01 01 60 00 be 00 6f 20 c0 01 60 00 00 00 00 00
+01 05 60 80 fe 73 81 20 00 00 00 00 00 00 80 3f
+01 0d 60 80 fe 73 82 20 00 00 00 00 66 66 66 3f
+01 09 60 80 fe 73 88 20 00 00 00 00 33 33 33 3f
+01 02 00 00 fd 73 00 24 00 00 00 00 00 00 00 40
+01 02 60 00 22 00 20 22 00 00 8d 00 00 00 00 00
+01 01 60 00 bd 00 8f 21 64 01 6e 00 00 00 00 00
+01 05 60 00 a5 00 c3 23 74 00 05 00 00 00 00 00
+01 09 60 00 e5 10 c8 23 00 00 00 00 00 00 00 00
+01 02 40 00 bd 03 80 23 e4 02 69 00 00 00 00 00
+01 03 60 00 e1 52 4f 23 00 00 00 00 00 30 40 00
+01 01 40 00 22 00 4f 20 a4 0c 6e 00 00 00 00 00
+01 01 60 00 e5 52 6e 22 00 00 00 00 00 30 40 48
+01 01 60 00 a1 03 6f 21 64 01 6e 00 00 00 00 00
+01 01 60 00 3d 00 8f 21 64 01 6e 00 00 00 00 00
+01 00 60 00 22 00 20 20 60 00 8d 00 00 00 00 00
+01 00 80 00 22 00 20 20 60 00 8d 00 00 00 00 00
+01 02 80 00 21 00 00 21 00 00 8d 00 00 00 00 00
+01 00 60 00 3e 00 20 20 80 00 8d 00 00 00 00 00
+01 00 80 00 3e 00 20 20 80 00 8d 00 00 00 00 00
+01 05 60 00 be 00 81 20 20 00 00 00 00 00 00 00
+01 0d 60 00 be 00 82 20 00 05 60 00 00 00 00 00
+01 05 60 00 bd 00 e1 21 e0 0a 60 00 00 00 00 00
+01 0d 60 00 bd 00 e2 21 00 0b 60 00 00 00 00 00
+01 09 60 00 be 00 88 20 40 05 60 00 00 00 00 00
+01 09 60 00 bd 00 e8 21 40 0b 60 00 00 00 00 00
+01 00 60 00 3d 00 e0 20 80 00 8d 00 00 00 00 00
+01 00 80 00 3d 00 e0 20 a0 00 8d 00 00 00 00 00
+01 01 60 00 a5 00 6f 20 64 01 6e 00 00 00 00 00
+01 01 60 00 bd 03 8f 22 c0 01 60 00 00 00 00 00
+01 05 60 00 bd 03 a2 20 a5 02 65 00 00 00 00 00
+01 0d 60 00 bd 03 a4 20 ea 02 6a 00 00 00 00 00
+01 09 60 00 a5 00 cd 20 af 00 6d 00 00 00 00 00
+01 05 60 00 fe 52 6c 20 00 00 00 00 00 00 00 30
+01 00 60 02 bd 03 80 20 40 60 00 00 00 00 00 00
+01 00 61 00 fd 73 80 20 00 00 00 00 00 00 80 bf
+01 00 80 02 bd 03 80 20 40 60 00 00 00 00 00 00
+01 00 81 00 fd 73 80 20 00 00 00 00 00 00 80 bf
+01 05 60 00 e5 10 ad 22 00 00 00 00 00 00 00 00
+01 09 60 00 fd 52 6e 20 00 00 00 00 00 00 00 30
+01 0d 60 00 a5 00 61 20 c0 00 60 00 00 00 00 00
+01 09 60 00 bd 03 61 20 40 42 60 00 00 00 00 00
+01 01 60 80 bd 03 81 21 2a 00 0a 00 00 00 00 00
+01 01 66 00 e5 10 81 20 00 00 00 00 ff ff ff ff
+01 0d 60 00 a6 00 44 20 4a 00 6a 00 00 00 00 00
+01 05 60 00 3d 00 67 20 34 00 0a 00 00 00 00 00
+01 09 60 00 3d 00 68 20 20 00 00 00 00 00 00 00
+01 00 60 00 a5 00 60 20 40 40 00 00 00 00 00 00
+01 00 80 00 a5 00 60 20 40 40 00 00 00 00 00 00
+01 01 60 02 a4 00 01 20 20 00 00 00 00 00 00 00
+01 00 60 00 a1 03 40 20 40 00 8d 00 00 00 00 00
+01 00 80 00 a1 03 40 20 40 00 8d 00 00 00 00 00
+01 00 60 80 bd 03 40 21 48 00 00 00 00 00 00 00
+01 00 80 80 bd 03 e0 21 48 00 00 00 00 00 00 00
+01 09 60 00 fe 10 6c 20 00 00 00 00 00 00 00 00
+01 00 60 02 a4 00 00 20 40 00 8d 00 00 00 00 00
+01 00 80 02 a4 00 00 20 e0 0a 8d 00 00 00 00 00
+01 00 60 00 e6 10 40 20 00 00 00 00 00 00 00 00
+01 00 80 00 e6 10 40 20 00 00 00 00 00 00 00 00
+01 09 60 80 be 03 88 20 8f 02 6f 00 00 00 00 00
+01 0d 60 00 e5 10 e4 26 00 00 00 00 cd cc 4c 3e
+01 01 67 00 e5 10 81 27 00 00 00 00 ff ff ff ff
+01 10 60 00 fe 73 e0 20 00 00 00 00 00 00 00 00
+01 01 60 80 fe 73 8f 20 00 00 00 00 00 00 80 3f
+01 01 60 00 fd 73 21 24 00 00 00 00 e8 03 00 00
+01 02 00 00 28 01 00 26 3c 00 00 00 00 00 00 00
+01 00 71 00 bd 03 80 20 40 00 8d 00 00 00 00 00
+01 10 71 00 bd 03 00 21 80 00 8d 00 00 00 00 00
+01 05 60 00 be 03 81 20 00 01 60 00 00 00 00 00
+01 09 60 00 be 03 82 20 00 01 60 00 00 00 00 00
+01 02 00 00 21 00 20 20 04 00 00 00 00 00 00 00
+01 02 00 00 09 01 fc 20 02 06 00 00 00 00 00 00
+01 02 60 00 69 63 80 21 00 00 00 00 10 32 10 32
+01 01 60 80 be 00 8f 20 c4 40 6e 00 00 00 00 00
+01 0d 60 00 be 03 a2 20 85 00 65 00 00 00 00 00
+01 01 60 00 85 00 81 21 04 04 6e 00 00 00 00 00
+01 01 60 00 e6 52 07 21 00 00 00 00 71 72 73 00
+01 09 60 00 e6 52 ec 20 00 00 00 00 00 00 6e 70
+01 05 60 80 be 00 87 20 a4 41 6a 00 00 00 00 00
+01 00 60 00 e2 73 40 20 00 00 00 00 00 00 00 00
+01 00 80 00 e2 73 40 20 00 00 00 00 00 00 00 00
+01 12 60 00 22 00 20 20 80 00 8d 00 00 00 00 00
+01 09 60 00 fe 73 82 20 00 00 00 00 00 00 a0 40
+01 00 60 00 e1 10 c0 20 00 00 00 00 00 00 00 00
+01 00 80 00 e1 10 00 21 00 00 00 00 00 00 00 00
+01 0d 60 00 fe 52 86 20 00 00 00 00 00 40 48 00
+01 01 60 00 3e 00 8f 20 44 01 6e 00 00 00 00 00
+01 09 60 00 e5 52 86 22 00 00 00 00 00 48 40 00
+01 0d 60 80 be 03 86 20 20 00 0a 00 00 00 00 00
+01 05 60 80 be 03 81 20 2f 40 0f 00 00 00 00 00
+01 0d 60 80 be 00 82 20 60 41 60 00 00 00 00 00
+01 09 60 80 be 00 88 20 a0 41 60 00 00 00 00 00
+01 00 60 00 a2 03 20 20 20 01 8d 00 00 00 00 00
+01 00 80 00 a2 03 20 20 60 01 8d 00 00 00 00 00
+01 00 60 00 21 01 80 2a 02 0a ae 00 00 00 00 00
+01 00 80 00 21 01 a0 25 a2 04 ae 00 00 00 00 00
+01 00 60 00 21 02 00 26 83 05 cf 00 00 00 00 00
+01 00 80 00 21 02 60 2c 63 0b cf 00 00 00 00 00
+01 00 60 01 a4 03 00 20 c0 02 8d 00 00 00 00 00
+01 00 80 01 a4 03 00 20 80 03 8d 00 00 00 00 00
+01 01 60 02 bd 03 6f 21 24 60 0e 00 00 00 00 00
+01 01 61 00 fd 73 6f 21 00 00 00 00 00 00 80 bf

diff --git a/src/intel/tools/tests/gen6/mul.asm b/src/intel/tools/tests/gen6/mul.asm
new file mode 100644 (file)
index 0000000..6fb1567
--- /dev/null
+++ b/src/intel/tools/tests/gen6/mul.asm
@@ -0,0 +1,62 @@
+mul(8)          m3<1>F          g2<8,8,1>F      g8<8,8,1>F      { align1 1Q };
+mul(16)         m5<1>F          g2<8,8,1>F      g14<8,8,1>F     { align1 1H };
+mul(8)          g7<1>F          g44<8,8,1>F     g4.1<0,1,0>F    { align1 1Q };
+mul(16)         g18<1>F         g28<8,8,1>F     g6.1<0,1,0>F    { align1 1H };
+mul(8)          g39<1>.xD       g28<4>.xD       g5<0>.xD        { align16 1Q };
+mul(8)          g39<1>.xD       g39<4>.xD       2D              { align16 1Q };
+mul(8)          g38<1>.xF       g2<0>.yF        g2<0>.yF        { align16 1Q };
+mul(8)          m4<1>.xyF       g6<4>.xyyyF     0x3f000000F  /* 0.5F */ { align16 NoDDClr 1Q };
+mul(8)          g8<1>F          g3<4>F          0x37800000F  /* 1.52588e-05F */ { align16 1Q };
+mul(8)          g2<1>F          g5<8,8,1>F      0x40490fdbF  /* 3.14159F */ { align1 1Q };
+mul(16)         g2<1>F          g7<8,8,1>F      0x40490fdbF  /* 3.14159F */ { align1 1H };
+mul(8)          m4<1>F          g12<4>F         0x3b808081F  /* 0.00392157F */ { align16 1Q };
+mul(8)          g61<1>UD        g61<4>UD        0x00000003UD    { align16 1Q };
+mul(8)          m1<1>F          g6<8,8,1>F      0x3c23d70aF  /* 0.01F */ { align1 1Q };
+mul(16)         m1<1>F          g10<8,8,1>F     0x3c23d70aF  /* 0.01F */ { align1 1H };
+mul(8)          g41<1>F         g40<4>.yF       0x3000VF /* [0F, 1F, 0F, 0F]VF */ { align16 1Q };
+mul(8)          g3<1>.wF        g23<4>.xF       0x3f000000F  /* 0.5F */ { align16 NoDDClr 1Q };
+mul.sat(8)      g10<1>F         g9<8,8,1>F      0x40a00001F  /* 5F */ { align1 1Q };
+mul.sat(16)     g13<1>F         g11<8,8,1>F     0x40a00001F  /* 5F */ { align1 1H };
+mul(8)          acc0<1>UD       g10<8,8,1>UD    0xaaaaaaabUD    { align1 1Q };
+mul(8)          acc0<1>D        g10<8,8,1>D     1431655766D     { align1 1Q };
+mul(8)          g14<1>D         g14<8,8,1>D     g13<8,8,1>D     { align1 1Q };
+mul(16)         acc0<1>UD       g14<8,8,1>UD    0xaaaaaaabUD    { align1 1H };
+mul(16)         acc0<1>D        g14<8,8,1>D     1431655766D     { align1 1H };
+mul(16)         g21<1>D         g23<8,8,1>D     g19<8,8,1>D     { align1 1H };
+mul(8)          m4<1>.yF        g12<4>.xF       0x3b800000F  /* 0.00390625F */ { align16 NoDDChk 1Q };
+mul(8)          g3<1>D          g2<0,1,0>UW     g2.2<0,1,0>D    { align1 1Q };
+mul(16)         g3<1>D          g2<0,1,0>UW     g2.2<0,1,0>D    { align1 1H };
+mul(8)          acc0<1>D        g1<0>D          g1.4<0>D        { align16 1Q };
+mul.l.f0.0(8)   g20<1>F         g2<8,8,1>F      0x42700000F  /* 60F */ { align1 1Q };
+mul.l.f0.0(16)  g14<1>F         g2<8,8,1>F      0x42700000F  /* 60F */ { align1 1H };
+mul(8)          m3<1>.xF        g15<4>.xF       0x40a66666F  /* 5.2F */ { align16 NoDDClr,NoDDChk 1Q };
+mul.sat(8)      m4<1>F          g6<4>F          0x3b800000F  /* 0.00390625F */ { align16 1Q };
+mul(8)          acc0<1>D        g1<4>.xD        741092396D      { align16 1Q };
+mul(8)          acc0<1>UD       g4<8,8,1>UD     g8<8,8,1>UD     { align1 1Q };
+mul(16)         acc0<1>UD       g4<8,8,1>UD     g12<8,8,1>UD    { align1 1H };
+mul(8)          m3<1>.xyzF      g2<4>.xyzzF     g11<4>.xF       { align16 NoDDClr 1Q };
+mul.sat(8)      m2<1>F          g6<8,8,1>F      g5<8,8,1>F      { align1 1Q };
+mul.sat(16)     m2<1>F          g12<8,8,1>F     g10<8,8,1>F     { align1 1H };
+mul(8)          acc0<1>D        g5<8,8,1>D      g9<8,8,1>D      { align1 1Q };
+mul(16)         acc0<1>D        g5<8,8,1>D      g13<8,8,1>D     { align1 1H };
+mul.sat(8)      m4<1>F          g2<4>F          g2<4>F          { align16 1Q };
+mul(8)          m3<1>F          g2<4>F          g3<4>F          { align16 1Q };
+mul(8)          g3<1>D          g2<0,1,0>UW     1774483385D     { align1 1Q };
+mul(16)         g3<1>D          g2<0,1,0>UW     1774483385D     { align1 1H };
+mul(8)          g15<1>.zF       g61<4>.xF       0x3e800000F  /* 0.25F */ { align16 NoDDClr,NoDDChk 1Q };
+mul(8)          acc0<1>UD       g22<4>.xUD      0x80000001UD    { align16 1Q };
+mul.nz.f0.0(8)  g6<1>F          g12<8,8,1>F     0x3f808000F  /* 1.00391F */ { align1 1Q };
+mul.nz.f0.0(16) g9<1>F          g7<8,8,1>F      0x3f808000F  /* 1.00391F */ { align1 1H };
+mul.sat(8)      m4<1>.xyF       g1<0>.wzzzF     g3<4>.wzzzF     { align16 NoDDClr 1Q };
+mul.sat(8)      m4<1>.zwF       g1<0>.yyyxF     g3<4>.yyyxF     { align16 NoDDChk 1Q };
+mul.sat(8)      m4<1>F          g4<4>F          0x20303030VF /* [1F, 1F, 1F, 0.5F]VF */ { align16 1Q };
+mul(8)          g4<1>.xyzF      g16<4>.zyxxF    g20<4>.xF       { align16 NoDDClr 1Q };
+mul(8)          acc0<1>UD       g9<4>UD         g11<4>UD        { align16 1Q };
+mul(8)          m4<1>F          g3<4>F          0x20305454VF /* [5F, 5F, 1F, 0.5F]VF */ { align16 1Q };
+mul(8)          m4<1>.xyzF      g3<4>.xyzzF     0x30302020VF /* [0.5F, 0.5F, 1F, 1F]VF */ { align16 NoDDClr 1Q };
+mul(8)          g3<1>.wF        g1<0>.zF        g11<4>.xF       { align16 NoDDClr,NoDDChk 1Q };
+mul(8)          m4<1>.yF        g15<4>.xF       g11<4>.xF       { align16 NoDDClr,NoDDChk 1Q };
+mul(8)          m5<1>.yF        g31<4>.xF       g11<4>.xF       { align16 NoDDChk 1Q };
+mul(8)          m17<1>D         g10<8,8,1>D     g9<8,8,1>D      { align1 1Q };
+mul(16)         m17<1>D         g16<8,8,1>D     g14<8,8,1>D     { align1 1H };
+mul.sat(8)      m4<1>.xyzF      g12<4>.xF       0x3030VF /* [1F, 1F, 0F, 0F]VF */ { align16 NoDDClr 1Q };

diff --git a/src/intel/tools/tests/gen6/mul.expected b/src/intel/tools/tests/gen6/mul.expected
new file mode 100644 (file)
index 0000000..7b85bb5
--- /dev/null
+++ b/src/intel/tools/tests/gen6/mul.expected
@@ -0,0 +1,62 @@
+41 00 60 00 be 77 60 20 40 00 8d 00 00 01 8d 00
+41 00 80 00 be 77 a0 20 40 00 8d 00 c0 01 8d 00
+41 00 60 00 bd 77 e0 20 80 05 8d 00 84 00 00 00
+41 00 80 00 bd 77 40 22 80 03 8d 00 c4 00 00 00
+41 01 60 00 a5 14 e1 24 80 03 60 00 a0 00 00 00
+41 01 60 00 a5 1c e1 24 e0 04 60 00 02 00 00 00
+41 01 60 00 bd 77 c1 24 45 00 05 00 45 00 05 00
+41 05 60 00 be 7f 83 20 c4 00 65 00 00 00 00 3f
+41 01 60 00 bd 7f 0f 21 64 00 6e 00 00 00 80 37
+41 00 60 00 bd 7f 40 20 a0 00 8d 00 db 0f 49 40
+41 00 80 00 bd 7f 40 20 e0 00 8d 00 db 0f 49 40
+41 01 60 00 be 7f 8f 20 84 01 6e 00 81 80 80 3b
+41 01 60 00 21 0c af 27 a4 07 6e 00 03 00 00 00
+41 00 60 00 be 7f 20 20 c0 00 8d 00 0a d7 23 3c
+41 00 80 00 be 7f 20 20 40 01 8d 00 0a d7 23 3c
+41 01 60 00 bd 5f 2f 25 05 05 65 00 00 30 00 00
+41 05 60 00 bd 7f 68 20 e0 02 60 00 00 00 00 3f
+41 00 60 80 bd 7f 40 21 20 01 8d 00 01 00 a0 40
+41 00 80 80 bd 7f a0 21 60 01 8d 00 01 00 a0 40
+41 00 60 00 20 0c 00 24 40 01 8d 00 ab aa aa aa
+41 00 60 00 a4 1c 00 24 40 01 8d 00 56 55 55 55
+41 00 60 00 a5 14 c0 21 c0 01 8d 00 a0 01 8d 00
+41 00 80 00 20 0c 00 24 c0 01 8d 00 ab aa aa aa
+41 00 80 00 a4 1c 00 24 c0 01 8d 00 56 55 55 55
+41 00 80 00 a5 14 a0 22 e0 02 8d 00 60 02 8d 00
+41 09 60 00 be 7f 82 20 80 01 60 00 00 00 80 3b
+41 00 60 00 25 15 60 20 40 00 00 00 48 00 00 00
+41 00 80 00 25 15 60 20 40 00 00 00 48 00 00 00
+41 01 60 00 a4 14 0f 24 24 00 0e 00 34 00 0e 00
+41 00 60 05 bd 7f 80 22 40 00 8d 00 00 00 70 42
+41 00 80 05 bd 7f c0 21 40 00 8d 00 00 00 70 42
+41 0d 60 00 be 7f 61 20 e0 01 60 00 66 66 a6 40
+41 01 60 80 be 7f 8f 20 c4 00 6e 00 00 00 80 3b
+41 01 60 00 a4 1c 0f 24 20 00 60 00 2c 2c 2c 2c
+41 00 60 00 20 04 00 24 80 00 8d 00 00 01 8d 00
+41 00 80 00 20 04 00 24 80 00 8d 00 80 01 8d 00
+41 05 60 00 be 77 67 20 44 00 6a 00 60 01 60 00
+41 00 60 80 be 77 40 20 c0 00 8d 00 a0 00 8d 00
+41 00 80 80 be 77 40 20 80 01 8d 00 40 01 8d 00
+41 00 60 00 a4 14 00 24 a0 00 8d 00 20 01 8d 00
+41 00 80 00 a4 14 00 24 a0 00 8d 00 a0 01 8d 00
+41 01 60 80 be 77 8f 20 44 00 6e 00 44 00 6e 00
+41 01 60 00 be 77 6f 20 44 00 6e 00 64 00 6e 00
+41 00 60 00 25 1d 60 20 40 00 00 00 b9 77 c4 69
+41 00 80 00 25 1d 60 20 40 00 00 00 b9 77 c4 69
+41 0d 60 00 bd 7f e4 21 a0 07 60 00 00 00 80 3e
+41 01 60 00 20 0c 0f 24 c0 02 60 00 01 00 00 80
+41 00 60 02 bd 7f c0 20 80 01 8d 00 00 80 80 3f
+41 00 80 02 bd 7f 20 21 e0 00 8d 00 00 80 80 3f
+41 05 60 80 be 77 83 20 2b 00 0a 00 6b 00 6a 00
+41 09 60 80 be 77 8c 20 25 00 01 00 65 00 61 00
+41 01 60 80 be 5f 8f 20 84 00 6e 00 30 30 30 20
+41 05 60 00 bd 77 87 20 06 02 60 00 80 02 60 00
+41 01 60 00 20 04 0f 24 24 01 6e 00 64 01 6e 00
+41 01 60 00 be 5f 8f 20 64 00 6e 00 54 54 30 20
+41 05 60 00 be 5f 87 20 64 00 6a 00 20 20 30 30
+41 0d 60 00 bd 77 68 20 2a 00 0a 00 60 01 60 00
+41 0d 60 00 be 77 82 20 e0 01 60 00 60 01 60 00
+41 09 60 00 be 77 a2 20 e0 03 60 00 60 01 60 00
+41 00 60 00 a6 14 20 22 40 01 8d 00 20 01 8d 00
+41 00 80 00 a6 14 20 22 00 02 8d 00 c0 01 8d 00
+41 05 60 80 be 5f 87 20 80 01 60 00 30 30 00 00

diff --git a/src/intel/tools/tests/gen6/not.asm b/src/intel/tools/tests/gen6/not.asm
new file mode 100644 (file)
index 0000000..380433a
--- /dev/null
+++ b/src/intel/tools/tests/gen6/not.asm
@@ -0,0 +1,4 @@
+not(8)          g29<1>.xD       g26<4>.xD                       { align16 1Q };
+not.nz.f0.0(8)  null<1>.xD      g13<4>.xD                       { align16 1Q };
+not(8)          g20<1>D         g19<8,8,1>D                     { align1 1Q };
+not(16)         g27<1>D         g25<8,8,1>D                     { align1 1H };

diff --git a/src/intel/tools/tests/gen6/not.expected b/src/intel/tools/tests/gen6/not.expected
new file mode 100644 (file)
index 0000000..1d38da6
--- /dev/null
+++ b/src/intel/tools/tests/gen6/not.expected
@@ -0,0 +1,4 @@
+04 01 60 00 a5 00 a1 23 40 03 60 00 00 00 00 00
+04 01 60 02 a4 00 01 20 a0 01 60 00 00 00 00 00
+04 00 60 00 a5 00 80 22 60 02 8d 00 00 00 00 00
+04 00 80 00 a5 00 60 23 20 03 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen6/or.asm b/src/intel/tools/tests/gen6/or.asm
new file mode 100644 (file)
index 0000000..aa3de46
--- /dev/null
+++ b/src/intel/tools/tests/gen6/or.asm
@@ -0,0 +1,15 @@
+or(8)           g29<1>UD        g9<4>.xUD       0x00000014UD    { align16 1Q };
+or(8)           g43<1>UD        g44<4>UD        1D              { align16 1Q };
+or(1)           g28<1>UD        g28<0,1,0>UD    g57<0,1,0>UD    { align1 1N };
+or(8)           g10<1>UD        g9<8,8,1>UD     g8<8,8,1>UD     { align1 1Q };
+or(16)          g16<1>UD        g14<8,8,1>UD    g12<8,8,1>UD    { align1 1H };
+or(1)           g9<1>UD         g0<0,1,0>UD     0x00000800UD    { align1 WE_all 1N };
+or.nz.f0.0(8)   null<1>.xUD     g17<4>.xUD      g16<4>.xUD      { align16 1Q };
+or.nz.f0.0(8)   null<1>UD       g16<8,8,1>UD    g17<8,8,1>UD    { align1 1Q };
+(+f0.0) or(8)   g18<1>UD        g18<8,8,1>UD    0x3f800000UD    { align1 1Q };
+or.nz.f0.0(16)  null<1>UD       g28<8,8,1>UD    g30<8,8,1>UD    { align1 1H };
+(+f0.0) or(16)  g31<1>UD        g31<8,8,1>UD    0x3f800000UD    { align1 1H };
+(+f0.0) or(8)   g22<1>.xUD      g22<4>.xUD      0x3f800000UD    { align16 1Q };
+or.nz.f0.0(8)   g8<1>UD         g4<8,8,1>UD     g7<8,8,1>UD     { align1 1Q };
+or.nz.f0.0(16)  g12<1>UD        g5<8,8,1>UD     g10<8,8,1>UD    { align1 1H };
+or(8)           g4<1>.xUD       g57<4>.xUD      g56<4>.xUD      { align16 1Q };

diff --git a/src/intel/tools/tests/gen6/or.expected b/src/intel/tools/tests/gen6/or.expected
new file mode 100644 (file)
index 0000000..ccaacac
--- /dev/null
+++ b/src/intel/tools/tests/gen6/or.expected
@@ -0,0 +1,15 @@
+06 01 60 00 21 0c af 23 20 01 60 00 14 00 00 00
+06 01 60 00 21 1c 6f 25 84 05 6e 00 01 00 00 00
+06 00 00 00 21 04 80 23 80 03 00 00 20 07 00 00
+06 00 60 00 21 04 40 21 20 01 8d 00 00 01 8d 00
+06 00 80 00 21 04 00 22 c0 01 8d 00 80 01 8d 00
+06 02 00 00 21 0c 20 21 00 00 00 00 00 08 00 00
+06 01 60 02 20 04 01 20 20 02 60 00 00 02 60 00
+06 00 60 02 20 04 00 20 00 02 8d 00 20 02 8d 00
+06 00 61 00 21 0c 40 22 40 02 8d 00 00 00 80 3f
+06 00 80 02 20 04 00 20 80 03 8d 00 c0 03 8d 00
+06 00 81 00 21 0c e0 23 e0 03 8d 00 00 00 80 3f
+06 01 61 00 21 0c c1 22 c0 02 60 00 00 00 80 3f
+06 00 60 02 21 04 00 21 80 00 8d 00 e0 00 8d 00
+06 00 80 02 21 04 80 21 a0 00 8d 00 40 01 8d 00
+06 01 60 00 21 04 81 20 20 07 60 00 00 07 60 00

diff --git a/src/intel/tools/tests/gen6/pln.asm b/src/intel/tools/tests/gen6/pln.asm
new file mode 100644 (file)
index 0000000..179e2fa
--- /dev/null
+++ b/src/intel/tools/tests/gen6/pln.asm
@@ -0,0 +1,12 @@
+pln(8)          m1<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln(16)         m1<1>F          g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln(8)          g41<1>F         g5<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln(16)         g22<1>F         g7<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.sat(8)      g8<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.sat(16)     g7<1>F          g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.g.f0.0(8)   g7<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.g.f0.0(16)  g11<1>F         g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.l.f0.0(8)   g8<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.l.f0.0(16)  g11<1>F         g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.nz.f0.0(8)  g18<1>F         g5<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.nz.f0.0(16) g14<1>F         g7<0,1,0>F      g2<8,8,1>F      { align1 1H };

diff --git a/src/intel/tools/tests/gen6/pln.expected b/src/intel/tools/tests/gen6/pln.expected
new file mode 100644 (file)
index 0000000..f35a3ed
--- /dev/null
+++ b/src/intel/tools/tests/gen6/pln.expected
@@ -0,0 +1,12 @@
+5a 00 60 00 be 77 20 20 80 00 00 00 40 00 8d 00
+5a 00 80 00 be 77 20 20 c0 00 00 00 40 00 8d 00
+5a 00 60 00 bd 77 20 25 a0 00 00 00 40 00 8d 00
+5a 00 80 00 bd 77 c0 22 e0 00 00 00 40 00 8d 00
+5a 00 60 80 bd 77 00 21 80 00 00 00 40 00 8d 00
+5a 00 80 80 bd 77 e0 20 c0 00 00 00 40 00 8d 00
+5a 00 60 03 bd 77 e0 20 80 00 00 00 40 00 8d 00
+5a 00 80 03 bd 77 60 21 c0 00 00 00 40 00 8d 00
+5a 00 60 05 bd 77 00 21 80 00 00 00 40 00 8d 00
+5a 00 80 05 bd 77 60 21 c0 00 00 00 40 00 8d 00
+5a 00 60 02 bd 77 40 22 a0 00 00 00 40 00 8d 00
+5a 00 80 02 bd 77 c0 21 e0 00 00 00 40 00 8d 00

diff --git a/src/intel/tools/tests/gen6/rndd.asm b/src/intel/tools/tests/gen6/rndd.asm
new file mode 100644 (file)
index 0000000..0a0e25d
--- /dev/null
+++ b/src/intel/tools/tests/gen6/rndd.asm
@@ -0,0 +1,7 @@
+rndd(8)         g18<1>.xF       g1<0>.xF                        { align16 1Q };
+rndd(8)         g3<1>F          g5<8,8,1>F                      { align1 1Q };
+rndd(16)        g8<1>F          g6<8,8,1>F                      { align1 1H };
+rndd(8)         g6<1>.zF        g22<4>.xF                       { align16 NoDDClr 1Q };
+rndd.z.f0.0(8)  null<1>F        g17<8,8,1>F                     { align1 1Q };
+rndd.z.f0.0(16) null<1>F        g28<8,8,1>F                     { align1 1H };
+rndd.sat(8)     m4<1>F          g6<4>F                          { align16 1Q };

diff --git a/src/intel/tools/tests/gen6/rndd.expected b/src/intel/tools/tests/gen6/rndd.expected
new file mode 100644 (file)
index 0000000..778037a
--- /dev/null
+++ b/src/intel/tools/tests/gen6/rndd.expected
@@ -0,0 +1,7 @@
+45 01 60 00 bd 03 41 22 20 00 00 00 00 00 00 00
+45 00 60 00 bd 03 60 20 a0 00 8d 00 00 00 00 00
+45 00 80 00 bd 03 00 21 c0 00 8d 00 00 00 00 00
+45 05 60 00 bd 03 c4 20 c0 02 60 00 00 00 00 00
+45 00 60 01 bc 03 00 20 20 02 8d 00 00 00 00 00
+45 00 80 01 bc 03 00 20 80 03 8d 00 00 00 00 00
+45 01 60 80 be 03 8f 20 c4 00 6e 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen6/rnde.asm b/src/intel/tools/tests/gen6/rnde.asm
new file mode 100644 (file)
index 0000000..10d6924
--- /dev/null
+++ b/src/intel/tools/tests/gen6/rnde.asm
@@ -0,0 +1,2 @@
+rnde(8)         g6<1>F          g3<8,8,1>F                      { align1 1Q };
+rnde(16)        g8<1>F          g4<8,8,1>F                      { align1 1H };

diff --git a/src/intel/tools/tests/gen6/rnde.expected b/src/intel/tools/tests/gen6/rnde.expected
new file mode 100644 (file)
index 0000000..374f68c
--- /dev/null
+++ b/src/intel/tools/tests/gen6/rnde.expected
@@ -0,0 +1,2 @@
+46 00 60 00 bd 03 c0 20 60 00 8d 00 00 00 00 00
+46 00 80 00 bd 03 00 21 80 00 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen6/rndz.asm b/src/intel/tools/tests/gen6/rndz.asm
new file mode 100644 (file)
index 0000000..975bac6
--- /dev/null
+++ b/src/intel/tools/tests/gen6/rndz.asm
@@ -0,0 +1,3 @@
+rndz(8)         g9<1>.xyzF      g1<0>.xyzzF                     { align16 1Q };
+rndz(8)         g6<1>F          g5<8,8,1>F                      { align1 1Q };
+rndz(16)        g8<1>F          g6<8,8,1>F                      { align1 1H };

diff --git a/src/intel/tools/tests/gen6/rndz.expected b/src/intel/tools/tests/gen6/rndz.expected
new file mode 100644 (file)
index 0000000..56068d9
--- /dev/null
+++ b/src/intel/tools/tests/gen6/rndz.expected
@@ -0,0 +1,3 @@
+47 01 60 00 bd 03 27 21 24 00 0a 00 00 00 00 00
+47 00 60 00 bd 03 c0 20 a0 00 8d 00 00 00 00 00
+47 00 80 00 bd 03 00 21 c0 00 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen6/sel.asm b/src/intel/tools/tests/gen6/sel.asm
new file mode 100644 (file)
index 0000000..03a8fe5
--- /dev/null
+++ b/src/intel/tools/tests/gen6/sel.asm
@@ -0,0 +1,58 @@
+(+f0.0) sel(8)  g40<1>UD        g5<4>UD         g6<4>UD         { align16 1Q };
+(-f0.0) sel(8)  g6<1>UD         g13<8,8,1>UD    0x00000000UD    { align1 1Q };
+(-f0.0) sel(16) g7<1>UD         g9<8,8,1>UD     0x00000000UD    { align1 1H };
+(+f0.0) sel(8)  g2<1>UD         g31<8,8,1>UD    g34<8,8,1>UD    { align1 1Q };
+(+f0.0) sel(8)  m1<1>UD         g67<8,8,1>UD    0x3f800000UD    { align1 1Q };
+(+f0.0) sel(16) g2<1>UD         g35<8,8,1>UD    g41<8,8,1>UD    { align1 1H };
+(+f0.0) sel(16) m1<1>UD         g31<8,8,1>UD    0x3f800000UD    { align1 1H };
+(+f0.0.all4h) sel(8) g45<1>UD   g23<4>UD        g24<4>UD        { align16 1Q };
+sel.ge(8)       g64<1>F         g5<8,8,1>F      0x0F  /* 0F */  { align1 1Q };
+sel.ge(16)      g17<1>F         g3<8,8,1>F      0x0F  /* 0F */  { align1 1H };
+sel.ge(8)       g3<1>.yF        g7<4>.xF        0x0F  /* 0F */  { align16 1Q };
+sel.l(8)        g11<1>.xF       g7<4>.wF        0x43000000F  /* 128F */ { align16 1Q };
+(-f0.0.z) sel(8) g3<1>.zUD      g17<4>.xUD      0x00000000UD    { align16 1Q };
+(+f0.0.x) sel(8) g32<1>.xUD     g12<4>.yUD      0x41a80000UD    { align16 1Q };
+(-f0.0.x) sel(8) g33<1>.xUD     g32<4>.xUD      0x41b80000UD    { align16 1Q };
+(+f0.0) sel(8)  m1<1>UD         g9<8,8,1>UD     g12<8,8,1>UD    { align1 1Q };
+(+f0.0) sel(16) m1<1>UD         g15<8,8,1>UD    g21<8,8,1>UD    { align1 1H };
+sel.ge(8)       g20<1>F         g19<8,8,1>F     g16<8,8,1>F     { align1 1Q };
+sel.ge(16)      g12<1>F         g10<8,8,1>F     g8<8,8,1>F      { align1 1H };
+sel.sat.l(8)    m4<1>F          g2<4>F          0x3f000000F  /* 0.5F */ { align16 1Q };
+(+f0.0.x) sel(8) g46<1>.xUD     g72<4>.yUD      g72<4>.xUD      { align16 1Q };
+sel.l(8)        g13<1>.xF       g1<0>.wF        g1<0>.zF        { align16 1Q };
+sel.ge(8)       g13<1>.xF       g1<0>.wF        g1<0>.zF        { align16 1Q };
+(+f0.0.any4h) sel(8) g15<1>UD   g14<4>UD        g4<4>UD         { align16 1Q };
+(-f0.0.any4h) sel(8) g67<1>.xUD g63<4>.xUD      0x00000000UD    { align16 1Q };
+(-f0.0) sel(8)  m1<1>UD         g13<8,8,1>UD    0x3f800000UD    { align1 1Q };
+(-f0.0) sel(16) m1<1>UD         g22<8,8,1>UD    0x3f800000UD    { align1 1H };
+sel.l(8)        g10<1>F         g2.3<0,1,0>F    g2.2<0,1,0>F    { align1 1Q };
+sel.l(16)       g15<1>F         g2.3<0,1,0>F    g2.2<0,1,0>F    { align1 1H };
+sel.ge(8)       g18<1>.zD       g18<4>.zD       1D              { align16 1Q };
+(+f0.0) sel(8)  g8<1>UD         g4<8,8,1>UD     0x00000000UD    { align1 1Q };
+(+f0.0) sel(16) g11<1>UD        g5<8,8,1>UD     0x00000000UD    { align1 1H };
+sel.ge(8)       g4<1>D          g3<0,1,0>D      -252D           { align1 1Q };
+sel.l(8)        g5<1>D          g4<8,8,1>D      254D            { align1 1Q };
+sel.ge(16)      g4<1>D          g3<0,1,0>D      -252D           { align1 1H };
+sel.l(16)       g6<1>D          g4<8,8,1>D      254D            { align1 1H };
+sel.sat.l(8)    m4<1>F          g1<0>F          g3<4>F          { align16 1Q };
+sel.l(8)        g6<1>F          g3<8,8,1>F      0x40400000F  /* 3F */ { align1 1Q };
+sel.l(16)       g20<1>F         g14<8,8,1>F     0x40400000F  /* 3F */ { align1 1H };
+(+f0.0) sel(8)  g8<1>F          (abs)g40<8,8,1>F g6<8,8,1>F     { align1 1Q };
+(-f0.0) sel(8)  g15<1>F         (abs)g14<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
+(+f0.0) sel(16) g13<1>F         (abs)g52<8,8,1>F g9<8,8,1>F     { align1 1H };
+(-f0.0) sel(16) g27<1>F         (abs)g25<8,8,1>F 0x3f800000F  /* 1F */ { align1 1H };
+(+f0.0) sel(8)  g21<1>.xyzUD    g19<4>.xyzzUD   0x00000000UD    { align16 1Q };
+sel.l(8)        m2<1>F          g3<8,8,1>F      g4<8,8,1>F      { align1 1Q };
+sel.l(16)       m3<1>F          g3<8,8,1>F      g5<8,8,1>F      { align1 1H };
+(-f0.0.y) sel(8) g3<1>.yUD      g10<4>.xUD      0x00000000UD    { align16 1Q };
+(+f0.0.y) sel(8) g3<1>.yUD      g1<0>.wUD       g1<0>.zUD       { align16 1Q };
+(-f0.0) sel(8)  g28<1>UD        g26<4>UD        0x00000000UD    { align16 1Q };
+sel.ge(8)       g22<1>.xD       g3.4<0>.xD      g5.4<0>.xD      { align16 1Q };
+sel.l(8)        m1<1>F          g36<8,8,1>F     0x3f800000F  /* 1F */ { align1 1Q };
+sel.l(16)       m1<1>F          g14<8,8,1>F     0x3f800000F  /* 1F */ { align1 1H };
+sel.sat.ge(8)   m4<1>F          g25<4>F         0xbf800000F  /* -1F */ { align16 1Q };
+sel.ge(8)       m2<1>F          g5<8,8,1>F      0x0F  /* 0F */  { align1 1Q };
+sel.ge(16)      m3<1>F          g7<8,8,1>F      0x0F  /* 0F */  { align1 1H };
+sel.l(8)        g13<1>D         g11<4>D         254D            { align16 1Q };
+sel.sat.l(8)    g47<1>F         g46<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
+sel.sat.l(16)   g54<1>F         g3<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 1H };

diff --git a/src/intel/tools/tests/gen6/sel.expected b/src/intel/tools/tests/gen6/sel.expected
new file mode 100644 (file)
index 0000000..246bc92
--- /dev/null
+++ b/src/intel/tools/tests/gen6/sel.expected
@@ -0,0 +1,58 @@
+02 01 61 00 21 04 0f 25 a4 00 6e 00 c4 00 6e 00
+02 00 71 00 21 0c c0 20 a0 01 8d 00 00 00 00 00
+02 00 91 00 21 0c e0 20 20 01 8d 00 00 00 00 00
+02 00 61 00 21 04 40 20 e0 03 8d 00 40 04 8d 00
+02 00 61 00 22 0c 20 20 60 08 8d 00 00 00 80 3f
+02 00 81 00 21 04 40 20 60 04 8d 00 20 05 8d 00
+02 00 81 00 22 0c 20 20 e0 03 8d 00 00 00 80 3f
+02 01 67 00 21 04 af 25 e4 02 6e 00 04 03 6e 00
+02 00 60 04 bd 7f 00 28 a0 00 8d 00 00 00 00 00
+02 00 80 04 bd 7f 20 22 60 00 8d 00 00 00 00 00
+02 01 60 04 bd 7f 62 20 e0 00 60 00 00 00 00 00
+02 01 60 05 bd 7f 61 21 ef 00 6f 00 00 00 00 43
+02 01 74 00 21 0c 64 20 20 02 60 00 00 00 00 00
+02 01 62 00 21 0c 01 24 85 01 65 00 00 00 a8 41
+02 01 72 00 21 0c 21 24 00 04 60 00 00 00 b8 41
+02 00 61 00 22 04 20 20 20 01 8d 00 80 01 8d 00
+02 00 81 00 22 04 20 20 e0 01 8d 00 a0 02 8d 00
+02 00 60 04 bd 77 80 22 60 02 8d 00 00 02 8d 00
+02 00 80 04 bd 77 80 21 40 01 8d 00 00 01 8d 00
+02 01 60 85 be 7f 8f 20 44 00 6e 00 00 00 00 3f
+02 01 62 00 21 04 c1 25 05 09 65 00 00 09 60 00
+02 01 60 05 bd 77 a1 21 2f 00 0f 00 2a 00 0a 00
+02 01 60 04 bd 77 a1 21 2f 00 0f 00 2a 00 0a 00
+02 01 66 00 21 04 ef 21 c4 01 6e 00 84 00 6e 00
+02 01 76 00 21 0c 61 28 e0 07 60 00 00 00 00 00
+02 00 71 00 22 0c 20 20 a0 01 8d 00 00 00 80 3f
+02 00 91 00 22 0c 20 20 c0 02 8d 00 00 00 80 3f
+02 00 60 05 bd 77 40 21 4c 00 00 00 48 00 00 00
+02 00 80 05 bd 77 e0 21 4c 00 00 00 48 00 00 00
+02 01 60 04 a5 1c 44 22 4a 02 6a 00 01 00 00 00
+02 00 61 00 21 0c 00 21 80 00 8d 00 00 00 00 00
+02 00 81 00 21 0c 60 21 a0 00 8d 00 00 00 00 00
+02 00 60 04 a5 1c 80 20 60 00 00 00 04 ff ff ff
+02 00 60 05 a5 1c a0 20 80 00 8d 00 fe 00 00 00
+02 00 80 04 a5 1c 80 20 60 00 00 00 04 ff ff ff
+02 00 80 05 a5 1c c0 20 80 00 8d 00 fe 00 00 00
+02 01 60 85 be 77 8f 20 24 00 0e 00 64 00 6e 00
+02 00 60 05 bd 7f c0 20 60 00 8d 00 00 00 40 40
+02 00 80 05 bd 7f 80 22 c0 01 8d 00 00 00 40 40
+02 00 61 00 bd 77 00 21 00 25 8d 00 c0 00 8d 00
+02 00 71 00 bd 7f e0 21 c0 21 8d 00 00 00 80 3f
+02 00 81 00 bd 77 a0 21 80 26 8d 00 20 01 8d 00
+02 00 91 00 bd 7f 60 23 20 23 8d 00 00 00 80 3f
+02 01 61 00 21 0c a7 22 64 02 6a 00 00 00 00 00
+02 00 60 05 be 77 40 20 60 00 8d 00 80 00 8d 00
+02 00 80 05 be 77 60 20 60 00 8d 00 a0 00 8d 00
+02 01 73 00 21 0c 62 20 40 01 60 00 00 00 00 00
+02 01 63 00 21 04 62 20 2f 00 0f 00 2a 00 0a 00
+02 01 71 00 21 0c 8f 23 44 03 6e 00 00 00 00 00
+02 01 60 04 a5 14 c1 22 70 00 00 00 b0 00 00 00
+02 00 60 05 be 7f 20 20 80 04 8d 00 00 00 80 3f
+02 00 80 05 be 7f 20 20 c0 01 8d 00 00 00 80 3f
+02 01 60 84 be 7f 8f 20 24 03 6e 00 00 00 80 bf
+02 00 60 04 be 7f 40 20 a0 00 8d 00 00 00 00 00
+02 00 80 04 be 7f 60 20 e0 00 8d 00 00 00 00 00
+02 01 60 05 a5 1c af 21 64 01 6e 00 fe 00 00 00
+02 00 60 85 bd 7f e0 25 c0 05 8d 00 00 00 00 3f
+02 00 80 85 bd 7f c0 26 60 00 8d 00 00 00 00 3f

diff --git a/src/intel/tools/tests/gen6/send.asm b/src/intel/tools/tests/gen6/send.asm
new file mode 100644 (file)
index 0000000..fa9fe22
--- /dev/null
+++ b/src/intel/tools/tests/gen6/send.asm
@@ -0,0 +1,516 @@
+send(8)         null<1>F        m1<4>F          0x8608c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 3 rlen 0 { align16 1Q EOT };
+send(8)         null<1>F        m1<4>F          0x8a08c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 5 rlen 0 { align16 1Q EOT };
+send(8)         g2<1>UW         m2<8,8,1>F      0x08417001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x10827001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g0<1>F          m21<4>F         0x060920ff
+                            render MsgDesc: OWORD dual block write MsgCtrl = 0x0 Surface = 255 mlen 3 rlen 0 { align16 1Q };
+send(8)         g41<1>F         m22<4>F         0x041840ff
+                            render MsgDesc: OWORD dual block read MsgCtrl = 0x0 Surface = 255 mlen 2 rlen 1 { align16 1Q };
+send(8)         null<1>F        m1<4>F          0x8e08c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 7 rlen 0 { align16 1Q EOT };
+send(8)         g2<1>UW         m1<8,8,1>F      0x16494001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 11 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m1<8,8,1>F      0x0e494001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g3<1>UW         m1<8,8,1>F      0x0e496001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g7<1>UW         m1<8,8,1>F      0x0e496102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 7 rlen 4 { align1 1Q };
+send(8)         g14<1>D         m2<4>F          0x04107040
+                            sampler MsgDesc: ld SIMD4x2 Surface = 64 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         g7<1>.xUD       m1<4>UD         0x02182001
+                            urb MsgDesc: 0 ff_sync allocate mlen 1 rlen 1   { align16 1Q };
+send(8)         g7<1>UD         m1<4>F          0x0a18e400
+                            urb MsgDesc: 0 urb_write interleave allocate used complete mlen 5 rlen 1 { align16 1Q };
+send(8)         null<1>F        m1<4>F          0x82088400
+                            urb MsgDesc: 0 urb_write interleave complete mlen 1 rlen 0 { align16 1Q EOT };
+send(8)         g8<1>UD         m1<4>F          0x0618e400
+                            urb MsgDesc: 0 urb_write interleave allocate used complete mlen 3 rlen 1 { align16 1Q };
+send(8)         null<1>F        m1<4>F          0x1e084400
+                            urb MsgDesc: 0 urb_write interleave used mlen 15 rlen 0 { align16 1Q };
+send(8)         null<1>F        m1<4>F          0x8608c470
+                            urb MsgDesc: 7 urb_write interleave used complete mlen 3 rlen 0 { align16 1Q EOT };
+send(8)         g7<1>UW         m2<8,8,1>F      0x04410001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g9<1>UW         m2<8,8,1>F      0x08820001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g7<1>UW         m2<8,8,1>F      0x02410001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g9<1>UW         m2<8,8,1>F      0x04820001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g24<1>UD        m17<4>F         0x04184000
+                            dp_sampler MsgDesc: (0, 0, 2, 0) mlen 2 rlen 1  { align16 1Q };
+send(8)         g8<1>UW         m2<8,8,1>F      0x0241a001
+                            sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x06418002
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g11<1>UW        m2<8,8,1>F      0x0482a001
+                            sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0c828002
+                            sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g15<1>D         m2<4>F          0x02107040
+                            sampler MsgDesc: ld SIMD4x2 Surface = 64 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x10414001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1Q };
+send(8)         g2<1>D          m2<4>F          0x0210a000
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g3<1>D          m2<4>F          0x0210a101
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 1 Sampler = 1 mlen 1 rlen 1 { align16 1Q };
+send(8)         g5<1>D          m2<4>F          0x0210a202
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 2 Sampler = 2 mlen 1 rlen 1 { align16 1Q };
+send(8)         g7<1>D          m2<4>F          0x0210a303
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 3 Sampler = 3 mlen 1 rlen 1 { align16 1Q };
+send(8)         g9<1>D          m2<4>F          0x0210a404
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 4 Sampler = 4 mlen 1 rlen 1 { align16 1Q };
+send(8)         g11<1>D         m2<4>F          0x0210a505
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 5 Sampler = 5 mlen 1 rlen 1 { align16 1Q };
+send(8)         g13<1>D         m2<4>F          0x0210a606
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 6 Sampler = 6 mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>F        m1<4>F          0x9208c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 9 rlen 0 { align16 1Q EOT };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04419001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08829001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g13<1>UW        m17<8,8,1>UD    0x02280301
+                            const MsgDesc: (1, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g11<1>D         m2<4>F          0x04188001
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a000
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 0 mlen 1 rlen 0 { align16 1Q };
+send(8)         g63<1>UD        m2<4>UD         0x021ba000
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x0a412001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x14822001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x02419001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x04829001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x0c416001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         null<1>F        m1<4>F          0x1e084470
+                            urb MsgDesc: 7 urb_write interleave used mlen 15 rlen 0 { align16 1Q };
+send(8)         null<1>F        m1<4>F          0x8e08c4e0
+                            urb MsgDesc: 14 urb_write interleave used complete mlen 7 rlen 0 { align16 1Q EOT };
+send(8)         g2<1>UW         m2<8,8,1>F      0x0a413001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x14823001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x06410001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0c820001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04418002
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08828002
+                            sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g8<1>F          m2<4>F          0x02107000
+                            sampler MsgDesc: ld SIMD4x2 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>F        m1<4>F          0x9e08c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 15 rlen 0 { align16 1Q EOT };
+send(8)         g2<1>UW         m16<8,8,1>F     0x04497001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m16<8,8,1>F     0x068a7001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m1<8,8,1>F      0x08498002
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m1<8,8,1>F      0x0e8a8002
+                            sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m1<8,8,1>F      0x0c491001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m1<8,8,1>F      0x168a1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(8)         g18<1>D         m2<4>F          0x0210a040
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 64 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g9<1>UW         m2<8,8,1>F      0x0241a102
+                            sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(8)         g9<1>UW         m2<8,8,1>F      0x0c416102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         m2<8,8,1>F      0x0482a102
+                            sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H };
+send(8)         g9<1>UD         m1<4>F          0x1618e400
+                            urb MsgDesc: 0 urb_write interleave allocate used complete mlen 11 rlen 1 { align16 1Q };
+send(8)         g19<1>F         m17<4>F         0x04184040
+                            dp_sampler MsgDesc: (64, 0, 2, 0) mlen 2 rlen 1 { align16 1Q };
+send(8)         g3<1>UW         m1<8,8,1>F      0x0c493001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g7<1>UW         m1<8,8,1>F      0x0c493102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 1Q };
+send(16)        g4<1>UW         m1<8,8,1>F      0x168a3001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(16)        g12<1>UW        m1<8,8,1>F      0x168a3102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 11 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x08418002
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x10828002
+                            sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x0a411001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x14821001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x0c415001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         m2<8,8,1>F      0x0c415102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 1Q };
+send(8)         g19<1>F         m17<4>F         0x04184001
+                            dp_sampler MsgDesc: (1, 0, 2, 0) mlen 2 rlen 1  { align16 1Q };
+send(8)         g2<1>UW         m1<8,8,1>F      0x06498002
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m1<8,8,1>F      0x0a8a8002
+                            sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         null<1>F        m1<4>F          0x9608c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 11 rlen 0 { align16 1Q EOT };
+send(8)         g7<1>UD         m2<4>F          0x04107000
+                            sampler MsgDesc: ld SIMD4x2 Surface = 0 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         g12<1>UD        m1<4>F          0x1a18e400
+                            urb MsgDesc: 0 urb_write interleave allocate used complete mlen 13 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x0a417001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x14827001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410304
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820304
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 8 { align1 1H };
+send(8)         g11<1>UD        m1<4>F          0x0e18e400
+                            urb MsgDesc: 0 urb_write interleave allocate used complete mlen 7 rlen 1 { align16 1Q };
+send(8)         g26<1>UD        m2<4>UD         0x021ba001
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x0c414001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x06419001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0c829001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        m2<4>UD         0x0209a001
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 1 mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a002
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 2 mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a003
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 3 mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a004
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 4 mlen 1 rlen 0 { align16 1Q };
+send(8)         g43<1>UD        m2<4>UD         0x021ba005
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 5 mlen 1 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         m1<8,8,1>F      0x12494001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 4 { align1 1Q };
+send(16)        g3<1>UW         m17<8,8,1>UD    0x02280302
+                            const MsgDesc: (2, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g7<1>UW         m2<8,8,1>F      0x0a413102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g12<1>UW        m2<8,8,1>F      0x14823102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m1<8,8,1>F      0x06490001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m1<8,8,1>F      0x0a8a0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410203
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 4 { align1 1Q };
+send(8)         g9<1>UW         m2<8,8,1>F      0x04410102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820203
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 8 { align1 1H };
+send(16)        g13<1>UW        m2<8,8,1>F      0x08820102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(8)         g3<1>UW         m2<8,8,1>F      0x0241a203
+                            sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 1Q };
+send(8)         g3<1>UW         m2<8,8,1>F      0x0241a304
+                            sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 4 { align1 1Q };
+send(8)         g3<1>UW         m2<8,8,1>F      0x0241a405
+                            sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 4 { align1 1Q };
+send(8)         g3<1>UW         m2<8,8,1>F      0x0241a506
+                            sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 4 { align1 1Q };
+send(8)         g3<1>UW         m2<8,8,1>F      0x0241a607
+                            sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 6 mlen 1 rlen 4 { align1 1Q };
+send(8)         g3<1>UW         m2<8,8,1>F      0x0241a708
+                            sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 7 mlen 1 rlen 4 { align1 1Q };
+send(8)         g3<1>UW         m2<8,8,1>F      0x0241a809
+                            sampler MsgDesc: resinfo SIMD8 Surface = 9 Sampler = 8 mlen 1 rlen 4 { align1 1Q };
+send(8)         g3<1>UW         m2<8,8,1>F      0x0241a90a
+                            sampler MsgDesc: resinfo SIMD8 Surface = 10 Sampler = 9 mlen 1 rlen 4 { align1 1Q };
+send(8)         g3<1>UW         m2<8,8,1>F      0x0241aa0b
+                            sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 10 mlen 1 rlen 4 { align1 1Q };
+send(8)         g3<1>UW         m2<8,8,1>F      0x0241ab0c
+                            sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 11 mlen 1 rlen 4 { align1 1Q };
+send(8)         g3<1>UW         m2<8,8,1>F      0x0241ac0d
+                            sampler MsgDesc: resinfo SIMD8 Surface = 13 Sampler = 12 mlen 1 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0482a203
+                            sampler MsgDesc: resinfo SIMD16 Surface = 3 Sampler = 2 mlen 2 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0482a304
+                            sampler MsgDesc: resinfo SIMD16 Surface = 4 Sampler = 3 mlen 2 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0482a405
+                            sampler MsgDesc: resinfo SIMD16 Surface = 5 Sampler = 4 mlen 2 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0482a506
+                            sampler MsgDesc: resinfo SIMD16 Surface = 6 Sampler = 5 mlen 2 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0482a607
+                            sampler MsgDesc: resinfo SIMD16 Surface = 7 Sampler = 6 mlen 2 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0482a708
+                            sampler MsgDesc: resinfo SIMD16 Surface = 8 Sampler = 7 mlen 2 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0482a809
+                            sampler MsgDesc: resinfo SIMD16 Surface = 9 Sampler = 8 mlen 2 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0482a90a
+                            sampler MsgDesc: resinfo SIMD16 Surface = 10 Sampler = 9 mlen 2 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0482aa0b
+                            sampler MsgDesc: resinfo SIMD16 Surface = 11 Sampler = 10 mlen 2 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0482ab0c
+                            sampler MsgDesc: resinfo SIMD16 Surface = 12 Sampler = 11 mlen 2 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0482ac0d
+                            sampler MsgDesc: resinfo SIMD16 Surface = 13 Sampler = 12 mlen 2 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x14414001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 1Q };
+send(8)         g17<1>F         m2<4>F          0x04102000
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 0 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410405
+                            sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410506
+                            sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410607
+                            sampler MsgDesc: sample SIMD8 Surface = 7 Sampler = 6 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410708
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410809
+                            sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 8 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x0441090a
+                            sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 9 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410a0b
+                            sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 10 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410b0c
+                            sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 11 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410c0d
+                            sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 12 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410d0e
+                            sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 13 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410e0f
+                            sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 14 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410f10
+                            sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820405
+                            sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820506
+                            sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820607
+                            sampler MsgDesc: sample SIMD16 Surface = 7 Sampler = 6 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820708
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820809
+                            sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 8 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x0882090a
+                            sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 9 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820a0b
+                            sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 10 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820b0c
+                            sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 11 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820c0d
+                            sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 12 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820d0e
+                            sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 13 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820e0f
+                            sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 14 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820f10
+                            sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 4 rlen 8 { align1 1H };
+send(8)         g6<1>UW         m2<8,8,1>F      0x02410102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        m2<8,8,1>F      0x04820102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m1<8,8,1>F      0x0c492001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m1<8,8,1>F      0x168a2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(8)         g3<1>UW         m1<8,8,1>F      0x0e495001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g7<1>UW         m1<8,8,1>F      0x0e495102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 7 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         m1<8,8,1>F      0x04490001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m1<8,8,1>F      0x068a0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410003
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x08820003
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x08417008
+                            sampler MsgDesc: ld SIMD8 Surface = 8 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         m2<8,8,1>F      0x08417109
+                            sampler MsgDesc: ld SIMD8 Surface = 9 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(8)         g7<1>UW         m2<8,8,1>F      0x0841720a
+                            sampler MsgDesc: ld SIMD8 Surface = 10 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
+send(8)         g8<1>UW         m2<8,8,1>F      0x0841730b
+                            sampler MsgDesc: ld SIMD8 Surface = 11 Sampler = 3 mlen 4 rlen 4 { align1 1Q };
+send(8)         g9<1>UW         m2<8,8,1>F      0x0841740c
+                            sampler MsgDesc: ld SIMD8 Surface = 12 Sampler = 4 mlen 4 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        m2<8,8,1>F      0x0841750d
+                            sampler MsgDesc: ld SIMD8 Surface = 13 Sampler = 5 mlen 4 rlen 4 { align1 1Q };
+send(8)         g11<1>UW        m2<8,8,1>F      0x0841760e
+                            sampler MsgDesc: ld SIMD8 Surface = 14 Sampler = 6 mlen 4 rlen 4 { align1 1Q };
+send(8)         g12<1>UW        m2<8,8,1>F      0x0841770f
+                            sampler MsgDesc: ld SIMD8 Surface = 15 Sampler = 7 mlen 4 rlen 4 { align1 1Q };
+send(16)        g4<1>UW         m2<8,8,1>F      0x10827008
+                            sampler MsgDesc: ld SIMD16 Surface = 8 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(16)        g12<1>UW        m2<8,8,1>F      0x10827109
+                            sampler MsgDesc: ld SIMD16 Surface = 9 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+send(16)        g12<1>UW        m2<8,8,1>F      0x1082720a
+                            sampler MsgDesc: ld SIMD16 Surface = 10 Sampler = 2 mlen 8 rlen 8 { align1 1H };
+send(16)        g13<1>UW        m2<8,8,1>F      0x1082730b
+                            sampler MsgDesc: ld SIMD16 Surface = 11 Sampler = 3 mlen 8 rlen 8 { align1 1H };
+send(16)        g14<1>UW        m2<8,8,1>F      0x1082740c
+                            sampler MsgDesc: ld SIMD16 Surface = 12 Sampler = 4 mlen 8 rlen 8 { align1 1H };
+send(16)        g15<1>UW        m2<8,8,1>F      0x1082750d
+                            sampler MsgDesc: ld SIMD16 Surface = 13 Sampler = 5 mlen 8 rlen 8 { align1 1H };
+send(16)        g16<1>UW        m2<8,8,1>F      0x1082760e
+                            sampler MsgDesc: ld SIMD16 Surface = 14 Sampler = 6 mlen 8 rlen 8 { align1 1H };
+send(16)        g17<1>UW        m2<8,8,1>F      0x1082770f
+                            sampler MsgDesc: ld SIMD16 Surface = 15 Sampler = 7 mlen 8 rlen 8 { align1 1H };
+send(8)         g30<1>UD        m2<4>UD         0x021ba002
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 2 mlen 1 rlen 1 { align16 1Q };
+send(8)         g5<1>F          m2<4>F          0x04102505
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 5 Sampler = 5 mlen 2 rlen 1 { align16 1Q };
+send(8)         g11<1>UW        m16<8,8,1>F     0x04497002
+                            sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g19<1>UW        m16<8,8,1>F     0x068a7002
+                            sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 0 mlen 3 rlen 8 { align1 1H };
+send(8)         g6<1>UW         m2<8,8,1>F      0x06410102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        m2<8,8,1>F      0x0c820102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        m1<4>F          0x8a08c470
+                            urb MsgDesc: 7 urb_write interleave used complete mlen 5 rlen 0 { align16 1Q EOT };
+send(8)         g6<1>UD         m1<4>F          0x1218e400
+                            urb MsgDesc: 0 urb_write interleave allocate used complete mlen 9 rlen 1 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a005
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 5 mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a006
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 6 mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a007
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 7 mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a008
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 8 mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a009
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 9 mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a00a
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 10 mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a00b
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 11 mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a00c
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 12 mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a00d
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 13 mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        m2<4>UD         0x0209a00e
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 14 mlen 1 rlen 0 { align16 1Q };
+send(8)         g18<1>UD        m2<4>UD         0x021ba00f
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 15 mlen 1 rlen 1 { align16 1Q };
+send(8)         g9<1>UD         m1<4>F          0x1a18e470
+                            urb MsgDesc: 7 urb_write interleave allocate used complete mlen 13 rlen 1 { align16 1Q };
+send(8)         null<1>F        m1<4>F          0x9a08c400
+                            urb MsgDesc: 0 urb_write interleave used complete mlen 13 rlen 0 { align16 1Q EOT };
+send(16)        g2<1>UW         m17<8,8,1>UD    0x02280304
+                            const MsgDesc: (4, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g2<1>UW         m17<8,8,1>UD    0x02280303
+                            const MsgDesc: (3, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g2<1>UW         m17<8,8,1>UD    0x02280306
+                            const MsgDesc: (6, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g2<1>UW         m17<8,8,1>UD    0x02280305
+                            const MsgDesc: (5, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g34<1>UD        m2<4>UD         0x021ba003
+                            render MsgDesc: streamed VB write MsgCtrl = 0x0 Surface = 3 mlen 1 rlen 1 { align16 1Q };
+send(8)         g15<1>D         m2<4>F          0x0210a707
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 7 Sampler = 7 mlen 1 rlen 1 { align16 1Q };
+send(8)         g17<1>D         m2<4>F          0x0210a808
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 8 Sampler = 8 mlen 1 rlen 1 { align16 1Q };
+send(8)         g19<1>D         m2<4>F          0x0210a909
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 9 Sampler = 9 mlen 1 rlen 1 { align16 1Q };
+send(8)         g21<1>D         m2<4>F          0x0210aa0a
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 10 Sampler = 10 mlen 1 rlen 1 { align16 1Q };
+send(8)         g23<1>D         m2<4>F          0x0210ab0b
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 11 Sampler = 11 mlen 1 rlen 1 { align16 1Q };
+send(8)         g25<1>D         m2<4>F          0x0210ac0c
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 12 Sampler = 12 mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>UW       m22<8,8,1>UD    0x040902ff
+                            render MsgDesc: OWORD block write MsgCtrl = 0x2 Surface = 255 mlen 2 rlen 0 { align1 1Q };
+send(8)         g69<1>UW        m22<8,8,1>UD    0x021802ff
+                            render MsgDesc: OWORD block read MsgCtrl = 0x2 Surface = 255 mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g9<1>UD         m1<4>F          0x0e18e4e0
+                            urb MsgDesc: 14 urb_write interleave allocate used complete mlen 7 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         m1<8,8,1>F      0x08490001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m1<8,8,1>F      0x0e8a0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g2<1>UW         m2<8,8,1>F      0x08410001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         m2<8,8,1>F      0x10820001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         null<1>F        m1<4>F          0x9a08c470
+                            urb MsgDesc: 7 urb_write interleave used complete mlen 13 rlen 0 { align16 1Q EOT };
+send(8)         g15<1>F         m17<4>F         0x04184043
+                            dp_sampler MsgDesc: (67, 0, 2, 0) mlen 2 rlen 1 { align16 1Q };
+send(8)         g21<1>F         m17<4>F         0x04184042
+                            dp_sampler MsgDesc: (66, 0, 2, 0) mlen 2 rlen 1 { align16 1Q };
+send(8)         g23<1>F         m17<4>F         0x04184041
+                            dp_sampler MsgDesc: (65, 0, 2, 0) mlen 2 rlen 1 { align16 1Q };
+send(8)         g4<1>F          m17<4>F         0x04184003
+                            dp_sampler MsgDesc: (3, 0, 2, 0) mlen 2 rlen 1  { align16 1Q };
+send(8)         g13<1>F         m17<4>F         0x04184002
+                            dp_sampler MsgDesc: (2, 0, 2, 0) mlen 2 rlen 1  { align16 1Q };
+send(8)         g14<1>UW        m2<8,8,1>F      0x0a417102
+                            sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g24<1>UW        m2<8,8,1>F      0x14827102
+                            sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H };
+send(16)        g2<1>UW         m17<8,8,1>UD    0x02280307
+                            const MsgDesc: (7, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g6<1>UW         m2<8,8,1>F      0x0a413203
+                            sampler MsgDesc: sample_c SIMD8 Surface = 3 Sampler = 2 mlen 5 rlen 4 { align1 1Q };
+send(16)        g13<1>UW        m2<8,8,1>F      0x14823203
+                            sampler MsgDesc: sample_c SIMD16 Surface = 3 Sampler = 2 mlen 10 rlen 8 { align1 1H };
+send(8)         g5<1>F          m2<4>F          0x04102303
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 3 Sampler = 3 mlen 2 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         m2<8,8,1>F      0x04410002
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g20<1>UW        m2<8,8,1>F      0x04410008
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g24<1>UW        m2<8,8,1>F      0x04410109
+                            sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(8)         g28<1>UW        m2<8,8,1>F      0x0441020a
+                            sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 2 mlen 2 rlen 4 { align1 1Q };
+send(8)         g32<1>UW        m2<8,8,1>F      0x0441030b
+                            sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 3 mlen 2 rlen 4 { align1 1Q };
+send(8)         g36<1>UW        m2<8,8,1>F      0x0441040c
+                            sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
+send(8)         g40<1>UW        m2<8,8,1>F      0x0441050d
+                            sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 5 mlen 2 rlen 4 { align1 1Q };
+send(8)         g44<1>UW        m2<8,8,1>F      0x0441060e
+                            sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 6 mlen 2 rlen 4 { align1 1Q };
+send(8)         g48<1>UW        m2<8,8,1>F      0x0441070f
+                            sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 7 mlen 2 rlen 4 { align1 1Q };
+send(16)        g22<1>UW        m2<8,8,1>F      0x08820008
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g30<1>UW        m2<8,8,1>F      0x08820109
+                            sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(16)        g22<1>UW        m2<8,8,1>F      0x0882020a
+                            sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 2 mlen 4 rlen 8 { align1 1H };
+send(16)        g38<1>UW        m2<8,8,1>F      0x0882030b
+                            sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 3 mlen 4 rlen 8 { align1 1H };
+send(16)        g30<1>UW        m2<8,8,1>F      0x0882040c
+                            sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 4 mlen 4 rlen 8 { align1 1H };
+send(16)        g46<1>UW        m2<8,8,1>F      0x0882050d
+                            sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 5 mlen 4 rlen 8 { align1 1H };
+send(16)        g22<1>UW        m2<8,8,1>F      0x0882060e
+                            sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 6 mlen 4 rlen 8 { align1 1H };
+send(16)        g54<1>UW        m2<8,8,1>F      0x0882070f
+                            sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 7 mlen 4 rlen 8 { align1 1H };
+send(8)         g5<1>F          m2<4>F          0x04102101
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 1 Sampler = 1 mlen 2 rlen 1 { align16 1Q };
+send(8)         g6<1>F          m2<4>F          0x04102202
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 2 Sampler = 2 mlen 2 rlen 1 { align16 1Q };
+send(8)         g8<1>F          m2<4>F          0x04102404
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 4 Sampler = 4 mlen 2 rlen 1 { align16 1Q };
+send(8)         g10<1>F         m2<4>F          0x04102606
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 6 Sampler = 6 mlen 2 rlen 1 { align16 1Q };
+send(8)         g11<1>F         m2<4>F          0x04102707
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 7 Sampler = 7 mlen 2 rlen 1 { align16 1Q };
+send(8)         g9<1>UD         m1<4>F          0x0a18e470
+                            urb MsgDesc: 7 urb_write interleave allocate used complete mlen 5 rlen 1 { align16 1Q };

diff --git a/src/intel/tools/tests/gen6/send.expected b/src/intel/tools/tests/gen6/send.expected
new file mode 100644 (file)
index 0000000..b89db52
--- /dev/null
+++ b/src/intel/tools/tests/gen6/send.expected
@@ -0,0 +1,258 @@
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+31 00 80 02 c9 0f e0 21 40 00 8d 00 0d 75 82 10
+31 00 80 02 c9 0f 00 22 40 00 8d 00 0e 76 82 10
+31 00 80 02 c9 0f 20 22 40 00 8d 00 0f 77 82 10
+31 01 60 05 41 0c cf 23 44 00 6e 00 02 a0 1b 02
+31 01 60 02 dd 0f af 20 44 00 6e 00 05 25 10 04
+31 00 60 02 c9 0f 60 21 00 02 8d 00 02 70 49 04
+31 00 80 02 c9 0f 60 22 00 02 8d 00 02 70 8a 06
+31 00 60 02 c9 0f c0 20 40 00 8d 00 02 01 41 06
+31 00 80 02 c9 0f 40 21 40 00 8d 00 02 01 82 0c
+31 01 60 06 dc 0f 0f 20 24 00 6e 00 70 c4 08 8a
+31 01 60 06 c1 0f cf 20 24 00 6e 00 00 e4 18 12
+31 01 60 05 5c 0c 0f 20 44 00 6e 00 05 a0 09 02
+31 01 60 05 5c 0c 0f 20 44 00 6e 00 06 a0 09 02
+31 01 60 05 5c 0c 0f 20 44 00 6e 00 07 a0 09 02
+31 01 60 05 5c 0c 0f 20 44 00 6e 00 08 a0 09 02
+31 01 60 05 5c 0c 0f 20 44 00 6e 00 09 a0 09 02
+31 01 60 05 5c 0c 0f 20 44 00 6e 00 0a a0 09 02
+31 01 60 05 5c 0c 0f 20 44 00 6e 00 0b a0 09 02
+31 01 60 05 5c 0c 0f 20 44 00 6e 00 0c a0 09 02
+31 01 60 05 5c 0c 0f 20 44 00 6e 00 0d a0 09 02
+31 01 60 05 5c 0c 0f 20 44 00 6e 00 0e a0 09 02
+31 01 60 05 41 0c 4f 22 44 00 6e 00 0f a0 1b 02
+31 01 60 06 c1 0f 2f 21 24 00 6e 00 70 e4 18 1a
+31 01 60 06 dc 0f 0f 20 24 00 6e 00 00 c4 08 9a
+31 02 80 09 49 0c 40 20 20 02 8d 00 04 03 28 02
+31 02 80 09 49 0c 40 20 20 02 8d 00 03 03 28 02
+31 02 80 09 49 0c 40 20 20 02 8d 00 06 03 28 02
+31 02 80 09 49 0c 40 20 20 02 8d 00 05 03 28 02
+31 01 60 05 41 0c 4f 24 44 00 6e 00 03 a0 1b 02
+31 01 60 02 c5 0f ef 21 44 00 6e 00 07 a7 10 02
+31 01 60 02 c5 0f 2f 22 44 00 6e 00 08 a8 10 02
+31 01 60 02 c5 0f 6f 22 44 00 6e 00 09 a9 10 02
+31 01 60 02 c5 0f af 22 44 00 6e 00 0a aa 10 02
+31 01 60 02 c5 0f ef 22 44 00 6e 00 0b ab 10 02
+31 01 60 02 c5 0f 2f 23 44 00 6e 00 0c ac 10 02
+31 00 60 05 48 0c 00 20 c0 02 8d 00 ff 02 09 04
+31 02 60 05 49 0c a0 28 c0 02 8d 00 ff 02 18 02
+31 01 60 06 c1 0f 2f 21 24 00 6e 00 e0 e4 18 0e
+31 00 60 02 c9 0f 40 20 20 00 8d 00 01 00 49 08
+31 00 80 02 c9 0f 40 20 20 00 8d 00 01 00 8a 0e
+31 00 60 02 c9 0f 40 20 40 00 8d 00 01 00 41 08
+31 00 80 02 c9 0f 40 20 40 00 8d 00 01 00 82 10
+31 01 60 06 dc 0f 0f 20 24 00 6e 00 70 c4 08 9a
+31 01 60 04 dd 0f ef 21 24 02 6e 00 43 40 18 04
+31 01 60 04 dd 0f af 22 24 02 6e 00 42 40 18 04
+31 01 60 04 dd 0f ef 22 24 02 6e 00 41 40 18 04
+31 01 60 04 dd 0f 8f 20 24 02 6e 00 03 40 18 04
+31 01 60 04 dd 0f af 21 24 02 6e 00 02 40 18 04
+31 00 60 02 c9 0f c0 21 40 00 8d 00 02 71 41 0a
+31 00 80 02 c9 0f 00 23 40 00 8d 00 02 71 82 14
+31 02 80 09 49 0c 40 20 20 02 8d 00 07 03 28 02
+31 00 60 02 c9 0f c0 20 40 00 8d 00 03 32 41 0a
+31 00 80 02 c9 0f a0 21 40 00 8d 00 03 32 82 14
+31 01 60 02 dd 0f af 20 44 00 6e 00 03 23 10 04
+31 00 60 02 c9 0f 40 20 40 00 8d 00 02 00 41 04
+31 00 60 02 c9 0f 80 22 40 00 8d 00 08 00 41 04
+31 00 60 02 c9 0f 00 23 40 00 8d 00 09 01 41 04
+31 00 60 02 c9 0f 80 23 40 00 8d 00 0a 02 41 04
+31 00 60 02 c9 0f 00 24 40 00 8d 00 0b 03 41 04
+31 00 60 02 c9 0f 80 24 40 00 8d 00 0c 04 41 04
+31 00 60 02 c9 0f 00 25 40 00 8d 00 0d 05 41 04
+31 00 60 02 c9 0f 80 25 40 00 8d 00 0e 06 41 04
+31 00 60 02 c9 0f 00 26 40 00 8d 00 0f 07 41 04
+31 00 80 02 c9 0f c0 22 40 00 8d 00 08 00 82 08
+31 00 80 02 c9 0f c0 23 40 00 8d 00 09 01 82 08
+31 00 80 02 c9 0f c0 22 40 00 8d 00 0a 02 82 08
+31 00 80 02 c9 0f c0 24 40 00 8d 00 0b 03 82 08
+31 00 80 02 c9 0f c0 23 40 00 8d 00 0c 04 82 08
+31 00 80 02 c9 0f c0 25 40 00 8d 00 0d 05 82 08
+31 00 80 02 c9 0f c0 22 40 00 8d 00 0e 06 82 08
+31 00 80 02 c9 0f c0 26 40 00 8d 00 0f 07 82 08
+31 01 60 02 dd 0f af 20 44 00 6e 00 01 21 10 04
+31 01 60 02 dd 0f cf 20 44 00 6e 00 02 22 10 04
+31 01 60 02 dd 0f 0f 21 44 00 6e 00 04 24 10 04
+31 01 60 02 dd 0f 4f 21 44 00 6e 00 06 26 10 04
+31 01 60 02 dd 0f 6f 21 44 00 6e 00 07 27 10 04
+31 01 60 06 c1 0f 2f 21 24 00 6e 00 70 e4 18 0a

diff --git a/src/intel/tools/tests/gen6/sendc.asm b/src/intel/tools/tests/gen6/sendc.asm
new file mode 100644 (file)
index 0000000..6526e54
--- /dev/null
+++ b/src/intel/tools/tests/gen6/sendc.asm
@@ -0,0 +1,76 @@
+sendc(8)        null<1>UW       m1<8,8,1>F      0x88019400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x90019000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       m2<8,8,1>F      0x82019100
+                            render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x8c099401
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x94099001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x0e098401
+                            render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x8e099402
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x18098001
+                            render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x98099002
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x0c098400
+                            render MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x0c098401
+                            render MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x0c098402
+                            render MsgDesc: RT write SIMD8 Surface = 2 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x0c098403
+                            render MsgDesc: RT write SIMD8 Surface = 3 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x0c098404
+                            render MsgDesc: RT write SIMD8 Surface = 4 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x8c099405
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 5 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x14098000
+                            render MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x14098001
+                            render MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x14098002
+                            render MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x14098003
+                            render MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x14098004
+                            render MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x94099005
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x8c099400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x94099000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x8a019400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x94099200
+                            render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x14099200
+                            render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x94099300
+                            render MsgDesc: RT write SIMD8/DualSrcHigh LastRT Surface = 0 mlen 10 rlen 0 { align1 2Q EOT };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x8c099402
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x94099002
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x0c098405
+                            render MsgDesc: RT write SIMD8 Surface = 5 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x0c098406
+                            render MsgDesc: RT write SIMD8 Surface = 6 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x8c099407
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 7 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x14098005
+                            render MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x14098006
+                            render MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x94099007
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x8e099401
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       m1<8,8,1>F      0x98099001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 12 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       m1<8,8,1>F      0x0e098400
+                            render MsgDesc: RT write SIMD8 Surface = 0 mlen 7 rlen 0 { align1 1Q };

diff --git a/src/intel/tools/tests/gen6/sendc.expected b/src/intel/tools/tests/gen6/sendc.expected
new file mode 100644 (file)
index 0000000..ff1644f
--- /dev/null
+++ b/src/intel/tools/tests/gen6/sendc.expected
@@ -0,0 +1,38 @@
+32 00 60 05 c8 0f 00 20 20 00 8d 00 00 94 01 88
+32 00 80 05 c8 0f 00 20 20 00 8d 00 00 90 01 90
+32 00 80 05 c8 0f 00 20 40 00 8d 00 00 91 01 82
+32 00 60 05 c8 0f 00 20 20 00 8d 00 01 94 09 8c
+32 00 80 05 c8 0f 00 20 20 00 8d 00 01 90 09 94
+32 00 60 05 c8 0f 00 20 20 00 8d 00 01 84 09 0e
+32 00 60 05 c8 0f 00 20 20 00 8d 00 02 94 09 8e
+32 00 80 05 c8 0f 00 20 20 00 8d 00 01 80 09 18
+32 00 80 05 c8 0f 00 20 20 00 8d 00 02 90 09 98
+32 00 60 05 c8 0f 00 20 20 00 8d 00 00 84 09 0c
+32 00 60 05 c8 0f 00 20 20 00 8d 00 01 84 09 0c
+32 00 60 05 c8 0f 00 20 20 00 8d 00 02 84 09 0c
+32 00 60 05 c8 0f 00 20 20 00 8d 00 03 84 09 0c
+32 00 60 05 c8 0f 00 20 20 00 8d 00 04 84 09 0c
+32 00 60 05 c8 0f 00 20 20 00 8d 00 05 94 09 8c
+32 00 80 05 c8 0f 00 20 20 00 8d 00 00 80 09 14
+32 00 80 05 c8 0f 00 20 20 00 8d 00 01 80 09 14
+32 00 80 05 c8 0f 00 20 20 00 8d 00 02 80 09 14
+32 00 80 05 c8 0f 00 20 20 00 8d 00 03 80 09 14
+32 00 80 05 c8 0f 00 20 20 00 8d 00 04 80 09 14
+32 00 80 05 c8 0f 00 20 20 00 8d 00 05 90 09 94
+32 00 60 05 c8 0f 00 20 20 00 8d 00 00 94 09 8c
+32 00 80 05 c8 0f 00 20 20 00 8d 00 00 90 09 94
+32 00 60 05 c8 0f 00 20 20 00 8d 00 00 94 01 8a
+32 00 60 05 c8 0f 00 20 20 00 8d 00 00 92 09 94
+32 00 60 05 c8 0f 00 20 20 00 8d 00 00 92 09 14
+32 10 60 05 c8 0f 00 20 20 00 8d 00 00 93 09 94
+32 00 60 05 c8 0f 00 20 20 00 8d 00 02 94 09 8c
+32 00 80 05 c8 0f 00 20 20 00 8d 00 02 90 09 94
+32 00 60 05 c8 0f 00 20 20 00 8d 00 05 84 09 0c
+32 00 60 05 c8 0f 00 20 20 00 8d 00 06 84 09 0c
+32 00 60 05 c8 0f 00 20 20 00 8d 00 07 94 09 8c
+32 00 80 05 c8 0f 00 20 20 00 8d 00 05 80 09 14
+32 00 80 05 c8 0f 00 20 20 00 8d 00 06 80 09 14
+32 00 80 05 c8 0f 00 20 20 00 8d 00 07 90 09 94
+32 00 60 05 c8 0f 00 20 20 00 8d 00 01 94 09 8e
+32 00 80 05 c8 0f 00 20 20 00 8d 00 01 90 09 98
+32 00 60 05 c8 0f 00 20 20 00 8d 00 00 84 09 0e

diff --git a/src/intel/tools/tests/gen6/shl.asm b/src/intel/tools/tests/gen6/shl.asm
new file mode 100644 (file)
index 0000000..a8fce90
--- /dev/null
+++ b/src/intel/tools/tests/gen6/shl.asm
@@ -0,0 +1,13 @@
+shl(8)          g25<1>.xD       g21<4>.xD       0x00000004UD    { align16 1Q };
+shl(8)          g3<1>D          g2.4<0,1,0>D    0x00000004UD    { align1 1Q };
+shl(16)         g3<1>D          g2.4<0,1,0>D    0x00000004UD    { align1 1H };
+shl(8)          g11<1>D         g11<4>D         16D             { align16 1Q };
+shl(1)          g28<1>UD        g28<0,1,0>UD    0x00000010UD    { align1 1N };
+shl(8)          g64<1>.xUD      g64<4>.xUD      0x00000010UD    { align16 1Q };
+shl(8)          m17<1>D         g2<0,1,0>D      0x00000004UD    { align1 1Q };
+shl(16)         m17<1>D         g2<0,1,0>D      0x00000004UD    { align1 1H };
+shl(8)          g2<1>D          g2<8,8,1>D      16D             { align1 1Q };
+shl(16)         g2<1>D          g2<8,8,1>D      16D             { align1 1H };
+shl(8)          g25<1>D         g2<0>D          g24<4>UD        { align16 1Q };
+shl(8)          g10<1>D         g2.5<0,1,0>D    g9<8,8,1>UD     { align1 1Q };
+shl(16)         g13<1>D         g2.5<0,1,0>D    g11<8,8,1>UD    { align1 1H };

diff --git a/src/intel/tools/tests/gen6/shl.expected b/src/intel/tools/tests/gen6/shl.expected
new file mode 100644 (file)
index 0000000..d07c862
--- /dev/null
+++ b/src/intel/tools/tests/gen6/shl.expected
@@ -0,0 +1,13 @@
+09 01 60 00 a5 0c 21 23 a0 02 60 00 04 00 00 00
+09 00 60 00 a5 0c 60 20 50 00 00 00 04 00 00 00
+09 00 80 00 a5 0c 60 20 50 00 00 00 04 00 00 00
+09 01 60 00 a5 1c 6f 21 64 01 6e 00 10 00 00 00
+09 00 00 00 21 0c 80 23 80 03 00 00 10 00 00 00
+09 01 60 00 21 0c 01 28 00 08 60 00 10 00 00 00
+09 00 60 00 a6 0c 20 22 40 00 00 00 04 00 00 00
+09 00 80 00 a6 0c 20 22 40 00 00 00 04 00 00 00
+09 00 60 00 a5 1c 40 20 40 00 8d 00 10 00 00 00
+09 00 80 00 a5 1c 40 20 40 00 8d 00 10 00 00 00
+09 01 60 00 a5 04 2f 23 44 00 0e 00 04 03 6e 00
+09 00 60 00 a5 04 40 21 54 00 00 00 20 01 8d 00
+09 00 80 00 a5 04 a0 21 54 00 00 00 60 01 8d 00

diff --git a/src/intel/tools/tests/gen6/shr.asm b/src/intel/tools/tests/gen6/shr.asm
new file mode 100644 (file)
index 0000000..3d4d99c
--- /dev/null
+++ b/src/intel/tools/tests/gen6/shr.asm
@@ -0,0 +1,8 @@
+shr(8)          m18<1>D         g25<4>.xUD      4D              { align16 1Q };
+shr(8)          g13<1>UD        g12<8,8,1>UD    0x00000001UD    { align1 1Q };
+shr(16)         g19<1>UD        g17<8,8,1>UD    0x00000001UD    { align1 1H };
+shr(1)          g22<1>UD        g22<0,1,0>UD    5D              { align1 WE_all 1N };
+shr(8)          g34<1>UD        g3<0>UD         g1<0>.yUD       { align16 1Q };
+shr(8)          g3<1>.xUD       g3<4>.xUD       0x00000001UD    { align16 1Q };
+shr(8)          g28<1>UD        g3.5<0,1,0>UD   g4.1<0,1,0>UD   { align1 1Q };
+shr(16)         g48<1>UD        g3.5<0,1,0>UD   g4.1<0,1,0>UD   { align1 1H };

diff --git a/src/intel/tools/tests/gen6/shr.expected b/src/intel/tools/tests/gen6/shr.expected
new file mode 100644 (file)
index 0000000..0e21804
--- /dev/null
+++ b/src/intel/tools/tests/gen6/shr.expected
@@ -0,0 +1,8 @@
+08 01 60 00 26 1c 4f 22 20 03 60 00 04 00 00 00
+08 00 60 00 21 0c a0 21 80 01 8d 00 01 00 00 00
+08 00 80 00 21 0c 60 22 20 02 8d 00 01 00 00 00
+08 02 00 00 21 1c c0 22 c0 02 00 00 05 00 00 00
+08 01 60 00 21 04 4f 24 64 00 0e 00 25 00 05 00
+08 01 60 00 21 0c 61 20 60 00 60 00 01 00 00 00
+08 00 60 00 21 04 80 23 74 00 00 00 84 00 00 00
+08 00 80 00 21 04 00 26 74 00 00 00 84 00 00 00

diff --git a/src/intel/tools/tests/gen6/while.asm b/src/intel/tools/tests/gen6/while.asm
new file mode 100644 (file)
index 0000000..0df3ed7
--- /dev/null
+++ b/src/intel/tools/tests/gen6/while.asm
@@ -0,0 +1,6 @@
+while(8)        JIP: -76                                        { align16 1Q };
+while(8)        JIP: -108                                       { align1 1Q };
+while(16)       JIP: -108                                       { align1 1H };
+(-f0.0) while(8) JIP: -48                                       { align1 1Q };
+(-f0.0) while(16) JIP: -48                                      { align1 1H };
+(-f0.0.x) while(8) JIP: -48                                     { align16 1Q };

diff --git a/src/intel/tools/tests/gen6/while.expected b/src/intel/tools/tests/gen6/while.expected
new file mode 100644 (file)
index 0000000..4ea711e
--- /dev/null
+++ b/src/intel/tools/tests/gen6/while.expected
@@ -0,0 +1,6 @@
+27 01 60 00 8f 10 b4 ff 04 00 6e 00 04 00 6e 00
+27 00 60 00 8f 10 94 ff 00 00 8d 00 00 00 8d 00
+27 00 80 00 8f 10 94 ff 00 00 8d 00 00 00 8d 00
+27 00 71 00 8f 10 d0 ff 00 00 8d 00 00 00 8d 00
+27 00 91 00 8f 10 d0 ff 00 00 8d 00 00 00 8d 00
+27 01 72 00 8f 10 d0 ff 04 00 6e 00 04 00 6e 00

diff --git a/src/intel/tools/tests/gen6/xor.asm b/src/intel/tools/tests/gen6/xor.asm
new file mode 100644 (file)
index 0000000..8df3d47
--- /dev/null
+++ b/src/intel/tools/tests/gen6/xor.asm
@@ -0,0 +1,5 @@
+xor(8)          g17<1>D         g17<4>D         g2<0>D          { align16 1Q };
+xor(8)          g7<1>D          g7<8,8,1>D      g2.5<0,1,0>D    { align1 1Q };
+xor(16)         g8<1>D          g8<8,8,1>D      g2.5<0,1,0>D    { align1 1H };
+xor(8)          g9<1>UD         g5<8,8,1>UD     0x000003ffUD    { align1 1Q };
+xor(16)         g4<1>UD         g7<8,8,1>UD     0x000003ffUD    { align1 1H };

diff --git a/src/intel/tools/tests/gen6/xor.expected b/src/intel/tools/tests/gen6/xor.expected
new file mode 100644 (file)
index 0000000..48cf314
--- /dev/null
+++ b/src/intel/tools/tests/gen6/xor.expected
@@ -0,0 +1,5 @@
+07 01 60 00 a5 14 2f 22 24 02 6e 00 44 00 0e 00
+07 00 60 00 a5 14 e0 20 e0 00 8d 00 54 00 00 00
+07 00 80 00 a5 14 00 21 00 01 8d 00 54 00 00 00
+07 00 60 00 21 0c 20 21 a0 00 8d 00 ff 03 00 00
+07 00 80 00 21 0c 80 20 e0 00 8d 00 ff 03 00 00

diff --git a/src/intel/tools/tests/gen7.5/add.asm b/src/intel/tools/tests/gen7.5/add.asm
new file mode 100644 (file)
index 0000000..efde5b6
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/add.asm
@@ -0,0 +1,65 @@
+add(8)          g124<1>F        g9<8,8,1>D      1D              { align1 1Q };
+add(16)         g120<1>F        g15<8,8,1>D     1D              { align1 1H };
+add(16)         g6<1>UW         g1.4<1,4,0>UW   0x11001010V     { align1 WE_all 1H };
+add(16)         g4<1>UW         g1.4<2,4,0>UW   0x10101010V     { align1 1H };
+add(1)          g11.4<1>UD      g11<0,1,0>UD    0x00000001UD    { align1 1N };
+add(8)          g17<1>F         g6<0>F          g7.4<0>F        { align16 1Q };
+add(1)          a0<1>UW         g11<0,1,0>UW    0x0008UW        { align1 WE_all 1N };
+add(8)          g14<1>D         g12<4>D         -g1.4<0>D       { align16 1Q };
+add(8)          g3<1>F          g18<4>F         0x3e800000F  /* 0.25F */ { align16 1Q };
+add(1)          g126.4<1>D      g39.4<0,1,0>D   1D              { align1 WE_all 1N };
+add(8)          g46<1>F         g42<8,8,1>F     -g4.4<0,1,0>F   { align1 1Q };
+add(16)         g55<1>F         g47<8,8,1>F     -g6.4<0,1,0>F   { align1 1H };
+add(8)          g17<1>D         g15<8,8,1>D     -g7.3<0,1,0>D   { align1 1Q };
+add(16)         g83<1>D         g79<8,8,1>D     -g9.3<0,1,0>D   { align1 1H };
+add(8)          g11<1>.xD       g5<4>.xD        64D             { align16 1Q };
+add(1)          g8.3<1>UD       g0.3<0,1,0>UD   g7<0,1,0>UD     { align1 WE_all 1N };
+add(1)          g2<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 WE_all 1N };
+add(8)          g8<1>F          g2<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 1Q };
+add(16)         g9<1>F          g2<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 1H };
+add(8)          a0<1>UW         g3<16,8,2>UW    0x0040UW        { align1 1Q };
+add(8)          a0<1>UW         g4<16,8,2>UW    0x0040UW        { align1 2Q };
+add(8)          g115<1>.xyF     g2<0>.xyyyF     g8<4>.xyyyF     { align16 NoDDClr 1Q };
+add(8)          g114<1>.xD      g4<4>.xD        7D              { align16 NoDDClr 1Q };
+add(8)          g115<1>.xyF     g10<4>.xyyyF    0x3f000000F  /* 0.5F */ { align16 NoDDClr 1Q };
+add(8)          g3<1>D          g3<8,8,1>D      12D             { align1 1Q };
+add(16)         g5<1>D          g3<8,8,1>D      12D             { align1 1H };
+add(8)          g114<1>.xyzD    g4<4>.xyzzD     g7<4>.xyzzD     { align16 NoDDClr 1Q };
+add(8)          g11<1>F         g10<4>.xF       0x48403000VF /* [0F, 1F, 2F, 3F]VF */ { align16 1Q };
+add(8)          g116<1>.zD      g1<0>.xD        2D              { align16 NoDDClr,NoDDChk 1Q };
+add(8)          g117<1>.wD      g1<0>.xD        7D              { align16 NoDDChk 1Q };
+add(8)          g3<1>.yF        g13<4>.xF       -g1<0>.xF       { align16 NoDDClr,NoDDChk 1Q };
+add(8)          g117<1>.zF      g1<0>.xF        0x40000000F  /* 2F */ { align16 NoDDClr,NoDDChk 1Q };
+add(8)          g12<1>.zF       g1<0>.xF        0x42180000F  /* 38F */ { align16 NoDDChk 1Q };
+(+f0.0) add(8)  g16<1>D         -g16<4>D        31D             { align16 1Q };
+add(8)          g18<1>.xUD      g16<4>.xUD      0xffffffffUD    { align16 1Q };
+add(8)          g115<1>.xyF     g5<4>.xyyyF     0x30VF /* [1F, 0F, 0F, 0F]VF */ { align16 NoDDClr 1Q };
+add(1)          a0<1>UD         a0<0,1,0>UD     0x00000200UD    { align1 WE_all 1N };
+add(8)          g3.1<2>UW       g3.1<16,8,2>UW  g13<16,8,2>UW   { align1 1Q };
+add(16)         g3.1<2>UW       g3.1<16,8,2>UW  g5<16,8,2>UW    { align1 1H };
+add(8)          g16<1>UD        g29<0,1,0>UD    g26<1,4,0>UW    { align1 1Q };
+add(8)          g17<1>UD        g29<0,1,0>UD    g26.2<1,4,0>UW  { align1 2Q };
+add(8)          g14<1>.xDF      g12<0>.xyxyDF   g7<0>.xyxyDF    { align16 1Q };
+add.sat(8)      g116<1>F        g2<4>.yzxwF     -g2<4>F         { align16 1Q };
+add(8)          g8<1>UD         g6<8,8,1>D      0x00000001UD    { align1 1Q };
+add(16)         g11<1>UD        g9<8,8,1>D      0x00000001UD    { align1 1H };
+(+f0.0) add(8)  g7<1>D          -g7<8,8,1>D     31D             { align1 1Q };
+(+f0.0) add(16) g8<1>D          -g8<8,8,1>D     31D             { align1 1H };
+add.sat(8)      g127<1>F        g2<0,1,0>F      g2.4<0,1,0>F    { align1 1Q };
+add.sat(16)     g126<1>F        g2<0,1,0>F      g2.4<0,1,0>F    { align1 1H };
+add(8)          g117<1>.xyD     g6<4>.xyyyD     g12<4>.xD       { align16 NoDDClr,NoDDChk 1Q };
+add(8)          g115<1>.yF      g3<0>.yF        g26<4>.yF       { align16 NoDDChk 1Q };
+add(8)          g13<1>UD        g11<8,8,1>UD    1D              { align1 1Q };
+add(16)         g19<1>UD        g16<8,8,1>UD    1D              { align1 1H };
+add.sat(8)      g116<1>.yF      g1<0>.zF        0x3f000000F  /* 0.5F */ { align16 NoDDClr 1Q };
+add(8)          g7<1>UD         g2<8,8,1>UD     -g6<8,8,1>UD    { align1 WE_all 1Q };
+add(8)          g7<1>UD         g3<8,8,1>UD     0x00000110UD    { align1 1Q };
+add(16)         g24<1>UD        g4<8,8,1>UD     0x00000110UD    { align1 1H };
+add.l.f0.0(8)   g14<1>.xD       g12<4>.xD       -g12<4>.yD      { align16 1Q };
+add(16)         g17<1>F         -g15<4>.xyxyF   g15<4>.zwzwF    { align16 1H };
+add.sat(8)      g116<1>F        g5<4>.xF        0xbf800000F  /* -1F */ { align16 1Q };
+add.sat(8)      g116<1>.yF      -g1<0>.xF       0x3f000000F  /* 0.5F */ { align16 NoDDClr,NoDDChk 1Q };
+add.sat(8)      g116<1>.wF      g3<4>.yF        0xc0000000F  /* -2F */ { align16 NoDDChk 1Q };
+add(1)          g4<1>UD         g4<0,1,0>UD     0x00000001UD    { align1 WE_all 3N };
+add(1)          g23.3<1>UD      g0.3<0,1,0>UD   g22<0,1,0>UD    { align1 WE_all 3N };
+add.nz.f0.0(8)  g15<1>.xD       g1<4>.zD        g1<4>.xD        { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/add.expected b/src/intel/tools/tests/gen7.5/add.expected
new file mode 100644 (file)
index 0000000..e639bd2
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/add.expected
@@ -0,0 +1,65 @@
+40 00 60 00 bd 1c 80 2f 20 01 8d 00 01 00 00 00
+40 00 80 00 bd 1c 00 2f e0 01 8d 00 01 00 00 00
+40 02 80 00 29 6d c0 20 28 00 28 00 10 10 00 11
+40 00 80 00 29 6d 80 20 28 00 48 00 10 10 10 10
+40 00 00 00 21 0c 70 21 60 01 00 00 01 00 00 00
+40 01 60 00 bd 77 2f 22 c4 00 0e 00 f4 00 0e 00
+40 02 00 00 28 2d 00 22 60 01 00 00 08 00 08 00
+40 01 60 00 a5 14 cf 21 84 01 6e 00 34 40 0e 00
+40 01 60 00 bd 7f 6f 20 44 02 6e 00 00 00 80 3e
+40 02 00 00 a5 1c d0 2f f0 04 00 00 01 00 00 00
+40 00 60 00 bd 77 c0 25 40 05 8d 00 90 40 00 00
+40 00 80 00 bd 77 e0 26 e0 05 8d 00 d0 40 00 00
+40 00 60 00 a5 14 20 22 e0 01 8d 00 ec 40 00 00
+40 00 80 00 a5 14 60 2a e0 09 8d 00 2c 41 00 00
+40 01 60 00 a5 1c 61 21 a0 00 60 00 40 00 00 00
+40 02 00 00 21 04 0c 21 0c 00 00 00 e0 00 00 00
+40 02 00 00 21 0c 40 20 40 00 00 00 01 00 00 00
+40 00 60 00 bd 7f 00 21 40 00 8d 00 00 00 00 3f
+40 00 80 00 bd 7f 20 21 40 00 8d 00 00 00 00 3f
+40 00 60 00 28 2d 00 22 60 00 ae 00 40 00 40 00
+40 10 60 00 28 2d 00 22 80 00 ae 00 40 00 40 00
+40 05 60 00 bd 77 63 2e 44 00 05 00 04 01 65 00
+40 05 60 00 a5 1c 41 2e 80 00 60 00 07 00 00 00
+40 05 60 00 bd 7f 63 2e 44 01 65 00 00 00 00 3f
+40 00 60 00 a5 1c 60 20 60 00 8d 00 0c 00 00 00
+40 00 80 00 a5 1c a0 20 60 00 8d 00 0c 00 00 00
+40 05 60 00 a5 14 47 2e 84 00 6a 00 e4 00 6a 00
+40 01 60 00 bd 5f 6f 21 40 01 60 00 00 30 40 48
+40 0d 60 00 a5 1c 84 2e 20 00 00 00 02 00 00 00
+40 09 60 00 a5 1c a8 2e 20 00 00 00 07 00 00 00
+40 0d 60 00 bd 77 62 20 a0 01 60 00 20 40 00 00
+40 0d 60 00 bd 7f a4 2e 20 00 00 00 00 00 00 40
+40 09 60 00 bd 7f 84 21 20 00 00 00 00 00 18 42
+40 01 61 00 a5 1c 0f 22 04 42 6e 00 1f 00 00 00
+40 01 60 00 21 0c 41 22 00 02 60 00 ff ff ff ff
+40 05 60 00 bd 5f 63 2e a4 00 65 00 30 00 00 00
+40 02 00 00 00 0c 00 22 00 02 00 00 00 02 00 00
+40 00 60 00 29 25 62 40 62 00 ae 00 a0 01 ae 00
+40 00 80 00 29 25 62 40 62 00 ae 00 a0 00 ae 00
+40 00 60 00 21 24 00 22 a0 03 00 00 40 03 28 00
+40 10 60 00 21 24 20 22 a0 03 00 00 44 03 28 00
+40 01 60 00 39 67 c1 21 84 01 04 00 e4 00 04 00
+40 01 60 80 bd 77 8f 2e 49 00 6c 00 44 40 6e 00
+40 00 60 00 a1 0c 00 21 c0 00 8d 00 01 00 00 00
+40 00 80 00 a1 0c 60 21 20 01 8d 00 01 00 00 00
+40 00 61 00 a5 1c e0 20 e0 40 8d 00 1f 00 00 00
+40 00 81 00 a5 1c 00 21 00 41 8d 00 1f 00 00 00
+40 00 60 80 bd 77 e0 2f 40 00 00 00 50 00 00 00
+40 00 80 80 bd 77 c0 2f 40 00 00 00 50 00 00 00
+40 0d 60 00 a5 14 a3 2e c4 00 65 00 80 01 60 00
+40 09 60 00 bd 77 62 2e 65 00 05 00 45 03 65 00
+40 00 60 00 21 1c a0 21 60 01 8d 00 01 00 00 00
+40 00 80 00 21 1c 60 22 00 02 8d 00 01 00 00 00
+40 05 60 80 bd 7f 82 2e 2a 00 0a 00 00 00 00 3f
+40 02 60 00 21 04 e0 20 40 00 8d 00 c0 40 8d 00
+40 00 60 00 21 0c e0 20 60 00 8d 00 10 01 00 00
+40 00 80 00 21 0c 00 23 80 00 8d 00 10 01 00 00
+40 01 60 05 a5 14 c1 21 80 01 60 00 85 41 65 00
+40 01 80 00 bd 77 2f 22 e4 41 64 00 ee 01 6e 00
+40 01 60 80 bd 7f 8f 2e a0 00 60 00 00 00 80 bf
+40 0d 60 80 bd 7f 82 2e 20 40 00 00 00 00 00 3f
+40 09 60 80 bd 7f 88 2e 65 00 65 00 00 00 00 c0
+40 12 00 00 21 0c 80 20 80 00 00 00 01 00 00 00
+40 12 00 00 21 04 ec 22 0c 00 00 00 c0 02 00 00
+40 01 60 02 a5 14 e1 21 2a 00 6a 00 20 00 60 00

diff --git a/src/intel/tools/tests/gen7.5/and.asm b/src/intel/tools/tests/gen7.5/and.asm
new file mode 100644 (file)
index 0000000..e07ff1d
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/and.asm
@@ -0,0 +1,37 @@
+and(8)          g4<1>UD         g2<0,1,0>UD     g3<8,8,1>UD     { align1 1Q };
+and(16)         g5<1>UD         g2<0,1,0>UD     g3<8,8,1>UD     { align1 1H };
+and(1)          g11<1>UD        g0.2<0,1,0>UD   0x00fe0000UD    { align1 1N };
+and(1)          g12.2<1>UD      g0.2<0,1,0>UD   0x0001e000UD    { align1 WE_all 1N };
+and(8)          g8<1>UD         g0.1<0,1,0>UW   0x07ffUW        { align1 1Q };
+and(16)         g20<1>UD        g0.1<0,1,0>UW   0x07ffUW        { align1 1H };
+and(8)          g16<1>UD        g14<8,8,1>UD    0xfffffff4UD    { align1 1Q };
+and(16)         g22<1>UD        g18<8,8,1>UD    0xfffffff4UD    { align1 1H };
+and(8)          g11<1>UD        g1<0>UD         g10<4>UD        { align16 1Q };
+and(8)          g59<1>.xUD      g38<4>.xUD      0x00000001UD    { align16 1Q };
+and.nz.f0.0(8)  null<1>UD       g24<8,8,1>UD    g25<8,8,1>UD    { align1 1Q };
+and.nz.f0.0(16) null<1>UD       g45<8,8,1>UD    g47<8,8,1>UD    { align1 1H };
+and(2)          g3<1>UD         g1.3<0,1,0>UD   0x00001fffUD    { align1 WE_all 1N };
+and(1)          a0<1>UD         a0<0,1,0>UD     0x00000fffUD    { align1 WE_all 1N };
+and.nz.f0.0(8)  null<1>.xUD     g25<4>.xUD      g24<4>.xUD      { align16 1Q };
+and(8)          g4<1>.xUD       g1<0>.xUD       0x0000ffffUD    { align16 NoDDClr 1Q };
+and(1)          a0<1>UD         g4<0,1,0>UD     0x000000ffUD    { align1 WE_all 1N };
+and(1)          g2<1>UD         g19<0,1,0>UD    0x000000ffUD    { align1 WE_all 3N };
+and.z.f0.0(8)   null<1>UD       g9<4>.xUD       0x0000001fUD    { align16 1Q };
+and(8)          g14<1>.xUD      g12<4>.xUD      0x00000003UD    { align16 WE_all 1Q };
+and.nz.f0.0(8)  null<1>UD       g4<0,1,0>UD     0x00000001UD    { align1 1Q };
+and.nz.f0.0(16) null<1>UD       g6<0,1,0>UD     0x00000001UD    { align1 1H };
+and.z.f0.0(8)   null<1>UD       g20<8,8,1>UD    0x00000001UD    { align1 1Q };
+and.z.f0.0(16)  null<1>UD       g44<8,8,1>UD    0x00000001UD    { align1 1H };
+and(8)          g6<1>UD         g2<8,8,1>UD     0x00000003UD    { align1 WE_all 1Q };
+and(8)          g4<1>UW         g3<8,8,1>UW     0xfffcUW        { align1 1Q };
+and(8)          g8<1>UD         g4<8,8,1>UW     0x5F  /* 7.00649e-45F */ { align1 1Q };
+and(16)         g13<1>UW        g21<16,8,2>UW   0xfffcUW        { align1 1H };
+and(16)         g13<1>UD        g19<8,8,1>UW    0x5F  /* 7.00649e-45F */ { align1 1H };
+and.nz.f0.0(8)  g10<1>UD        g9<8,8,1>UD     0x00000001UD    { align1 1Q };
+and.nz.f0.0(16) g15<1>UD        g13<8,8,1>UD    0x00000001UD    { align1 1H };
+and.nz.f0.0(8)  g29<1>UD        g28<8,8,1>UD    g27<8,8,1>UD    { align1 1Q };
+and.nz.f0.0(16) g53<1>UD        g51<8,8,1>UD    g49<8,8,1>UD    { align1 1H };
+and.z.f0.0(8)   g26<1>.xUD      g24<4>.xUD      0x00000003UD    { align16 1Q };
+and(16)         g120<1>D        g7<8,8,1>D      g2<8,8,1>D      { align1 1H };
+and.z.f0.0(8)   null<1>UD       g12<8,8,1>UD    g16<8,8,1>UD    { align1 1Q };
+and.z.f0.0(16)  null<1>UD       g27<8,8,1>UD    g18<8,8,1>UD    { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/and.expected b/src/intel/tools/tests/gen7.5/and.expected
new file mode 100644 (file)
index 0000000..4327e64
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/and.expected
@@ -0,0 +1,37 @@
+05 00 60 00 21 04 80 20 40 00 00 00 60 00 8d 00
+05 00 80 00 21 04 a0 20 40 00 00 00 60 00 8d 00
+05 00 00 00 21 0c 60 21 08 00 00 00 00 00 fe 00
+05 02 00 00 21 0c 88 21 08 00 00 00 00 e0 01 00
+05 00 60 00 21 2d 00 21 02 00 00 00 ff 07 ff 07
+05 00 80 00 21 2d 80 22 02 00 00 00 ff 07 ff 07
+05 00 60 00 21 0c 00 22 c0 01 8d 00 f4 ff ff ff
+05 00 80 00 21 0c c0 22 40 02 8d 00 f4 ff ff ff
+05 01 60 00 21 04 6f 21 24 00 0e 00 44 01 6e 00
+05 01 60 00 21 0c 61 27 c0 04 60 00 01 00 00 00
+05 00 60 02 20 04 00 20 00 03 8d 00 20 03 8d 00
+05 00 80 02 20 04 00 20 a0 05 8d 00 e0 05 8d 00
+05 02 20 00 21 0c 60 20 2c 00 00 00 ff 1f 00 00
+05 02 00 00 00 0c 00 22 00 02 00 00 ff 0f 00 00
+05 01 60 02 20 04 01 20 20 03 60 00 00 03 60 00
+05 05 60 00 21 0c 81 20 20 00 00 00 ff ff 00 00
+05 02 00 00 20 0c 00 22 80 00 00 00 ff 00 00 00
+05 12 00 00 21 0c 40 20 60 02 00 00 ff 00 00 00
+05 01 60 01 20 0c 0f 20 20 01 60 00 1f 00 00 00
+05 03 60 00 21 0c c1 21 80 01 60 00 03 00 00 00
+05 00 60 02 20 0c 00 20 80 00 00 00 01 00 00 00
+05 00 80 02 20 0c 00 20 c0 00 00 00 01 00 00 00
+05 00 60 01 20 0c 00 20 80 02 8d 00 01 00 00 00
+05 00 80 01 20 0c 00 20 80 05 8d 00 01 00 00 00
+05 02 60 00 21 0c c0 20 40 00 8d 00 03 00 00 00
+05 00 60 00 29 2d 80 20 60 00 8d 00 fc ff fc ff
+05 00 60 00 21 7d 00 21 80 00 8d 00 05 00 00 00
+05 00 80 00 29 2d a0 21 a0 02 ae 00 fc ff fc ff
+05 00 80 00 21 7d a0 21 60 02 8d 00 05 00 00 00
+05 00 60 02 21 0c 40 21 20 01 8d 00 01 00 00 00
+05 00 80 02 21 0c e0 21 a0 01 8d 00 01 00 00 00
+05 00 60 02 21 04 a0 23 80 03 8d 00 60 03 8d 00
+05 00 80 02 21 04 a0 26 60 06 8d 00 20 06 8d 00
+05 01 60 01 21 0c 41 23 00 03 60 00 03 00 00 00
+05 00 80 00 a5 14 00 2f e0 00 8d 00 40 00 8d 00
+05 00 60 01 20 04 00 20 80 01 8d 00 00 02 8d 00
+05 00 80 01 20 04 00 20 60 03 8d 00 40 02 8d 00

diff --git a/src/intel/tools/tests/gen7.5/asr.asm b/src/intel/tools/tests/gen7.5/asr.asm
new file mode 100644 (file)
index 0000000..dc38883
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/asr.asm
@@ -0,0 +1,12 @@
+asr(8)          g13<1>.xD       g5.4<0>.zD      g5.4<0>.wUD     { align16 1Q };
+asr(8)          g57<1>.xD       g38<4>.xD       0x00000001UD    { align16 1Q };
+asr(8)          g3<1>D          g2<0,1,0>D      g2.1<0,1,0>UD   { align1 1Q };
+asr(16)         g3<1>D          g2<0,1,0>D      g2.1<0,1,0>UD   { align1 1H };
+asr(8)          g6<1>D          g5<8,8,1>D      0x00000001UD    { align1 1Q };
+asr(16)         g8<1>D          g6<8,8,1>D      0x00000001UD    { align1 1H };
+asr(8)          g4<1>.xD        g14<4>.xD       0x00000010UD    { align16 NoDDClr 1Q };
+asr(8)          g4<1>.yD        g1<0>.xD        0x00000010UD    { align16 NoDDChk 1Q };
+asr.nz.f0.0(8)  null<1>D        -g0<0,1,0>W     15D             { align1 1Q };
+asr.nz.f0.0(16) null<1>D        -g0<0,1,0>W     15D             { align1 1H };
+asr(8)          g2<1>D          -g0<0,1,0>W     15D             { align1 1Q };
+asr(16)         g2<1>D          -g0<0,1,0>W     15D             { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/asr.expected b/src/intel/tools/tests/gen7.5/asr.expected
new file mode 100644 (file)
index 0000000..0ce1f33
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/asr.expected
@@ -0,0 +1,12 @@
+0c 01 60 00 a5 04 a1 21 ba 00 0a 00 bf 00 0f 00
+0c 01 60 00 a5 0c 21 27 c0 04 60 00 01 00 00 00
+0c 00 60 00 a5 04 60 20 40 00 00 00 44 00 00 00
+0c 00 80 00 a5 04 60 20 40 00 00 00 44 00 00 00
+0c 00 60 00 a5 0c c0 20 a0 00 8d 00 01 00 00 00
+0c 00 80 00 a5 0c 00 21 c0 00 8d 00 01 00 00 00
+0c 05 60 00 a5 0c 81 20 c0 01 60 00 10 00 00 00
+0c 09 60 00 a5 0c 82 20 20 00 00 00 10 00 00 00
+0c 00 60 02 a4 1d 00 20 00 40 00 00 0f 00 00 00
+0c 00 80 02 a4 1d 00 20 00 40 00 00 0f 00 00 00
+0c 00 60 00 a5 1d 40 20 00 40 00 00 0f 00 00 00
+0c 00 80 00 a5 1d 40 20 00 40 00 00 0f 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/bfe.asm b/src/intel/tools/tests/gen7.5/bfe.asm
new file mode 100644 (file)
index 0000000..7d5532b
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/bfe.asm
@@ -0,0 +1,4 @@
+bfe(8)          g31<1>UD        g48<4,4,1>UD    g64<4,4,1>UD    g29<4,4,1>UD { align16 1Q };
+bfe(16)         g56<1>UD        g87<4,4,1>UD    g19<4,4,1>UD    g52<4,4,1>UD { align16 1H };
+bfe(8)          g20<1>D         g18<4,4,1>.xD   g17<4,4,1>.xD   g16<4,4,1>D { align16 1Q };
+bfe(16)         g13<1>D         g11<4,4,1>D     g42<4,4,1>D     g5<4,4,1>D { align16 1H };

diff --git a/src/intel/tools/tests/gen7.5/bfe.expected b/src/intel/tools/tests/gen7.5/bfe.expected
new file mode 100644 (file)
index 0000000..8711981
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/bfe.expected
@@ -0,0 +1,4 @@
+18 01 60 00 00 28 1e 1f c8 01 03 39 80 20 47 07
+18 01 80 00 00 28 1e 38 c8 71 05 39 26 20 07 0d
+18 01 60 00 00 14 1e 14 00 20 01 00 22 20 07 04
+18 01 80 00 00 14 1e 0d c8 b1 00 39 54 20 47 01

diff --git a/src/intel/tools/tests/gen7.5/bfi1.asm b/src/intel/tools/tests/gen7.5/bfi1.asm
new file mode 100644 (file)
index 0000000..1e50f9a
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/bfi1.asm
@@ -0,0 +1,3 @@
+bfi1(8)         g22<1>UD        g20<4>.xD       g19<4>.xD       { align16 1Q };
+bfi1(8)         g12<1>UD        g11<8,8,1>D     g10<8,8,1>D     { align1 1Q };
+bfi1(8)         g17<1>UD        g15<8,8,1>D     g21<8,8,1>D     { align1 2Q };

diff --git a/src/intel/tools/tests/gen7.5/bfi1.expected b/src/intel/tools/tests/gen7.5/bfi1.expected
new file mode 100644 (file)
index 0000000..6e4e4a0
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/bfi1.expected
@@ -0,0 +1,3 @@
+19 01 60 00 a1 14 cf 22 80 02 60 00 60 02 60 00
+19 00 60 00 a1 14 80 21 60 01 8d 00 40 01 8d 00
+19 10 60 00 a1 14 20 22 e0 01 8d 00 a0 02 8d 00

diff --git a/src/intel/tools/tests/gen7.5/bfi2.asm b/src/intel/tools/tests/gen7.5/bfi2.asm
new file mode 100644 (file)
index 0000000..6bde108
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/bfi2.asm
@@ -0,0 +1,2 @@
+bfi2(8)         g23<1>UD        g22<4,4,1>UD    g18<4,4,1>UD    g17<4,4,1>UD { align16 1Q };
+bfi2(8)         g19<1>UD        g17<4,4,1>UD    g52<4,4,1>UD    g7<4,4,1>UD { align16 2Q };

diff --git a/src/intel/tools/tests/gen7.5/bfi2.expected b/src/intel/tools/tests/gen7.5/bfi2.expected
new file mode 100644 (file)
index 0000000..b671e27
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/bfi2.expected
@@ -0,0 +1,2 @@
+1a 01 60 00 00 28 1e 17 c8 61 01 39 24 20 47 04
+1a 11 60 00 00 28 1e 13 c8 11 01 39 68 20 c7 01

diff --git a/src/intel/tools/tests/gen7.5/bfrev.asm b/src/intel/tools/tests/gen7.5/bfrev.asm
new file mode 100644 (file)
index 0000000..101d2cc
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/bfrev.asm
@@ -0,0 +1,3 @@
+bfrev(8)        g5<1>UD         g5<8,8,1>UD                     { align1 1Q };
+bfrev(16)       g6<1>UD         g8<8,8,1>UD                     { align1 1H };
+bfrev(8)        g11<1>UD        g10<4>UD                        { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/bfrev.expected b/src/intel/tools/tests/gen7.5/bfrev.expected
new file mode 100644 (file)
index 0000000..5dda563
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/bfrev.expected
@@ -0,0 +1,3 @@
+17 00 60 00 21 00 a0 20 a0 00 8d 00 00 00 00 00
+17 00 80 00 21 00 c0 20 00 01 8d 00 00 00 00 00
+17 01 60 00 21 00 6f 21 44 01 6e 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/break.asm b/src/intel/tools/tests/gen7.5/break.asm
new file mode 100644 (file)
index 0000000..fb3fb5c
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/break.asm
@@ -0,0 +1,6 @@
+break(8)        JIP: 2          UIP: 8                          { align1 1Q };
+break(16)       JIP: 2          UIP: 8                          { align1 1H };
+break(8)        JIP: 2          UIP: 10                         { align16 1Q };
+(+f0.0) break(8) JIP: 4         UIP: 10                         { align1 1Q };
+(+f0.0) break(16) JIP: 4        UIP: 10                         { align1 1H };
+(+f0.0.x) break(8) JIP: 110     UIP: 110                        { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/break.expected b/src/intel/tools/tests/gen7.5/break.expected
new file mode 100644 (file)
index 0000000..8f8ccc8
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/break.expected
@@ -0,0 +1,6 @@
+28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 08 00
+28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 08 00
+28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 0a 00
+28 00 61 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
+28 00 81 00 84 1c 00 20 00 00 8d 00 04 00 0a 00
+28 01 62 00 84 1c 0f 20 04 00 6e 00 6e 00 6e 00

diff --git a/src/intel/tools/tests/gen7.5/cbit.asm b/src/intel/tools/tests/gen7.5/cbit.asm
new file mode 100644 (file)
index 0000000..ffd6ed6
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/cbit.asm
@@ -0,0 +1,3 @@
+cbit(8)         g11<1>UD        g10<4>UD                        { align16 1Q };
+cbit(8)         g5<1>UD         g5<8,8,1>UD                     { align1 1Q };
+cbit(16)        g6<1>UD         g8<8,8,1>UD                     { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/cbit.expected b/src/intel/tools/tests/gen7.5/cbit.expected
new file mode 100644 (file)
index 0000000..8d18735
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/cbit.expected
@@ -0,0 +1,3 @@
+4d 01 60 00 21 00 6f 21 44 01 6e 00 00 00 00 00
+4d 00 60 00 21 00 a0 20 a0 00 8d 00 00 00 00 00
+4d 00 80 00 21 00 c0 20 00 01 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/cmp.asm b/src/intel/tools/tests/gen7.5/cmp.asm
new file mode 100644 (file)
index 0000000..9c59eb1
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/cmp.asm
@@ -0,0 +1,158 @@
+cmp.z.f0.0(8)   g7<1>D          g6<8,8,1>D      g2.5<0,1,0>D    { align1 1Q };
+cmp.z.f0.0(16)  g11<1>D         g9<8,8,1>D      g2.5<0,1,0>D    { align1 1H };
+cmp.ge.f0.0(8)  null<1>F        g45<4>.xF       g43<4>.xF       { align16 1Q switch };
+cmp.g.f0.0(8)   g18<1>.xyF      g13<4>.zwwwF    0x3f800000F  /* 1F */ { align16 1Q };
+cmp.nz.f0.0(8)  null<1>D        g18<4>.xyyyD    0D              { align16 1Q switch };
+cmp.g.f0.0(8)   null<1>F        g14<4>F         0x3f800000F  /* 1F */ { align16 1Q switch };
+cmp.le.f0.0(8)  g24<1>.xyF      g13<4>.zwwwF    0x3f800000F  /* 1F */ { align16 1Q };
+cmp.ge.f0.0(8)  g15<1>D         (abs)g14<4>D    1D              { align16 1Q };
+cmp.ge.f0.0(8)  g16<1>F         g15<4>F         0x3f800000F  /* 1F */ { align16 1Q };
+cmp.nz.f0.0(8)  null<1>F        g3<0>.xyzzF     0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16 1Q switch };
+cmp.z.f0.0(8)   null<1>D        g13<4>.xyyyD    g6<0>.yzzzD     { align16 1Q switch };
+cmp.ge.f0.0(8)  g33<1>F         g32<8,8,1>F     0x3189705fF  /* 4e-09F */ { align1 1Q };
+cmp.l.f0.0(8)   g34<1>F         g32<8,8,1>F     0x3189705fF  /* 4e-09F */ { align1 1Q };
+cmp.ge.f0.0(16) g71<1>F         g69<8,8,1>F     0x3189705fF  /* 4e-09F */ { align1 1H };
+cmp.l.f0.0(16)  g73<1>F         g69<8,8,1>F     0x3189705fF  /* 4e-09F */ { align1 1H };
+cmp.nz.f0.0(8)  g2<1>D          g6<8,8,1>D      255D            { align1 1Q };
+(+f0.1) cmp.z.f0.1(8) null<1>D  g2<8,8,1>D      0D              { align1 1Q switch };
+cmp.nz.f0.0(16) g2<1>D          g8<8,8,1>D      255D            { align1 1H };
+(+f0.1) cmp.z.f0.1(16) null<1>D g2<8,8,1>D      0D              { align1 1H switch };
+cmp.z.f0.0(8)   g6<1>D          g2<8,8,1>D      255D            { align1 1Q };
+cmp.z.f0.0(16)  g2<1>D          g40<8,8,1>D     255D            { align1 1H };
+cmp.z.f0.0(8)   null<1>D        g22<8,8,1>D     1D              { align1 1Q switch };
+cmp.z.f0.0(16)  null<1>D        g92<8,8,1>D     1D              { align1 1H switch };
+cmp.ge.f0.0(8)  g31<1>UD        g30<8,8,1>UD    g5.7<0,1,0>UD   { align1 1Q };
+cmp.l.f0.0(8)   g32<1>UD        g30<8,8,1>UD    g5.3<0,1,0>UD   { align1 1Q };
+cmp.ge.f0.0(16) g49<1>UD        g47<8,8,1>UD    g7.7<0,1,0>UD   { align1 1H };
+cmp.l.f0.0(16)  g51<1>UD        g47<8,8,1>UD    g7.3<0,1,0>UD   { align1 1H };
+cmp.l.f0.0(8)   g43<1>F         g42<8,8,1>F     g41<8,8,1>F     { align1 1Q };
+cmp.ge.f0.0(8)  g44<1>F         g42<8,8,1>F     g41<8,8,1>F     { align1 1Q };
+cmp.l.f0.0(16)  g80<1>F         g6<8,8,1>F      g78<8,8,1>F     { align1 1H };
+cmp.ge.f0.0(16) g82<1>F         g6<8,8,1>F      g78<8,8,1>F     { align1 1H };
+cmp.z.f0.0(8)   null<1>D        g4<0>.xD        0D              { align16 1Q switch };
+cmp.l.f0.0(8)   null<1>F        g35<4>.xF       0x3189705fF  /* 4e-09F */ { align16 1Q switch };
+cmp.z.f0.0(8)   null<1>F        g3<0>.zwwwF     g3<0>.xyyyF     { align16 1Q switch };
+cmp.l.f0.0(8)   g12<1>.xF       g5.4<0>.zF      g5.4<0>.wF      { align16 1Q };
+cmp.nz.f0.0(8)  g5<1>D          g4<8,8,1>D      g2.1<0,1,0>D    { align1 1Q };
+cmp.nz.f0.0(16) g7<1>D          g5<8,8,1>D      g2.1<0,1,0>D    { align1 1H };
+cmp.ge.f0.0(8)  g9<1>.xF        g1<0>.xF        g1<0>.yF        { align16 1Q };
+cmp.l.f0.0(8)   null<1>UD       g6<4>.xUD       0x00000003UD    { align16 1Q switch };
+cmp.nz.f0.0(8)  null<1>F        g42<4>F         g3<0>F          { align16 1Q switch };
+cmp.l.f0.0(8)   null<1>D        g4<0,1,0>D      1D              { align1 1Q switch };
+cmp.z.f0.0(8)   g20<1>F         g3<8,8,1>F      g4.3<0,1,0>F    { align1 1Q };
+cmp.l.f0.0(16)  null<1>D        g6<0,1,0>D      1D              { align1 1H switch };
+cmp.z.f0.0(16)  g37<1>F         g4<8,8,1>F      g6.3<0,1,0>F    { align1 1H };
+cmp.ge.f0.0(8)  g21<1>.xyUD     g1<0>.xyyyUD    g1<0>.zwwwUD    { align16 1Q };
+cmp.ge.f0.0(8)  null<1>.xD      g2<0>.xD        16D             { align16 1Q switch };
+cmp.le.f0.0(8)  null<1>.zF      g7<4>.xF        0x0F  /* 0F */  { align16 1Q switch };
+cmp.nz.f0.0(8)  null<1>F        g2<0,1,0>F      0x0F  /* 0F */  { align1 1Q switch };
+cmp.nz.f0.0(16) null<1>F        g2<0,1,0>F      0x0F  /* 0F */  { align1 1H switch };
+cmp.z.f0.0(8)   g3<1>F          g2.1<0,1,0>F    0x41000000F  /* 8F */ { align1 1Q };
+cmp.z.f0.0(16)  g3<1>F          g2.1<0,1,0>F    0x41000000F  /* 8F */ { align1 1H };
+cmp.nz.f0.0(8)  g20<1>.xyzD     g1<0>.xyzzD     g1.4<0>.xyzzD   { align16 1Q };
+cmp.z.f0.0(8)   g31<1>.yzwD     g3<0>.xD        g19<4>.yyzwD    { align16 1Q };
+cmp.z.f0.0(8)   null<1>F        g10<8,8,1>F     g4.1<0,1,0>F    { align1 1Q switch };
+cmp.z.f0.0(16)  null<1>F        g17<8,8,1>F     g6.1<0,1,0>F    { align1 1H switch };
+cmp.nz.f0.0(8)  g6<1>F          g5<8,8,1>F      g2.2<0,1,0>F    { align1 1Q };
+cmp.nz.f0.0(16) g8<1>F          g6<8,8,1>F      g2.2<0,1,0>F    { align1 1H };
+cmp.ge.f0.0(8)  g12<1>.xD       g5.4<0>.zD      g5.4<0>.wD      { align16 1Q };
+cmp.nz.f0.0(8)  g47<1>.xD       g5.4<0>.zD      0D              { align16 1Q };
+cmp.z.f0.0(8)   g11<1>.xF       g58<4>.xF       g56<4>.xF       { align16 1Q };
+cmp.nz.f0.0(8)  null<1>D        g13<4>.xyyyD    g42<4>.xD       { align16 1Q switch };
+cmp.nz.f0.0(8)  null<1>D        g4<0,1,0>D      0D              { align1 1Q switch };
+cmp.nz.f0.0(16) null<1>D        g6<0,1,0>D      0D              { align1 1H switch };
+cmp.z.f0.0(8)   g17<1>.xD       g1<0>.xD        1D              { align16 1Q };
+cmp.nz.f0.0(8)  null<1>F        g2.4<0,1,0>F    g22.1<0,1,0>F   { align1 1Q switch };
+cmp.nz.f0.0(16) null<1>F        g2.4<0,1,0>F    g39.1<0,1,0>F   { align1 1H switch };
+cmp.nz.f0.0(8)  null<1>F        g47<4>.xyzzF    0x0F  /* 0F */  { align16 1Q switch };
+cmp.l.f0.0(8)   g70<1>.xyzF     g68<4>.xyzzF    0x0F  /* 0F */  { align16 1Q };
+cmp.z.f0.0(8)   null<1>.xF      (abs)g13<4>.xF  0x7f800000F  /* infF */ { align16 1Q switch };
+cmp.l.f0.0(8)   null<1>.xF      g5<4>.xF        g13<4>.xF       { align16 1Q switch };
+cmp.l.f0.0(8)   g10<1>UD        g9<4>UD         g1<0>UD         { align16 1Q };
+cmp.g.f0.0(8)   g32<1>F         g31<8,8,1>F     0x3727c5acF  /* 1e-05F */ { align1 1Q };
+cmp.le.f0.0(8)  g33<1>F         g31<8,8,1>F     0x3727c5acF  /* 1e-05F */ { align1 1Q };
+cmp.g.f0.0(16)  g65<1>F         g63<8,8,1>F     0x3727c5acF  /* 1e-05F */ { align1 1H };
+cmp.le.f0.0(16) g67<1>F         g63<8,8,1>F     0x3727c5acF  /* 1e-05F */ { align1 1H };
+cmp.z.f0.0(8)   null<1>F        g4.1<0,1,0>F    0x3f800000F  /* 1F */ { align1 1Q switch };
+cmp.z.f0.0(16)  null<1>F        g6.1<0,1,0>F    0x3f800000F  /* 1F */ { align1 1H switch };
+cmp.ge.f0.0(8)  g5<1>D          g2<0,1,0>D      1D              { align1 1Q };
+cmp.ge.f0.0(16) g7<1>D          g2<0,1,0>D      1D              { align1 1H };
+cmp.g.f0.0(8)   null<1>F        g124<8,8,1>F    0x0F  /* 0F */  { align1 1Q switch };
+cmp.g.f0.0(16)  null<1>F        g120<8,8,1>F    0x0F  /* 0F */  { align1 1H switch };
+cmp.l.f0.0(8)   g24<1>.xD       g18<4>.xD       4D              { align16 1Q };
+cmp.nz.f0.0(8)  g26<1>F         g75<8,8,1>F     0x40000000F  /* 2F */ { align1 1Q };
+cmp.nz.f0.0(16) g88<1>F         g42<8,8,1>F     0x40000000F  /* 2F */ { align1 1H };
+cmp.l.f0.0(8)   g57<1>D         g3<0,1,0>D      1D              { align1 1Q };
+cmp.l.f0.0(16)  g110<1>D        g3<0,1,0>D      1D              { align1 1H };
+cmp.ge.f0.0(8)  g3<1>D          g2.3<0,1,0>D    g2<0,1,0>D      { align1 1Q };
+cmp.ge.f0.0(16) g3<1>D          g2.3<0,1,0>D    g2<0,1,0>D      { align1 1H };
+cmp.nz.f0.0(8)  null<1>D        g10<8,8,1>D     g15<8,8,1>D     { align1 1Q switch };
+cmp.nz.f0.0(16) null<1>D        g15<8,8,1>D     g25<8,8,1>D     { align1 1H switch };
+cmp.l.f0.0(8)   null<1>UD       g1<0>.yUD       g1<0>.xUD       { align16 1Q switch };
+cmp.nz.f0.0(8)  g8<1>.xyzF      g1<0>.xyzzF     g1.4<0>.xyzzF   { align16 1Q };
+cmp.z.f0.0(8)   g2<1>DF         g8<4,4,1>DF     g5<0,1,0>DF     { align1 1Q };
+cmp.z.f0.0(8)   g11<1>DF        g8<4,4,1>DF     g5<0,1,0>DF     { align1 2Q };
+cmp.le.f0.0(8)  null<1>D        g1<0>.xD        0D              { align16 1Q switch };
+cmp.l.f0.0(8)   g3<1>D          g2.1<0,1,0>D    g2<0,1,0>D      { align1 1Q };
+cmp.l.f0.0(16)  g3<1>D          g2.1<0,1,0>D    g2<0,1,0>D      { align1 1H };
+cmp.l.f0.0(8)   null<1>.xD      g68<4>.xD       3D              { align16 1Q switch };
+cmp.l.f0.0(8)   g21<1>.xyD      g1<0>.zwwwD     g1<0>.xyyyD     { align16 1Q };
+cmp.le.f0.0(8)  null<1>F        g63<8,8,1>F     g2.1<0,1,0>F    { align1 1Q switch };
+cmp.le.f0.0(8)  null<1>F        g79<8,8,1>F     0x3fc00000F  /* 1.5F */ { align1 1Q switch };
+cmp.le.f0.0(16) null<1>F        g116<8,8,1>F    g2.1<0,1,0>F    { align1 1H switch };
+cmp.le.f0.0(16) null<1>F        g38<8,8,1>F     0x3fc00000F  /* 1.5F */ { align1 1H switch };
+cmp.z.f0.0(8)   null<1>F        g3<0>.xyzzF     0x6e6e6c6aVF /* [13F, 14F, 15F, 15F]VF */ { align16 1Q switch };
+cmp.z.f0.0(8)   null<1>D        g6<0,1,0>D      g2<0,1,0>D      { align1 1Q switch };
+cmp.z.f0.0(16)  null<1>D        g6<0,1,0>D      g2<0,1,0>D      { align1 1H switch };
+cmp.le.f0.0(8)  null<1>D        g6<8,8,1>D      50D             { align1 1Q switch };
+cmp.ge.f0.0(8)  null<1>F        g25<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q switch };
+cmp.le.f0.0(16) null<1>D        g14<8,8,1>D     50D             { align1 1H switch };
+cmp.ge.f0.0(16) null<1>F        g42<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1H switch };
+cmp.z.f0.0(8)   g26<1>.xF       g2.4<0>.zF      0x40800000F  /* 4F */ { align16 1Q };
+cmp.ge.f0.0(8)  null<1>.xD      g5<4>.xD        g3<0>.xD        { align16 1Q switch };
+cmp.ge.f0.0(8)  null<1>D        g6<8,8,1>D      4D              { align1 1Q switch };
+cmp.ge.f0.0(16) null<1>D        g10<8,8,1>D     4D              { align1 1H switch };
+cmp.g.f0.0(8)   null<1>D        g1<0>.zD        31D             { align16 1Q switch };
+cmp.ge.f0.0(8)  null<1>.xF      (abs)g35<4>.xF  0x5d5e0b6bF  /* 1e+18F */ { align16 1Q switch };
+cmp.l.f0.0(8)   null<1>F        g4<0,1,0>F      0x0F  /* 0F */  { align1 1Q switch };
+cmp.l.f0.0(16)  null<1>F        g6<0,1,0>F      0x0F  /* 0F */  { align1 1H switch };
+cmp.ge.f0.0(8)  null<1>UD       g1<0>.yUD       g1<0>.xUD       { align16 1Q switch };
+cmp.le.f0.0(8)  g93<1>F         g2.4<0,1,0>F    g89<0,1,0>F     { align1 1Q };
+cmp.ge.f0.0(8)  null<1>F        (abs)g14<8,8,1>F g89.1<0,1,0>F  { align1 1Q switch };
+cmp.g.f0.0(8)   g86<1>F         (abs)g38<8,8,1>F g59<0,1,0>F    { align1 1Q };
+cmp.l.f0.0(8)   null<1>F        g118<8,8,1>F    g89<0,1,0>F     { align1 1Q switch };
+cmp.le.f0.0(16) g96<1>F         g2.4<0,1,0>F    g45<0,1,0>F     { align1 1H };
+cmp.ge.f0.0(16) null<1>F        (abs)g114<8,8,1>F g45.1<0,1,0>F { align1 1H switch };
+cmp.g.f0.0(16)  g60<1>F         (abs)g68<8,8,1>F g46<0,1,0>F    { align1 1H };
+cmp.l.f0.0(16)  null<1>F        g37<8,8,1>F     g45<0,1,0>F     { align1 1H switch };
+cmp.g.f0.0(8)   null<1>UD       g1<0>.zUD       0x0000001fUD    { align16 1Q switch };
+cmp.l.f0.0(8)   null<1>D        g1<0>.yD        g1<0>.xD        { align16 1Q switch };
+cmp.l.f0.0(8)   null<1>UD       g2<8,8,1>UD     g4.1<0,1,0>UD   { align1 1Q switch };
+cmp.l.f0.0(16)  null<1>UD       g24<8,8,1>UD    g6.1<0,1,0>UD   { align1 1H switch };
+cmp.g.f0.0(8)   null<1>D        g2.1<0,1,0>D    0D              { align1 1Q switch };
+cmp.ge.f0.0(8)  null<1>D        g3<8,8,1>D      g2.1<0,1,0>D    { align1 1Q switch };
+cmp.g.f0.0(16)  null<1>D        g2.1<0,1,0>D    0D              { align1 1H switch };
+cmp.ge.f0.0(16) null<1>D        g3<8,8,1>D      g2.1<0,1,0>D    { align1 1H switch };
+cmp.nz.f0.0(8)  null<1>UD       g9<4>.xUD       0x00000000UD    { align16 1Q switch };
+cmp.nz.f0.0(8)  g2<1>DF         g15<0,1,0>DF    g28<4,4,1>DF    { align1 1Q };
+cmp.nz.f0.0(8)  g4<1>DF         g63<0,1,0>DF    g16<4,4,1>DF    { align1 2Q };
+cmp.l.f0.0(8)   null<1>D        g2<8,8,1>D      g3<8,8,1>D      { align1 1Q switch };
+cmp.l.f0.0(16)  null<1>D        g2<8,8,1>D      g4<8,8,1>D      { align1 1H switch };
+cmp.g.f0.0(8)   null<1>F        (abs)g14<8,8,1>F g45<0,1,0>F    { align1 1Q switch };
+cmp.g.f0.0(16)  null<1>F        (abs)g21<8,8,1>F g6<0,1,0>F     { align1 1H switch };
+(+f0.1) cmp.nz.f0.1(8) null<1>UW g0<8,8,1>UW    g0<8,8,1>UW     { align1 1Q switch };
+(+f0.1) cmp.nz.f0.1(16) null<1>UW g0<8,8,1>UW   g0<8,8,1>UW     { align1 1H switch };
+cmp.nz.f0.0(8)  g8<1>F          g7<4>F          0x0F  /* 0F */  { align16 1Q };
+cmp.le.f0.0(8)  g3<1>D          g2<0,1,0>D      0D              { align1 1Q };
+cmp.le.f0.0(16) g3<1>D          g2<0,1,0>D      0D              { align1 1H };
+cmp.l.f0.0(8)   null<1>UD       g12<8,8,1>UD    0x00000040UD    { align1 1Q switch };
+cmp.l.f0.0(16)  null<1>UD       g19<8,8,1>UD    0x00000040UD    { align1 1H switch };
+cmp.l.f0.0(8)   g14<1>UD        g11<8,8,1>UD    0x00000007UD    { align1 1Q };
+cmp.le.f0.0(8)  null<1>UD       g19<8,8,1>UD    0x000000ffUD    { align1 1Q switch };
+cmp.l.f0.0(16)  g24<1>UD        g18<8,8,1>UD    0x00000007UD    { align1 1H };
+cmp.le.f0.0(16) null<1>UD       g32<8,8,1>UD    0x000000ffUD    { align1 1H switch };
+cmp.ge.f0.0(8)  null<1>UD       g4<8,8,1>UD     g2.3<0,1,0>UD   { align1 1Q switch };
+cmp.ge.f0.0(16) null<1>UD       g5<8,8,1>UD     g2.3<0,1,0>UD   { align1 1H switch };
+cmp.le.f0.0(8)  g9<1>.xUD       g1<0>.xUD       0x00000001UD    { align16 1Q };
+cmp.g.f0.0(8)   null<1>UD       g4.2<0,1,0>UD   0x0000001fUD    { align1 1Q switch };
+cmp.g.f0.0(16)  null<1>UD       g4.2<0,1,0>UD   0x0000001fUD    { align1 1H switch };

diff --git a/src/intel/tools/tests/gen7.5/cmp.expected b/src/intel/tools/tests/gen7.5/cmp.expected
new file mode 100644 (file)
index 0000000..436fc77
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/cmp.expected
@@ -0,0 +1,158 @@
+10 00 60 01 a5 14 e0 20 c0 00 8d 00 54 00 00 00
+10 00 80 01 a5 14 60 21 20 01 8d 00 54 00 00 00
+10 81 60 04 bc 77 0f 20 a0 05 60 00 60 05 60 00
+10 01 60 03 bd 7f 43 22 ae 01 6f 00 00 00 80 3f
+10 81 60 02 a4 1c 0f 20 44 02 65 00 00 00 00 00
+10 81 60 03 bc 7f 0f 20 c4 01 6e 00 00 00 80 3f
+10 01 60 06 bd 7f 03 23 ae 01 6f 00 00 00 80 3f
+10 01 60 04 a5 1c ef 21 c4 21 6e 00 01 00 00 00
+10 01 60 04 bd 7f 0f 22 e4 01 6e 00 00 00 80 3f
+10 81 60 02 bc 5f 0f 20 64 00 0a 00 64 6e 74 74
+10 81 60 01 a4 14 0f 20 a4 01 65 00 c9 00 0a 00
+10 00 60 04 bd 7f 20 24 00 04 8d 00 5f 70 89 31
+10 00 60 05 bd 7f 40 24 00 04 8d 00 5f 70 89 31
+10 00 80 04 bd 7f e0 28 a0 08 8d 00 5f 70 89 31
+10 00 80 05 bd 7f 20 29 a0 08 8d 00 5f 70 89 31
+10 00 60 02 a5 1c 40 20 c0 00 8d 00 ff 00 00 00
+10 80 61 01 a4 1c 00 20 40 00 8d 02 00 00 00 00
+10 00 80 02 a5 1c 40 20 00 01 8d 00 ff 00 00 00
+10 80 81 01 a4 1c 00 20 40 00 8d 02 00 00 00 00
+10 00 60 01 a5 1c c0 20 40 00 8d 00 ff 00 00 00
+10 00 80 01 a5 1c 40 20 00 05 8d 00 ff 00 00 00
+10 80 60 01 a4 1c 00 20 c0 02 8d 00 01 00 00 00
+10 80 80 01 a4 1c 00 20 80 0b 8d 00 01 00 00 00
+10 00 60 04 21 04 e0 23 c0 03 8d 00 bc 00 00 00
+10 00 60 05 21 04 00 24 c0 03 8d 00 ac 00 00 00
+10 00 80 04 21 04 20 26 e0 05 8d 00 fc 00 00 00
+10 00 80 05 21 04 60 26 e0 05 8d 00 ec 00 00 00
+10 00 60 05 bd 77 60 25 40 05 8d 00 20 05 8d 00
+10 00 60 04 bd 77 80 25 40 05 8d 00 20 05 8d 00
+10 00 80 05 bd 77 00 2a c0 00 8d 00 c0 09 8d 00
+10 00 80 04 bd 77 40 2a c0 00 8d 00 c0 09 8d 00
+10 81 60 01 a4 1c 0f 20 80 00 00 00 00 00 00 00
+10 81 60 05 bc 7f 0f 20 60 04 60 00 5f 70 89 31
+10 81 60 01 bc 77 0f 20 6e 00 0f 00 64 00 05 00
+10 01 60 05 bd 77 81 21 ba 00 0a 00 bf 00 0f 00
+10 00 60 02 a5 14 a0 20 80 00 8d 00 44 00 00 00
+10 00 80 02 a5 14 e0 20 a0 00 8d 00 44 00 00 00
+10 01 60 04 bd 77 21 21 20 00 00 00 25 00 05 00
+10 81 60 05 20 0c 0f 20 c0 00 60 00 03 00 00 00
+10 81 60 02 bc 77 0f 20 44 05 6e 00 64 00 0e 00
+10 80 60 05 a4 1c 00 20 80 00 00 00 01 00 00 00
+10 00 60 01 bd 77 80 22 60 00 8d 00 8c 00 00 00
+10 80 80 05 a4 1c 00 20 c0 00 00 00 01 00 00 00
+10 00 80 01 bd 77 a0 24 80 00 8d 00 cc 00 00 00
+10 01 60 04 21 04 a3 22 24 00 05 00 2e 00 0f 00
+10 81 60 04 a4 1c 01 20 40 00 00 00 10 00 00 00
+10 81 60 06 bc 7f 04 20 e0 00 60 00 00 00 00 00
+10 80 60 02 bc 7f 00 20 40 00 00 00 00 00 00 00
+10 80 80 02 bc 7f 00 20 40 00 00 00 00 00 00 00
+10 00 60 01 bd 7f 60 20 44 00 00 00 00 00 00 41
+10 00 80 01 bd 7f 60 20 44 00 00 00 00 00 00 41
+10 01 60 02 a5 14 87 22 24 00 0a 00 34 00 0a 00
+10 01 60 01 a5 14 ee 23 60 00 00 00 65 02 6e 00
+10 80 60 01 bc 77 00 20 40 01 8d 00 84 00 00 00
+10 80 80 01 bc 77 00 20 20 02 8d 00 c4 00 00 00
+10 00 60 02 bd 77 c0 20 a0 00 8d 00 48 00 00 00
+10 00 80 02 bd 77 00 21 c0 00 8d 00 48 00 00 00
+10 01 60 04 a5 14 81 21 ba 00 0a 00 bf 00 0f 00
+10 01 60 02 a5 1c e1 25 ba 00 0a 00 00 00 00 00
+10 01 60 01 bd 77 61 21 40 07 60 00 00 07 60 00
+10 81 60 02 a4 14 0f 20 a4 01 65 00 40 05 60 00
+10 80 60 02 a4 1c 00 20 80 00 00 00 00 00 00 00
+10 80 80 02 a4 1c 00 20 c0 00 00 00 00 00 00 00
+10 01 60 01 a5 1c 21 22 20 00 00 00 01 00 00 00
+10 80 60 02 bc 77 00 20 50 00 00 00 c4 02 00 00
+10 80 80 02 bc 77 00 20 50 00 00 00 e4 04 00 00
+10 81 60 02 bc 7f 0f 20 e4 05 6a 00 00 00 00 00
+10 01 60 05 bd 7f c7 28 84 08 6a 00 00 00 00 00
+10 81 60 01 bc 7f 01 20 a0 21 60 00 00 00 80 7f
+10 81 60 05 bc 77 01 20 a0 00 60 00 a0 01 60 00
+10 01 60 05 21 04 4f 21 24 01 6e 00 24 00 0e 00
+10 00 60 03 bd 7f 00 24 e0 03 8d 00 ac c5 27 37
+10 00 60 06 bd 7f 20 24 e0 03 8d 00 ac c5 27 37
+10 00 80 03 bd 7f 20 28 e0 07 8d 00 ac c5 27 37
+10 00 80 06 bd 7f 60 28 e0 07 8d 00 ac c5 27 37
+10 80 60 01 bc 7f 00 20 84 00 00 00 00 00 80 3f
+10 80 80 01 bc 7f 00 20 c4 00 00 00 00 00 80 3f
+10 00 60 04 a5 1c a0 20 40 00 00 00 01 00 00 00
+10 00 80 04 a5 1c e0 20 40 00 00 00 01 00 00 00
+10 80 60 03 bc 7f 00 20 80 0f 8d 00 00 00 00 00
+10 80 80 03 bc 7f 00 20 00 0f 8d 00 00 00 00 00
+10 01 60 05 a5 1c 01 23 40 02 60 00 04 00 00 00
+10 00 60 02 bd 7f 40 23 60 09 8d 00 00 00 00 40
+10 00 80 02 bd 7f 00 2b 40 05 8d 00 00 00 00 40
+10 00 60 05 a5 1c 20 27 60 00 00 00 01 00 00 00
+10 00 80 05 a5 1c c0 2d 60 00 00 00 01 00 00 00
+10 00 60 04 a5 14 60 20 4c 00 00 00 40 00 00 00
+10 00 80 04 a5 14 60 20 4c 00 00 00 40 00 00 00
+10 80 60 02 a4 14 00 20 40 01 8d 00 e0 01 8d 00
+10 80 80 02 a4 14 00 20 e0 01 8d 00 20 03 8d 00
+10 81 60 05 20 04 0f 20 25 00 05 00 20 00 00 00
+10 01 60 02 bd 77 07 21 24 00 0a 00 34 00 0a 00
+10 00 60 01 39 67 40 20 00 01 69 00 a0 00 00 00
+10 10 60 01 39 67 60 21 00 01 69 00 a0 00 00 00
+10 81 60 06 a4 1c 0f 20 20 00 00 00 00 00 00 00
+10 00 60 05 a5 14 60 20 44 00 00 00 40 00 00 00
+10 00 80 05 a5 14 60 20 44 00 00 00 40 00 00 00
+10 81 60 05 a4 1c 01 20 80 08 60 00 03 00 00 00
+10 01 60 05 a5 14 a3 22 2e 00 0f 00 24 00 05 00
+10 80 60 06 bc 77 00 20 e0 07 8d 00 44 00 00 00
+10 80 60 06 bc 7f 00 20 e0 09 8d 00 00 00 c0 3f
+10 80 80 06 bc 77 00 20 80 0e 8d 00 44 00 00 00
+10 80 80 06 bc 7f 00 20 c0 04 8d 00 00 00 c0 3f
+10 81 60 01 bc 5f 0f 20 64 00 0a 00 6a 6c 6e 6e
+10 80 60 01 a4 14 00 20 c0 00 00 00 40 00 00 00
+10 80 80 01 a4 14 00 20 c0 00 00 00 40 00 00 00
+10 80 60 06 a4 1c 00 20 c0 00 8d 00 32 00 00 00
+10 80 60 04 bc 7f 00 20 20 03 8d 00 00 00 00 3f
+10 80 80 06 a4 1c 00 20 c0 01 8d 00 32 00 00 00
+10 80 80 04 bc 7f 00 20 40 05 8d 00 00 00 00 3f
+10 01 60 01 bd 7f 41 23 5a 00 0a 00 00 00 80 40
+10 81 60 04 a4 14 01 20 a0 00 60 00 60 00 00 00
+10 80 60 04 a4 1c 00 20 c0 00 8d 00 04 00 00 00
+10 80 80 04 a4 1c 00 20 40 01 8d 00 04 00 00 00
+10 81 60 03 a4 1c 0f 20 2a 00 0a 00 1f 00 00 00
+10 81 60 04 bc 7f 01 20 60 24 60 00 6b 0b 5e 5d
+10 80 60 05 bc 7f 00 20 80 00 00 00 00 00 00 00
+10 80 80 05 bc 7f 00 20 c0 00 00 00 00 00 00 00
+10 81 60 04 20 04 0f 20 25 00 05 00 20 00 00 00
+10 00 60 06 bd 77 a0 2b 50 00 00 00 20 0b 00 00
+10 80 60 04 bc 77 00 20 c0 21 8d 00 24 0b 00 00
+10 00 60 03 bd 77 c0 2a c0 24 8d 00 60 07 00 00
+10 80 60 05 bc 77 00 20 c0 0e 8d 00 20 0b 00 00
+10 00 80 06 bd 77 00 2c 50 00 00 00 a0 05 00 00
+10 80 80 04 bc 77 00 20 40 2e 8d 00 a4 05 00 00
+10 00 80 03 bd 77 80 27 80 28 8d 00 c0 05 00 00
+10 80 80 05 bc 77 00 20 a0 04 8d 00 a0 05 00 00
+10 81 60 03 20 0c 0f 20 2a 00 0a 00 1f 00 00 00
+10 81 60 05 a4 14 0f 20 25 00 05 00 20 00 00 00
+10 80 60 05 20 04 00 20 40 00 8d 00 84 00 00 00
+10 80 80 05 20 04 00 20 00 03 8d 00 c4 00 00 00
+10 80 60 03 a4 1c 00 20 44 00 00 00 00 00 00 00
+10 80 60 04 a4 14 00 20 60 00 8d 00 44 00 00 00
+10 80 80 03 a4 1c 00 20 44 00 00 00 00 00 00 00
+10 80 80 04 a4 14 00 20 60 00 8d 00 44 00 00 00
+10 81 60 02 20 0c 0f 20 20 01 60 00 00 00 00 00
+10 00 60 02 39 67 40 20 e0 01 00 00 80 03 69 00
+10 10 60 02 39 67 80 20 e0 07 00 00 00 02 69 00
+10 80 60 05 a4 14 00 20 40 00 8d 00 60 00 8d 00
+10 80 80 05 a4 14 00 20 40 00 8d 00 80 00 8d 00
+10 80 60 03 bc 77 00 20 c0 21 8d 00 a0 05 00 00
+10 80 80 03 bc 77 00 20 a0 22 8d 00 c0 00 00 00
+10 80 61 02 28 25 00 20 00 00 8d 02 00 00 8d 00
+10 80 81 02 28 25 00 20 00 00 8d 02 00 00 8d 00
+10 01 60 02 bd 7f 0f 21 e4 00 6e 00 00 00 00 00
+10 00 60 06 a5 1c 60 20 40 00 00 00 00 00 00 00
+10 00 80 06 a5 1c 60 20 40 00 00 00 00 00 00 00
+10 80 60 05 20 0c 00 20 80 01 8d 00 40 00 00 00
+10 80 80 05 20 0c 00 20 60 02 8d 00 40 00 00 00
+10 00 60 05 21 0c c0 21 60 01 8d 00 07 00 00 00
+10 80 60 06 20 0c 00 20 60 02 8d 00 ff 00 00 00
+10 00 80 05 21 0c 00 23 40 02 8d 00 07 00 00 00
+10 80 80 06 20 0c 00 20 00 04 8d 00 ff 00 00 00
+10 80 60 04 20 04 00 20 80 00 8d 00 4c 00 00 00
+10 80 80 04 20 04 00 20 a0 00 8d 00 4c 00 00 00
+10 01 60 06 21 0c 21 21 20 00 00 00 01 00 00 00
+10 80 60 03 20 0c 00 20 88 00 00 00 1f 00 00 00
+10 80 80 03 20 0c 00 20 88 00 00 00 1f 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/cont.asm b/src/intel/tools/tests/gen7.5/cont.asm
new file mode 100644 (file)
index 0000000..7f7a9c4
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/cont.asm
@@ -0,0 +1,3 @@
+cont(8)         JIP: 2          UIP: 8                          { align1 1Q };
+cont(16)        JIP: 2          UIP: 8                          { align1 1H };
+cont(8)         JIP: 2          UIP: 8                          { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/cont.expected b/src/intel/tools/tests/gen7.5/cont.expected
new file mode 100644 (file)
index 0000000..a8376c2
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/cont.expected
@@ -0,0 +1,3 @@
+29 00 60 00 00 1c 00 34 00 14 60 00 02 00 08 00
+29 00 80 00 00 1c 00 34 00 14 60 00 02 00 08 00
+29 01 60 00 00 1c 0f 34 04 14 6e 00 02 00 08 00

diff --git a/src/intel/tools/tests/gen7.5/dim.asm b/src/intel/tools/tests/gen7.5/dim.asm
new file mode 100644 (file)
index 0000000..df8e9ca
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/dim.asm
@@ -0,0 +1,2 @@
+dim(4)          g2<1>.xDF       0x3ff0000000000000F /* 1F */    { align16 WE_all 1N };
+dim(1)          g4<1>DF         0x4018000000000000F /* 6F */    { align1 WE_all 1N };

diff --git a/src/intel/tools/tests/gen7.5/dim.expected b/src/intel/tools/tests/gen7.5/dim.expected
new file mode 100644 (file)
index 0000000..bd8d497
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/dim.expected
@@ -0,0 +1,2 @@
+0a 03 40 00 f9 73 41 20 00 00 00 00 00 00 f0 3f
+0a 02 00 00 f9 73 80 20 00 00 00 00 00 00 18 40

diff --git a/src/intel/tools/tests/gen7.5/dp2.asm b/src/intel/tools/tests/gen7.5/dp2.asm
new file mode 100644 (file)
index 0000000..da76db0
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/dp2.asm
@@ -0,0 +1,4 @@
+dp2(8)          g24<1>.xF       g23<4>.xyyyF    g23<4>.xyyyF    { align16 1Q };
+dp2(8)          g116<1>.xF      g1<0>.yF        g1<0>.yF        { align16 NoDDClr 1Q };
+dp2(8)          g116<1>.yzF     g1<0>.xF        g1<0>.zwwwF     { align16 NoDDClr,NoDDChk 1Q };
+dp2(8)          g116<1>.wF      g1<0>.ywwwF     g1<0>.wyyyF     { align16 NoDDChk 1Q };

diff --git a/src/intel/tools/tests/gen7.5/dp2.expected b/src/intel/tools/tests/gen7.5/dp2.expected
new file mode 100644 (file)
index 0000000..c093405
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/dp2.expected
@@ -0,0 +1,4 @@
+57 01 60 00 bd 77 01 23 e4 02 65 00 e4 02 65 00
+57 05 60 00 bd 77 81 2e 25 00 05 00 25 00 05 00
+57 0d 60 00 bd 77 86 2e 20 00 00 00 2e 00 0f 00
+57 09 60 00 bd 77 88 2e 2d 00 0f 00 27 00 05 00

diff --git a/src/intel/tools/tests/gen7.5/dp3.asm b/src/intel/tools/tests/gen7.5/dp3.asm
new file mode 100644 (file)
index 0000000..7ed7e91
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/dp3.asm
@@ -0,0 +1,6 @@
+dp3(8)          g12<1>.xF       g11<4>.xyzzF    g11<4>.xyzzF    { align16 1Q };
+dp3(8)          g116<1>.xF      g3<0>.xyzzF     g6<4>.xyzzF     { align16 NoDDClr 1Q };
+dp3(8)          g116<1>.yF      g3.4<0>.xyzzF   g6<4>.xyzzF     { align16 NoDDClr,NoDDChk 1Q };
+dp3(8)          g5<1>.zF        g1<0>.xyzzF     g2.4<0>.xyzzF   { align16 NoDDChk 1Q };
+dp3.le.f0.0(8)  g40<1>.xF       g31<4>.xyzzF    g3.4<0>.xyzzF   { align16 1Q };
+dp3.sat(8)      g37<1>.xF       g31<4>.xyzzF    g35<4>.xyzzF    { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/dp3.expected b/src/intel/tools/tests/gen7.5/dp3.expected
new file mode 100644 (file)
index 0000000..eced97a
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/dp3.expected
@@ -0,0 +1,6 @@
+56 01 60 00 bd 77 81 21 64 01 6a 00 64 01 6a 00
+56 05 60 00 bd 77 81 2e 64 00 0a 00 c4 00 6a 00
+56 0d 60 00 bd 77 82 2e 74 00 0a 00 c4 00 6a 00
+56 09 60 00 bd 77 a4 20 24 00 0a 00 54 00 0a 00
+56 01 60 06 bd 77 01 25 e4 03 6a 00 74 00 0a 00
+56 01 60 80 bd 77 a1 24 e4 03 6a 00 64 04 6a 00

diff --git a/src/intel/tools/tests/gen7.5/dp4.asm b/src/intel/tools/tests/gen7.5/dp4.asm
new file mode 100644 (file)
index 0000000..e63b3e0
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/dp4.asm
@@ -0,0 +1,6 @@
+dp4(8)          g115<1>.xF      g3<4>F          g1<0>F          { align16 NoDDClr 1Q };
+dp4(8)          g115<1>.yF      g3<4>F          g1.4<0>F        { align16 NoDDClr,NoDDChk 1Q };
+dp4(8)          g115<1>.wF      g3<4>F          g2.4<0>F        { align16 NoDDChk 1Q };
+dp4(8)          g115<1>.wF      g5<4>F          g2.4<0>F        { align16 1Q };
+dp4.sat(8)      g116<1>F        g2<4>.xF        g2<4>F          { align16 1Q };
+dp4(8)          g5<1>.xF        g1<4>F          0x3f800000F  /* 1F */ { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/dp4.expected b/src/intel/tools/tests/gen7.5/dp4.expected
new file mode 100644 (file)
index 0000000..4d76b24
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/dp4.expected
@@ -0,0 +1,6 @@
+54 05 60 00 bd 77 61 2e 64 00 6e 00 24 00 0e 00
+54 0d 60 00 bd 77 62 2e 64 00 6e 00 34 00 0e 00
+54 09 60 00 bd 77 68 2e 64 00 6e 00 54 00 0e 00
+54 01 60 00 bd 77 68 2e a4 00 6e 00 54 00 0e 00
+54 01 60 80 bd 77 8f 2e 40 00 60 00 44 00 6e 00
+54 01 60 00 bd 7f a1 20 24 00 6e 00 00 00 80 3f

diff --git a/src/intel/tools/tests/gen7.5/dph.asm b/src/intel/tools/tests/gen7.5/dph.asm
new file mode 100644 (file)
index 0000000..c28a841
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/dph.asm
@@ -0,0 +1,5 @@
+dph(8)          g116<1>.xF      g4<4>.xyzxF     g5<4>F          { align16 1Q };
+dph.sat(8)      g116<1>F        g1<0>.xyzxF     g3<4>F          { align16 1Q };
+dph(8)          g115<1>.xF      g5<4>.xyzxF     g1<0>F          { align16 NoDDClr 1Q };
+dph(8)          g115<1>.yF      g5<4>.xyzxF     g1.4<0>F        { align16 NoDDClr,NoDDChk 1Q };
+dph(8)          g115<1>.wF      g5<4>.xyzxF     g2.4<0>F        { align16 NoDDChk 1Q };

diff --git a/src/intel/tools/tests/gen7.5/dph.expected b/src/intel/tools/tests/gen7.5/dph.expected
new file mode 100644 (file)
index 0000000..02bd5f6
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/dph.expected
@@ -0,0 +1,5 @@
+55 01 60 00 bd 77 81 2e 84 00 62 00 a4 00 6e 00
+55 01 60 80 bd 77 8f 2e 24 00 02 00 64 00 6e 00
+55 05 60 00 bd 77 61 2e a4 00 62 00 24 00 0e 00
+55 0d 60 00 bd 77 62 2e a4 00 62 00 34 00 0e 00
+55 09 60 00 bd 77 68 2e a4 00 62 00 54 00 0e 00

diff --git a/src/intel/tools/tests/gen7.5/else.asm b/src/intel/tools/tests/gen7.5/else.asm
new file mode 100644 (file)
index 0000000..080628a
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/else.asm
@@ -0,0 +1,3 @@
+else(8)         JIP: 4                                          { align16 1Q };
+else(8)         JIP: 72                                         { align1 1Q };
+else(16)        JIP: 72                                         { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/else.expected b/src/intel/tools/tests/gen7.5/else.expected
new file mode 100644 (file)
index 0000000..f780798
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/else.expected
@@ -0,0 +1,3 @@
+24 01 60 00 84 3c 0f 20 04 00 6e 00 04 00 00 00
+24 00 60 00 84 3c 00 20 00 00 8d 00 48 00 00 00
+24 00 80 00 84 3c 00 20 00 00 8d 00 48 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/endif.asm b/src/intel/tools/tests/gen7.5/endif.asm
new file mode 100644 (file)
index 0000000..4595507
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/endif.asm
@@ -0,0 +1,3 @@
+endif(8)        JIP: 6                                          { align1 1Q };
+endif(16)       JIP: 6                                          { align1 1H };
+endif(8)        JIP: 2                                          { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/endif.expected b/src/intel/tools/tests/gen7.5/endif.expected
new file mode 100644 (file)
index 0000000..73a60a3
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/endif.expected
@@ -0,0 +1,3 @@
+25 00 60 00 84 3c 00 20 00 00 8d 00 06 00 00 00
+25 00 80 00 84 3c 00 20 00 00 8d 00 06 00 00 00
+25 01 60 00 84 3c 0f 20 04 00 6e 00 02 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/f16to32.asm b/src/intel/tools/tests/gen7.5/f16to32.asm
new file mode 100644 (file)
index 0000000..aef3da1
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/f16to32.asm
@@ -0,0 +1,2 @@
+f16to32(8)      g124<1>F        g2<16,8,2>UW                    { align1 1Q };
+f16to32(16)     g120<1>F        g10<16,8,2>UW                   { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/f16to32.expected b/src/intel/tools/tests/gen7.5/f16to32.expected
new file mode 100644 (file)
index 0000000..1a37f6d
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/f16to32.expected
@@ -0,0 +1,2 @@
+14 00 60 00 3d 01 80 2f 40 00 ae 00 00 00 00 00
+14 00 80 00 3d 01 00 2f 40 01 ae 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/f32to16.asm b/src/intel/tools/tests/gen7.5/f32to16.asm
new file mode 100644 (file)
index 0000000..27e377d
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/f32to16.asm
@@ -0,0 +1,2 @@
+f32to16(8)      g21<2>W         g22<8,8,1>F                     { align1 1Q };
+f32to16(16)     g40<2>W         g42<8,8,1>F                     { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/f32to16.expected b/src/intel/tools/tests/gen7.5/f32to16.expected
new file mode 100644 (file)
index 0000000..50515f4
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/f32to16.expected
@@ -0,0 +1,2 @@
+13 00 60 00 ad 03 a0 42 c0 02 8d 00 00 00 00 00
+13 00 80 00 ad 03 00 45 40 05 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/fbh.asm b/src/intel/tools/tests/gen7.5/fbh.asm
new file mode 100644 (file)
index 0000000..f54933b
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/fbh.asm
@@ -0,0 +1,3 @@
+fbh(8)          g16<1>D         g15<4>D                         { align16 1Q };
+fbh(8)          g7<1>D          g4<8,8,1>D                      { align1 1Q };
+fbh(16)         g8<1>D          g4<8,8,1>D                      { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/fbh.expected b/src/intel/tools/tests/gen7.5/fbh.expected
new file mode 100644 (file)
index 0000000..72fad95
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/fbh.expected
@@ -0,0 +1,3 @@
+4b 01 60 00 a5 00 0f 22 e4 01 6e 00 00 00 00 00
+4b 00 60 00 a5 00 e0 20 80 00 8d 00 00 00 00 00
+4b 00 80 00 a5 00 00 21 80 00 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/fbl.asm b/src/intel/tools/tests/gen7.5/fbl.asm
new file mode 100644 (file)
index 0000000..cf176ed
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/fbl.asm
@@ -0,0 +1,5 @@
+fbl(8)          g5<1>UD         g5<8,8,1>UD                     { align1 1Q };
+fbl(16)         g6<1>UD         g8<8,8,1>UD                     { align1 1H };
+fbl(1)          g27<1>UD        f1<0,1,0>UB                     { align1 WE_all 1N };
+fbl(1)          g57<1>UD        f1<0,1,0>UW                     { align1 WE_all 1N };
+fbl(8)          g11<1>UD        g10<4>UD                        { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/fbl.expected b/src/intel/tools/tests/gen7.5/fbl.expected
new file mode 100644 (file)
index 0000000..ef623f0
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/fbl.expected
@@ -0,0 +1,5 @@
+4c 00 60 00 21 00 a0 20 a0 00 8d 00 00 00 00 00
+4c 00 80 00 21 00 c0 20 00 01 8d 00 00 00 00 00
+4c 02 00 00 01 02 60 23 20 06 00 00 00 00 00 00
+4c 02 00 00 01 01 20 27 20 06 00 00 00 00 00 00
+4c 01 60 00 21 00 6f 21 44 01 6e 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/frc.asm b/src/intel/tools/tests/gen7.5/frc.asm
new file mode 100644 (file)
index 0000000..91a7059
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/frc.asm
@@ -0,0 +1,4 @@
+frc.sat(8)      g116<1>F        g3<4>F                          { align16 1Q };
+frc(8)          g20<1>.xF       g1<0>.xF                        { align16 1Q };
+frc(8)          g52<1>F         g43<8,8,1>F                     { align1 1Q };
+frc(16)         g78<1>F         g95<8,8,1>F                     { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/frc.expected b/src/intel/tools/tests/gen7.5/frc.expected
new file mode 100644 (file)
index 0000000..cedfd5a
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/frc.expected
@@ -0,0 +1,4 @@
+43 01 60 80 bd 03 8f 2e 64 00 6e 00 00 00 00 00
+43 01 60 00 bd 03 81 22 20 00 00 00 00 00 00 00
+43 00 60 00 bd 03 80 26 60 05 8d 00 00 00 00 00
+43 00 80 00 bd 03 c0 29 e0 0b 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/halt.asm b/src/intel/tools/tests/gen7.5/halt.asm
new file mode 100644 (file)
index 0000000..71ad27b
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/halt.asm
@@ -0,0 +1,4 @@
+(-f0.1.any4h) halt(8) JIP: 72   UIP: 74                         { align1 1Q };
+halt(8)         JIP: 2          UIP: 2                          { align1 1Q };
+(-f0.1.any4h) halt(16) JIP: 72  UIP: 74                         { align1 1H };
+halt(16)        JIP: 2          UIP: 2                          { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/halt.expected b/src/intel/tools/tests/gen7.5/halt.expected
new file mode 100644 (file)
index 0000000..84b32b1
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/halt.expected
@@ -0,0 +1,4 @@
+2a 00 76 00 84 1c 00 20 00 00 8d 02 48 00 4a 00
+2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
+2a 00 96 00 84 1c 00 20 00 00 8d 02 48 00 4a 00
+2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen7.5/if.asm b/src/intel/tools/tests/gen7.5/if.asm
new file mode 100644 (file)
index 0000000..0ebd44d
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/if.asm
@@ -0,0 +1,6 @@
+(-f0.0) if(8)   JIP: 8          UIP: 8                          { align1 1Q };
+(-f0.0) if(16)  JIP: 8          UIP: 8                          { align1 1H };
+(+f0.0.x) if(8) JIP: 18         UIP: 18                         { align16 1Q };
+(+f0.0) if(8)   JIP: 14         UIP: 14                         { align16 1Q };
+(+f0.0) if(8)   JIP: 12         UIP: 82                         { align1 1Q };
+(+f0.0) if(16)  JIP: 12         UIP: 82                         { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/if.expected b/src/intel/tools/tests/gen7.5/if.expected
new file mode 100644 (file)
index 0000000..d2bccde
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/if.expected
@@ -0,0 +1,6 @@
+22 00 71 00 84 3c 00 20 00 00 00 00 08 00 08 00
+22 00 91 00 84 3c 00 20 00 00 00 00 08 00 08 00
+22 01 62 00 84 3c 0f 20 04 00 0e 00 12 00 12 00
+22 01 61 00 84 3c 0f 20 04 00 0e 00 0e 00 0e 00
+22 00 61 00 84 3c 00 20 00 00 00 00 0c 00 52 00
+22 00 81 00 84 3c 00 20 00 00 00 00 0c 00 52 00

diff --git a/src/intel/tools/tests/gen7.5/lrp.asm b/src/intel/tools/tests/gen7.5/lrp.asm
new file mode 100644 (file)
index 0000000..44988cf
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/lrp.asm
@@ -0,0 +1,4 @@
+lrp(8)          g42<1>F         g41<4,4,1>.xF   g40<4,4,1>F     g39<4,4,1>F { align16 1Q };
+lrp(16)         g4<1>F          g2.4<0,1,0>F    g2.2<0,1,0>F    g2.0<0,1,0>F { align16 1H };
+lrp.sat(8)      g7<1>F          g10<4,4,1>F     g13<4,4,1>F     g16<4,4,1>F { align16 1Q };
+lrp.sat(16)     g18<1>F         g20<4,4,1>F     g26<4,4,1>F     g32<4,4,1>F { align16 1H };

diff --git a/src/intel/tools/tests/gen7.5/lrp.expected b/src/intel/tools/tests/gen7.5/lrp.expected
new file mode 100644 (file)
index 0000000..f9e7426
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/lrp.expected
@@ -0,0 +1,4 @@
+5c 01 60 00 00 00 1e 2a 00 90 02 39 50 20 c7 09
+5c 01 80 00 00 00 1e 04 01 28 20 80 04 04 80 00
+5c 01 60 80 00 00 1e 07 c8 a1 00 39 1a 20 07 04
+5c 01 80 80 00 00 1e 12 c8 41 01 39 34 20 07 08

diff --git a/src/intel/tools/tests/gen7.5/lzd.asm b/src/intel/tools/tests/gen7.5/lzd.asm
new file mode 100644 (file)
index 0000000..da2da08
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/lzd.asm
@@ -0,0 +1,3 @@
+lzd(8)          g20<1>UD        g2.4<0>UD                       { align16 1Q };
+lzd(8)          g17<1>UD        g3.1<0,1,0>UD                   { align1 1Q };
+lzd(16)         g27<1>UD        g3.1<0,1,0>UD                   { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/lzd.expected b/src/intel/tools/tests/gen7.5/lzd.expected
new file mode 100644 (file)
index 0000000..429bf45
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/lzd.expected
@@ -0,0 +1,3 @@
+4a 01 60 00 21 00 8f 22 54 00 0e 00 00 00 00 00
+4a 00 60 00 21 00 20 22 64 00 00 00 00 00 00 00
+4a 00 80 00 21 00 60 23 64 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/mach.asm b/src/intel/tools/tests/gen7.5/mach.asm
new file mode 100644 (file)
index 0000000..fc7e3c5
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/mach.asm
@@ -0,0 +1,14 @@
+mach(8)         g19<1>UD        g17<8,8,1>UD    0xaaaaaaabUD    { align1 1Q AccWrEnable };
+mach(8)         g10<1>D         g17<8,8,1>D     1431655766D     { align1 1Q AccWrEnable };
+mach(8)         g87<1>UD        g84<8,8,1>UD    0xaaaaaaabUD    { align1 2Q AccWrEnable };
+mach(8)         g95<1>D         g84<8,8,1>D     1431655766D     { align1 2Q AccWrEnable };
+mach(8)         null<1>D        g1<0>.xyzzD     g1<0>.wD        { align16 1Q AccWrEnable };
+mach(8)         g12<1>UD        g9<4>UD         g11<4>UD        { align16 1Q AccWrEnable };
+mach(8)         g12<1>UD        g4<8,8,1>UD     g8<8,8,1>UD     { align1 1Q AccWrEnable };
+mach(8)         g21<1>UD        g5<8,8,1>UD     g13<8,8,1>UD    { align1 2Q AccWrEnable };
+mach(8)         g15<1>D         g12<4>D         g14<4>D         { align16 1Q AccWrEnable };
+mach(8)         g7<1>.xUD       g5<4>.xUD       0xaaaaaaabUD    { align16 1Q AccWrEnable };
+mach(8)         g15<1>.xD       g5<4>.xD        1431655766D     { align16 1Q AccWrEnable };
+mach(8)         null<1>D        g1<4>.xD        741092396D      { align16 1Q AccWrEnable };
+mach(8)         g13<1>D         g5<8,8,1>D      g9<8,8,1>D      { align1 1Q AccWrEnable };
+mach(8)         g22<1>D         g6<8,8,1>D      g14<8,8,1>D     { align1 2Q AccWrEnable };

diff --git a/src/intel/tools/tests/gen7.5/mach.expected b/src/intel/tools/tests/gen7.5/mach.expected
new file mode 100644 (file)
index 0000000..ffd7aa4
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/mach.expected
@@ -0,0 +1,14 @@
+49 00 60 10 21 0c 60 22 20 02 8d 00 ab aa aa aa
+49 00 60 10 a5 1c 40 21 20 02 8d 00 56 55 55 55
+49 10 60 10 21 0c e0 2a 80 0a 8d 00 ab aa aa aa
+49 10 60 10 a5 1c e0 2b 80 0a 8d 00 56 55 55 55
+49 01 60 10 a4 14 0f 20 24 00 0a 00 2f 00 0f 00
+49 01 60 10 21 04 8f 21 24 01 6e 00 64 01 6e 00
+49 00 60 10 21 04 80 21 80 00 8d 00 00 01 8d 00
+49 10 60 10 21 04 a0 22 a0 00 8d 00 a0 01 8d 00
+49 01 60 10 a5 14 ef 21 84 01 6e 00 c4 01 6e 00
+49 01 60 10 21 0c e1 20 a0 00 60 00 ab aa aa aa
+49 01 60 10 a5 1c e1 21 a0 00 60 00 56 55 55 55
+49 01 60 10 a4 1c 0f 20 20 00 60 00 2c 2c 2c 2c
+49 00 60 10 a5 14 a0 21 a0 00 8d 00 20 01 8d 00
+49 10 60 10 a5 14 c0 22 c0 00 8d 00 c0 01 8d 00

diff --git a/src/intel/tools/tests/gen7.5/mad.asm b/src/intel/tools/tests/gen7.5/mad.asm
new file mode 100644 (file)
index 0000000..2d9394a
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/mad.asm
@@ -0,0 +1,39 @@
+mad(8)          g11<1>F         g4.7<0,1,0>F    g4.3<0,1,0>F    g9<4,4,1>F { align16 1Q };
+mad(16)         g24<1>F         g6.7<0,1,0>F    g6.3<0,1,0>F    g20<4,4,1>F { align16 1H };
+mad(8)          g18<1>.xyzF     -g16<4,4,1>.xyzzF g11<4,4,1>.xyzzF g9<4,4,1>.xyzzF { align16 1Q };
+mad(16)         g3<1>F          -g2.4<0,1,0>F   g9.0<0,1,0>F    g2.0<0,1,0>F { align16 1H };
+mad(8)          g116<1>.xyzF    g9<4,4,1>.xyzzF g6<4,4,1>.xyzzF g30<4,4,1>.xyzzF { align16 NoDDClr 1Q };
+mad.le.f0.0(8)  g9<1>F          g3<4,4,1>F      g4.2<0,1,0>F    g15<4,4,1>F { align16 1Q };
+mad.le.f0.0(16) g15<1>F         g4<4,4,1>F      g6.2<0,1,0>F    g24<4,4,1>F { align16 1H };
+mad(8)          g32<1>F         g31<4,4,1>F     g2.3<0,1,0>F    -g15<4,4,1>F { align16 1Q };
+mad(16)         g56<1>F         g54<4,4,1>F     g2.3<0,1,0>F    -g5<4,4,1>F { align16 1H };
+mad.sat(8)      g12<1>F         g4.1<0,1,0>F    g4.0<0,1,0>F    g13<4,4,1>F { align16 1Q };
+mad.sat(16)     g18<1>F         g6.1<0,1,0>F    g6.0<0,1,0>F    g10<4,4,1>F { align16 1H };
+mad(8)          g22<1>.xF       g10<4,4,1>.xF   g21<4,4,1>.xF   (abs)g5.6<0,1,0>F { align16 1Q };
+mad.sat(8)      g116<1>.xyzF    g95<4,4,1>.xyzzF g89<4,4,1>.xyzzF g93<4,4,1>.zF { align16 NoDDClr 1Q };
+mad.ge.f0.0(8)  g16<1>.xF       g4<4,4,1>.xF    g15<4,4,1>.xF   -g1.4<0,1,0>F { align16 1Q };
+mad(8)          g5<1>.zF        g34<4,4,1>.xF   g25<4,4,1>.xF   g1.7<0,1,0>F { align16 NoDDClr,NoDDChk 1Q };
+mad.ge.f0.0(16) g23<1>F         g44.0<0,1,0>F   g6<4,4,1>F      -g3.0<0,1,0>F { align16 1H };
+mad(8)          g53<1>F         -g52<4,4,1>F    g21<4,4,1>F     -g21<4,4,1>F { align16 1Q };
+mad(8)          g71<1>F         -g8<4,4,1>F     -g2.4<0,1,0>F   -g21<4,4,1>F { align16 1Q };
+mad(16)         g96<1>F         -g94<4,4,1>F    g86<4,4,1>F     -g86<4,4,1>F { align16 1H };
+mad(16)         g5<1>F          -g92<4,4,1>F    -g2.4<0,1,0>F   -g86<4,4,1>F { align16 1H };
+mad(8)          g115<1>.xyF     g14<4,4,1>.xF   g13<4,4,1>.xF   g22<4,4,1>.xyyyF { align16 NoDDChk 1Q };
+mad(8)          g30<1>F         g44.1<0,1,0>F   -g44.0<0,1,0>F  g27<4,4,1>F { align16 1Q };
+mad(16)         g56<1>F         g6.1<0,1,0>F    -g6.0<0,1,0>F   g51<4,4,1>F { align16 1H };
+mad.sat(8)      g116<1>.xyzF    -g9<4,4,1>.xyzzF g8<4,4,1>.zxyyF g6<4,4,1>.yzxxF { align16 NoDDClr 1Q };
+mad(8)          g2<1>F          -g6<4,4,1>F     (abs)g5<4,4,1>F g14.0<0,1,0>F { align16 1Q };
+mad(16)         g2<1>F          -g8<4,4,1>F     (abs)g6<4,4,1>F g25.0<0,1,0>F { align16 1H };
+mad(8)          g17<1>.xF       -g29<4,4,1>.xF  g2.2<0,1,0>F    g1.5<0,1,0>F { align16 NoDDClr 1Q };
+mad(8)          g18<1>.yF       -g36<4,4,1>.xF  g2.2<0,1,0>F    g1.0<0,1,0>F { align16 NoDDClr,NoDDChk 1Q };
+mad(8)          g17<1>.zF       -g39<4,4,1>.xF  g1.6<0,1,0>F    g1.1<0,1,0>F { align16 NoDDChk 1Q };
+mad.l.f0.0(8)   g27<1>F         g7<4,4,1>F      g2.7<0,1,0>F    g3.3<0,1,0>F { align16 1Q };
+mad.l.f0.0(16)  g5<1>F          g9<4,4,1>F      g2.7<0,1,0>F    g3.3<0,1,0>F { align16 1H };
+mad(8)          g5<1>F          -g20.2<0,1,0>F  g11<4,4,1>F     (abs)g6<4,4,1>F { align16 1Q };
+mad(16)         g21<1>F         -g6.2<0,1,0>F   g19<4,4,1>F     (abs)g9<4,4,1>F { align16 1H };
+mad(16)         g23<1>F         g6.1<0,1,0>F    g21<4,4,1>F     (abs)g9<4,4,1>F { align16 1H };
+mad(8)          g9<1>F          g3.2<0,1,0>F    -g3.3<0,1,0>F   (abs)g2.0<0,1,0>F { align16 1Q };
+mad(16)         g15<1>F         g35.2<0,1,0>F   -g35.3<0,1,0>F  (abs)g2.0<0,1,0>F { align16 1H };
+mad(8)          g2<1>.xF        g12<4,4,1>.xF   g34<4,4,1>.xF   -g6<4,4,1>.xF { align16 NoDDClr 1Q };
+mad.nz.f0.0(8)  g10<1>F         -g12.0<0,1,0>F  g7<4,4,1>F      g10<4,4,1>F { align16 1Q };
+mad.nz.f0.0(16) g15<1>F         -g33.0<0,1,0>F  g9<4,4,1>F      g17<4,4,1>F { align16 1H };

diff --git a/src/intel/tools/tests/gen7.5/mad.expected b/src/intel/tools/tests/gen7.5/mad.expected
new file mode 100644 (file)
index 0000000..413c99b
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/mad.expected
@@ -0,0 +1,39 @@
+5b 01 60 00 00 00 1e 0b 01 4e 20 c0 08 20 47 02
+5b 01 80 00 00 00 1e 18 01 6e 20 c0 0c 20 07 05
+5b 01 60 00 20 00 0e 12 48 01 01 29 16 20 45 02
+5b 01 80 00 20 00 1e 03 01 28 20 00 12 04 80 00
+5b 05 60 00 00 00 0e 74 48 91 00 29 0c 20 85 07
+5b 01 60 06 00 00 1e 09 c8 31 20 80 08 20 c7 03
+5b 01 80 06 00 00 1e 0f c8 41 20 80 0c 20 07 06
+5b 01 60 00 00 02 1e 20 c8 f1 21 c0 04 20 c7 03
+5b 01 80 00 00 02 1e 38 c8 61 23 c0 04 20 47 01
+5b 01 60 80 00 00 1e 0c 01 42 20 00 08 20 47 03
+5b 01 80 80 00 00 1e 12 01 62 20 00 0c 20 87 02
+5b 01 60 00 00 01 02 16 00 a0 00 00 2a 04 70 01
+5b 05 60 80 00 00 0e 74 48 f1 05 29 b2 50 45 17
+5b 01 60 04 00 02 02 10 00 40 00 00 1e 04 60 00
+5b 0d 60 00 00 00 08 05 00 20 02 00 32 04 78 00
+5b 01 80 04 00 02 1e 17 01 c0 02 39 0c 04 c0 00
+5b 01 60 00 20 02 1e 35 c8 41 03 39 2a 20 47 05
+5b 01 60 00 a0 02 1e 47 c8 81 20 00 05 20 47 05
+5b 01 80 00 20 02 1e 60 c8 e1 05 39 ac 20 87 15
+5b 01 80 00 a0 02 1e 05 c8 c1 25 00 05 20 87 15
+5b 09 60 00 00 00 06 73 00 e0 00 00 1a a0 82 05
+5b 01 60 00 80 00 1e 1e 01 c2 22 00 58 20 c7 06
+5b 01 80 00 80 00 1e 38 01 62 20 00 0c 20 c7 0c
+5b 05 60 80 20 00 0e 74 48 91 80 14 10 48 80 01
+5b 01 60 00 60 00 1e 02 c8 61 00 39 0a 04 80 03
+5b 01 80 00 60 00 1e 02 c8 81 00 39 0c 04 40 06
+5b 05 60 00 20 00 02 11 00 d0 21 80 04 04 68 00
+5b 0d 60 00 20 00 04 12 00 40 22 80 04 04 40 00
+5b 09 60 00 20 00 08 11 00 70 22 80 03 04 48 00
+5b 01 60 05 00 00 1e 1b c8 71 20 c0 05 04 d8 00
+5b 01 80 05 00 00 1e 05 c8 91 20 c0 05 04 d8 00
+5b 01 60 00 20 01 1e 05 01 44 01 39 16 20 87 01
+5b 01 80 00 20 01 1e 15 01 64 00 39 26 20 47 02
+5b 01 80 00 00 01 1e 17 01 62 00 39 2a 20 47 02
+5b 01 60 00 80 01 1e 09 01 34 20 c0 06 04 80 00
+5b 01 80 00 80 01 1e 0f 01 34 22 c0 46 04 80 00
+5b 05 60 00 00 02 02 02 00 c0 00 00 44 00 80 01
+5b 01 60 02 20 00 1e 0a 01 c0 00 39 0e 20 87 02
+5b 01 80 02 20 00 1e 0f 01 10 02 39 12 20 47 04

diff --git a/src/intel/tools/tests/gen7.5/math.asm b/src/intel/tools/tests/gen7.5/math.asm
new file mode 100644 (file)
index 0000000..e3179b5
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/math.asm
@@ -0,0 +1,45 @@
+math sqrt(8)    g25<1>.xF       g24<4>.xF       null<4>F        { align16 1Q };
+math inv(8)     g5<1>F          g4<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math inv(16)    g10<1>F         g8<8,8,1>F      null<8,8,1>F    { align1 1H };
+math intmod(8)  g21<1>.xyUD     g1<0>.xUD       g1<0>.yzzzUD    { align16 1Q };
+math inv(8)     g11<1>.xyzF     g2<0>.xyzzF     null<4>F        { align16 1Q };
+math sqrt(8)    g9<1>F          g8<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math sqrt(16)   g15<1>F         g13<8,8,1>F     null<8,8,1>F    { align1 1H };
+math pow(8)     g20<1>F         g14<8,8,1>F     g20<0,1,0>F     { align1 1Q };
+math pow(16)    g26<1>F         g24<8,8,1>F     g28<0,1,0>F     { align1 1H };
+math intmod(8)  g4<1>UD         g2<0,1,0>UD     g2.3<0,1,0>UD   { align1 1Q };
+math intmod(8)  g5<1>UD         g2<0,1,0>UD     g2.3<0,1,0>UD   { align1 2Q };
+math pow(8)     g14<1>.xF       g13<4>.xF       g12<4>.xF       { align16 1Q };
+math log(8)     g7<1>F          g6<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math log(16)    g11<1>F         g9<8,8,1>F      null<8,8,1>F    { align1 1H };
+math cos(8)     g3<1>F          g2<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math cos(16)    g4<1>F          g2<8,8,1>F      null<8,8,1>F    { align1 1H };
+math cos(8)     g5<1>.yF        g14<4>.xF       null<4>F        { align16 1Q };
+math sin(8)     g21<1>.xF       g16<4>.xF       null<4>F        { align16 1Q };
+math exp(8)     g16<1>.xF       g15<4>.xF       null<4>F        { align16 1Q };
+math log(8)     g15<1>.xF       g14<4>.xF       null<4>F        { align16 1Q };
+math intdiv(8)  g10<1>D         g1<0>.xD        g1.4<0>D        { align16 1Q };
+math exp(8)     g124<1>F        g5<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math exp(16)    g120<1>F        g7<8,8,1>F      null<8,8,1>F    { align1 1H };
+math intdiv(8)  g3<1>UD         g2<0,1,0>UD     g2.2<0,1,0>UD   { align1 1Q };
+math intdiv(8)  g4<1>UD         g2<0,1,0>UD     g2.2<0,1,0>UD   { align1 2Q };
+math intdiv(8)  g14<1>.xyzUD    g6<0>.xyzzUD    g6.4<0>.xyzzUD  { align16 1Q };
+math intdiv(8)  g4<1>D          g2<0,1,0>D      g2.4<0,1,0>D    { align1 1Q };
+math intdiv(8)  g5<1>D          g2<0,1,0>D      g2.4<0,1,0>D    { align1 2Q };
+math rsq(8)     g69<1>.xF       (abs)g68<4>.xF  null<4>F        { align16 1Q };
+math sin(8)     g3<1>F          g2<0,1,0>F      null<8,8,1>F    { align1 1Q };
+math sin(16)    g3<1>F          g2<0,1,0>F      null<8,8,1>F    { align1 1H };
+math rsq(8)     g127<1>F        g2.1<0,1,0>F    null<8,8,1>F    { align1 1Q };
+math rsq(16)    g126<1>F        g2.1<0,1,0>F    null<8,8,1>F    { align1 1H };
+math.sat pow(8) g3<1>F          g2<0,1,0>F      g2.4<0,1,0>F    { align1 1Q };
+math.sat pow(16) g3<1>F         g2<0,1,0>F      g2.4<0,1,0>F    { align1 1H };
+math.sat sqrt(8) g3<1>F         g2<0,1,0>F      null<8,8,1>F    { align1 1Q };
+math.sat sqrt(16) g3<1>F        g2<0,1,0>F      null<8,8,1>F    { align1 1H };
+math.sat exp(8) g3<1>F          g2<0,1,0>F      null<8,8,1>F    { align1 1Q };
+math.sat exp(16) g3<1>F         g2<0,1,0>F      null<8,8,1>F    { align1 1H };
+math.sat sqrt(8) g8<1>F         g1<0>F          null<4>F        { align16 1Q };
+math.sat exp(8) g8<1>F          g1<0>F          null<4>F        { align16 1Q };
+math.sat rsq(8) g116<1>F        (abs)g6<4>.xF   null<4>F        { align16 1Q };
+math.sat pow(8) g116<1>F        g2<4>.xF        g2<4>.yF        { align16 1Q };
+math.sat inv(8) g116<1>.xF      g1<0>.xF        null<4>F        { align16 1Q };
+math.sat log(8) g116<1>F        g6<4>.xF        null<4>F        { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/math.expected b/src/intel/tools/tests/gen7.5/math.expected
new file mode 100644 (file)
index 0000000..e7ddbd6
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/math.expected
@@ -0,0 +1,45 @@
+38 01 60 04 bd 73 21 23 00 03 60 00 04 00 6e 00
+38 00 60 01 bd 73 a0 20 80 00 8d 00 00 00 8d 00
+38 00 80 01 bd 73 40 21 00 01 8d 00 00 00 8d 00
+38 01 60 0d 21 04 a3 22 20 00 00 00 29 00 0a 00
+38 01 60 01 bd 73 67 21 44 00 0a 00 04 00 6e 00
+38 00 60 04 bd 73 20 21 00 01 8d 00 00 00 8d 00
+38 00 80 04 bd 73 e0 21 a0 01 8d 00 00 00 8d 00
+38 00 60 0a bd 77 80 22 c0 01 8d 00 80 02 00 00
+38 00 80 0a bd 77 40 23 00 03 8d 00 80 03 00 00
+38 00 60 0d 21 04 80 20 40 00 00 00 4c 00 00 00
+38 10 60 0d 21 04 a0 20 40 00 00 00 4c 00 00 00
+38 01 60 0a bd 77 c1 21 a0 01 60 00 80 01 60 00
+38 00 60 02 bd 73 e0 20 c0 00 8d 00 00 00 8d 00
+38 00 80 02 bd 73 60 21 20 01 8d 00 00 00 8d 00
+38 00 60 07 bd 73 60 20 40 00 8d 00 00 00 8d 00
+38 00 80 07 bd 73 80 20 40 00 8d 00 00 00 8d 00
+38 01 60 07 bd 73 a2 20 c0 01 60 00 04 00 6e 00
+38 01 60 06 bd 73 a1 22 00 02 60 00 04 00 6e 00
+38 01 60 03 bd 73 01 22 e0 01 60 00 04 00 6e 00
+38 01 60 02 bd 73 e1 21 c0 01 60 00 04 00 6e 00
+38 01 60 0c a5 14 4f 21 20 00 00 00 34 00 0e 00
+38 00 60 03 bd 73 80 2f a0 00 8d 00 00 00 8d 00
+38 00 80 03 bd 73 00 2f e0 00 8d 00 00 00 8d 00
+38 00 60 0c 21 04 60 20 40 00 00 00 48 00 00 00
+38 10 60 0c 21 04 80 20 40 00 00 00 48 00 00 00
+38 01 60 0c 21 04 c7 21 c4 00 0a 00 d4 00 0a 00
+38 00 60 0c a5 14 80 20 40 00 00 00 50 00 00 00
+38 10 60 0c a5 14 a0 20 40 00 00 00 50 00 00 00
+38 01 60 05 bd 73 a1 28 80 28 60 00 04 00 6e 00
+38 00 60 06 bd 73 60 20 40 00 00 00 00 00 8d 00
+38 00 80 06 bd 73 60 20 40 00 00 00 00 00 8d 00
+38 00 60 05 bd 73 e0 2f 44 00 00 00 00 00 8d 00
+38 00 80 05 bd 73 c0 2f 44 00 00 00 00 00 8d 00
+38 00 60 8a bd 77 60 20 40 00 00 00 50 00 00 00
+38 00 80 8a bd 77 60 20 40 00 00 00 50 00 00 00
+38 00 60 84 bd 73 60 20 40 00 00 00 00 00 8d 00
+38 00 80 84 bd 73 60 20 40 00 00 00 00 00 8d 00
+38 00 60 83 bd 73 60 20 40 00 00 00 00 00 8d 00
+38 00 80 83 bd 73 60 20 40 00 00 00 00 00 8d 00
+38 01 60 84 bd 73 0f 21 24 00 0e 00 04 00 6e 00
+38 01 60 83 bd 73 0f 21 24 00 0e 00 04 00 6e 00
+38 01 60 85 bd 73 8f 2e c0 20 60 00 04 00 6e 00
+38 01 60 8a bd 77 8f 2e 40 00 60 00 45 00 65 00
+38 01 60 81 bd 73 81 2e 20 00 00 00 04 00 6e 00
+38 01 60 82 bd 73 8f 2e c0 00 60 00 04 00 6e 00

diff --git a/src/intel/tools/tests/gen7.5/mov.asm b/src/intel/tools/tests/gen7.5/mov.asm
new file mode 100644 (file)
index 0000000..8a3d6a8
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/mov.asm
@@ -0,0 +1,187 @@
+mov(8)          g114<1>D        0D                              { align16 1Q };
+mov.sat(8)      g116<1>F        g4<4>F                          { align16 1Q };
+mov(8)          g114<1>.wF      g5<4>.xF                        { align16 1Q };
+mov(8)          g113<1>UD       g0<4>UD                         { align16 WE_all 1Q };
+mov(4)          g114<1>F        g2.3<8,2,4>F                    { align1 WE_all 1N };
+mov(8)          g126<1>F        0x0F             /* 0F */       { align1 1Q };
+mov(8)          g125<1>F        -g9<8,8,1>D                     { align1 1Q };
+mov(16)         g124<1>F        0x0F             /* 0F */       { align1 1H };
+mov(16)         g122<1>F        -g15<8,8,1>D                    { align1 1H };
+mov(8)          g126<1>D        1065353216D                     { align1 1Q };
+mov.nz.f0.0(8)  null<1>D        g2<0,1,0>D                      { align1 1Q };
+mov(16)         g124<1>D        1065353216D                     { align1 1H };
+mov.nz.f0.0(16) null<1>D        g2<0,1,0>D                      { align1 1H };
+mov(8)          g115<1>F        0x41700000F      /* 15F */      { align16 1Q };
+mov(8)          g124<1>F        g2<0,1,0>F                      { align1 1Q };
+mov(16)         g120<1>F        g2<0,1,0>F                      { align1 1H };
+mov(8)          g2<1>F          g6<8,4,1>UW                     { align1 1Q };
+mov(8)          g7<1>D          g2<8,8,1>F                      { align1 1Q };
+mov(16)         g2<1>F          g4<8,8,1>UW                     { align1 1H };
+mov(16)         g8<1>D          g2<8,8,1>F                      { align1 1H };
+mov(8)          g12<1>F         0x30003000VF    /* [0F, 1F, 0F, 1F]VF */ { align16 1Q };
+mov(8)          g51<1>UD        0x00000000UD                    { align1 WE_all 1Q };
+mov(1)          g51.5<1>UD      0x0000ff00UD                    { align1 WE_all 1N };
+mov(1)          g51<1>UD        g[a0]<0,1,0>UD                  { align1 WE_all 1N };
+mov(2)          g12<1>UD        g0<0,1,0>UD                     { align1 WE_all 1N };
+mov(8)          g13<1>D         g50<4>D                         { align16 WE_all 1Q };
+mov(8)          g15<1>.xUD      g5<0>.wUD                       { align16 1Q };
+(+f0.0.any4h) mov(8) g19<1>.xD  -1D                             { align16 1Q };
+mov.z.f0.0(8)   null<1>F        g11<0>.xUD                      { align16 1Q };
+mov(8)          g126<1>F        0x00000000UD                    { align1 WE_all 1Q };
+mov(8)          g39<1>D         g3.4<0>D                        { align16 1Q };
+mov(8)          g114<1>.xD      g1<0>.xD                        { align16 NoDDClr 1Q };
+mov(8)          g114<1>.yzwF    0x0VF           /* [0F, 0F, 0F, 0F]VF */ { align16 NoDDChk 1Q };
+mov.nz.f0.0(8)  null<1>.xD      g16<4>.xD                       { align16 1Q };
+mov(8)          g17<1>F         -g15<4>D                        { align16 1Q };
+mov(8)          g15<1>F         g14<4>UD                        { align16 1Q };
+mov(2)          g113.3<1>UD     0x00000000UD                    { align1 WE_all 1N };
+mov(2)          g113.4<1>UW     g33<8,1,0>UW                    { align1 WE_all 1N };
+mov(1)          g126<1>D        0D                              { align1 WE_all 1N };
+mov(1)          g126<1>D        g39<0,1,0>D                     { align1 WE_all 1N };
+mov(1)          f0.1<1>UW       g1.14<0,1,0>UW                  { align1 WE_all 1N };
+mov(8)          g18<1>UD        g2<8,8,1>D                      { align1 1Q };
+mov(8)          g124<1>D        g8<8,8,1>D                      { align1 1Q };
+mov(1)          g32<1>F         0x3e800000F      /* 0.25F */    { align1 WE_all 1N };
+mov(16)         g12<1>UD        g40<8,8,1>D                     { align1 1H };
+mov(16)         g120<1>D        g48<8,8,1>D                     { align1 1H };
+mov(8)          g116<1>.xD      1059749626D                     { align16 NoDDClr 1Q };
+mov(8)          g116<1>.yD      1143373824D                     { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g117<1>.yD      -1093874483D                    { align16 NoDDChk 1Q };
+mov(8)          g7<1>UD         g0<8,8,1>UD                     { align1 WE_all 1Q };
+mov(8)          g21<1>UD        g0<8,8,1>UD                     { align1 WE_all 2Q };
+mov(8)          g23<1>F         g6<0,1,0>F                      { align1 2Q };
+mov(1)          g21.2<1>UD      0x000003f2UD                    { align1 WE_all 3N };
+mov(8)          g8<1>.yD        g4<0>.yD                        { align16 NoDDChk 1Q };
+mov(8)          g21<1>.xyzD     acc0<4>D                        { align16 1Q };
+mov(8)          g116<1>.xF      -g9<4>.xD                       { align16 NoDDClr 1Q };
+mov(8)          g115<1>.yUD     0x00000000UD                    { align16 NoDDChk 1Q };
+mov(8)          g7<1>UD         g0.1<0,1,0>UD                   { align1 1Q };
+mov.sat(8)      g124<1>F        g2<0,1,0>F                      { align1 1Q };
+mov.sat(16)     g120<1>F        g2<0,1,0>F                      { align1 1H };
+mov(8)          g19<1>.xD       g18<4>.xF                       { align16 1Q };
+mov(8)          g8<1>D          1065353216D                     { align16 WE_all 1Q };
+mov(8)          g6<1>F          g2<8,8,1>UD                     { align1 1Q };
+mov(16)         g2<1>F          g18<8,8,1>UD                    { align1 1H };
+mov(8)          g115<1>.wF      0D                              { align16 NoDDChk 1Q };
+(+f0.0.all4h) mov(8) g66<1>.xD  -1D                             { align16 1Q };
+mov.sat(8)      g116<1>.xF      0x3f800000F      /* 1F */       { align16 NoDDClr 1Q };
+mov.sat(8)      g116<1>.yF      0x3f666666F      /* 0.9F */     { align16 NoDDClr,NoDDChk 1Q };
+mov.sat(8)      g116<1>.wF      0x3f333333F      /* 0.7F */     { align16 NoDDChk 1Q };
+mov(8)          g19<1>.yzwD     0x48403000VF    /* [0F, 1F, 2F, 3F]VF */ { align16 1Q };
+mov(16)         g13<1>UD        g0<8,8,1>UD                     { align1 WE_all 1H };
+mov(1)          f1<1>UD         g1.7<0,1,0>UD                   { align1 WE_all 1N };
+mov(8)          g116<1>.yF      g56<4>.xD                       { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g116<1>.wF      g58<4>.xD                       { align16 NoDDChk 1Q };
+mov(8)          g115<1>.zwF     0x30000000VF    /* [0F, 0F, 0F, 1F]VF */ { align16 NoDDClr 1Q };
+mov.nz.f0.0(8)  g4<1>F          -(abs)g2<0,1,0>F                { align1 1Q };
+(+f0.0) mov(8)  g4<1>F          -g22<0,1,0>F                    { align1 1Q };
+mov.nz.f0.0(16) g4<1>F          -(abs)g2<0,1,0>F                { align1 1H };
+(+f0.0) mov(16) g4<1>F          -g39<0,1,0>F                    { align1 1H };
+mov(8)          g11<1>UD        0D                              { align1 WE_all 1Q };
+mov(1)          g11.7<1>UD      65535D                          { align1 WE_all 1N };
+mov(8)          g11<1>UD        0D                              { align1 WE_all 2Q };
+mov(8)          g12<1>D         g25<8,8,1>D                     { align1 2Q };
+mov(1)          g11.7<1>UD      65535D                          { align1 WE_all 3N };
+mov(1)          g7.7<1>UD       g1.7<0,1,0>UD                   { align1 WE_all 3N };
+mov(8)          g116<1>.xyD     g4<4>.xyyyD                     { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g3<1>.xF        -g16<4>.xF                      { align16 NoDDChk 1Q };
+mov(8)          g7<1>.xUD       0x00000000UD                    { align16 1Q };
+mov(8)          g20<1>.xUD      0D                              { align16 WE_all 1Q };
+mov(8)          g19<1>.xUD      g11<4>.xD                       { align16 1Q };
+mov.nz.f1.0(4)  null<1>F        g14<4>.xUD                      { align16 WE_all 1N };
+mov(8)          g8<1>.xUD       g1<0>.xF                        { align16 1Q };
+mov(8)          g9<1>UD         g7<8,8,1>F                      { align1 1Q };
+mov(8)          g11<1>UD        g9<16,8,2>UW                    { align1 1Q };
+mov(16)         g15<1>UD        g11<8,8,1>F                     { align1 1H };
+mov(16)         g19<1>UD        g15<16,8,2>UW                   { align1 1H };
+mov(8)          g4<1>.xUD       0x00000000UD                    { align16 WE_all 1Q };
+mov.z.f0.0(8)   null<1>.xD      0x00000000UD                    { align16 1Q };
+mov(8)          g7<1>D          0x00000000UD                    { align1 1Q };
+mov(8)          g9<1>D          g5<8,8,1>UD                     { align1 1Q };
+mov(16)         g75<1>D         0x00000000UD                    { align1 1H };
+mov(16)         g79<1>D         g17<8,8,1>UD                    { align1 1H };
+mov(8)          g116<1>.xyzF    g3.4<0>.xyzzF                   { align16 NoDDClr 1Q };
+mov.sat(8)      g116<1>.wF      g20<4>.wF                       { align16 NoDDChk 1Q };
+mov(1)          f1<1>UD         0x00000000UD                    { align1 WE_all 1N };
+mov.z.f1.0(8)   null<1>UW       0x0000UW                        { align1 1Q };
+mov.z.f1.0(16)  null<1>UW       0x0000UW                        { align1 1H };
+mov(8)          g3<1>.xyzF      g1.4<0>.xyzzUD                  { align16 NoDDClr 1Q };
+mov(8)          g3<1>.wF        g1<0>.xUD                       { align16 NoDDChk 1Q };
+mov(8)          g26<1>UW        0x32103210V                     { align1 WE_all 1Q };
+mov(8)          g5<1>.yF        -g32<4>.xF                      { align16 NoDDClr,NoDDChk 1Q };
+mov(4)          g4<1>.xDF       g2<0>.xyxyDF                    { align16 1N };
+mov(8)          g5<1>.xDF       g2<0>.xyxyDF                    { align16 1Q };
+mov(4)          g4<1>.zDF       g6<0>.xyxyDF                    { align16 2N };
+mov(8)          g9<1>F          g7<4>F                          { align16 WE_all 2N };
+mov(4)          g6<2>UD         g2.3<0,1,0>UD                   { align1 1N };
+mov(4)          g7<2>UD         g2.3<0,1,0>UD                   { align1 2N };
+mov(4)          g6<2>UD         g2.3<0,1,0>UD                   { align1 3N };
+mov(4)          g7<2>UD         g2.3<0,1,0>UD                   { align1 4N };
+mov(8)          g10<1>D         g11<8,4,2>UD                    { align1 2Q };
+mov(8)          g113<1>UD       g0<4>UD                         { align16 WE_all 2N };
+mov(4)          g6<2>D          g5.3<0,1,0>D                    { align1 1N };
+mov(4)          g7<2>D          g5.3<0,1,0>D                    { align1 2N };
+mov(8)          g14<2>F         g6<4,4,1>DF                     { align1 1Q };
+mov(4)          g8<2>D          g5.3<0,1,0>D                    { align1 3N };
+mov(4)          g9<2>D          g5.3<0,1,0>D                    { align1 4N };
+mov(8)          g4<2>F          g8<4,4,1>DF                     { align1 2Q };
+mov(8)          g121<1>UD       g4<8,4,2>UD                     { align1 2Q };
+mov.sat(8)      g116<1>F        0x3f800000F      /* 1F */       { align16 1Q };
+mov(8)          g2<1>.xUD       2D                              { align16 NoDDClr 1Q };
+mov(8)          g2<1>.yzwUD     0D                              { align16 NoDDChk 1Q };
+mov(8)          g5<1>F          0x0F             /* 0F */       { align1 WE_all 1Q };
+mov(16)         g4<1>UD         0x00000000UD                    { align1 WE_all 1H };
+mov(8)          g11<1>D         0D                              { align1 2Q };
+mov(8)          g8<1>UD         0x00000006UD                    { align1 1Q };
+mov(16)         g10<1>UD        0x00000006UD                    { align1 1H };
+mov(8)          g18<1>F         g19<4>F                         { align16 WE_all 1Q };
+mov(8)          g25<1>UD        0x00000000UD                    { align1 WE_all 2N };
+mov(1)          g25.5<1>UD      0x0000ff00UD                    { align1 WE_all 2N };
+mov(2)          g25<1>UD        g0<0,1,0>UD                     { align1 WE_all 2N };
+mov.sat(8)      g116<1>F        -g6<4>D                         { align16 1Q };
+mov(8)          g119<1>.zwD     0x706e0000VF    /* [0F, 0F, 15F, 16F]VF */ { align16 NoDDChk 1Q };
+mov.sat(8)      g116<1>.xyzF    -g11<4>.xyzzD                   { align16 NoDDClr 1Q };
+mov(8)          g116<1>.xF      0x3e800000F      /* 0.25F */    { align16 NoDDChk 1Q };
+mov(1)          g26.7<1>UD      f0.1<0,1,0>UW                   { align1 WE_all 1N };
+mov(1)          g2.7<1>UD       f0.1<0,1,0>UW                   { align1 WE_all 3N };
+mov(4)          g65<1>.xUD      0x00000001UD                    { align16 WE_all 1N };
+mov(4)          g65<1>.xUD      0x00000000UD                    { align16 1N };
+mov(8)          g14<1>UD        g13<32,8,4>UB                   { align1 1Q };
+mov(16)         g22<1>UD        g20<32,8,4>UB                   { align1 1H };
+mov(8)          g44<1>F         0xffffffe0F      /* -nanF */    { align1 2Q };
+mov(8)          g5<1>F          g2<0,1,0>B                      { align1 1Q };
+mov(16)         g6<1>F          g2<0,1,0>B                      { align1 1H };
+mov(8)          g4<1>.xUD       0x00000020UD                    { align16 NoDDClr 1Q };
+mov(8)          g116<1>.zwF     0x30000000VF    /* [0F, 0F, 0F, 1F]VF */ { align16 NoDDClr,NoDDChk 1Q };
+mov(16)         g5<1>UD         g2<0,1,0>UD                     { align1 1H };
+mov(1)          f1<1>UW         f0.1<0,1,0>UW                   { align1 WE_all 1N };
+mov.sat(8)      g116<1>.xF      g4<4>.xF                        { align16 NoDDClr 1Q };
+mov.sat(8)      g116<1>.yzF     g5<4>.xxyyF                     { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g9<1>.zwF       0D                              { align16 1Q };
+mov(8)          g3<1>.yzwUD     0D                              { align16 1Q };
+mov(8)          g5<1>UD         1043072D                        { align1 1Q };
+mov(8)          g18<2>UW        g9<8,8,1>F                      { align1 1Q };
+mov(8)          g3<1>UW         g18<16,8,2>UW                   { align1 1Q };
+mov(8)          g12<1>UW        g8<16,8,2>UW                    { align1 WE_all 1Q };
+mov(16)         g15<1>UD        1043072D                        { align1 1H };
+mov(16)         g21<2>UW        g17<8,8,1>F                     { align1 1H };
+mov(16)         g4<1>UW         g13<16,8,2>UW                   { align1 WE_all 1H };
+mov(8)          g4<1>.xF        0x42100000F      /* 36F */      { align16 NoDDClr 1Q };
+mov(8)          g11<1>UD        0x78706000VF    /* [0F, 8F, 16F, 24F]VF */ { align16 1Q };
+mov(8)          g13<1>F         g12<4,1,0>UB                    { align1 1Q };
+mov(16)         g6<1>F          g2<0,1,0>UB                     { align1 1H };
+mov.z.f0.0(8)   null<1>.xD      g1<4>D                          { align16 1Q };
+mov(8)          g9<1>UD         0x0F             /* 0F */       { align1 1Q };
+mov(16)         g10<1>UD        0x0F             /* 0F */       { align1 1H };
+mov.sat(8)      g116<1>.yF      -g11<4>.xD                      { align16 NoDDClr,NoDDChk 1Q };
+mov.sat(8)      g116<1>.wF      -g13<4>.xD                      { align16 NoDDChk 1Q };
+mov(8)          g2<1>D          g14<16,8,2>W                    { align1 1Q };
+mov(16)         g41<1>D         g20<16,8,2>W                    { align1 1H };
+mov(8)          g2<1>D          g14<32,8,4>B                    { align1 1Q };
+mov(16)         g41<1>D         g20<32,8,4>B                    { align1 1H };
+mov(8)          g2<1>F          g14<16,8,2>W                    { align1 1Q };
+mov(16)         g43<1>F         g4<16,8,2>W                     { align1 1H };
+mov(4)          g8<1>UB         g13<4,1,0>UB                    { align1 NoDDClr 1N };
+mov(4)          g8.16<1>UB      g13.16<4,1,0>UB                 { align1 NoDDChk 1N };
+mov.nz.f0.0(8)  g11<1>F         -(abs)g1<0>F                    { align16 1Q };
+(+f0.0) mov(8)  g11<1>F         0xbf800000F      /* -1F */      { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/mov.expected b/src/intel/tools/tests/gen7.5/mov.expected
new file mode 100644 (file)
index 0000000..25fddcf
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/mov.expected
@@ -0,0 +1,187 @@
+01 01 60 00 e5 10 4f 2e 00 00 00 00 00 00 00 00
+01 01 60 80 bd 03 8f 2e 84 00 6e 00 00 00 00 00
+01 01 60 00 bd 03 48 2e a0 00 60 00 00 00 00 00
+01 03 60 00 21 00 2f 2e 04 00 6e 00 00 00 00 00
+01 02 40 00 bd 03 40 2e 4c 00 87 00 00 00 00 00
+01 00 60 00 fd 73 c0 2f 00 00 00 00 00 00 00 00
+01 00 60 00 bd 00 a0 2f 20 41 8d 00 00 00 00 00
+01 00 80 00 fd 73 80 2f 00 00 00 00 00 00 00 00
+01 00 80 00 bd 00 40 2f e0 41 8d 00 00 00 00 00
+01 00 60 00 e5 10 c0 2f 00 00 00 00 00 00 80 3f
+01 00 60 02 a4 00 00 20 40 00 00 00 00 00 00 00
+01 00 80 00 e5 10 80 2f 00 00 00 00 00 00 80 3f
+01 00 80 02 a4 00 00 20 40 00 00 00 00 00 00 00
+01 01 60 00 fd 73 6f 2e 00 00 00 00 00 00 70 41
+01 00 60 00 bd 03 80 2f 40 00 00 00 00 00 00 00
+01 00 80 00 bd 03 00 2f 40 00 00 00 00 00 00 00
+01 00 60 00 3d 01 40 20 c0 00 89 00 00 00 00 00
+01 00 60 00 a5 03 e0 20 40 00 8d 00 00 00 00 00
+01 00 80 00 3d 01 40 20 80 00 8d 00 00 00 00 00
+01 00 80 00 a5 03 00 21 40 00 8d 00 00 00 00 00
+01 01 60 00 fd 52 8f 21 00 00 00 00 00 30 00 30
+01 02 60 00 61 00 60 26 00 00 00 00 00 00 00 00
+01 02 00 00 61 00 74 26 00 00 00 00 00 ff 00 00
+01 02 00 00 21 00 60 26 00 80 00 00 00 00 00 00
+01 02 20 00 21 00 80 21 00 00 00 00 00 00 00 00
+01 03 60 00 a5 00 af 21 44 06 6e 00 00 00 00 00
+01 01 60 00 21 00 e1 21 af 00 0f 00 00 00 00 00
+01 01 66 00 e5 10 61 22 00 00 00 00 ff ff ff ff
+01 01 60 01 3c 00 0f 20 60 01 00 00 00 00 00 00
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+01 01 60 02 a4 00 01 20 00 02 60 00 00 00 00 00
+01 01 60 00 bd 00 2f 22 e4 41 6e 00 00 00 00 00
+01 01 60 00 3d 00 ef 21 c4 01 6e 00 00 00 00 00
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+01 02 20 00 29 01 28 2e 20 04 80 00 00 00 00 00
+01 02 00 00 e5 10 c0 2f 00 00 00 00 00 00 00 00
+01 02 00 00 a5 00 c0 2f e0 04 00 00 00 00 00 00
+01 02 00 00 28 01 02 26 3c 00 00 00 00 00 00 00
+01 00 60 00 a1 00 40 22 40 00 8d 00 00 00 00 00
+01 00 60 00 a5 00 80 2f 00 01 8d 00 00 00 00 00
+01 02 00 00 fd 73 00 24 00 00 00 00 00 00 80 3e
+01 00 80 00 a1 00 80 21 00 05 8d 00 00 00 00 00
+01 00 80 00 a5 00 00 2f 00 06 8d 00 00 00 00 00
+01 05 60 00 e5 10 81 2e 00 00 00 00 fa 7e 2a 3f
+01 0d 60 00 e5 10 82 2e 00 00 00 00 00 80 26 44
+01 09 60 00 e5 10 a2 2e 00 00 00 00 cd cc cc be
+01 02 60 00 21 00 e0 20 00 00 8d 00 00 00 00 00
+01 12 60 00 21 00 a0 22 00 00 8d 00 00 00 00 00
+01 10 60 00 bd 03 e0 22 c0 00 00 00 00 00 00 00
+01 12 00 00 61 00 a8 22 00 00 00 00 f2 03 00 00
+01 09 60 00 a5 00 02 21 85 00 05 00 00 00 00 00
+01 01 60 00 85 00 a7 22 04 04 6e 00 00 00 00 00
+01 05 60 00 bd 00 81 2e 20 41 60 00 00 00 00 00
+01 09 60 00 61 00 62 2e 00 00 00 00 00 00 00 00
+01 00 60 00 21 00 e0 20 04 00 00 00 00 00 00 00
+01 00 60 80 bd 03 80 2f 40 00 00 00 00 00 00 00
+01 00 80 80 bd 03 00 2f 40 00 00 00 00 00 00 00
+01 01 60 00 a5 03 61 22 40 02 60 00 00 00 00 00
+01 03 60 00 e5 10 0f 21 00 00 00 00 00 00 80 3f
+01 00 60 00 3d 00 c0 20 40 00 8d 00 00 00 00 00
+01 00 80 00 3d 00 40 20 40 02 8d 00 00 00 00 00
+01 09 60 00 fd 10 68 2e 00 00 00 00 00 00 00 00
+01 01 67 00 e5 10 41 28 00 00 00 00 ff ff ff ff
+01 05 60 80 fd 73 81 2e 00 00 00 00 00 00 80 3f
+01 0d 60 80 fd 73 82 2e 00 00 00 00 66 66 66 3f
+01 09 60 80 fd 73 88 2e 00 00 00 00 33 33 33 3f
+01 01 60 00 e5 52 6e 22 00 00 00 00 00 30 40 48
+01 02 80 00 21 00 a0 21 00 00 8d 00 00 00 00 00
+01 02 00 00 20 00 20 26 3c 00 00 00 00 00 00 00
+01 0d 60 00 bd 00 82 2e 00 07 60 00 00 00 00 00
+01 09 60 00 bd 00 88 2e 40 07 60 00 00 00 00 00
+01 05 60 00 fd 52 6c 2e 00 00 00 00 00 00 00 30
+01 00 60 02 bd 03 80 20 40 60 00 00 00 00 00 00
+01 00 61 00 bd 03 80 20 c0 42 00 00 00 00 00 00
+01 00 80 02 bd 03 80 20 40 60 00 00 00 00 00 00
+01 00 81 00 bd 03 80 20 e0 44 00 00 00 00 00 00
+01 02 60 00 e1 10 60 21 00 00 00 00 00 00 00 00
+01 02 00 00 e1 10 7c 21 00 00 00 00 ff ff 00 00
+01 12 60 00 e1 10 60 21 00 00 00 00 00 00 00 00
+01 10 60 00 a5 00 80 21 20 03 8d 00 00 00 00 00
+01 12 00 00 e1 10 7c 21 00 00 00 00 ff ff 00 00
+01 12 00 00 21 00 fc 20 3c 00 00 00 00 00 00 00
+01 0d 60 00 a5 00 83 2e 84 00 65 00 00 00 00 00
+01 09 60 00 bd 03 61 20 00 42 60 00 00 00 00 00
+01 01 60 00 61 00 e1 20 00 00 00 00 00 00 00 00
+01 03 60 00 e1 10 81 22 00 00 00 00 00 00 00 00
+01 01 60 00 a1 00 61 22 60 01 60 00 00 00 00 00
+01 03 40 02 3c 00 0f 20 c0 01 60 04 00 00 00 00
+01 01 60 00 a1 03 01 21 20 00 00 00 00 00 00 00
+01 00 60 00 a1 03 20 21 e0 00 8d 00 00 00 00 00
+01 00 60 00 21 01 60 21 20 01 ae 00 00 00 00 00
+01 00 80 00 a1 03 e0 21 60 01 8d 00 00 00 00 00
+01 00 80 00 21 01 60 22 e0 01 ae 00 00 00 00 00
+01 03 60 00 61 00 81 20 00 00 00 00 00 00 00 00
+01 01 60 01 64 00 01 20 00 00 00 00 00 00 00 00
+01 00 60 00 65 00 e0 20 00 00 00 00 00 00 00 00
+01 00 60 00 25 00 20 21 a0 00 8d 00 00 00 00 00
+01 00 80 00 65 00 60 29 00 00 00 00 00 00 00 00
+01 00 80 00 25 00 e0 29 20 02 8d 00 00 00 00 00
+01 05 60 00 bd 03 87 2e 74 00 0a 00 00 00 00 00
+01 09 60 80 bd 03 88 2e 8f 02 6f 00 00 00 00 00
+01 02 00 00 60 00 20 26 00 00 00 00 00 00 00 00
+01 00 60 01 68 21 00 20 00 00 00 04 00 00 00 00
+01 00 80 01 68 21 00 20 00 00 00 04 00 00 00 00
+01 05 60 00 3d 00 67 20 34 00 0a 00 00 00 00 00
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+01 01 40 00 39 03 81 20 44 00 04 00 00 00 00 00
+01 01 60 00 39 03 a1 20 44 00 04 00 00 00 00 00
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+01 03 60 00 bd 83 2f 21 e4 00 6e 00 00 00 00 00
+01 00 40 00 21 00 c0 40 4c 00 00 00 00 00 00 00
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+01 00 60 00 3d 03 c0 41 c0 00 69 00 00 00 00 00
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+01 10 40 00 a5 80 20 41 ac 00 00 00 00 00 00 00
+01 10 60 00 3d 03 80 40 00 01 69 00 00 00 00 00
+01 10 60 00 21 00 20 2f 80 00 8a 00 00 00 00 00
+01 01 60 80 fd 73 8f 2e 00 00 00 00 00 00 80 3f
+01 05 60 00 e1 10 41 20 00 00 00 00 02 00 00 00
+01 09 60 00 e1 10 4e 20 00 00 00 00 00 00 00 00
+01 02 60 00 fd 73 a0 20 00 00 00 00 00 00 00 00
+01 02 80 00 61 00 80 20 00 00 00 00 00 00 00 00
+01 10 60 00 e5 10 60 21 00 00 00 00 00 00 00 00
+01 00 60 00 61 00 00 21 00 00 00 00 06 00 00 00
+01 00 80 00 61 00 40 21 00 00 00 00 06 00 00 00
+01 03 60 00 bd 03 4f 22 64 02 6e 00 00 00 00 00
+01 02 60 00 61 80 20 23 00 00 00 00 00 00 00 00
+01 02 00 00 61 80 34 23 00 00 00 00 00 ff 00 00
+01 02 20 00 21 80 20 23 00 00 00 00 00 00 00 00
+01 01 60 80 bd 00 8f 2e c4 40 6e 00 00 00 00 00
+01 09 60 00 e5 52 ec 2e 00 00 00 00 00 00 6e 70
+01 05 60 80 bd 00 87 2e 64 41 6a 00 00 00 00 00
+01 09 60 00 fd 73 81 2e 00 00 00 00 00 00 80 3e
+01 02 00 00 01 01 5c 23 02 06 00 00 00 00 00 00
+01 12 00 00 01 01 5c 20 02 06 00 00 00 00 00 00
+01 03 40 00 61 00 21 28 00 00 00 00 01 00 00 00
+01 01 40 00 61 00 21 28 00 00 00 00 00 00 00 00
+01 00 60 00 21 02 c0 21 a0 01 cf 00 00 00 00 00
+01 00 80 00 21 02 c0 22 80 02 cf 00 00 00 00 00
+01 10 60 00 fd 73 80 25 00 00 00 00 e0 ff ff ff
+01 00 60 00 bd 02 a0 20 40 00 00 00 00 00 00 00
+01 00 80 00 bd 02 c0 20 40 00 00 00 00 00 00 00
+01 05 60 00 61 00 81 20 00 00 00 00 20 00 00 00
+01 0d 60 00 fd 52 8c 2e 00 00 00 00 00 00 00 30
+01 00 80 00 21 00 a0 20 40 00 00 00 00 00 00 00
+01 02 00 00 08 01 20 26 02 06 00 00 00 00 00 00
+01 05 60 80 bd 03 81 2e 80 00 60 00 00 00 00 00
+01 0d 60 80 bd 03 86 2e a0 00 65 00 00 00 00 00
+01 01 60 00 fd 10 2c 21 00 00 00 00 00 00 00 00
+01 01 60 00 e1 10 6e 20 00 00 00 00 00 00 00 00
+01 00 60 00 e1 10 a0 20 00 00 00 00 80 ea 0f 00
+01 00 60 00 a9 03 40 42 20 01 8d 00 00 00 00 00
+01 00 60 00 29 01 60 20 40 02 ae 00 00 00 00 00
+01 02 60 00 29 01 80 21 00 01 ae 00 00 00 00 00
+01 00 80 00 e1 10 e0 21 00 00 00 00 80 ea 0f 00
+01 00 80 00 a9 03 a0 42 20 02 8d 00 00 00 00 00
+01 02 80 00 29 01 80 20 a0 01 ae 00 00 00 00 00
+01 05 60 00 fd 73 81 20 00 00 00 00 00 00 10 42
+01 01 60 00 e1 52 6f 21 00 00 00 00 00 60 70 78
+01 00 60 00 3d 02 a0 21 80 01 60 00 00 00 00 00
+01 00 80 00 3d 02 c0 20 40 00 00 00 00 00 00 00
+01 01 60 01 a4 00 01 20 24 00 6e 00 00 00 00 00
+01 00 60 00 e1 73 20 21 00 00 00 00 00 00 00 00
+01 00 80 00 e1 73 40 21 00 00 00 00 00 00 00 00
+01 0d 60 80 bd 00 82 2e 60 41 60 00 00 00 00 00
+01 09 60 80 bd 00 88 2e a0 41 60 00 00 00 00 00
+01 00 60 00 a5 01 40 20 c0 01 ae 00 00 00 00 00
+01 00 80 00 a5 01 20 25 80 02 ae 00 00 00 00 00
+01 00 60 00 a5 02 40 20 c0 01 cf 00 00 00 00 00
+01 00 80 00 a5 02 20 25 80 02 cf 00 00 00 00 00
+01 00 60 00 bd 01 40 20 c0 01 ae 00 00 00 00 00
+01 00 80 00 bd 01 60 25 80 00 ae 00 00 00 00 00
+01 04 40 00 31 02 00 21 a0 01 60 00 00 00 00 00
+01 08 40 00 31 02 10 21 b0 01 60 00 00 00 00 00
+01 01 60 02 bd 03 6f 21 24 60 0e 00 00 00 00 00
+01 01 61 00 fd 73 6f 21 00 00 00 00 00 00 80 bf

diff --git a/src/intel/tools/tests/gen7.5/mul.asm b/src/intel/tools/tests/gen7.5/mul.asm
new file mode 100644 (file)
index 0000000..560a9c0
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/mul.asm
@@ -0,0 +1,55 @@
+mul(8)          g45<1>.xF       g5.4<0>.zF      g5.4<0>.zF      { align16 1Q };
+mul(8)          g18<1>F         g17<4>F         0x3f000000F  /* 0.5F */ { align16 1Q };
+mul(8)          g39<1>.xD       g5<0>.xD        2D              { align16 1Q };
+mul(8)          g7<1>F          g39<8,8,1>F     g4.1<0,1,0>F    { align1 1Q };
+mul(16)         g19<1>F         g37<8,8,1>F     g6.1<0,1,0>F    { align1 1H };
+mul(8)          acc0<1>UD       g17<8,8,1>UD    0xaaaaaaabUD    { align1 1Q };
+mul(8)          acc0<1>D        g17<8,8,1>D     1431655766D     { align1 1Q };
+mul(8)          g21<1>D         g20<8,8,1>D     3W              { align1 1Q };
+mul(8)          g7<1>F          g5<8,8,1>F      0x3e800000F  /* 0.25F */ { align1 1Q };
+mul(8)          acc0<1>UD       g84<8,8,1>UD    0xaaaaaaabUD    { align1 2Q };
+mul(16)         g90<1>D         g88<8,8,1>D     3W              { align1 1H };
+mul(8)          acc0<1>D        g84<8,8,1>D     1431655766D     { align1 2Q };
+mul(16)         g74<1>F         g37<8,8,1>F     0x3e800000F  /* 0.25F */ { align1 1H };
+mul(8)          acc0<1>D        g1<0>.xyzzD     g1<0>.wD        { align16 1Q };
+mul(2)          g113.3<1>UD     g12<8,2,4>UD    0x0001UW        { align1 WE_all 1N };
+mul.sat(8)      g19<1>.xyzF     g15<4>.xyzzF    g18<4>.xF       { align16 1Q };
+mul(8)          g116<1>.xyF     g6<4>.xyyyF     0x3f000000F  /* 0.5F */ { align16 NoDDClr 1Q };
+mul.sat(8)      g2<1>F          g6<8,8,1>F      g5<8,8,1>F      { align1 1Q };
+mul.sat(16)     g2<1>F          g12<8,8,1>F     g10<8,8,1>F     { align1 1H };
+mul(8)          g29<1>F         g28<4>.yF       0x3000VF /* [0F, 1F, 0F, 0F]VF */ { align16 1Q };
+mul.l.f0.0(8)   null<1>.xF      g6<0>.xF        g5.4<0>.wF      { align16 1Q };
+mul(8)          acc0<1>UD       g9<4>UD         g11<4>UD        { align16 1Q };
+mul(8)          acc0<1>UD       g4<8,8,1>UD     g8<8,8,1>UD     { align1 1Q };
+mul(8)          acc0<1>UD       g5<8,8,1>UD     g13<8,8,1>UD    { align1 2Q };
+mul(8)          g3<1>D          g2<0,1,0>D      g2.4<0,1,0>UW   { align1 1Q };
+mul(16)         g3<1>D          g2<0,1,0>D      g2.4<0,1,0>UW   { align1 1H };
+mul(8)          g116<1>.xyF     g7<4>.xyyyF     0x3f000000F  /* 0.5F */ { align16 NoDDChk 1Q };
+mul(8)          g115<1>.xyzF    g2<4>.xyzzF     g10<4>.xF       { align16 NoDDClr 1Q };
+mul(8)          g115<1>.xF      g15<4>.xF       0x40a66666F  /* 5.2F */ { align16 NoDDClr,NoDDChk 1Q };
+mul(1)          g6<1>UD         g12<0,1,0>UD    0x0101UW        { align1 WE_all 1N };
+mul(8)          acc0<1>UD       g5<4>.xUD       0xaaaaaaabUD    { align16 1Q };
+mul(8)          acc0<1>D        g5<4>.xD        1431655766D     { align16 1Q };
+mul.sat(8)      g116<1>F        g6<4>F          0x3b800000F  /* 0.00390625F */ { align16 1Q };
+mul(8)          acc0<1>D        g5<8,8,1>D      g9<8,8,1>D      { align1 1Q };
+mul(8)          acc0<1>D        g6<8,8,1>D      g14<8,8,1>D     { align1 2Q };
+mul(8)          g3<1>D          g2<0,1,0>D      0x77b9UW        { align1 1Q };
+mul(16)         g3<1>D          g2<0,1,0>D      0x77b9UW        { align1 1H };
+mul(8)          g37<1>.xD       g6<4>.xD        g14<4>.xD       { align16 1Q };
+mul.l.f0.0(8)   null<1>F        g2.2<0,1,0>F    g2.1<0,1,0>F    { align1 1Q };
+mul.l.f0.0(16)  null<1>F        g2.2<0,1,0>F    g2.1<0,1,0>F    { align1 1H };
+mul(8)          g6<1>UW         g6<8,8,1>UW     0x0808UW        { align1 1Q };
+mul(16)         g15<1>UW        g14<16,16,1>UW  0x0808UW        { align1 1H };
+mul.sat(8)      g11<1>F         g17<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
+mul.sat(16)     g21<1>F         g17<8,8,1>F     0x40800000F  /* 4F */ { align1 1H };
+mul.nz.f0.0(8)  g6<1>F          g12<8,8,1>F     0x3f808000F  /* 1.00391F */ { align1 1Q };
+mul.nz.f0.0(16) g9<1>F          g7<8,8,1>F      0x3f808000F  /* 1.00391F */ { align1 1H };
+mul.sat(8)      g116<1>.xyF     g1<0>.wzzzF     g3<4>.wzzzF     { align16 NoDDClr 1Q };
+mul.sat(8)      g116<1>.zwF     g1<0>.yyyxF     g3<4>.yyyxF     { align16 NoDDChk 1Q };
+mul(8)          g116<1>.xyzF    g3<4>.xyzzF     0x30302020VF /* [0.5F, 0.5F, 1F, 1F]VF */ { align16 NoDDClr 1Q };
+mul.sat(8)      g116<1>F        g6<4>F          0x20303030VF /* [1F, 1F, 1F, 0.5F]VF */ { align16 1Q };
+mul(8)          g3<1>.wF        g1<0>.zF        g9<4>.xF        { align16 NoDDClr,NoDDChk 1Q };
+mul(1)          g4<1>UD         g4<0,1,0>UD     0x0101UW        { align1 WE_all 3N };
+mul(8)          g117<1>.yF      g29<4>.xF       g9<4>.xF        { align16 NoDDChk 1Q };
+mul.sat(8)      g116<1>.xF      g19<4>.xF       0x3dcccccdF  /* 0.1F */ { align16 NoDDClr 1Q };
+mul.sat(8)      g116<1>.xyzF    g12<4>.xF       0x3030VF /* [1F, 1F, 0F, 0F]VF */ { align16 NoDDClr 1Q };

diff --git a/src/intel/tools/tests/gen7.5/mul.expected b/src/intel/tools/tests/gen7.5/mul.expected
new file mode 100644 (file)
index 0000000..18093fa
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/mul.expected
@@ -0,0 +1,55 @@
+41 01 60 00 bd 77 a1 25 ba 00 0a 00 ba 00 0a 00
+41 01 60 00 bd 7f 4f 22 24 02 6e 00 00 00 00 3f
+41 01 60 00 a5 1c e1 24 a0 00 00 00 02 00 00 00
+41 00 60 00 bd 77 e0 20 e0 04 8d 00 84 00 00 00
+41 00 80 00 bd 77 60 22 a0 04 8d 00 c4 00 00 00
+41 00 60 00 20 0c 00 24 20 02 8d 00 ab aa aa aa
+41 00 60 00 a4 1c 00 24 20 02 8d 00 56 55 55 55
+41 00 60 00 a5 3c a0 22 80 02 8d 00 03 00 03 00
+41 00 60 00 bd 7f e0 20 a0 00 8d 00 00 00 80 3e
+41 10 60 00 20 0c 00 24 80 0a 8d 00 ab aa aa aa
+41 00 80 00 a5 3c 40 2b 00 0b 8d 00 03 00 03 00
+41 10 60 00 a4 1c 00 24 80 0a 8d 00 56 55 55 55
+41 00 80 00 bd 7f 40 29 a0 04 8d 00 00 00 80 3e
+41 01 60 00 a4 14 0f 24 24 00 0a 00 2f 00 0f 00
+41 02 20 00 21 2c 2c 2e 80 01 87 00 01 00 01 00
+41 01 60 80 bd 77 67 22 e4 01 6a 00 40 02 60 00
+41 05 60 00 bd 7f 83 2e c4 00 65 00 00 00 00 3f
+41 00 60 80 bd 77 40 20 c0 00 8d 00 a0 00 8d 00
+41 00 80 80 bd 77 40 20 80 01 8d 00 40 01 8d 00
+41 01 60 00 bd 5f af 23 85 03 65 00 00 30 00 00
+41 01 60 05 bc 77 01 20 c0 00 00 00 bf 00 0f 00
+41 01 60 00 20 04 0f 24 24 01 6e 00 64 01 6e 00
+41 00 60 00 20 04 00 24 80 00 8d 00 00 01 8d 00
+41 10 60 00 20 04 00 24 a0 00 8d 00 a0 01 8d 00
+41 00 60 00 a5 24 60 20 40 00 00 00 48 00 00 00
+41 00 80 00 a5 24 60 20 40 00 00 00 48 00 00 00
+41 09 60 00 bd 7f 83 2e e4 00 65 00 00 00 00 3f
+41 05 60 00 bd 77 67 2e 44 00 6a 00 40 01 60 00
+41 0d 60 00 bd 7f 61 2e e0 01 60 00 66 66 a6 40
+41 02 00 00 21 2c c0 20 80 01 00 00 01 01 01 01
+41 01 60 00 20 0c 0f 24 a0 00 60 00 ab aa aa aa
+41 01 60 00 a4 1c 0f 24 a0 00 60 00 56 55 55 55
+41 01 60 80 bd 7f 8f 2e c4 00 6e 00 00 00 80 3b
+41 00 60 00 a4 14 00 24 a0 00 8d 00 20 01 8d 00
+41 10 60 00 a4 14 00 24 c0 00 8d 00 c0 01 8d 00
+41 00 60 00 a5 2c 60 20 40 00 00 00 b9 77 b9 77
+41 00 80 00 a5 2c 60 20 40 00 00 00 b9 77 b9 77
+41 01 60 00 a5 14 a1 24 c0 00 60 00 c0 01 60 00
+41 00 60 05 bc 77 00 20 48 00 00 00 44 00 00 00
+41 00 80 05 bc 77 00 20 48 00 00 00 44 00 00 00
+41 00 60 00 29 2d c0 20 c0 00 8d 00 08 08 08 08
+41 00 80 00 29 2d e0 21 c0 01 b1 00 08 08 08 08
+41 00 60 80 bd 7f 60 21 20 02 8d 00 00 00 80 40
+41 00 80 80 bd 7f a0 22 20 02 8d 00 00 00 80 40
+41 00 60 02 bd 7f c0 20 80 01 8d 00 00 80 80 3f
+41 00 80 02 bd 7f 20 21 e0 00 8d 00 00 80 80 3f
+41 05 60 80 bd 77 83 2e 2b 00 0a 00 6b 00 6a 00
+41 09 60 80 bd 77 8c 2e 25 00 01 00 65 00 61 00
+41 05 60 00 bd 5f 87 2e 64 00 6a 00 20 20 30 30
+41 01 60 80 bd 5f 8f 2e c4 00 6e 00 30 30 30 20
+41 0d 60 00 bd 77 68 20 2a 00 0a 00 20 01 60 00
+41 12 00 00 21 2c 80 20 80 00 00 00 01 01 01 01
+41 09 60 00 bd 77 a2 2e a0 03 60 00 20 01 60 00
+41 05 60 80 bd 7f 81 2e 60 02 60 00 cd cc cc 3d
+41 05 60 80 bd 5f 87 2e 80 01 60 00 30 30 00 00

diff --git a/src/intel/tools/tests/gen7.5/not.asm b/src/intel/tools/tests/gen7.5/not.asm
new file mode 100644 (file)
index 0000000..c93eb1a
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/not.asm
@@ -0,0 +1,4 @@
+not(8)          g3<1>D          g2.2<0,1,0>D                    { align1 1Q };
+not(16)         g3<1>D          g2.2<0,1,0>D                    { align1 1H };
+not(8)          g10<1>D         (abs)g1.4<0>D                   { align16 1Q };
+not.nz.f0.0(8)  null<1>.xD      g13<4>.xD                       { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/not.expected b/src/intel/tools/tests/gen7.5/not.expected
new file mode 100644 (file)
index 0000000..0df6966
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/not.expected
@@ -0,0 +1,4 @@
+04 00 60 00 a5 00 60 20 48 00 00 00 00 00 00 00
+04 00 80 00 a5 00 60 20 48 00 00 00 00 00 00 00
+04 01 60 00 a5 00 4f 21 34 20 0e 00 00 00 00 00
+04 01 60 02 a4 00 01 20 a0 01 60 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/or.asm b/src/intel/tools/tests/gen7.5/or.asm
new file mode 100644 (file)
index 0000000..9f7ea86
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/or.asm
@@ -0,0 +1,22 @@
+or(1)           g113.5<1>UD     g0.5<0,1,0>UD   0x0000ff00UD    { align1 WE_all 1N };
+or.nz.f0.0(8)   null<1>.xUD     g21<4>.xUD      g19<4>.xUD      { align16 1Q };
+or(8)           g13<1>.xyUD     g5.4<0>.zwwwUD  g6<0>.xUD       { align16 1Q };
+or.nz.f0.0(8)   null<1>UD       g12<8,8,1>UD    g6<8,8,1>UD     { align1 1Q };
+or.nz.f0.0(16)  null<1>UD       g4<8,8,1>UD     g2<8,8,1>UD     { align1 1H };
+or(8)           g20<1>UD        g19<8,8,1>UD    g17<8,8,1>UD    { align1 1Q };
+or(16)          g30<1>UD        g28<8,8,1>UD    g24<8,8,1>UD    { align1 1H };
+or(1)           g2<1>UD         g2<0,1,0>UD     g4<0,1,0>UD     { align1 WE_all 1N };
+or(1)           a0<1>UD         g2<0,1,0>UD     0x064a7000UD    { align1 WE_all 1N };
+(+f0.0) or(8)   g3<1>UD         g3<8,8,1>UD     0x3f800000UD    { align1 1Q };
+(+f0.0) or(16)  g3<1>UD         g3<8,8,1>UD     0x3f800000UD    { align1 1H };
+(+f0.0) or(8)   g64<1>.xyzUD    g64<4>.xyzzUD   0x3f800000UD    { align16 1Q };
+or(1)           a0<1>UD         a0<0,1,0>UD     g15<0,1,0>UD    { align1 WE_all 1N };
+or(1)           a0<1>UD         a0<0,1,0>UD     0x06182000UD    { align1 WE_all 1N };
+or.nz.f0.0(8)   g8<1>UD         g4<8,8,1>UD     g7<8,8,1>UD     { align1 1Q };
+or.nz.f0.0(16)  g12<1>UD        g5<8,8,1>UD     g10<8,8,1>UD    { align1 1H };
+or(8)           g13<1>UD        g12<8,8,1>UD    0x00000001UD    { align1 1Q };
+or(16)          g20<1>UD        g18<8,8,1>UD    0x00000001UD    { align1 1H };
+or(1)           a0<1>UD         g2<0,1,0>UD     0x0e0b6000UD    { align1 WE_all 3N };
+or(1)           g113.21<1>UB    g16<0,1,0>UB    g16.16<0,1,0>UB { align1 WE_all 1N };
+or(8)           g4<1>UW         g4<8,8,1>UW     g6<8,8,1>UW     { align1 1Q };
+or(16)          g16<1>UW        g14<16,16,1>UW  g15<16,16,1>UW  { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/or.expected b/src/intel/tools/tests/gen7.5/or.expected
new file mode 100644 (file)
index 0000000..2d77bf6
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/or.expected
@@ -0,0 +1,22 @@
+06 02 00 00 21 0c 34 2e 14 00 00 00 00 ff 00 00
+06 01 60 02 20 04 01 20 a0 02 60 00 60 02 60 00
+06 01 60 00 21 04 a3 21 be 00 0f 00 c0 00 00 00
+06 00 60 02 20 04 00 20 80 01 8d 00 c0 00 8d 00
+06 00 80 02 20 04 00 20 80 00 8d 00 40 00 8d 00
+06 00 60 00 21 04 80 22 60 02 8d 00 20 02 8d 00
+06 00 80 00 21 04 c0 23 80 03 8d 00 00 03 8d 00
+06 02 00 00 21 04 40 20 40 00 00 00 80 00 00 00
+06 02 00 00 20 0c 00 22 40 00 00 00 00 70 4a 06
+06 00 61 00 21 0c 60 20 60 00 8d 00 00 00 80 3f
+06 00 81 00 21 0c 60 20 60 00 8d 00 00 00 80 3f
+06 01 61 00 21 0c 07 28 04 08 6a 00 00 00 80 3f
+06 02 00 00 00 04 00 22 00 02 00 00 e0 01 00 00
+06 02 00 00 00 0c 00 22 00 02 00 00 00 20 18 06
+06 00 60 02 21 04 00 21 80 00 8d 00 e0 00 8d 00
+06 00 80 02 21 04 80 21 a0 00 8d 00 40 01 8d 00
+06 00 60 00 21 0c a0 21 80 01 8d 00 01 00 00 00
+06 00 80 00 21 0c 80 22 40 02 8d 00 01 00 00 00
+06 12 00 00 20 0c 00 22 40 00 00 00 00 60 0b 0e
+06 02 00 00 31 46 35 2e 00 02 00 00 10 02 00 00
+06 00 60 00 29 25 80 20 80 00 8d 00 c0 00 8d 00
+06 00 80 00 29 25 00 22 c0 01 b1 00 e0 01 b1 00

diff --git a/src/intel/tools/tests/gen7.5/pln.asm b/src/intel/tools/tests/gen7.5/pln.asm
new file mode 100644 (file)
index 0000000..5b0adcf
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/pln.asm
@@ -0,0 +1,10 @@
+pln(8)          g124<1>F        g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln(16)         g120<1>F        g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.sat(8)      g9<1>F          g5<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.sat(16)     g12<1>F         g7<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.g.f0.0(8)   g7<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.g.f0.0(16)  g11<1>F         g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.l.f0.0(8)   g8<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.l.f0.0(16)  g11<1>F         g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.nz.f0.0(8)  g18<1>F         g5<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.nz.f0.0(16) g14<1>F         g7<0,1,0>F      g2<8,8,1>F      { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/pln.expected b/src/intel/tools/tests/gen7.5/pln.expected
new file mode 100644 (file)
index 0000000..471b1c9
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/pln.expected
@@ -0,0 +1,10 @@
+5a 00 60 00 bd 77 80 2f 80 00 00 00 40 00 8d 00
+5a 00 80 00 bd 77 00 2f c0 00 00 00 40 00 8d 00
+5a 00 60 80 bd 77 20 21 a0 00 00 00 40 00 8d 00
+5a 00 80 80 bd 77 80 21 e0 00 00 00 40 00 8d 00
+5a 00 60 03 bd 77 e0 20 80 00 00 00 40 00 8d 00
+5a 00 80 03 bd 77 60 21 c0 00 00 00 40 00 8d 00
+5a 00 60 05 bd 77 00 21 80 00 00 00 40 00 8d 00
+5a 00 80 05 bd 77 60 21 c0 00 00 00 40 00 8d 00
+5a 00 60 02 bd 77 40 22 a0 00 00 00 40 00 8d 00
+5a 00 80 02 bd 77 c0 21 e0 00 00 00 40 00 8d 00

diff --git a/src/intel/tools/tests/gen7.5/rndd.asm b/src/intel/tools/tests/gen7.5/rndd.asm
new file mode 100644 (file)
index 0000000..aa450ba
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/rndd.asm
@@ -0,0 +1,7 @@
+rndd(8)         g18<1>.xF       g1<0>.xF                        { align16 1Q };
+rndd(8)         g5<1>F          g4<8,8,1>F                      { align1 1Q };
+rndd(16)        g7<1>F          g5<8,8,1>F                      { align1 1H };
+rndd(8)         g6<1>.zF        g22<4>.xF                       { align16 NoDDClr 1Q };
+rndd.z.f0.0(8)  null<1>F        g17<8,8,1>F                     { align1 1Q };
+rndd.z.f0.0(16) null<1>F        g38<8,8,1>F                     { align1 1H };
+rndd.sat(8)     g116<1>F        g6<4>F                          { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/rndd.expected b/src/intel/tools/tests/gen7.5/rndd.expected
new file mode 100644 (file)
index 0000000..0444a6d
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/rndd.expected
@@ -0,0 +1,7 @@
+45 01 60 00 bd 03 41 22 20 00 00 00 00 00 00 00
+45 00 60 00 bd 03 a0 20 80 00 8d 00 00 00 00 00
+45 00 80 00 bd 03 e0 20 a0 00 8d 00 00 00 00 00
+45 05 60 00 bd 03 c4 20 c0 02 60 00 00 00 00 00
+45 00 60 01 bc 03 00 20 20 02 8d 00 00 00 00 00
+45 00 80 01 bc 03 00 20 c0 04 8d 00 00 00 00 00
+45 01 60 80 bd 03 8f 2e c4 00 6e 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/rnde.asm b/src/intel/tools/tests/gen7.5/rnde.asm
new file mode 100644 (file)
index 0000000..2a2fc14
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/rnde.asm
@@ -0,0 +1,3 @@
+rnde(8)         g7<1>F          g5<8,8,1>F                      { align1 1Q };
+rnde(16)        g11<1>F         g7<8,8,1>F                      { align1 1H };
+rnde(8)         g8<1>.xyzF      g1<0>.xyzzF                     { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/rnde.expected b/src/intel/tools/tests/gen7.5/rnde.expected
new file mode 100644 (file)
index 0000000..91b8b5a
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/rnde.expected
@@ -0,0 +1,3 @@
+46 00 60 00 bd 03 e0 20 a0 00 8d 00 00 00 00 00
+46 00 80 00 bd 03 60 21 e0 00 8d 00 00 00 00 00
+46 01 60 00 bd 03 07 21 24 00 0a 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/rndz.asm b/src/intel/tools/tests/gen7.5/rndz.asm
new file mode 100644 (file)
index 0000000..15d9b70
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/rndz.asm
@@ -0,0 +1,3 @@
+rndz(8)         g8<1>.xF        g1<0>.xF                        { align16 1Q };
+rndz(8)         g54<1>F         g43<8,8,1>F                     { align1 1Q };
+rndz(16)        g98<1>F         g95<8,8,1>F                     { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/rndz.expected b/src/intel/tools/tests/gen7.5/rndz.expected
new file mode 100644 (file)
index 0000000..120cdcb
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/rndz.expected
@@ -0,0 +1,3 @@
+47 01 60 00 bd 03 01 21 20 00 00 00 00 00 00 00
+47 00 60 00 bd 03 c0 26 60 05 8d 00 00 00 00 00
+47 00 80 00 bd 03 40 2c e0 0b 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/sel.asm b/src/intel/tools/tests/gen7.5/sel.asm
new file mode 100644 (file)
index 0000000..1c77a49
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/sel.asm
@@ -0,0 +1,63 @@
+(+f0.0) sel(8)  g47<1>UD        g12<4>UD        g13<4>UD        { align16 1Q };
+(-f0.0) sel(8)  g25<1>.xyUD     g13<4>.zwwwUD   0x40000000UD    { align16 1Q };
+(+f0.0.any4h) sel(8) g30<1>UD   g13<4>UD        g12<4>UD        { align16 1Q };
+(+f0.0.all4h) sel(8) g16<1>UD   g8<4>UD         g9<4>UD         { align16 1Q };
+(+f0.0) sel(8)  g23<1>UD        g8<8,8,1>UD     g23<8,8,1>UD    { align1 1Q };
+(+f0.0) sel(16) g42<1>UD        g76<8,8,1>UD    g78<8,8,1>UD    { align1 1H };
+sel.l(8)        g3<1>UD         g2.1<0,1,0>UD   0x00000001UD    { align1 1Q };
+sel.l(16)       g3<1>UD         g2.1<0,1,0>UD   0x00000001UD    { align1 1H };
+sel.ge(8)       g3<1>D          g2<0,1,0>D      -1D             { align1 1Q };
+sel.l(8)        g4<1>D          g3<8,8,1>D      1D              { align1 1Q };
+sel.ge(16)      g3<1>D          g2<0,1,0>D      -1D             { align1 1H };
+sel.l(16)       g5<1>D          g3<8,8,1>D      1D              { align1 1H };
+(+f0.0) sel(8)  g124<1>UD       g67<8,8,1>UD    0x3f800000UD    { align1 1Q };
+(+f0.0) sel(16) g120<1>UD       g27<8,8,1>UD    0x3f800000UD    { align1 1H };
+sel.ge(8)       g64<1>F         g9<8,8,1>F      0x0F  /* 0F */  { align1 1Q };
+(-f0.0) sel(8)  g16<1>UD        g20<8,8,1>UD    0x00000000UD    { align1 1Q };
+sel.ge(16)      g24<1>F         g20<8,8,1>F     0x0F  /* 0F */  { align1 1H };
+(-f0.0) sel(16) g28<1>UD        g26<8,8,1>UD    0x00000000UD    { align1 1H };
+(+f0.0) sel(8)  g8<1>.xyUD      g17<4>.xyyyUD   0x3f000000UD    { align16 1Q };
+sel.l(8)        g13<1>.xyzD     g6<0>.xyzzD     g5.4<0>.zD      { align16 1Q };
+sel.l(8)        g86<1>UD        g14<4>.xUD      0x0fffffffUD    { align16 1Q };
+sel.ge(8)       g3<1>.yF        g7<4>.xF        0x0F  /* 0F */  { align16 1Q };
+sel.l(8)        g11<1>.xF       g7<4>.wF        0x43000000F  /* 128F */ { align16 1Q };
+(-f0.0.z) sel(8) g3<1>.zUD      g14<4>.xUD      0x00000000UD    { align16 1Q };
+sel.l(8)        g14<1>UD        g6<0>UD         g6.4<0>UD       { align16 1Q };
+(+f0.0.x) sel(8) g32<1>.xUD     g12<4>.yUD      0x41a80000UD    { align16 1Q };
+(-f0.0.x) sel(8) g33<1>.xUD     g32<4>.xUD      0x41b80000UD    { align16 1Q };
+sel.ge(8)       g4<1>D          g2<0,1,0>D      g2.4<0,1,0>D    { align1 1Q };
+sel.l(8)        g8<1>D          g4<8,8,1>D      g3<0,1,0>D      { align1 1Q };
+sel.ge(16)      g4<1>D          g2<0,1,0>D      g2.4<0,1,0>D    { align1 1H };
+sel.l(16)       g12<1>D         g4<8,8,1>D      g3<0,1,0>D      { align1 1H };
+sel.ge(8)       g21<1>.xyD      g1<0>.xyyyD     g1<0>.zwwwD     { align16 1Q };
+(+f0.0.x) sel(8) g25<1>.xUD     g23<4>.yUD      g23<4>.xUD      { align16 1Q };
+sel.ge(8)       g22<1>UD        g1<0>UD         g1.4<0>.xUD     { align16 1Q };
+sel.l(8)        g3<1>UD         g2<0,1,0>UD     g2.1<0,1,0>UD   { align1 1Q };
+sel.l(16)       g3<1>UD         g2<0,1,0>UD     g2.1<0,1,0>UD   { align1 1H };
+sel.sat.l(8)    g116<1>F        g2<4>F          0x3f000000F  /* 0.5F */ { align16 1Q };
+(+f0.0) sel(8)  g37<1>.xyzF     (abs)g1.4<0>.xyzzF g1<0>.xyzzF  { align16 1Q };
+sel.l(8)        g68<1>.xyzF     g1<0>.xyzzF     g42<4>.xyzzF    { align16 1Q };
+(-f0.0) sel(8)  g47<1>.xyzF     (abs)g44<4>.xyzzF 0x3f800000F  /* 1F */ { align16 1Q };
+sel.ge(8)       g13<1>.xF       g1<0>.wF        g1<0>.zF        { align16 1Q };
+sel.ge(8)       g13<1>F         g12<8,8,1>F     (abs)g7<8,8,1>F { align1 1Q };
+sel.ge(16)      g29<1>F         g27<8,8,1>F     (abs)g17<8,8,1>F { align1 1H };
+(+f1.0) sel(4)  g15<1>.xUD      g13.4<4>.xUD    g13<4>.xUD      { align16 WE_all 1N };
+(-f0.0.any4h) sel(8) g67<1>.xUD g63<4>.xUD      0x00000000UD    { align16 1Q };
+sel.ge(8)       g4<1>UD         g2<0,1,0>UD     g2.3<0,1,0>UD   { align1 1Q };
+sel.ge(16)      g4<1>UD         g2<0,1,0>UD     g2.3<0,1,0>UD   { align1 1H };
+(+f0.0.x) sel(8) g17<1>.xF      g5.4<0>.zF      -g5.4<0>.zF     { align16 1Q };
+sel.l(8)        g124<1>F        g2.3<0,1,0>F    g2.2<0,1,0>F    { align1 1Q };
+sel.l(16)       g120<1>F        g2.3<0,1,0>F    g2.2<0,1,0>F    { align1 1H };
+(+f0.0.any4h) sel(8) g17<1>.xUD g8<4>.xUD       0x00000001UD    { align16 1Q };
+sel.ge(8)       g12<1>.xD       g5.4<0>.zD      -1D             { align16 1Q };
+sel.l(8)        g14<1>.xD       g12<4>.xD       1D              { align16 1Q };
+sel.sat.l(8)    g116<1>F        g1<0>F          g3<4>F          { align16 1Q };
+(-f0.0.x) sel(8) g44<1>.xF      (abs)g41<4>.xF  0x3f800000F  /* 1F */ { align16 1Q };
+sel.l(8)        g6<1>F          g3<8,8,1>F      0x40400000F  /* 3F */ { align1 1Q };
+sel.l(16)       g2<1>F          g20<8,8,1>F     0x40400000F  /* 3F */ { align1 1H };
+(+f0.0) sel(8)  g8<1>F          (abs)g40<8,8,1>F g6<8,8,1>F     { align1 1Q };
+(-f0.0) sel(8)  g15<1>F         (abs)g14<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
+(+f0.0) sel(16) g13<1>F         (abs)g72<8,8,1>F g58<8,8,1>F    { align1 1H };
+(-f0.0) sel(16) g27<1>F         (abs)g25<8,8,1>F 0x3f800000F  /* 1F */ { align1 1H };
+(-f0.0.y) sel(8) g3<1>.yUD      g10<4>.xUD      0x00000000UD    { align16 1Q };
+(+f0.0.y) sel(8) g3<1>.yUD      g1<0>.wUD       g1<0>.zUD       { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/sel.expected b/src/intel/tools/tests/gen7.5/sel.expected
new file mode 100644 (file)
index 0000000..12131bb
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/sel.expected
@@ -0,0 +1,63 @@
+02 01 61 00 21 04 ef 25 84 01 6e 00 a4 01 6e 00
+02 01 71 00 21 0c 23 23 ae 01 6f 00 00 00 00 40
+02 01 66 00 21 04 cf 23 a4 01 6e 00 84 01 6e 00
+02 01 67 00 21 04 0f 22 04 01 6e 00 24 01 6e 00
+02 00 61 00 21 04 e0 22 00 01 8d 00 e0 02 8d 00
+02 00 81 00 21 04 40 25 80 09 8d 00 c0 09 8d 00
+02 00 60 05 21 0c 60 20 44 00 00 00 01 00 00 00
+02 00 80 05 21 0c 60 20 44 00 00 00 01 00 00 00
+02 00 60 04 a5 1c 60 20 40 00 00 00 ff ff ff ff
+02 00 60 05 a5 1c 80 20 60 00 8d 00 01 00 00 00
+02 00 80 04 a5 1c 60 20 40 00 00 00 ff ff ff ff
+02 00 80 05 a5 1c a0 20 60 00 8d 00 01 00 00 00
+02 00 61 00 21 0c 80 2f 60 08 8d 00 00 00 80 3f
+02 00 81 00 21 0c 00 2f 60 03 8d 00 00 00 80 3f
+02 00 60 04 bd 7f 00 28 20 01 8d 00 00 00 00 00
+02 00 71 00 21 0c 00 22 80 02 8d 00 00 00 00 00
+02 00 80 04 bd 7f 00 23 80 02 8d 00 00 00 00 00
+02 00 91 00 21 0c 80 23 40 03 8d 00 00 00 00 00
+02 01 61 00 21 0c 03 21 24 02 65 00 00 00 00 3f
+02 01 60 05 a5 14 a7 21 c4 00 0a 00 ba 00 0a 00
+02 01 60 05 21 0c cf 2a c0 01 60 00 ff ff ff 0f
+02 01 60 04 bd 7f 62 20 e0 00 60 00 00 00 00 00
+02 01 60 05 bd 7f 61 21 ef 00 6f 00 00 00 00 43
+02 01 74 00 21 0c 64 20 c0 01 60 00 00 00 00 00
+02 01 60 05 21 04 cf 21 c4 00 0e 00 d4 00 0e 00
+02 01 62 00 21 0c 01 24 85 01 65 00 00 00 a8 41
+02 01 72 00 21 0c 21 24 00 04 60 00 00 00 b8 41
+02 00 60 04 a5 14 80 20 40 00 00 00 50 00 00 00
+02 00 60 05 a5 14 00 21 80 00 8d 00 60 00 00 00
+02 00 80 04 a5 14 80 20 40 00 00 00 50 00 00 00
+02 00 80 05 a5 14 80 21 80 00 8d 00 60 00 00 00
+02 01 60 04 a5 14 a3 22 24 00 05 00 2e 00 0f 00
+02 01 62 00 21 04 21 23 e5 02 65 00 e0 02 60 00
+02 01 60 04 21 04 cf 22 24 00 0e 00 30 00 00 00
+02 00 60 05 21 04 60 20 40 00 00 00 44 00 00 00
+02 00 80 05 21 04 60 20 40 00 00 00 44 00 00 00
+02 01 60 85 bd 7f 8f 2e 44 00 6e 00 00 00 00 3f
+02 01 61 00 bd 77 a7 24 34 20 0a 00 24 00 0a 00
+02 01 60 05 bd 77 87 28 24 00 0a 00 44 05 6a 00
+02 01 71 00 bd 7f e7 25 84 25 6a 00 00 00 80 3f
+02 01 60 04 bd 77 a1 21 2f 00 0f 00 2a 00 0a 00
+02 00 60 04 bd 77 a0 21 80 01 8d 00 e0 20 8d 00
+02 00 80 04 bd 77 a0 23 60 03 8d 00 20 22 8d 00
+02 03 41 00 21 04 e1 21 b0 01 60 04 a0 01 60 00
+02 01 76 00 21 0c 61 28 e0 07 60 00 00 00 00 00
+02 00 60 04 21 04 80 20 40 00 00 00 4c 00 00 00
+02 00 80 04 21 04 80 20 40 00 00 00 4c 00 00 00
+02 01 62 00 bd 77 21 22 ba 00 0a 00 ba 40 0a 00
+02 00 60 05 bd 77 80 2f 4c 00 00 00 48 00 00 00
+02 00 80 05 bd 77 00 2f 4c 00 00 00 48 00 00 00
+02 01 66 00 21 0c 21 22 00 01 60 00 01 00 00 00
+02 01 60 04 a5 1c 81 21 ba 00 0a 00 ff ff ff ff
+02 01 60 05 a5 1c c1 21 80 01 60 00 01 00 00 00
+02 01 60 85 bd 77 8f 2e 24 00 0e 00 64 00 6e 00
+02 01 72 00 bd 7f 81 25 20 25 60 00 00 00 80 3f
+02 00 60 05 bd 7f c0 20 60 00 8d 00 00 00 40 40
+02 00 80 05 bd 7f 40 20 80 02 8d 00 00 00 40 40
+02 00 61 00 bd 77 00 21 00 25 8d 00 c0 00 8d 00
+02 00 71 00 bd 7f e0 21 c0 21 8d 00 00 00 80 3f
+02 00 81 00 bd 77 a0 21 00 29 8d 00 40 07 8d 00
+02 00 91 00 bd 7f 60 23 20 23 8d 00 00 00 80 3f
+02 01 73 00 21 0c 62 20 40 01 60 00 00 00 00 00
+02 01 63 00 21 04 62 20 2f 00 0f 00 2a 00 0a 00

diff --git a/src/intel/tools/tests/gen7.5/send.asm b/src/intel/tools/tests/gen7.5/send.asm
new file mode 100644 (file)
index 0000000..f672d60
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/send.asm
@@ -0,0 +1,1504 @@
+send(8)         null<1>F        g113<4>F        0x8a08c000
+                            urb MsgDesc: 0 write HWord interleave complete mlen 5 rlen 0 { align16 1Q EOT };
+send(8)         null<1>F        g113<4>F        0x8608c000
+                            urb MsgDesc: 0 write HWord interleave complete mlen 3 rlen 0 { align16 1Q EOT };
+send(8)         g124<1>UW       g13<8,8,1>UD    0x08427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g10<8,8,1>UD    0x10847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g50<1>D         g51<4>UD        0x02194013
+                            urb MsgDesc: 2 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>F        g12<4>UD        0x04094019
+                            urb MsgDesc: 3 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g13<4>UD        0x04094011
+                            urb MsgDesc: 2 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g12<4>UD        0x04094009
+                            urb MsgDesc: 1 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g12<4>UD        0x04094001
+                            urb MsgDesc: 0 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         g14<1>D         g15<4>UD        0x0219400b
+                            urb MsgDesc: 1 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g13<1>D         g12<4>UD        0x02194003
+                            urb MsgDesc: 0 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>UW       g12<4,4,1>UD    0x02008004
+                            gateway MsgDesc: (barrier msg) mlen 1 rlen 0    { align1 WE_all 1Q };
+send(8)         null<1>F        g13<4>UD        0x0208c003
+                            urb MsgDesc: 0 read OWord interleave complete mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        g126<4>F        0x84080001
+                            urb MsgDesc: 0 write OWord mlen 2 rlen 0        { align16 1Q EOT };
+send(8)         g12<1>D         g114<4>F        0x02107000
+                            sampler MsgDesc: ld SIMD4x2 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x0a094000
+                            urb MsgDesc: 0 write HWord per-slot interleave mlen 5 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x82084000
+                            urb MsgDesc: 0 write HWord interleave mlen 1 rlen 0 { align16 1Q EOT };
+send(8)         g0<1>F          g125<4>F        0x060a80ff
+                            data MsgDesc: ( DC OWORD dual block write, 255, 0) mlen 3 rlen 0 { align16 1Q };
+send(8)         g41<1>F         g126<4>F        0x041880ff
+                            data MsgDesc: ( DC OWORD dual block read, 255, 0) mlen 2 rlen 1 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x8e08c000
+                            urb MsgDesc: 0 write HWord interleave complete mlen 7 rlen 0 { align16 1Q EOT };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x08840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x0643d001
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g8<1>UW         g16<8,8,1>UD    0x0c85d001
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g8<1>UW         g17<8,8,1>UD    0x0a43e001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g48<1>UW        g10<8,8,1>UD    0x1485e001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g11<8,8,1>UD    0x06420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g16<8,8,1>UD    0x0c840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x144a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g8<8,8,1>UD     a0<0,1,0>UD     0x00000200
+                            sampler MsgDesc: indirect                       { align1 1Q };
+send(8)         g124<1>UW       g8<8,8,1>UD     0x084a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x064a8002
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x0a8c8002
+                            sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x0a4a6001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g12<8,8,1>UD    0x0a4a6102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x128c6001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g20<8,8,1>UD    0x128c6102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 8 { align1 1H };
+send(8)         g10<1>D         g114<4>F        0x0411e000
+                            sampler MsgDesc: ld2dms SIMD4x2 Surface = 0 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         null<1>F        g9<4>UD         0x04094021
+                            urb MsgDesc: 4 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g9<4>UD         0x02088003
+                            urb MsgDesc: 0 read OWord complete mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x06094000
+                            urb MsgDesc: 0 write HWord per-slot interleave mlen 3 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x1a084000
+                            urb MsgDesc: 0 write HWord interleave mlen 13 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x8a08c030
+                            urb MsgDesc: 6 write HWord interleave complete mlen 5 rlen 0 { align16 1Q EOT };
+send(8)         g5<1>UW         g21<8,8,1>UD    0x02420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g26<8,8,1>UD    0x04840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g12<1>D         g114<4>F        0x0210a000
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g8<1>UW         g10<8,8,1>UD    0x0242a001
+                            sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x0c4b1002
+                            sampler MsgDesc: gather4_po SIMD8 Surface = 2 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(16)        g22<1>UW        g19<8,8,1>UD    0x0484a001
+                            sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(16)        g18<1>UW        g7<8,8,1>UD     0x168d1002
+                            sampler MsgDesc: gather4_po SIMD16 Surface = 2 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(8)         null<1>F        g9<4>UD         0x04094029
+                            urb MsgDesc: 5 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x084a8002
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g14<1>UW        g7<8,8,1>UD     0x0e8c8002
+                            sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g14<1>D         g114<4>F        0x06191001
+                            sampler MsgDesc: gather4_po SIMD4x2 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align16 1Q };
+send(8)         g3<1>D          g114<4>F        0x0210a101
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 1 Sampler = 1 mlen 1 rlen 1 { align16 1Q };
+send(8)         g5<1>D          g114<4>F        0x0210a202
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 2 Sampler = 2 mlen 1 rlen 1 { align16 1Q };
+send(8)         g7<1>D          g114<4>F        0x0210a303
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 3 Sampler = 3 mlen 1 rlen 1 { align16 1Q };
+send(8)         g9<1>D          g114<4>F        0x0210a404
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 4 Sampler = 4 mlen 1 rlen 1 { align16 1Q };
+send(8)         g11<1>D         g114<4>F        0x0210a505
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 5 Sampler = 5 mlen 1 rlen 1 { align16 1Q };
+send(8)         g13<1>D         g114<4>F        0x0210a606
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 6 Sampler = 6 mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>F        g54<4>UD        0x04094109
+                            urb MsgDesc: 33 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094111
+                            urb MsgDesc: 34 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094119
+                            urb MsgDesc: 35 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094121
+                            urb MsgDesc: 36 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094129
+                            urb MsgDesc: 37 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094131
+                            urb MsgDesc: 38 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094139
+                            urb MsgDesc: 39 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094141
+                            urb MsgDesc: 40 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094149
+                            urb MsgDesc: 41 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094151
+                            urb MsgDesc: 42 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094159
+                            urb MsgDesc: 43 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094161
+                            urb MsgDesc: 44 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094169
+                            urb MsgDesc: 45 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094171
+                            urb MsgDesc: 46 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094179
+                            urb MsgDesc: 47 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094181
+                            urb MsgDesc: 48 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094189
+                            urb MsgDesc: 49 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094191
+                            urb MsgDesc: 50 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x04094199
+                            urb MsgDesc: 51 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g53<4>UD        0x040941a1
+                            urb MsgDesc: 52 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g54<4>UD        0x040941a9
+                            urb MsgDesc: 53 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g55<4>UD        0x040941b1
+                            urb MsgDesc: 54 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g56<4>UD        0x040941b9
+                            urb MsgDesc: 55 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g59<4>UD        0x040941c1
+                            urb MsgDesc: 56 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g60<4>UD        0x040941c9
+                            urb MsgDesc: 57 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g61<4>UD        0x040941d1
+                            urb MsgDesc: 58 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g62<4>UD        0x040941d9
+                            urb MsgDesc: 59 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g63<4>UD        0x040941e1
+                            urb MsgDesc: 60 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g64<4>UD        0x040941e9
+                            urb MsgDesc: 61 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g65<4>UD        0x040941f1
+                            urb MsgDesc: 62 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g66<4>UD        0x040941f9
+                            urb MsgDesc: 63 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g71<4>UD        0x04094031
+                            urb MsgDesc: 6 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g72<4>UD        0x04094039
+                            urb MsgDesc: 7 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g73<4>UD        0x04094041
+                            urb MsgDesc: 8 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g74<4>UD        0x04094049
+                            urb MsgDesc: 9 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g75<4>UD        0x04094051
+                            urb MsgDesc: 10 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g76<4>UD        0x04094059
+                            urb MsgDesc: 11 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g77<4>UD        0x04094061
+                            urb MsgDesc: 12 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g78<4>UD        0x04094069
+                            urb MsgDesc: 13 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g79<4>UD        0x04094071
+                            urb MsgDesc: 14 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g80<4>UD        0x04094079
+                            urb MsgDesc: 15 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g81<4>UD        0x04094081
+                            urb MsgDesc: 16 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g82<4>UD        0x04094089
+                            urb MsgDesc: 17 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g83<4>UD        0x04094091
+                            urb MsgDesc: 18 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g84<4>UD        0x04094099
+                            urb MsgDesc: 19 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g85<4>UD        0x040940a1
+                            urb MsgDesc: 20 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g86<4>UD        0x040940a9
+                            urb MsgDesc: 21 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g87<4>UD        0x040940b1
+                            urb MsgDesc: 22 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g88<4>UD        0x040940b9
+                            urb MsgDesc: 23 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g89<4>UD        0x040940c1
+                            urb MsgDesc: 24 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g90<4>UD        0x040940c9
+                            urb MsgDesc: 25 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g91<4>UD        0x040940d1
+                            urb MsgDesc: 26 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g92<4>UD        0x040940d9
+                            urb MsgDesc: 27 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g93<4>UD        0x040940e1
+                            urb MsgDesc: 28 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g94<4>UD        0x040940e9
+                            urb MsgDesc: 29 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g95<4>UD        0x040940f1
+                            urb MsgDesc: 30 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g96<4>UD        0x040940f9
+                            urb MsgDesc: 31 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g8<4>UD         0x04094101
+                            urb MsgDesc: 32 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         g17<1>D         g16<4>UD        0x0219418b
+                            urb MsgDesc: 49 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g22<1>D         g21<4>UD        0x0219428b
+                            urb MsgDesc: 81 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g27<1>D         g26<4>UD        0x0219438b
+                            urb MsgDesc: 113 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g32<1>D         g31<4>UD        0x0219448b
+                            urb MsgDesc: 145 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g39<1>D         g38<4>UD        0x02194093
+                            urb MsgDesc: 18 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g42<1>D         g41<4>UD        0x0219410b
+                            urb MsgDesc: 33 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g47<1>D         g46<4>UD        0x0219420b
+                            urb MsgDesc: 65 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g52<1>D         g51<4>UD        0x0219430b
+                            urb MsgDesc: 97 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g57<1>D         g56<4>UD        0x0219440b
+                            urb MsgDesc: 129 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g71<1>D         g3<4>UD         0x02194103
+                            urb MsgDesc: 32 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g74<1>D         g3<4>UD         0x02194203
+                            urb MsgDesc: 64 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g77<1>D         g3<4>UD         0x02194303
+                            urb MsgDesc: 96 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g80<1>D         g3<4>UD         0x02194403
+                            urb MsgDesc: 128 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x9208c000
+                            urb MsgDesc: 0 write HWord interleave complete mlen 9 rlen 0 { align16 1Q EOT };
+send(8)         g5<1>UW         g3<8,8,1>UD     0x02427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g8<1>UW         g5<8,8,1>UD     0x04847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x1a084030
+                            urb MsgDesc: 6 write HWord interleave mlen 13 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x9608c060
+                            urb MsgDesc: 12 write HWord interleave complete mlen 11 rlen 0 { align16 1Q EOT };
+send(8)         g58<1>D         g59<4>UD        0x0219401b
+                            urb MsgDesc: 3 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g65<1>D         g66<4>UD        0x02194023
+                            urb MsgDesc: 4 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g72<1>D         g73<4>UD        0x0219402b
+                            urb MsgDesc: 5 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g79<1>D         g80<4>UD        0x02194033
+                            urb MsgDesc: 6 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g86<1>D         g87<4>UD        0x0219403b
+                            urb MsgDesc: 7 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g93<1>D         g94<4>UD        0x02194043
+                            urb MsgDesc: 8 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g100<1>D        g101<4>UD       0x0219404b
+                            urb MsgDesc: 9 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g107<1>D        g108<4>UD       0x02194053
+                            urb MsgDesc: 10 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g13<1>D         g14<4>UD        0x0219405b
+                            urb MsgDesc: 11 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g20<1>D         g21<4>UD        0x02194063
+                            urb MsgDesc: 12 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g27<1>D         g28<4>UD        0x0219406b
+                            urb MsgDesc: 13 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g34<1>D         g35<4>UD        0x02194073
+                            urb MsgDesc: 14 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g43<1>D         g47<4>UD        0x0219407b
+                            urb MsgDesc: 15 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g53<1>D         g54<4>UD        0x02194083
+                            urb MsgDesc: 16 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g60<1>D         g61<4>UD        0x0219408b
+                            urb MsgDesc: 17 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g74<1>D         g75<4>UD        0x0219409b
+                            urb MsgDesc: 19 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g81<1>D         g82<4>UD        0x021940a3
+                            urb MsgDesc: 20 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g88<1>D         g89<4>UD        0x021940ab
+                            urb MsgDesc: 21 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g95<1>D         g96<4>UD        0x021940b3
+                            urb MsgDesc: 22 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g102<1>D        g103<4>UD       0x021940bb
+                            urb MsgDesc: 23 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g110<4>UD       0x021940c3
+                            urb MsgDesc: 24 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g13<1>D         g14<4>UD        0x021940cb
+                            urb MsgDesc: 25 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g20<1>D         g21<4>UD        0x021940d3
+                            urb MsgDesc: 26 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g27<1>D         g28<4>UD        0x021940db
+                            urb MsgDesc: 27 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g34<1>D         g35<4>UD        0x021940e3
+                            urb MsgDesc: 28 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g43<1>D         g47<4>UD        0x021940eb
+                            urb MsgDesc: 29 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g53<1>D         g54<4>UD        0x021940f3
+                            urb MsgDesc: 30 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g60<1>D         g61<4>UD        0x021940fb
+                            urb MsgDesc: 31 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x02429001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x04849001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x0e434001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+(+f1.0) send(8) g12<1>UW        g2<8,8,1>UD     0x0410b201
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g2<8,8,1>UD     0x02009501
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 0 { align1 1Q };
+(+f1.0) send(16) g14<1>UW       g16<8,8,1>UD    0x0820a201
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) null<1>UW      g2<8,8,1>UD     0x04008501
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x08434001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g5<1>UW         g11<8,8,1>UD    0x06495001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 3 rlen 4 { align1 1Q };
+send(8)         null<1>UW       g14<8,8,1>UD    0x0e0b5002
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0x0) mlen 7 rlen 0 { align1 1Q };
+send(8)         g2<1>UW         g11<8,8,1>UD    0x06496001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 3 rlen 4 { align1 2Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x0e0b6002
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0x0) mlen 7 rlen 0 { align1 2Q };
+send(8)         null<1>F        g113<4>F        0x8608c030
+                            urb MsgDesc: 6 write HWord interleave complete mlen 3 rlen 0 { align16 1Q EOT };
+send(8)         g12<1>F         g114<4>F        0x06190001
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align16 1Q };
+send(8)         g7<1>UW         g0<8,8,1>UD     0x02200008
+                            pixel interp MsgDesc: (persp, per_message_offset, 0x08) mlen 1 rlen 2 { align1 1Q };
+send(16)        g9<1>UW         g0<8,8,1>UD     0x02410008
+                            pixel interp MsgDesc: (persp, per_message_offset, 0x08) mlen 1 rlen 4 { align1 1H };
+send(8)         g2<1>UW         g11<8,8,1>UD    0x0443d001
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g9<8,8,1>UD     0x0843e001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g15<8,8,1>UD    0x0885d001
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g43<1>UW        g11<8,8,1>UD    0x1085e001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g11<8,8,1>UD    0x0a4a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g19<8,8,1>UD    0x128c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x9608c000
+                            urb MsgDesc: 0 write HWord interleave complete mlen 11 rlen 0 { align16 1Q EOT };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x0a4a8002
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g16<1>UW        g7<8,8,1>UD     0x128c8002
+                            sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x06094008
+                            urb MsgDesc: 1 write HWord per-slot interleave mlen 3 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x04084001
+                            urb MsgDesc: 0 write OWord interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         g14<1>UD        g114<4>F        0x04188001
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         g16<1>.xD       g114<4>F        0x0218b000
+                            sampler MsgDesc: sampleinfo SIMD4x2 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x0a094008
+                            urb MsgDesc: 1 write HWord per-slot interleave mlen 5 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x16094000
+                            urb MsgDesc: 0 write HWord per-slot interleave mlen 11 rlen 0 { align16 1Q };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x08427005
+                            sampler MsgDesc: ld SIMD8 Surface = 5 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g10<8,8,1>UD    0x08427006
+                            sampler MsgDesc: ld SIMD8 Surface = 6 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g14<8,8,1>UD    0x08427007
+                            sampler MsgDesc: ld SIMD8 Surface = 7 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g18<8,8,1>UD    0x08427008
+                            sampler MsgDesc: ld SIMD8 Surface = 8 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g65<1>UW        g73<8,8,1>UD    0x10847005
+                            sampler MsgDesc: ld SIMD16 Surface = 5 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(16)        g32<1>UW        g81<8,8,1>UD    0x10847006
+                            sampler MsgDesc: ld SIMD16 Surface = 6 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(16)        g40<1>UW        g49<8,8,1>UD    0x10847007
+                            sampler MsgDesc: ld SIMD16 Surface = 7 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(16)        g48<1>UW        g57<8,8,1>UD    0x10847008
+                            sampler MsgDesc: ld SIMD16 Surface = 8 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x064a3001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g9<8,8,1>UD     0x064a3102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0a8c3001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0a8c3102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 5 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x04420102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06420304
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08840102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0c840304
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 6 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x04420304
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06420708
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08840304
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0c840708
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x06421001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x0c841001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        g4<1>UD         g13<8,8,1>UD    0x02280301
+                            const MsgDesc: (1, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x0a4b1002
+                            sampler MsgDesc: gather4_po SIMD8 Surface = 2 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g35<1>UW        g7<8,8,1>UD     0x128d1002
+                            sampler MsgDesc: gather4_po SIMD16 Surface = 2 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g12<8,8,1>UD    0x084b0002
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x0e8d0002
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 2 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g17<8,8,1>UD    0x0e434102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 7 rlen 4 { align1 1Q };
+send(8)         g4<1>D          g114<4>F        0x04188003
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 3 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         g5<1>D          g114<4>F        0x04188104
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 4 Sampler = 1 mlen 2 rlen 1 { align16 1Q };
+send(8)         g8<1>D          g114<4>F        0x04188205
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 5 Sampler = 2 mlen 2 rlen 1 { align16 1Q };
+send(8)         g124<1>UW       g4<8,8,1>UD     0x0c424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g5<8,8,1>UD     0x06427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0c847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g9<1>F          g114<4>F        0x04102000
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 0 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         g3<1>.xUW       g1<4>UD         0x0410eb00
+                            dp data 1 MsgDesc: ( DC untyped 4x2 atomic op, Surface = 0,  imin) mlen 2 rlen 1 { align16 1Q };
+send(8)         g5<1>UW         g4<8,8,1>UD     0x08495001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 4 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x08496001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 4 rlen 4 { align1 2Q };
+send(8)         g2<1>UW         g9<8,8,1>UD     0x08427002
+                            sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g14<8,8,1>UD    0x10847002
+                            sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x06423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x0c843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x1a094000
+                            urb MsgDesc: 0 write HWord per-slot interleave mlen 13 rlen 0 { align16 1Q };
+send(8)         g124<1>UW       g8<8,8,1>UD     0x08422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g10<8,8,1>UD    0x10842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g16<1>F         g17<4>.xUD      0x02107001
+                            sampler MsgDesc: ld SIMD4x2 Surface = 1 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         g9<8,8,1>UD     0x08423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g16<1>UW        g8<8,8,1>UD     0x10843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x08843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g4<1>UW         g0<8,8,1>UD     0x02201000
+                            pixel interp MsgDesc: (persp, sample_position, 0x00) mlen 1 rlen 2 { align1 1Q };
+send(16)        g6<1>UW         g0<8,8,1>UD     0x02411000
+                            pixel interp MsgDesc: (persp, sample_position, 0x00) mlen 1 rlen 4 { align1 1H };
+send(8)         g124<1>UW       g14<8,8,1>UD    0x0a4b0002
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x128d0002
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 2 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x06422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g14<8,8,1>UD    0x04429001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g14<1>UW        g8<8,8,1>UD     0x0c842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        g14<1>UW        g10<8,8,1>UD    0x08849001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x0e094000
+                            urb MsgDesc: 0 write HWord per-slot interleave mlen 7 rlen 0 { align16 1Q };
+send(8)         g36<1>D         g35<4>UD        0x0219419b
+                            urb MsgDesc: 51 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g41<1>D         g40<4>UD        0x0219429b
+                            urb MsgDesc: 83 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g46<1>D         g45<4>UD        0x0219439b
+                            urb MsgDesc: 115 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g58<1>D         g57<4>UD        0x0219411b
+                            urb MsgDesc: 35 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g63<1>D         g62<4>UD        0x0219421b
+                            urb MsgDesc: 67 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g68<1>D         g67<4>UD        0x0219431b
+                            urb MsgDesc: 99 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g78<1>D         g19<4>UD        0x02194113
+                            urb MsgDesc: 34 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g81<1>D         g19<4>UD        0x02194213
+                            urb MsgDesc: 66 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g84<1>D         g19<4>UD        0x02194313
+                            urb MsgDesc: 98 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x08842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x06429001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g12<8,8,1>UD    0x0c849001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x12094000
+                            urb MsgDesc: 0 write HWord per-slot interleave mlen 9 rlen 0 { align16 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x06426001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x0c846001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x08847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g5<8,8,1>UD     0x08425001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x10845001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x064a8006
+                            sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g14<8,8,1>UD    0x064a840a
+                            sampler MsgDesc: gather4 SIMD8 Surface = 10 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x084a8107
+                            sampler MsgDesc: gather4 SIMD8 Surface = 7 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g10<8,8,1>UD    0x084a8208
+                            sampler MsgDesc: gather4 SIMD8 Surface = 8 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g26<8,8,1>UD    0x0a4a8309
+                            sampler MsgDesc: gather4 SIMD8 Surface = 9 Sampler = 3 mlen 5 rlen 4 { align1 1Q };
+send(16)        g35<1>UW        g2<8,8,1>UD     0x0a8c8006
+                            sampler MsgDesc: gather4 SIMD16 Surface = 6 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(16)        g18<1>UW        g43<8,8,1>UD    0x0a8c840a
+                            sampler MsgDesc: gather4 SIMD16 Surface = 10 Sampler = 4 mlen 5 rlen 8 { align1 1H };
+send(16)        g43<1>UW        g7<8,8,1>UD     0x0e8c8107
+                            sampler MsgDesc: gather4 SIMD16 Surface = 7 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g51<8,8,1>UD    0x0e8c8208
+                            sampler MsgDesc: gather4 SIMD16 Surface = 8 Sampler = 2 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g26<8,8,1>UD    0x128c8309
+                            sampler MsgDesc: gather4 SIMD16 Surface = 9 Sampler = 3 mlen 9 rlen 8 { align1 1H };
+(+f1.0) send(8) null<1>UW       g7<8,8,1>UD     0x0a026001
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 5 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g9<8,8,1>UD     0x14025001
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 10 rlen 0 { align1 1H };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x0e4a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g9<8,8,1>UD     0x0a422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x14842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g9<8,8,1>UD     0x0a421001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x14841001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g25<1>UW        g13<8,8,1>UD    0x06195e01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 3 rlen 1 { align1 1Q };
+send(8)         null<1>UW       g26<8,8,1>UD    0x080b5e01
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1Q };
+send(8)         g11<1>UW        g18<8,8,1>UD    0x06196e01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 3 rlen 1 { align1 2Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x080b6e01
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g13<8,8,1>UD    0x06098501
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, inc) mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06099501
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, inc) mlen 3 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g26<8,8,1>UD    0x08098c01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, umax) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099c01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, umax) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g26<8,8,1>UD    0x08098401
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, mov) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099401
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, mov) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g28<8,8,1>UD    0x0a098e01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, cmpwr) mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g16<8,8,1>UD    0x0a099e01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, cmpwr) mlen 5 rlen 0 { align1 2Q };
+send(8)         g124<1>UW       g5<8,8,1>UD     0x064a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x0a8c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06423102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g26<8,8,1>UD    0x0c843102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         g22<1>UW        g22<8,8,1>UD    0x0242a203
+                            sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g26<8,8,1>UD    0x0242a304
+                            sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 4 { align1 1Q };
+send(8)         g30<1>UW        g30<8,8,1>UD    0x0242a405
+                            sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 4 { align1 1Q };
+send(8)         g34<1>UW        g34<8,8,1>UD    0x0242a506
+                            sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g20<8,8,1>UD    0x0242a102
+                            sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(8)         g38<1>UW        g38<8,8,1>UD    0x0242a607
+                            sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 6 mlen 1 rlen 4 { align1 1Q };
+send(8)         g42<1>UW        g42<8,8,1>UD    0x0242a708
+                            sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 7 mlen 1 rlen 4 { align1 1Q };
+send(8)         g46<1>UW        g46<8,8,1>UD    0x0242a809
+                            sampler MsgDesc: resinfo SIMD8 Surface = 9 Sampler = 8 mlen 1 rlen 4 { align1 1Q };
+send(8)         g50<1>UW        g50<8,8,1>UD    0x0242a90a
+                            sampler MsgDesc: resinfo SIMD8 Surface = 10 Sampler = 9 mlen 1 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g54<8,8,1>UD    0x0242aa0b
+                            sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 10 mlen 1 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g55<8,8,1>UD    0x0242ab0c
+                            sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 11 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g56<8,8,1>UD    0x0242ac0d
+                            sampler MsgDesc: resinfo SIMD8 Surface = 13 Sampler = 12 mlen 1 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0484a102
+                            sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H };
+send(16)        g82<1>UW        g110<8,8,1>UD   0x0484aa0b
+                            sampler MsgDesc: resinfo SIMD16 Surface = 11 Sampler = 10 mlen 2 rlen 8 { align1 1H };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x0484a203
+                            sampler MsgDesc: resinfo SIMD16 Surface = 3 Sampler = 2 mlen 2 rlen 8 { align1 1H };
+send(16)        g90<1>UW        g112<8,8,1>UD   0x0484ab0c
+                            sampler MsgDesc: resinfo SIMD16 Surface = 12 Sampler = 11 mlen 2 rlen 8 { align1 1H };
+send(16)        g98<1>UW        g106<8,8,1>UD   0x0484ac0d
+                            sampler MsgDesc: resinfo SIMD16 Surface = 13 Sampler = 12 mlen 2 rlen 8 { align1 1H };
+send(16)        g26<1>UW        g34<8,8,1>UD    0x0484a304
+                            sampler MsgDesc: resinfo SIMD16 Surface = 4 Sampler = 3 mlen 2 rlen 8 { align1 1H };
+send(16)        g34<1>UW        g42<8,8,1>UD    0x0484a405
+                            sampler MsgDesc: resinfo SIMD16 Surface = 5 Sampler = 4 mlen 2 rlen 8 { align1 1H };
+send(16)        g42<1>UW        g50<8,8,1>UD    0x0484a506
+                            sampler MsgDesc: resinfo SIMD16 Surface = 6 Sampler = 5 mlen 2 rlen 8 { align1 1H };
+send(16)        g50<1>UW        g58<8,8,1>UD    0x0484a607
+                            sampler MsgDesc: resinfo SIMD16 Surface = 7 Sampler = 6 mlen 2 rlen 8 { align1 1H };
+send(16)        g58<1>UW        g66<8,8,1>UD    0x0484a708
+                            sampler MsgDesc: resinfo SIMD16 Surface = 8 Sampler = 7 mlen 2 rlen 8 { align1 1H };
+send(16)        g66<1>UW        g74<8,8,1>UD    0x0484a809
+                            sampler MsgDesc: resinfo SIMD16 Surface = 9 Sampler = 8 mlen 2 rlen 8 { align1 1H };
+send(16)        g74<1>UW        g108<8,8,1>UD   0x0484a90a
+                            sampler MsgDesc: resinfo SIMD16 Surface = 10 Sampler = 9 mlen 2 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x06424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x04420203
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g11<8,8,1>UD    0x04420405
+                            sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x04420506
+                            sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x04420607
+                            sampler MsgDesc: sample SIMD8 Surface = 7 Sampler = 6 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g14<8,8,1>UD    0x04420708
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g15<8,8,1>UD    0x04420809
+                            sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 8 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g16<8,8,1>UD    0x0442090a
+                            sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 9 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g17<8,8,1>UD    0x04420a0b
+                            sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 10 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g18<8,8,1>UD    0x04420b0c
+                            sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 11 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g19<8,8,1>UD    0x04420c0d
+                            sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 12 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g20<8,8,1>UD    0x04420d0e
+                            sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 13 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g21<8,8,1>UD    0x04420e0f
+                            sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 14 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g22<8,8,1>UD    0x04420f10
+                            sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0011
+                            sampler MsgDesc: sample SIMD8 Surface = 17 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0112
+                            sampler MsgDesc: sample SIMD8 Surface = 18 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0213
+                            sampler MsgDesc: sample SIMD8 Surface = 19 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0314
+                            sampler MsgDesc: sample SIMD8 Surface = 20 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0415
+                            sampler MsgDesc: sample SIMD8 Surface = 21 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0516
+                            sampler MsgDesc: sample SIMD8 Surface = 22 Sampler = 5 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0617
+                            sampler MsgDesc: sample SIMD8 Surface = 23 Sampler = 6 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0718
+                            sampler MsgDesc: sample SIMD8 Surface = 24 Sampler = 7 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0819
+                            sampler MsgDesc: sample SIMD8 Surface = 25 Sampler = 8 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a091a
+                            sampler MsgDesc: sample SIMD8 Surface = 26 Sampler = 9 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0a1b
+                            sampler MsgDesc: sample SIMD8 Surface = 27 Sampler = 10 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0b1c
+                            sampler MsgDesc: sample SIMD8 Surface = 28 Sampler = 11 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0c1d
+                            sampler MsgDesc: sample SIMD8 Surface = 29 Sampler = 12 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0d1e
+                            sampler MsgDesc: sample SIMD8 Surface = 30 Sampler = 13 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0e1f
+                            sampler MsgDesc: sample SIMD8 Surface = 31 Sampler = 14 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0f20
+                            sampler MsgDesc: sample SIMD8 Surface = 32 Sampler = 15 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g26<8,8,1>UD    0x08840203
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g28<8,8,1>UD    0x08840405
+                            sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g29<8,8,1>UD    0x08840506
+                            sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g30<8,8,1>UD    0x08840607
+                            sampler MsgDesc: sample SIMD16 Surface = 7 Sampler = 6 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g31<8,8,1>UD    0x08840708
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g32<8,8,1>UD    0x08840809
+                            sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 8 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g33<8,8,1>UD    0x0884090a
+                            sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 9 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g34<8,8,1>UD    0x08840a0b
+                            sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 10 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g35<8,8,1>UD    0x08840b0c
+                            sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 11 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g36<8,8,1>UD    0x08840c0d
+                            sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 12 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g37<8,8,1>UD    0x08840d0e
+                            sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 13 mlen 4 rlen 8 { align1 1H };
+send(16)        g7<1>UW         g38<8,8,1>UD    0x08840e0f
+                            sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 14 mlen 4 rlen 8 { align1 1H };
+send(16)        g23<1>UW        g39<8,8,1>UD    0x08840f10
+                            sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 4 rlen 8 { align1 1H };
+send(16)        g17<1>UW        g2<8,8,1>UD     0x0a8c0011
+                            sampler MsgDesc: sample SIMD16 Surface = 17 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(16)        g29<1>UW        g7<8,8,1>UD     0x0a8c0112
+                            sampler MsgDesc: sample SIMD16 Surface = 18 Sampler = 1 mlen 5 rlen 8 { align1 1H };
+send(16)        g27<1>UW        g12<8,8,1>UD    0x0a8c0213
+                            sampler MsgDesc: sample SIMD16 Surface = 19 Sampler = 2 mlen 5 rlen 8 { align1 1H };
+send(16)        g32<1>UW        g17<8,8,1>UD    0x0a8c0314
+                            sampler MsgDesc: sample SIMD16 Surface = 20 Sampler = 3 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g22<8,8,1>UD    0x0a8c0415
+                            sampler MsgDesc: sample SIMD16 Surface = 21 Sampler = 4 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g27<8,8,1>UD    0x0a8c0516
+                            sampler MsgDesc: sample SIMD16 Surface = 22 Sampler = 5 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g32<8,8,1>UD    0x0a8c0617
+                            sampler MsgDesc: sample SIMD16 Surface = 23 Sampler = 6 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g37<8,8,1>UD    0x0a8c0718
+                            sampler MsgDesc: sample SIMD16 Surface = 24 Sampler = 7 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g42<8,8,1>UD    0x0a8c0819
+                            sampler MsgDesc: sample SIMD16 Surface = 25 Sampler = 8 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g47<8,8,1>UD    0x0a8c091a
+                            sampler MsgDesc: sample SIMD16 Surface = 26 Sampler = 9 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g52<8,8,1>UD    0x0a8c0a1b
+                            sampler MsgDesc: sample SIMD16 Surface = 27 Sampler = 10 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g57<8,8,1>UD    0x0a8c0b1c
+                            sampler MsgDesc: sample SIMD16 Surface = 28 Sampler = 11 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g62<8,8,1>UD    0x0a8c0c1d
+                            sampler MsgDesc: sample SIMD16 Surface = 29 Sampler = 12 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g67<8,8,1>UD    0x0a8c0d1e
+                            sampler MsgDesc: sample SIMD16 Surface = 30 Sampler = 13 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g72<8,8,1>UD    0x0a8c0e1f
+                            sampler MsgDesc: sample SIMD16 Surface = 31 Sampler = 14 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g77<8,8,1>UD    0x0a8c0f20
+                            sampler MsgDesc: sample SIMD16 Surface = 32 Sampler = 15 mlen 5 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g2<8,8,1>UD     0x02420102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g2<8,8,1>UD     0x04840102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x02406001
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x04805001
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 2 rlen 8 { align1 1H };
+send(8)         g29<1>UW        g5<8,8,1>UD     0x0e4b2002
+                            sampler MsgDesc: gather4_po_c SIMD8 Surface = 2 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x084a2001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x0e8c2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x044a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g4<8,8,1>UD     0x068c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 8 { align1 1H };
+send(8)         g17<1>UW        g12<8,8,1>UD    0x04420003
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g39<8,8,1>UD    0x08840003
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g8<8,8,1>UD     0x064a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g15<8,8,1>UD    0x0a8c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x9a08c000
+                            urb MsgDesc: 0 write HWord interleave complete mlen 13 rlen 0 { align16 1Q EOT };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x084a6001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x084a6102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x0e8c6001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0e8c6102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(8)         g108<1>D        g105<4>UD       0x02194223
+                            urb MsgDesc: 68 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g107<1>D        g105<4>UD       0x02194323
+                            urb MsgDesc: 100 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x02194123
+                            urb MsgDesc: 36 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x0219412b
+                            urb MsgDesc: 37 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g107<1>D        g105<4>UD       0x0219422b
+                            urb MsgDesc: 69 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x0219432b
+                            urb MsgDesc: 101 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x02194133
+                            urb MsgDesc: 38 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g110<1>D        g105<4>UD       0x02194233
+                            urb MsgDesc: 70 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x02194333
+                            urb MsgDesc: 102 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g107<1>D        g105<4>UD       0x0219413b
+                            urb MsgDesc: 39 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x0219423b
+                            urb MsgDesc: 71 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x0219433b
+                            urb MsgDesc: 103 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g110<1>D        g105<4>UD       0x02194143
+                            urb MsgDesc: 40 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x02194243
+                            urb MsgDesc: 72 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x02194343
+                            urb MsgDesc: 104 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x0219414b
+                            urb MsgDesc: 41 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x0219424b
+                            urb MsgDesc: 73 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x0219434b
+                            urb MsgDesc: 105 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x02194153
+                            urb MsgDesc: 42 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x02194253
+                            urb MsgDesc: 74 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g107<1>D        g105<4>UD       0x02194353
+                            urb MsgDesc: 106 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g107<1>D        g105<4>UD       0x0219415b
+                            urb MsgDesc: 43 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x0219425b
+                            urb MsgDesc: 75 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x0219435b
+                            urb MsgDesc: 107 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x02194163
+                            urb MsgDesc: 44 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g110<1>D        g105<4>UD       0x02194263
+                            urb MsgDesc: 76 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x02194363
+                            urb MsgDesc: 108 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g107<1>D        g105<4>UD       0x0219416b
+                            urb MsgDesc: 45 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x0219426b
+                            urb MsgDesc: 77 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x0219436b
+                            urb MsgDesc: 109 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g110<1>D        g105<4>UD       0x02194173
+                            urb MsgDesc: 46 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x02194273
+                            urb MsgDesc: 78 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x02194373
+                            urb MsgDesc: 110 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x0219417b
+                            urb MsgDesc: 47 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x0219427b
+                            urb MsgDesc: 79 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x0219437b
+                            urb MsgDesc: 111 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x02194183
+                            urb MsgDesc: 48 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x02194283
+                            urb MsgDesc: 80 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g107<1>D        g105<4>UD       0x02194383
+                            urb MsgDesc: 112 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x02194193
+                            urb MsgDesc: 50 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g110<1>D        g105<4>UD       0x02194293
+                            urb MsgDesc: 82 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x02194393
+                            urb MsgDesc: 114 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x021941a3
+                            urb MsgDesc: 52 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g110<1>D        g105<4>UD       0x021942a3
+                            urb MsgDesc: 84 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x021943a3
+                            urb MsgDesc: 116 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x021941ab
+                            urb MsgDesc: 53 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x021942ab
+                            urb MsgDesc: 85 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x021943ab
+                            urb MsgDesc: 117 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g107<1>D        g105<4>UD       0x021941b3
+                            urb MsgDesc: 54 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x021942b3
+                            urb MsgDesc: 86 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x021943b3
+                            urb MsgDesc: 118 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x021941bb
+                            urb MsgDesc: 55 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g110<1>D        g105<4>UD       0x021942bb
+                            urb MsgDesc: 87 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x021943bb
+                            urb MsgDesc: 119 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g110<1>D        g105<4>UD       0x021941c3
+                            urb MsgDesc: 56 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x021942c3
+                            urb MsgDesc: 88 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x021943c3
+                            urb MsgDesc: 120 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x021941cb
+                            urb MsgDesc: 57 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x021942cb
+                            urb MsgDesc: 89 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x021943cb
+                            urb MsgDesc: 121 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x021941d3
+                            urb MsgDesc: 58 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x021942d3
+                            urb MsgDesc: 90 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x021943d3
+                            urb MsgDesc: 122 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x021941db
+                            urb MsgDesc: 59 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x021942db
+                            urb MsgDesc: 91 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x021943db
+                            urb MsgDesc: 123 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x021941e3
+                            urb MsgDesc: 60 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x021942e3
+                            urb MsgDesc: 92 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g110<1>D        g105<4>UD       0x021943e3
+                            urb MsgDesc: 124 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x021941eb
+                            urb MsgDesc: 61 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x021942eb
+                            urb MsgDesc: 93 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x021943eb
+                            urb MsgDesc: 125 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g108<1>D        g105<4>UD       0x021941f3
+                            urb MsgDesc: 62 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g110<1>D        g105<4>UD       0x021942f3
+                            urb MsgDesc: 94 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x021943f3
+                            urb MsgDesc: 126 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g109<1>D        g105<4>UD       0x021941fb
+                            urb MsgDesc: 63 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g111<1>D        g105<4>UD       0x021942fb
+                            urb MsgDesc: 95 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g106<1>D        g105<4>UD       0x021943fb
+                            urb MsgDesc: 127 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x02106e01
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x04205e01
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+(+f1.0) send(8) null<1>UW       g6<8,8,1>UD     0x04026e01
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g6<8,8,1>UD     0x04026e02
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g8<8,8,1>UD     0x08025e01
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g8<8,8,1>UD     0x08025e02
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x0a4a5001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g17<8,8,1>UD    0x0a4a5102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g25<1>UW        g7<8,8,1>UD     0x128c5001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(16)        g33<1>UW        g16<8,8,1>UD    0x128c5102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x0c4b2002
+                            sampler MsgDesc: gather4_po_c SIMD8 Surface = 2 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g15<8,8,1>UD    0x168d2002
+                            sampler MsgDesc: gather4_po_c SIMD16 Surface = 2 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(8)         g68<1>.xUW      g65<4>UD        0x0210e500
+                            dp data 1 MsgDesc: ( DC untyped 4x2 atomic op, Surface = 0,  inc) mlen 1 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x124b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g16<8,8,1>UD    0x124b4102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 9 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x0a4a2001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g9<8,8,1>UD     0x128c2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         g24<1>F         g25<4>.xUD      0x02107002
+                            sampler MsgDesc: ld SIMD4x2 Surface = 2 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g30<1>F         g31<4>.xUD      0x02107003
+                            sampler MsgDesc: ld SIMD4x2 Surface = 3 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g35<1>F         g36<4>.xUD      0x02107004
+                            sampler MsgDesc: ld SIMD4x2 Surface = 4 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g41<1>F         g42<4>.xUD      0x02107005
+                            sampler MsgDesc: ld SIMD4x2 Surface = 5 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g47<1>F         g48<4>.xUD      0x02107006
+                            sampler MsgDesc: ld SIMD4x2 Surface = 6 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g53<1>F         g54<4>.xUD      0x02107007
+                            sampler MsgDesc: ld SIMD4x2 Surface = 7 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g59<1>F         g60<4>.xUD      0x02107008
+                            sampler MsgDesc: ld SIMD4x2 Surface = 8 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g65<1>F         g66<4>.xUD      0x02107009
+                            sampler MsgDesc: ld SIMD4x2 Surface = 9 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g71<1>F         g72<4>.xUD      0x0210700a
+                            sampler MsgDesc: ld SIMD4x2 Surface = 10 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g77<1>F         g78<4>.xUD      0x0210700b
+                            sampler MsgDesc: ld SIMD4x2 Surface = 11 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g83<1>F         g84<4>.xUD      0x0210700c
+                            sampler MsgDesc: ld SIMD4x2 Surface = 12 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g89<1>F         g90<4>.xUD      0x0210700d
+                            sampler MsgDesc: ld SIMD4x2 Surface = 13 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g5<1>F          g114<4>F        0x04102505
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 5 Sampler = 5 mlen 2 rlen 1 { align16 1Q };
+(+f1.0) send(8) g3<1>UW         g3<8,8,1>UD     0x0410b702
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, add) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(16) g4<1>UW        g6<8,8,1>UD     0x0820a702
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, add) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(8) g2<1>UW         g5<8,8,1>UD     0x0210b501
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 1 { align1 1Q };
+(+f1.0) send(16) g2<1>UW        g7<8,8,1>UD     0x0420a501
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 2 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x08420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x10840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+(+f1.0) send(8) g4<1>UW         g12<8,8,1>UD    0x0210b502
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, inc) mlen 1 rlen 1 { align1 1Q };
+(+f1.0) send(16) g5<1>UW        g17<8,8,1>UD    0x0420a502
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, inc) mlen 2 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g11<8,8,1>UD    0x084a5001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g15<8,8,1>UD    0x084a5102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g21<8,8,1>UD    0x0e8c5001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g28<8,8,1>UD    0x0e8c5102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g9<8,8,1>UD     0x024ab001
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x028cb001
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 1 Sampler = 0 mlen 1 rlen 8 { align1 1H };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x06026c01
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0xc) mlen 3 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g4<8,8,1>UD     0x0c025c01
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0xc) mlen 6 rlen 0 { align1 1H };
+send(8)         g3<1>UW         g8<8,8,1>UD     0x02427002
+                            sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g4<1>UW         g26<8,8,1>UD    0x04847002
+                            sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+(+f1.0) send(8) g14<1>UW        g13<8,8,1>UD    0x0410bb02
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, imin) mlen 2 rlen 1 { align1 1Q };
+send(8)         g15<1>UW        g3<8,8,1>UD     0x02106e02
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+(+f1.0) send(8) g18<1>UW        g4<8,8,1>UD     0x0410b402
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, mov) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(16) g21<1>UW       g23<8,8,1>UD    0x0820ab02
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, imin) mlen 4 rlen 2 { align1 1H };
+send(16)        g22<1>UW        g3<8,8,1>UD     0x04205e02
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+(+f1.0) send(16) g25<1>UW       g6<8,8,1>UD     0x0820a402
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, mov) mlen 4 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g3<8,8,1>UD     0x04203000
+                            pixel interp MsgDesc: (persp, per_slot_offset, 0x00) mlen 2 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g15<8,8,1>UD    0x08413000
+                            pixel interp MsgDesc: (persp, per_slot_offset, 0x00) mlen 4 rlen 4 { align1 1H };
+send(1)         g2<1>UW         g2<0,1,0>UW     0x0209c000
+                            data MsgDesc: ( DC mfence, 0, 0) mlen 1 rlen 0  { align1 WE_all 1N };
+send(8)         g2<1>UW         g0<8,8,1>UD     0x02201010
+                            pixel interp MsgDesc: (persp, sample_position, 0x10) mlen 1 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g0<8,8,1>UD     0x02411010
+                            pixel interp MsgDesc: (persp, sample_position, 0x10) mlen 1 rlen 4 { align1 1H };
+send(8)         g2<1>UW         g0<8,8,1>UD     0x02201020
+                            pixel interp MsgDesc: (persp, sample_position, 0x20) mlen 1 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g0<8,8,1>UD     0x02411020
+                            pixel interp MsgDesc: (persp, sample_position, 0x20) mlen 1 rlen 4 { align1 1H };
+send(8)         g2<1>UW         g0<8,8,1>UD     0x02201030
+                            pixel interp MsgDesc: (persp, sample_position, 0x30) mlen 1 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g0<8,8,1>UD     0x02411030
+                            pixel interp MsgDesc: (persp, sample_position, 0x30) mlen 1 rlen 4 { align1 1H };
+(+f1.0) send(8) null<1>UW       g119<8,8,1>UD   0x02009601
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, dec) mlen 1 rlen 0 { align1 1Q };
+(+f1.0) send(8) g48<1>UW        g119<8,8,1>UD   0x0210b601
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, dec) mlen 1 rlen 1 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g3<8,8,1>UD     0x04008601
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, dec) mlen 2 rlen 0 { align1 1H };
+(+f1.0) send(16) g97<1>UW       g3<8,8,1>UD     0x0420a601
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, dec) mlen 2 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x064a8004
+                            sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x084a8105
+                            sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g10<8,8,1>UD    0x064a8206
+                            sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0a8c8004
+                            sampler MsgDesc: gather4 SIMD16 Surface = 4 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0e8c8105
+                            sampler MsgDesc: gather4 SIMD16 Surface = 5 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(16)        g26<1>UW        g34<8,8,1>UD    0x0a8c8206
+                            sampler MsgDesc: gather4 SIMD16 Surface = 6 Sampler = 2 mlen 5 rlen 8 { align1 1H };
+send(8)         g39<1>.xUW      g36<4>UD        0x0210e600
+                            dp data 1 MsgDesc: ( DC untyped 4x2 atomic op, Surface = 0,  dec) mlen 1 rlen 1 { align16 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06420102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0c840102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x8e08c030
+                            urb MsgDesc: 6 write HWord interleave complete mlen 7 rlen 0 { align16 1Q EOT };
+send(8)         g6<1>UW         g9<8,8,1>UD     0x02406002
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 1Q };
+send(16)        g16<1>UW        g14<8,8,1>UD    0x04805002
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD16, Mask = 0x0) mlen 2 rlen 8 { align1 1H };
+send(8)         g5<1>UW         g5<8,8,1>UD     0x04195e01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 2 rlen 1 { align1 1Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x060b5e02
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 3 rlen 0 { align1 1Q };
+send(8)         g7<1>UW         g10<8,8,1>UD    0x04196e01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 2 rlen 1 { align1 2Q };
+send(8)         null<1>UW       g12<8,8,1>UD    0x060b6e02
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 3 rlen 0 { align1 2Q };
+send(8)         null<1>F        g113<4>F        0x1a094030
+                            urb MsgDesc: 6 write HWord per-slot interleave mlen 13 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x06094060
+                            urb MsgDesc: 12 write HWord per-slot interleave mlen 3 rlen 0 { align16 1Q };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x084a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g15<8,8,1>UD    0x0e8c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g13<1>UD        g114<4>F        0x0211d000
+                            sampler MsgDesc: ld_mcs SIMD4x2 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g3<1>UD         g114<4>F        0x04188005
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 5 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         g4<1>UD         g114<4>F        0x04188106
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 6 Sampler = 1 mlen 2 rlen 1 { align16 1Q };
+send(8)         g6<1>UD         g114<4>F        0x04188207
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 7 Sampler = 2 mlen 2 rlen 1 { align16 1Q };
+send(8)         g9<1>UD         g114<4>F        0x04188308
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 8 Sampler = 3 mlen 2 rlen 1 { align16 1Q };
+send(8)         g11<1>UD        g114<4>F        0x04188409
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 9 Sampler = 4 mlen 2 rlen 1 { align16 1Q };
+(+f1.0) send(8) null<1>UW       g11<8,8,1>UD    0x0a026002
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD8, Mask = 0x0) mlen 5 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g13<8,8,1>UD    0x14025002
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0x0) mlen 10 rlen 0 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x16094060
+                            urb MsgDesc: 12 write HWord per-slot interleave mlen 11 rlen 0 { align16 1Q };
+send(8)         null<1>UW       g126<8,8,1>UD   0x040a02ff
+                            data MsgDesc: ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0009
+                            data MsgDesc: ( DC OWORD block read, 9, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0001
+                            data MsgDesc: ( DC OWORD block read, 1, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0008
+                            data MsgDesc: ( DC OWORD block read, 8, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0002
+                            data MsgDesc: ( DC OWORD block read, 2, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0007
+                            data MsgDesc: ( DC OWORD block read, 7, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0000
+                            data MsgDesc: ( DC OWORD block read, 0, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g68<1>UW        g0<8,8,1>F      0x021c0005
+                            data MsgDesc: ( DC OWORD block read, 5, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0004
+                            data MsgDesc: ( DC OWORD block read, 4, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g64<1>UW        g0<8,8,1>F      0x021c0006
+                            data MsgDesc: ( DC OWORD block read, 6, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g64<1>UW        g0<8,8,1>F      0x021c0003
+                            data MsgDesc: ( DC OWORD block read, 3, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g2<1>UW         g9<8,8,1>UD     0x0a423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g19<1>UW        g9<8,8,1>UD     0x14843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g8<8,8,1>UD     0x08426001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g10<8,8,1>UD    0x10846001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+(+f1.0) send(8) g14<1>UW        g13<8,8,1>UD    0x0410bd02
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, umin) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(16) g21<1>UW       g23<8,8,1>UD    0x0820ad02
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, umin) mlen 4 rlen 2 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x12424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 4 { align1 1Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x080b5e02
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x080b6e02
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 4 rlen 0 { align1 2Q };
+send(8)         g26<1>UW        g20<8,8,1>UD    0x06295c01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xc) mlen 3 rlen 2 { align1 1Q };
+send(8)         null<1>UW       g23<8,8,1>UD    0x0a0b5c02
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xc) mlen 5 rlen 0 { align1 1Q };
+send(8)         g5<1>UW         g43<8,8,1>UD    0x06296c01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xc) mlen 3 rlen 2 { align1 2Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x0a0b6c02
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xc) mlen 5 rlen 0 { align1 2Q };
+send(8)         null<1>F        g113<4>F        0x8608c060
+                            urb MsgDesc: 12 write HWord interleave complete mlen 3 rlen 0 { align16 1Q EOT };
+send(8)         g2<1>UW         g16<8,8,1>UD    0x04495001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g31<8,8,1>UD    0x04496001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 2 rlen 4 { align1 2Q };
+send(8)         g2<1>UW         g16<8,8,1>UD    0x04295c01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xc) mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UW         g31<8,8,1>UD    0x04296c01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xc) mlen 2 rlen 2 { align1 2Q };
+send(8)         g20<1>UW        g16<8,8,1>UD    0x04195e02
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD16, Mask = 0xe) mlen 2 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g18<8,8,1>UD    0x0619a701
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, add) mlen 3 rlen 1 { align1 1Q };
+send(8)         g4<1>UW         g31<8,8,1>UD    0x04196e02
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD8, Mask = 0xe) mlen 2 rlen 1 { align1 2Q };
+send(8)         g121<1>UW       g2<8,8,1>UD     0x0619b701
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, add) mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g18<8,8,1>UD    0x0619ad01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, umin) mlen 3 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g2<8,8,1>UD     0x0619bd01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, umin) mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g18<8,8,1>UD    0x0619ac01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, umax) mlen 3 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g2<8,8,1>UD     0x0619bc01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, umax) mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g18<8,8,1>UD    0x0619a101
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, and) mlen 3 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g2<8,8,1>UD     0x0619b101
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, and) mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g18<8,8,1>UD    0x0619a201
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, or) mlen 3 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g2<8,8,1>UD     0x0619b201
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, or) mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g18<8,8,1>UD    0x0619a301
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, xor) mlen 3 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g2<8,8,1>UD     0x0619b301
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, xor) mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g18<8,8,1>UD    0x0619a401
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, mov) mlen 3 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g2<8,8,1>UD     0x0619b401
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, mov) mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g18<8,8,1>UD    0x0819ae01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, cmpwr) mlen 4 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g2<8,8,1>UD     0x0819be01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, cmpwr) mlen 4 rlen 1 { align1 2Q };
+send(8)         g9<1>UW         g19<8,8,1>UD    0x0843e102
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g23<1>UW        g7<8,8,1>UD     0x1085e102
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g5<8,8,1>UD     0x0c4b0002
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x168d0002
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 2 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g5<8,8,1>UD     0x06425001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x0c845001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+(+f1.0) send(8) null<1>UW       g9<8,8,1>UD     0x0a026003
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 5 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g11<8,8,1>UD    0x14025003
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 10 rlen 0 { align1 1H };
+send(8)         null<1>UW       g2<8,8,1>UD     0x060b5e01
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x060b6e01
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 3 rlen 0 { align1 2Q };
+send(8)         g2<1>UW         g11<8,8,1>UD    0x084a3001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g15<8,8,1>UD    0x084a3102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g22<8,8,1>UD    0x0e8c3001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g29<8,8,1>UD    0x0e8c3102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(16)        g2<1>UD         g26<8,8,1>UD    0x02280302
+                            const MsgDesc: (2, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g16<1>UD        g27<8,8,1>UD    0x02280303
+                            const MsgDesc: (3, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x0a4a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g12<8,8,1>UD    0x04009701
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, add) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g19<8,8,1>UD    0x08008701
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, add) mlen 4 rlen 0 { align1 1H };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x0c4b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g13<8,8,1>UD    0x0c4b4102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x0443d002
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0885d002
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x02306801
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0x8) mlen 1 rlen 3 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x04605801
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0x8) mlen 2 rlen 6 { align1 1H };
+(+f1.0) send(8) null<1>UW       g2<8,8,1>UD     a0<0,1,0>UD     0x00000200
+                            dp data 1 MsgDesc: indirect                     { align1 1Q };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x104b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g20<8,8,1>UD    0x104b4102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 8 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g10<8,8,1>UD    0x04420004
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x08840004
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g11<1>F         g114<4>F        0x06192001
+                            sampler MsgDesc: gather4_po_c SIMD4x2 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align16 1Q };
+(+f1.0) send(8) g3<1>UW         g10<8,8,1>UD    0x0410b701
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, add) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g5<1>UW         g10<8,8,1>UD    0x0410bd01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umin) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g6<1>UW         g10<8,8,1>UD    0x0410bc01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umax) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g7<1>UW         g10<8,8,1>UD    0x0410b101
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, and) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g9<1>UW         g10<8,8,1>UD    0x0410b301
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, xor) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g10<1>UW        g10<8,8,1>UD    0x0410b401
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, mov) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g11<1>UW        g11<8,8,1>UD    0x0610be01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, cmpwr) mlen 3 rlen 1 { align1 1Q };
+(+f1.0) send(16) g3<1>UW        g19<8,8,1>UD    0x0820a701
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, add) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g7<1>UW        g19<8,8,1>UD    0x0820ad01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umin) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g9<1>UW        g19<8,8,1>UD    0x0820ac01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umax) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g11<1>UW       g19<8,8,1>UD    0x0820a101
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, and) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g15<1>UW       g19<8,8,1>UD    0x0820a301
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, xor) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g17<1>UW       g19<8,8,1>UD    0x0820a401
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, mov) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g19<1>UW       g21<8,8,1>UD    0x0c20ae01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, cmpwr) mlen 6 rlen 2 { align1 1H };
+send(8)         null<1>UW       g5<8,8,1>UD     0x0e0b5001
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 7 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x0e0b6001
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 7 rlen 0 { align1 2Q };
+send(8)         g4<1>F          g114<4>F        0x06190005
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 5 Sampler = 0 mlen 3 rlen 1 { align16 1Q };
+send(8)         g5<1>F          g114<4>F        0x06190106
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 6 Sampler = 1 mlen 3 rlen 1 { align16 1Q };
+send(8)         g7<1>F          g114<4>F        0x06190207
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 7 Sampler = 2 mlen 3 rlen 1 { align16 1Q };
+send(8)         g10<1>F         g114<4>F        0x06190308
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 8 Sampler = 3 mlen 3 rlen 1 { align16 1Q };
+send(8)         g12<1>F         g114<4>F        0x06190409
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 9 Sampler = 4 mlen 3 rlen 1 { align16 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04009d01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umin) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04009c01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umax) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04009101
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, and) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04009201
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04009301
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, xor) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04009401
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, mov) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g9<8,8,1>UD     0x06009e01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, cmpwr) mlen 3 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g13<8,8,1>UD    0x08008d01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umin) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g13<8,8,1>UD    0x08008c01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umax) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g13<8,8,1>UD    0x08008101
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, and) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g13<8,8,1>UD    0x08008201
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g13<8,8,1>UD    0x08008301
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, xor) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g13<8,8,1>UD    0x08008401
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, mov) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g13<8,8,1>UD    0x0c008e01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, cmpwr) mlen 6 rlen 0 { align1 1H };
+send(8)         g9<1>UW         g5<8,8,1>UD     0x04420002
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g13<1>UW        g7<8,8,1>UD     0x08840002
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x0419a501
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, inc) mlen 2 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g2<8,8,1>UD     0x0419b501
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, inc) mlen 2 rlen 1 { align1 2Q };
+send(8)         null<1>UW       g20<8,8,1>UD    0x06098101
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, and) mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06099101
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, and) mlen 3 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g19<8,8,1>UD    0x06098201
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, or) mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06099201
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, or) mlen 3 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g19<8,8,1>UD    0x06098301
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, xor) mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06099301
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, xor) mlen 3 rlen 0 { align1 2Q };
+send(8)         g29<1>UW        g18<8,8,1>UD    0x04420008
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g35<1>UW        g18<8,8,1>UD    0x04420109
+                            sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(8)         g41<1>UW        g18<8,8,1>UD    0x0442020a
+                            sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 2 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g18<8,8,1>UD    0x0442030b
+                            sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 3 mlen 2 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g18<8,8,1>UD    0x0442040c
+                            sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g18<8,8,1>UD    0x0442050d
+                            sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 5 mlen 2 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g18<8,8,1>UD    0x0442060e
+                            sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 6 mlen 2 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x0442070f
+                            sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 7 mlen 2 rlen 4 { align1 1Q };
+send(16)        g32<1>UW        g22<8,8,1>UD    0x08840008
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g42<1>UW        g22<8,8,1>UD    0x08840109
+                            sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(16)        g60<1>UW        g22<8,8,1>UD    0x0884020a
+                            sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 2 mlen 4 rlen 8 { align1 1H };
+send(16)        g70<1>UW        g22<8,8,1>UD    0x0884030b
+                            sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 3 mlen 4 rlen 8 { align1 1H };
+send(16)        g78<1>UW        g22<8,8,1>UD    0x0884040c
+                            sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 4 mlen 4 rlen 8 { align1 1H };
+send(16)        g86<1>UW        g22<8,8,1>UD    0x0884050d
+                            sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 5 mlen 4 rlen 8 { align1 1H };
+send(16)        g94<1>UW        g22<8,8,1>UD    0x0884060e
+                            sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 6 mlen 4 rlen 8 { align1 1H };
+send(16)        g52<1>UW        g22<8,8,1>UD    0x0884070f
+                            sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 7 mlen 4 rlen 8 { align1 1H };
+send(8)         g5<1>F          g114<4>F        0x04102101
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 1 Sampler = 1 mlen 2 rlen 1 { align16 1Q };
+send(8)         g6<1>F          g114<4>F        0x04102202
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 2 Sampler = 2 mlen 2 rlen 1 { align16 1Q };
+send(8)         g7<1>F          g114<4>F        0x04102303
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 3 Sampler = 3 mlen 2 rlen 1 { align16 1Q };
+send(8)         g8<1>F          g114<4>F        0x04102404
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 4 Sampler = 4 mlen 2 rlen 1 { align16 1Q };
+send(8)         g10<1>F         g114<4>F        0x04102606
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 6 Sampler = 6 mlen 2 rlen 1 { align16 1Q };
+send(8)         g11<1>F         g114<4>F        0x04102707
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 7 Sampler = 7 mlen 2 rlen 1 { align16 1Q };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x084a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g18<8,8,1>UD    0x0e8c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x0e094030
+                            urb MsgDesc: 6 write HWord per-slot interleave mlen 7 rlen 0 { align16 1Q };
+send(8)         null<1>UW       g20<8,8,1>UD    0x08098701
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, add) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099701
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, add) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g20<8,8,1>UD    0x08098d01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, umin) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099d01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, umin) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g20<8,8,1>UD    0x08098101
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, and) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099101
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, and) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g20<8,8,1>UD    0x08098201
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, or) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099201
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, or) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g20<8,8,1>UD    0x08098301
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, xor) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099301
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, xor) mlen 4 rlen 0 { align1 2Q };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x084b0006
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 6 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x0a4b0107
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 7 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g11<8,8,1>UD    0x0a4b0208
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 8 Sampler = 2 mlen 5 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x0c4b0309
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 9 Sampler = 3 mlen 6 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g24<8,8,1>UD    0x084b040a
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 10 Sampler = 4 mlen 4 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x128d0208
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 8 Sampler = 2 mlen 9 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0e8d0006
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 6 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(16)        g26<1>UW        g35<8,8,1>UD    0x168d0309
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 9 Sampler = 3 mlen 11 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g53<8,8,1>UD    0x128d0107
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 7 Sampler = 1 mlen 9 rlen 8 { align1 1H };
+send(16)        g34<1>UW        g46<8,8,1>UD    0x0e8d040a
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 10 Sampler = 4 mlen 7 rlen 8 { align1 1H };
+send(8)         null<1>UW       g9<8,8,1>UD     0x0e0b5003
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 7 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g15<8,8,1>UD    0x0e0b6003
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 7 rlen 0 { align1 2Q };

diff --git a/src/intel/tools/tests/gen7.5/send.expected b/src/intel/tools/tests/gen7.5/send.expected
new file mode 100644 (file)
index 0000000..749b53b
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/send.expected
@@ -0,0 +1,752 @@
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+31 00 80 02 29 0c 40 20 40 01 8d 00 06 00 8d 0e
+31 00 80 02 29 0c 40 23 60 04 8d 00 09 03 8d 16
+31 00 80 02 29 0c 40 21 a0 06 8d 00 07 01 8d 12
+31 00 80 02 29 0c 40 24 c0 05 8d 00 0a 04 8d 0e
+31 00 60 0c 28 0c 00 20 20 01 8d 00 03 50 0b 0e
+31 10 60 0c 28 0c 00 20 e0 01 8d 00 03 60 0b 0e

diff --git a/src/intel/tools/tests/gen7.5/sendc.asm b/src/intel/tools/tests/gen7.5/sendc.asm
new file mode 100644 (file)
index 0000000..279f51e
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/sendc.asm
@@ -0,0 +1,104 @@
+sendc(8)        null<1>UW       g124<8,8,1>F    0x88031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g120<8,8,1>F    0x90031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       g114<8,8,1>F    0x82031100
+                            render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
+(+f0.1) sendc(8) null<1>UW      g124<8,8,1>F    0x88031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
+(+f0.1) sendc(16) null<1>UW     g120<8,8,1>F    0x90031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g13<8,8,1>F     0x0e0b0401
+                            render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g121<8,8,1>F    0x8e0b1402
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g7<8,8,1>F      0x180b0001
+                            render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g116<8,8,1>F    0x980b1002
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g123<8,8,1>F    0x8a031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x94031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g22<8,8,1>F     0x0c0b0400
+                            render MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g28<8,8,1>F     0x0c0b0401
+                            render MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g34<8,8,1>F     0x0c0b0402
+                            render MsgDesc: RT write SIMD8 Surface = 2 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1403
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g2<8,8,1>F      0x140b0000
+                            render MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g12<8,8,1>F     0x140b0001
+                            render MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g22<8,8,1>F     0x140b0002
+                            render MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1003
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 1H EOT };
+(+f0.1) sendc(8) null<1>UW      g123<8,8,1>F    0x8a031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT };
+(+f0.1) sendc(16) null<1>UW     g118<8,8,1>F    0x94031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g118<8,8,1>F    0x940b1200
+                            render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g3<8,8,1>F      0x140b1200
+                            render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g118<8,8,1>F    0x940b1300
+                            render MsgDesc: RT write SIMD8/DualSrcHigh LastRT Surface = 0 mlen 10 rlen 0 { align1 2Q EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1401
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1402
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1002
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g3<8,8,1>F      0x0c0b0403
+                            render MsgDesc: RT write SIMD8 Surface = 3 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g3<8,8,1>F      0x0c0b0404
+                            render MsgDesc: RT write SIMD8 Surface = 4 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g3<8,8,1>F      0x0c0b0405
+                            render MsgDesc: RT write SIMD8 Surface = 5 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g3<8,8,1>F      0x0c0b0406
+                            render MsgDesc: RT write SIMD8 Surface = 6 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1407
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 7 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g3<8,8,1>F      0x140b0003
+                            render MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g3<8,8,1>F      0x140b0004
+                            render MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g3<8,8,1>F      0x140b0005
+                            render MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g3<8,8,1>F      0x140b0006
+                            render MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1007
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g10<8,8,1>F     0x0e0b0400
+                            render MsgDesc: RT write SIMD8 Surface = 0 mlen 7 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g121<8,8,1>F    0x8e0b1401
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g2<8,8,1>F      0x160b0000
+                            render MsgDesc: RT write SIMD16 Surface = 0 mlen 11 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g117<8,8,1>F    0x960b1001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 11 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1405
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 5 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1005
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       g116<8,8,1>F    0x980b1001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 12 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x88031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g119<8,8,1>F    0x92031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 9 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       g11<8,8,1>F     0x180b0000
+                            render MsgDesc: RT write SIMD16 Surface = 0 mlen 12 rlen 0 { align1 1H };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1404
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 4 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1004
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1406
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 6 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1006
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 1H EOT };

diff --git a/src/intel/tools/tests/gen7.5/sendc.expected b/src/intel/tools/tests/gen7.5/sendc.expected
new file mode 100644 (file)
index 0000000..a70230a
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/sendc.expected
@@ -0,0 +1,52 @@
+32 00 60 05 a8 0f 00 20 80 0f 8d 00 00 14 03 88
+32 00 80 05 a8 0f 00 20 00 0f 8d 00 00 10 03 90
+32 00 80 05 a8 0f 00 20 40 0e 8d 00 00 11 03 82
+32 00 61 05 a8 0f 00 20 80 0f 8d 02 00 14 03 88
+32 00 81 05 a8 0f 00 20 00 0f 8d 02 00 10 03 90
+32 00 60 05 a8 0f 00 20 a0 01 8d 00 01 04 0b 0e
+32 00 60 05 a8 0f 00 20 20 0f 8d 00 02 14 0b 8e
+32 00 80 05 a8 0f 00 20 e0 00 8d 00 01 00 0b 18
+32 00 80 05 a8 0f 00 20 80 0e 8d 00 02 10 0b 98
+32 00 60 05 a8 0f 00 20 60 0f 8d 00 00 14 03 8a
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 00 10 03 94
+32 00 60 05 a8 0f 00 20 c0 02 8d 00 00 04 0b 0c
+32 00 60 05 a8 0f 00 20 80 03 8d 00 01 04 0b 0c
+32 00 60 05 a8 0f 00 20 40 04 8d 00 02 04 0b 0c
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 03 14 0b 8c
+32 00 80 05 a8 0f 00 20 40 00 8d 00 00 00 0b 14
+32 00 80 05 a8 0f 00 20 80 01 8d 00 01 00 0b 14
+32 00 80 05 a8 0f 00 20 c0 02 8d 00 02 00 0b 14
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 03 10 0b 94
+32 00 61 05 a8 0f 00 20 60 0f 8d 02 00 14 03 8a
+32 00 81 05 a8 0f 00 20 c0 0e 8d 02 00 10 03 94
+32 00 60 05 a8 0f 00 20 c0 0e 8d 00 00 12 0b 94
+32 00 60 05 a8 0f 00 20 60 00 8d 00 00 12 0b 14
+32 10 60 05 a8 0f 00 20 c0 0e 8d 00 00 13 0b 94
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 01 14 0b 8c
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 01 10 0b 94
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 02 14 0b 8c
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 02 10 0b 94
+32 00 60 05 a8 0f 00 20 60 00 8d 00 03 04 0b 0c
+32 00 60 05 a8 0f 00 20 60 00 8d 00 04 04 0b 0c
+32 00 60 05 a8 0f 00 20 60 00 8d 00 05 04 0b 0c
+32 00 60 05 a8 0f 00 20 60 00 8d 00 06 04 0b 0c
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 07 14 0b 8c
+32 00 80 05 a8 0f 00 20 60 00 8d 00 03 00 0b 14
+32 00 80 05 a8 0f 00 20 60 00 8d 00 04 00 0b 14
+32 00 80 05 a8 0f 00 20 60 00 8d 00 05 00 0b 14
+32 00 80 05 a8 0f 00 20 60 00 8d 00 06 00 0b 14
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 07 10 0b 94
+32 00 60 05 a8 0f 00 20 40 01 8d 00 00 04 0b 0e
+32 00 60 05 a8 0f 00 20 20 0f 8d 00 01 14 0b 8e
+32 00 80 05 a8 0f 00 20 40 00 8d 00 00 00 0b 16
+32 00 80 05 a8 0f 00 20 a0 0e 8d 00 01 10 0b 96
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 05 14 0b 8c
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 05 10 0b 94
+32 00 80 05 a8 0f 00 20 80 0e 8d 00 01 10 0b 98
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 00 14 03 88
+32 00 80 05 a8 0f 00 20 e0 0e 8d 00 00 10 03 92
+32 00 80 05 a8 0f 00 20 60 01 8d 00 00 00 0b 18
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 04 14 0b 8c
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 04 10 0b 94
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 06 14 0b 8c
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 06 10 0b 94

diff --git a/src/intel/tools/tests/gen7.5/shl.asm b/src/intel/tools/tests/gen7.5/shl.asm
new file mode 100644 (file)
index 0000000..921918a
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/shl.asm
@@ -0,0 +1,15 @@
+shl(1)          a0<1>UW         a0<0,1,0>UW     0x0002UW        { align1 WE_all 1N };
+shl(1)          g12.2<1>UD      g12.2<0,1,0>UD  0x0000000bUD    { align1 WE_all 1N };
+shl(8)          g19<1>D         g18<8,8,1>D     0x00000002UD    { align1 1Q };
+shl(16)         g28<1>D         g26<8,8,1>D     0x00000002UD    { align1 1H };
+shl(8)          g10<1>.xD       g1<0>.yD        0x00000004UD    { align16 1Q };
+shl(8)          g21<1>.xyD      g1<0>.xyyyD     g1<0>.zwwwUD    { align16 1Q };
+shl(8)          g3<1>D          g3<8,8,1>D      g8<8,8,1>UD     { align1 1Q };
+shl(16)         g18<1>D         g4<8,8,1>D      g9<8,8,1>UD     { align1 1H };
+shl(1)          a0<1>UD         g18<0,1,0>UD    0x00000008UD    { align1 WE_all 1N };
+shl(8)          g4<1>.xUD       g17<4>.xUD      g18<4>.xUD      { align16 1Q };
+shl(8)          g14<1>.xUD      g12<4>.yUD      0x00000010UD    { align16 1Q };
+shl(8)          g16<1>.xUD      g15<4>.xUD      g14<4>.xUD      { align16 WE_all 1Q };
+shl(1)          g22<1>UD        g22<0,1,0>UD    0x00000004UD    { align1 WE_all 3N };
+shl(8)          g21<1>UD        g21<8,8,1>UD    0x00000010UD    { align1 1Q };
+shl(16)         g40<1>UD        g40<8,8,1>UD    0x00000010UD    { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/shl.expected b/src/intel/tools/tests/gen7.5/shl.expected
new file mode 100644 (file)
index 0000000..2f453f2
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/shl.expected
@@ -0,0 +1,15 @@
+09 02 00 00 08 2d 00 22 00 02 00 00 02 00 02 00
+09 02 00 00 21 0c 88 21 88 01 00 00 0b 00 00 00
+09 00 60 00 a5 0c 60 22 40 02 8d 00 02 00 00 00
+09 00 80 00 a5 0c 80 23 40 03 8d 00 02 00 00 00
+09 01 60 00 a5 0c 41 21 25 00 05 00 04 00 00 00
+09 01 60 00 a5 04 a3 22 24 00 05 00 2e 00 0f 00
+09 00 60 00 a5 04 60 20 60 00 8d 00 00 01 8d 00
+09 00 80 00 a5 04 40 22 80 00 8d 00 20 01 8d 00
+09 02 00 00 20 0c 00 22 40 02 00 00 08 00 00 00
+09 01 60 00 21 04 81 20 20 02 60 00 40 02 60 00
+09 01 60 00 21 0c c1 21 85 01 65 00 10 00 00 00
+09 03 60 00 21 04 01 22 e0 01 60 00 c0 01 60 00
+09 12 00 00 21 0c c0 22 c0 02 00 00 04 00 00 00
+09 00 60 00 21 0c a0 22 a0 02 8d 00 10 00 00 00
+09 00 80 00 21 0c 00 25 00 05 8d 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen7.5/shr.asm b/src/intel/tools/tests/gen7.5/shr.asm
new file mode 100644 (file)
index 0000000..dcee9b8
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/shr.asm
@@ -0,0 +1,11 @@
+shr(1)          g11<1>UD        g11<0,1,0>UD    0x00000010UD    { align1 1N };
+shr(8)          g20<1>UD        g19<8,8,1>UD    0x00000001UD    { align1 1Q };
+shr(16)         g88<1>UD        g86<8,8,1>UD    0x00000001UD    { align1 1H };
+shr(8)          g10<1>.xyzUD    g1<0>.xyzzUD    g1.4<0>.xyzzUD  { align16 1Q };
+shr(8)          g3<1>UD         g2<0,1,0>UD     g2.2<0,1,0>UD   { align1 1Q };
+shr(16)         g3<1>UD         g2<0,1,0>UD     g2.2<0,1,0>UD   { align1 1H };
+shr(8)          g4<1>.yUD       g1<0>.xUD       0x00000010UD    { align16 NoDDChk 1Q };
+shr(1)          g29<1>UD        g29<0,1,0>UD    5D              { align1 WE_all 1N };
+shr(8)          g8<1>.xUD       g7<4>.xUD       0x00000001UD    { align16 1Q };
+shr(8)          g19<2>UW        g5<8,8,1>UD     g4<8,8,1>UW     { align1 1Q };
+shr(8)          g23<2>UW        g16<8,8,1>UD    g13.8<8,8,1>UW  { align1 2Q };

diff --git a/src/intel/tools/tests/gen7.5/shr.expected b/src/intel/tools/tests/gen7.5/shr.expected
new file mode 100644 (file)
index 0000000..96d7dd5
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/shr.expected
@@ -0,0 +1,11 @@
+08 00 00 00 21 0c 60 21 60 01 00 00 10 00 00 00
+08 00 60 00 21 0c 80 22 60 02 8d 00 01 00 00 00
+08 00 80 00 21 0c 00 2b c0 0a 8d 00 01 00 00 00
+08 01 60 00 21 04 47 21 24 00 0a 00 34 00 0a 00
+08 00 60 00 21 04 60 20 40 00 00 00 48 00 00 00
+08 00 80 00 21 04 60 20 40 00 00 00 48 00 00 00
+08 09 60 00 21 0c 82 20 20 00 00 00 10 00 00 00
+08 02 00 00 21 1c a0 23 a0 03 00 00 05 00 00 00
+08 01 60 00 21 0c 01 21 e0 00 60 00 01 00 00 00
+08 00 60 00 29 24 60 42 a0 00 8d 00 80 00 8d 00
+08 10 60 00 29 24 e0 42 00 02 8d 00 b0 01 8d 00

diff --git a/src/intel/tools/tests/gen7.5/wait.asm b/src/intel/tools/tests/gen7.5/wait.asm
new file mode 100644 (file)
index 0000000..ea69c7e
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/wait.asm
@@ -0,0 +1 @@
+wait(1)                         n0<0>.xUD                       { align16 WE_all 1N };

diff --git a/src/intel/tools/tests/gen7.5/wait.expected b/src/intel/tools/tests/gen7.5/wait.expected
new file mode 100644 (file)
index 0000000..c227101
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/wait.expected
@@ -0,0 +1 @@
+30 03 00 00 00 70 01 32 00 12 00 00 04 00 6e 00

diff --git a/src/intel/tools/tests/gen7.5/while.asm b/src/intel/tools/tests/gen7.5/while.asm
new file mode 100644 (file)
index 0000000..a6d5abc
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/while.asm
@@ -0,0 +1,6 @@
+while(8)        JIP: -20                                        { align1 1Q };
+while(16)       JIP: -20                                        { align1 1H };
+while(8)        JIP: -30                                        { align16 1Q };
+(-f0.0) while(8) JIP: -48                                       { align1 1Q };
+(-f0.0) while(16) JIP: -48                                      { align1 1H };
+(-f0.0.x) while(8) JIP: -48                                     { align16 1Q };

diff --git a/src/intel/tools/tests/gen7.5/while.expected b/src/intel/tools/tests/gen7.5/while.expected
new file mode 100644 (file)
index 0000000..769cbaf
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/while.expected
@@ -0,0 +1,6 @@
+27 00 60 00 84 3c 00 20 00 00 8d 00 ec ff 00 00
+27 00 80 00 84 3c 00 20 00 00 8d 00 ec ff 00 00
+27 01 60 00 84 3c 0f 20 04 00 6e 00 e2 ff 00 00
+27 00 71 00 84 3c 00 20 00 00 8d 00 d0 ff 00 00
+27 00 91 00 84 3c 00 20 00 00 8d 00 d0 ff 00 00
+27 01 72 00 84 3c 0f 20 04 00 6e 00 d0 ff 00 00

diff --git a/src/intel/tools/tests/gen7.5/xor.asm b/src/intel/tools/tests/gen7.5/xor.asm
new file mode 100644 (file)
index 0000000..3b99c73
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/xor.asm
@@ -0,0 +1,5 @@
+xor(8)          g14<1>.xUD      g5.4<0>.zUD     g13<4>.xUD      { align16 1Q };
+xor(8)          g4<1>UD         g2<0,1,0>UD     g3<8,8,1>UD     { align1 1Q };
+xor(16)         g5<1>UD         g2<0,1,0>UD     g3<8,8,1>UD     { align1 1H };
+xor(8)          g124<1>UD       g5<8,8,1>UD     0x000003ffUD    { align1 1Q };
+xor(16)         g120<1>UD       g13<8,8,1>UD    0x000003ffUD    { align1 1H };

diff --git a/src/intel/tools/tests/gen7.5/xor.expected b/src/intel/tools/tests/gen7.5/xor.expected
new file mode 100644 (file)
index 0000000..387688e
--- /dev/null
+++ b/src/intel/tools/tests/gen7.5/xor.expected
@@ -0,0 +1,5 @@
+07 01 60 00 21 04 c1 21 ba 00 0a 00 a0 01 60 00
+07 00 60 00 21 04 80 20 40 00 00 00 60 00 8d 00
+07 00 80 00 21 04 a0 20 40 00 00 00 60 00 8d 00
+07 00 60 00 21 0c 80 2f a0 00 8d 00 ff 03 00 00
+07 00 80 00 21 0c 00 2f a0 01 8d 00 ff 03 00 00

diff --git a/src/intel/tools/tests/gen7/add.asm b/src/intel/tools/tests/gen7/add.asm
new file mode 100644 (file)
index 0000000..e3d3dfe
--- /dev/null
+++ b/src/intel/tools/tests/gen7/add.asm
@@ -0,0 +1,54 @@
+add(16)         g6<1>UW         g1.4<1,4,0>UW   0x11001010V     { align1 WE_all 1H };
+add(16)         g4<1>UW         g1.4<2,4,0>UW   0x10101010V     { align1 1H };
+add(1)          g11.4<1>UD      g11<0,1,0>UD    0x00000001UD    { align1 1N };
+add(8)          g17<1>F         g6<0>F          g7.4<0>F        { align16 1Q };
+add(1)          a0<1>UW         g11<0,1,0>UW    0x0008UW        { align1 WE_all 1N };
+add(8)          g46<1>F         g42<8,8,1>F     -g4.4<0,1,0>F   { align1 1Q };
+add(16)         g19<1>F         g11<8,8,1>F     -g6.4<0,1,0>F   { align1 1H };
+add(1)          g126.4<1>D      g39.4<0,1,0>D   1D              { align1 WE_all 1N };
+add(8)          g124<1>D        g3.3<0,1,0>D    g2<0,1,0>D      { align1 1Q };
+add(16)         g120<1>D        g3.3<0,1,0>D    g2<0,1,0>D      { align1 1H };
+add(8)          g98<1>.xD       g96<4>.xD       1D              { align16 1Q };
+add(8)          g80<1>.xD       g4<0>.zD        g96<4>.xD       { align16 1Q };
+add(8)          g8<1>F          g5<8,8,1>F      0xbd4ccccdF  /* -0.05F */ { align1 1Q };
+add(16)         g12<1>F         g9<8,8,1>F      0xbd4ccccdF  /* -0.05F */ { align1 1H };
+add(8)          g28<1>.xF       g58<4>.xF       0xbf800000F  /* -1F */ { align16 1Q };
+add(8)          g114<1>.xD      g4<4>.xD        7D              { align16 NoDDClr 1Q };
+add(8)          g124<1>F        g43<8,8,1>D     1D              { align1 1Q };
+add(16)         g120<1>F        g79<8,8,1>D     1D              { align1 1H };
+add(8)          g115<1>.xyF     g10<4>.xyyyF    0x3f000000F  /* 0.5F */ { align16 NoDDClr 1Q };
+add(8)          g3<1>D          g3<8,8,1>D      12D             { align1 1Q };
+add(16)         g5<1>D          g3<8,8,1>D      12D             { align1 1H };
+add(8)          g114<1>.xyzD    g4<4>.xyzzD     g7<4>.xyzzD     { align16 NoDDClr 1Q };
+add(8)          g11<1>F         g10<4>.xF       0x48403000VF /* [0F, 1F, 2F, 3F]VF */ { align16 1Q };
+add(8)          g27<1>.xUD      g21<4>.xUD      0xffffffffUD    { align16 1Q };
+add(8)          g116<1>.zD      g1<0>.xD        2D              { align16 NoDDClr,NoDDChk 1Q };
+add(8)          g117<1>.wD      g1<0>.xD        7D              { align16 NoDDChk 1Q };
+add(8)          g3<1>.yF        g5<4>.xF        -g1<0>.xF       { align16 NoDDClr 1Q };
+add(8)          g3<1>.yF        g13<4>.xF       -g1<0>.xF       { align16 NoDDClr,NoDDChk 1Q };
+add(8)          g66<1>.zF       g1<0>.xF        0x41f80000F  /* 31F */ { align16 NoDDChk 1Q };
+add(8)          g117<1>.zF      g1<0>.xF        0x40000000F  /* 2F */ { align16 NoDDClr,NoDDChk 1Q };
+(+f0.0) add(8)  g16<1>D         -g16<4>D        31D             { align16 1Q };
+add(8)          a0<1>UW         g3<16,8,2>UW    0x004cUW        { align1 1Q };
+add(8)          a0<1>UW         g4<16,8,2>UW    0x004cUW        { align1 2Q };
+add(8)          g4.1<2>UW       g4.1<16,8,2>UW  g16<16,8,2>UW   { align1 1Q };
+add(16)         g4.1<2>UW       g4.1<16,8,2>UW  g10<16,8,2>UW   { align1 1H };
+add.sat(8)      g116<1>F        g2<4>.yzxwF     -g2<4>F         { align16 1Q };
+add(8)          g8<1>UD         g6<8,8,1>D      0x00000001UD    { align1 1Q };
+add(16)         g11<1>UD        g9<8,8,1>D      0x00000001UD    { align1 1H };
+(+f0.0) add(8)  g7<1>D          -g7<8,8,1>D     31D             { align1 1Q };
+(+f0.0) add(16) g8<1>D          -g8<8,8,1>D     31D             { align1 1H };
+add(8)          g115<1>.xyF     g2<4>.xyyyF     g1<0>.xyyyF     { align16 NoDDChk 1Q };
+add(8)          g117<1>.xyD     g6<4>.xyyyD     g12<4>.xD       { align16 NoDDClr,NoDDChk 1Q };
+add(8)          g13<1>UD        g11<8,8,1>UD    1D              { align1 1Q };
+add(16)         g19<1>UD        g16<8,8,1>UD    1D              { align1 1H };
+add(8)          g2<1>UD         g9<0,1,0>UD     g8<1,4,0>UW     { align1 1Q };
+add(8)          g3<1>UD         g9<0,1,0>UD     g8.2<1,4,0>UW   { align1 2Q };
+add.sat(8)      g124<1>F        g2<8,8,1>F      g10<8,8,1>F     { align1 1Q };
+add.sat(16)     g120<1>F        g2<8,8,1>F      g18<8,8,1>F     { align1 1H };
+add(1)          g2<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 WE_all 1N };
+add(8)          g7<1>UD         g2<8,8,1>UD     -g6<8,8,1>UD    { align1 WE_all 1Q };
+add.sat(8)      g22<1>.xUD      g20<4>.xUD      g10<4>.xUD      { align16 1Q };
+add.sat(8)      g116<1>F        g5<4>.xF        0xbf800000F  /* -1F */ { align16 1Q };
+add(1)          a0<1>UD         a0<0,1,0>UD     0x00000200UD    { align1 WE_all 1N };
+add(8)          g18<1>F         -g16<4>.xyxyF   g16<4>.zwzwF    { align16 2Q };

diff --git a/src/intel/tools/tests/gen7/add.expected b/src/intel/tools/tests/gen7/add.expected
new file mode 100644 (file)
index 0000000..bf8583b
--- /dev/null
+++ b/src/intel/tools/tests/gen7/add.expected
@@ -0,0 +1,54 @@
+40 02 80 00 29 6d c0 20 28 00 28 00 10 10 00 11
+40 00 80 00 29 6d 80 20 28 00 48 00 10 10 10 10
+40 00 00 00 21 0c 70 21 60 01 00 00 01 00 00 00
+40 01 60 00 bd 77 2f 22 c4 00 0e 00 f4 00 0e 00
+40 02 00 00 28 2d 00 22 60 01 00 00 08 00 08 00
+40 00 60 00 bd 77 c0 25 40 05 8d 00 90 40 00 00
+40 00 80 00 bd 77 60 22 60 01 8d 00 d0 40 00 00
+40 02 00 00 a5 1c d0 2f f0 04 00 00 01 00 00 00
+40 00 60 00 a5 14 80 2f 6c 00 00 00 40 00 00 00
+40 00 80 00 a5 14 00 2f 6c 00 00 00 40 00 00 00
+40 01 60 00 a5 1c 41 2c 00 0c 60 00 01 00 00 00
+40 01 60 00 a5 14 01 2a 8a 00 0a 00 00 0c 60 00
+40 00 60 00 bd 7f 00 21 a0 00 8d 00 cd cc 4c bd
+40 00 80 00 bd 7f 80 21 20 01 8d 00 cd cc 4c bd
+40 01 60 00 bd 7f 81 23 40 07 60 00 00 00 80 bf
+40 05 60 00 a5 1c 41 2e 80 00 60 00 07 00 00 00
+40 00 60 00 bd 1c 80 2f 60 05 8d 00 01 00 00 00
+40 00 80 00 bd 1c 00 2f e0 09 8d 00 01 00 00 00
+40 05 60 00 bd 7f 63 2e 44 01 65 00 00 00 00 3f
+40 00 60 00 a5 1c 60 20 60 00 8d 00 0c 00 00 00
+40 00 80 00 a5 1c a0 20 60 00 8d 00 0c 00 00 00
+40 05 60 00 a5 14 47 2e 84 00 6a 00 e4 00 6a 00
+40 01 60 00 bd 5f 6f 21 40 01 60 00 00 30 40 48
+40 01 60 00 21 0c 61 23 a0 02 60 00 ff ff ff ff
+40 0d 60 00 a5 1c 84 2e 20 00 00 00 02 00 00 00
+40 09 60 00 a5 1c a8 2e 20 00 00 00 07 00 00 00
+40 05 60 00 bd 77 62 20 a0 00 60 00 20 40 00 00
+40 0d 60 00 bd 77 62 20 a0 01 60 00 20 40 00 00
+40 09 60 00 bd 7f 44 28 20 00 00 00 00 00 f8 41
+40 0d 60 00 bd 7f a4 2e 20 00 00 00 00 00 00 40
+40 01 61 00 a5 1c 0f 22 04 42 6e 00 1f 00 00 00
+40 00 60 00 28 2d 00 22 60 00 ae 00 4c 00 4c 00
+40 10 60 00 28 2d 00 22 80 00 ae 00 4c 00 4c 00
+40 00 60 00 29 25 82 40 82 00 ae 00 00 02 ae 00
+40 00 80 00 29 25 82 40 82 00 ae 00 40 01 ae 00
+40 01 60 80 bd 77 8f 2e 49 00 6c 00 44 40 6e 00
+40 00 60 00 a1 0c 00 21 c0 00 8d 00 01 00 00 00
+40 00 80 00 a1 0c 60 21 20 01 8d 00 01 00 00 00
+40 00 61 00 a5 1c e0 20 e0 40 8d 00 1f 00 00 00
+40 00 81 00 a5 1c 00 21 00 41 8d 00 1f 00 00 00
+40 09 60 00 bd 77 63 2e 44 00 65 00 24 00 05 00
+40 0d 60 00 a5 14 a3 2e c4 00 65 00 80 01 60 00
+40 00 60 00 21 1c a0 21 60 01 8d 00 01 00 00 00
+40 00 80 00 21 1c 60 22 00 02 8d 00 01 00 00 00
+40 00 60 00 21 24 40 20 20 01 00 00 00 01 28 00
+40 10 60 00 21 24 60 20 20 01 00 00 04 01 28 00
+40 00 60 80 bd 77 80 2f 40 00 8d 00 40 01 8d 00
+40 00 80 80 bd 77 00 2f 40 00 8d 00 40 02 8d 00
+40 02 00 00 21 0c 40 20 40 00 00 00 01 00 00 00
+40 02 60 00 21 04 e0 20 40 00 8d 00 c0 40 8d 00
+40 01 60 80 21 04 c1 22 80 02 60 00 40 01 60 00
+40 01 60 80 bd 7f 8f 2e a0 00 60 00 00 00 80 bf
+40 02 00 00 00 0c 00 22 00 02 00 00 00 02 00 00
+40 11 60 00 bd 77 4f 22 04 42 64 00 0e 02 6e 00

diff --git a/src/intel/tools/tests/gen7/and.asm b/src/intel/tools/tests/gen7/and.asm
new file mode 100644 (file)
index 0000000..34bcffc
--- /dev/null
+++ b/src/intel/tools/tests/gen7/and.asm
@@ -0,0 +1,30 @@
+and(1)          g11<1>UD        g0.2<0,1,0>UD   0x007f0000UD    { align1 1N };
+and(1)          g12.2<1>UD      g0.2<0,1,0>UD   0x0000f000UD    { align1 WE_all 1N };
+and(8)          g13<1>UD        g6<0>UD         g5.4<0>.zUD     { align16 1Q };
+and(8)          g59<1>.xUD      g38<4>.xUD      0x00000001UD    { align16 1Q };
+and(8)          g22<1>UD        g21<8,8,1>UD    g20<8,8,1>UD    { align1 1Q };
+and.nz.f0.0(8)  null<1>UD       g24<8,8,1>UD    g25<8,8,1>UD    { align1 1Q };
+and(16)         g41<1>UD        g39<8,8,1>UD    g37<8,8,1>UD    { align1 1H };
+and.nz.f0.0(16) null<1>UD       g45<8,8,1>UD    g47<8,8,1>UD    { align1 1H };
+and(8)          g12<1>UD        g11<8,8,1>UD    0x00000001UD    { align1 1Q };
+and(16)         g19<1>UD        g17<8,8,1>UD    0x00000001UD    { align1 1H };
+and(8)          g8<1>UD         g0.1<0,1,0>UW   0x07ffUW        { align1 1Q };
+and(16)         g20<1>UD        g0.1<0,1,0>UW   0x07ffUW        { align1 1H };
+and(1)          a0<1>UD         g9<0,1,0>UD     0x000000ffUD    { align1 WE_all 1N };
+and.nz.f0.0(8)  null<1>.xUD     g82<4>.xUD      g81<4>.xUD      { align16 1Q };
+and(1)          g2<1>UD         g19<0,1,0>UD    0x000000ffUD    { align1 WE_all 3N };
+and.nz.f0.0(8)  null<1>UD       g4<0,1,0>UD     0x00000001UD    { align1 1Q };
+and.nz.f0.0(16) null<1>UD       g6<0,1,0>UD     0x00000001UD    { align1 1H };
+and.z.f0.0(8)   null<1>UD       g20<8,8,1>UD    0x00000001UD    { align1 1Q };
+and.z.f0.0(16)  null<1>UD       g44<8,8,1>UD    0x00000001UD    { align1 1H };
+and(1)          a0<1>UD         a0<0,1,0>UD     0x00000fffUD    { align1 WE_all 1N };
+and.z.f0.0(8)   null<1>UD       g9<4>.xUD       0x0000001fUD    { align16 1Q };
+and(8)          g57<1>.xUD      g54<4>.xUD      0x00000003UD    { align16 WE_all 1Q };
+and(8)          g6<1>UD         g2<8,8,1>UD     0x00000003UD    { align1 WE_all 1Q };
+and(2)          g99<1>UD        g1.3<0,1,0>UD   0x00001fffUD    { align1 WE_all 1N };
+and.nz.f0.0(8)  g10<1>UD        g9<8,8,1>UD     0x00000001UD    { align1 1Q };
+and.nz.f0.0(16) g15<1>UD        g13<8,8,1>UD    0x00000001UD    { align1 1H };
+and.nz.f0.0(8)  g20<1>UD        g19<8,8,1>UD    g18<8,8,1>UD    { align1 1Q };
+and.nz.f0.0(16) g34<1>UD        g32<8,8,1>UD    g30<8,8,1>UD    { align1 1H };
+and.z.f0.0(8)   null<1>UD       g7<8,8,1>UD     g21<8,8,1>UD    { align1 1Q };
+and.z.f0.0(16)  null<1>UD       g8<8,8,1>UD     g35<8,8,1>UD    { align1 1H };

diff --git a/src/intel/tools/tests/gen7/and.expected b/src/intel/tools/tests/gen7/and.expected
new file mode 100644 (file)
index 0000000..8c9a40c
--- /dev/null
+++ b/src/intel/tools/tests/gen7/and.expected
@@ -0,0 +1,30 @@
+05 00 00 00 21 0c 60 21 08 00 00 00 00 00 7f 00
+05 02 00 00 21 0c 88 21 08 00 00 00 00 f0 00 00
+05 01 60 00 21 04 af 21 c4 00 0e 00 ba 00 0a 00
+05 01 60 00 21 0c 61 27 c0 04 60 00 01 00 00 00
+05 00 60 00 21 04 c0 22 a0 02 8d 00 80 02 8d 00
+05 00 60 02 20 04 00 20 00 03 8d 00 20 03 8d 00
+05 00 80 00 21 04 20 25 e0 04 8d 00 a0 04 8d 00
+05 00 80 02 20 04 00 20 a0 05 8d 00 e0 05 8d 00
+05 00 60 00 21 0c 80 21 60 01 8d 00 01 00 00 00
+05 00 80 00 21 0c 60 22 20 02 8d 00 01 00 00 00
+05 00 60 00 21 2d 00 21 02 00 00 00 ff 07 ff 07
+05 00 80 00 21 2d 80 22 02 00 00 00 ff 07 ff 07
+05 02 00 00 20 0c 00 22 20 01 00 00 ff 00 00 00
+05 01 60 02 20 04 01 20 40 0a 60 00 20 0a 60 00
+05 12 00 00 21 0c 40 20 60 02 00 00 ff 00 00 00
+05 00 60 02 20 0c 00 20 80 00 00 00 01 00 00 00
+05 00 80 02 20 0c 00 20 c0 00 00 00 01 00 00 00
+05 00 60 01 20 0c 00 20 80 02 8d 00 01 00 00 00
+05 00 80 01 20 0c 00 20 80 05 8d 00 01 00 00 00
+05 02 00 00 00 0c 00 22 00 02 00 00 ff 0f 00 00
+05 01 60 01 20 0c 0f 20 20 01 60 00 1f 00 00 00
+05 03 60 00 21 0c 21 27 c0 06 60 00 03 00 00 00
+05 02 60 00 21 0c c0 20 40 00 8d 00 03 00 00 00
+05 02 20 00 21 0c 60 2c 2c 00 00 00 ff 1f 00 00
+05 00 60 02 21 0c 40 21 20 01 8d 00 01 00 00 00
+05 00 80 02 21 0c e0 21 a0 01 8d 00 01 00 00 00
+05 00 60 02 21 04 80 22 60 02 8d 00 40 02 8d 00
+05 00 80 02 21 04 40 24 00 04 8d 00 c0 03 8d 00
+05 00 60 01 20 04 00 20 e0 00 8d 00 a0 02 8d 00
+05 00 80 01 20 04 00 20 00 01 8d 00 60 04 8d 00

diff --git a/src/intel/tools/tests/gen7/asr.asm b/src/intel/tools/tests/gen7/asr.asm
new file mode 100644 (file)
index 0000000..e85346b
--- /dev/null
+++ b/src/intel/tools/tests/gen7/asr.asm
@@ -0,0 +1,8 @@
+asr(8)          g13<1>.xD       g5.4<0>.zD      g5.4<0>.wUD     { align16 1Q };
+asr(8)          g57<1>.xD       g38<4>.xD       0x00000001UD    { align16 1Q };
+asr(8)          g6<1>D          g5<8,8,1>D      0x00000001UD    { align1 1Q };
+asr(16)         g8<1>D          g6<8,8,1>D      0x00000001UD    { align1 1H };
+asr.nz.f0.0(8)  null<1>D        -g0<0,1,0>W     15D             { align1 1Q };
+asr.nz.f0.0(16) null<1>D        -g0<0,1,0>W     15D             { align1 1H };
+asr(8)          g2<1>D          -g0<0,1,0>W     15D             { align1 1Q };
+asr(16)         g2<1>D          -g0<0,1,0>W     15D             { align1 1H };

diff --git a/src/intel/tools/tests/gen7/asr.expected b/src/intel/tools/tests/gen7/asr.expected
new file mode 100644 (file)
index 0000000..ea6ae73
--- /dev/null
+++ b/src/intel/tools/tests/gen7/asr.expected
@@ -0,0 +1,8 @@
+0c 01 60 00 a5 04 a1 21 ba 00 0a 00 bf 00 0f 00
+0c 01 60 00 a5 0c 21 27 c0 04 60 00 01 00 00 00
+0c 00 60 00 a5 0c c0 20 a0 00 8d 00 01 00 00 00
+0c 00 80 00 a5 0c 00 21 c0 00 8d 00 01 00 00 00
+0c 00 60 02 a4 1d 00 20 00 40 00 00 0f 00 00 00
+0c 00 80 02 a4 1d 00 20 00 40 00 00 0f 00 00 00
+0c 00 60 00 a5 1d 40 20 00 40 00 00 0f 00 00 00
+0c 00 80 00 a5 1d 40 20 00 40 00 00 0f 00 00 00

diff --git a/src/intel/tools/tests/gen7/bfe.asm b/src/intel/tools/tests/gen7/bfe.asm
new file mode 100644 (file)
index 0000000..d19155e
--- /dev/null
+++ b/src/intel/tools/tests/gen7/bfe.asm
@@ -0,0 +1,4 @@
+bfe(8)          g33<1>UD        g50<4,4,1>UD    g64<4,4,1>UD    g31<4,4,1>UD { align16 1Q };
+bfe(8)          g61<1>UD        g92<4,4,1>UD    g20<4,4,1>UD    g57<4,4,1>UD { align16 2Q };
+bfe(8)          g20<1>D         g18<4,4,1>.xD   g17<4,4,1>.xD   g16<4,4,1>D { align16 1Q };
+bfe(8)          g14<1>D         g12<4,4,1>D     g43<4,4,1>D     g6<4,4,1>D { align16 2Q };

diff --git a/src/intel/tools/tests/gen7/bfe.expected b/src/intel/tools/tests/gen7/bfe.expected
new file mode 100644 (file)
index 0000000..bf16a1c
--- /dev/null
+++ b/src/intel/tools/tests/gen7/bfe.expected
@@ -0,0 +1,4 @@
+18 01 60 00 00 28 1e 21 c8 21 03 39 80 20 c7 07
+18 11 60 00 00 28 1e 3d c8 c1 05 39 28 20 47 0e
+18 01 60 00 00 14 1e 14 00 20 01 00 22 20 07 04
+18 11 60 00 00 14 1e 0e c8 c1 00 39 56 20 87 01

diff --git a/src/intel/tools/tests/gen7/bfi1.asm b/src/intel/tools/tests/gen7/bfi1.asm
new file mode 100644 (file)
index 0000000..317b5cb
--- /dev/null
+++ b/src/intel/tools/tests/gen7/bfi1.asm
@@ -0,0 +1,3 @@
+bfi1(8)         g22<1>UD        g20<4>.xD       g19<4>.xD       { align16 1Q };
+bfi1(8)         g12<1>UD        g11<8,8,1>D     g10<8,8,1>D     { align1 1Q };
+bfi1(16)        g16<1>UD        g14<8,8,1>D     g12<8,8,1>D     { align1 1H };

diff --git a/src/intel/tools/tests/gen7/bfi1.expected b/src/intel/tools/tests/gen7/bfi1.expected
new file mode 100644 (file)
index 0000000..53d5c12
--- /dev/null
+++ b/src/intel/tools/tests/gen7/bfi1.expected
@@ -0,0 +1,3 @@
+19 01 60 00 a1 14 cf 22 80 02 60 00 60 02 60 00
+19 00 60 00 a1 14 80 21 60 01 8d 00 40 01 8d 00
+19 00 80 00 a1 14 00 22 c0 01 8d 00 80 01 8d 00

diff --git a/src/intel/tools/tests/gen7/bfi2.asm b/src/intel/tools/tests/gen7/bfi2.asm
new file mode 100644 (file)
index 0000000..052ba3e
--- /dev/null
+++ b/src/intel/tools/tests/gen7/bfi2.asm
@@ -0,0 +1,2 @@
+bfi2(8)         g23<1>UD        g22<4,4,1>UD    g18<4,4,1>UD    g17<4,4,1>UD { align16 1Q };
+bfi2(8)         g19<1>UD        g17<4,4,1>UD    g54<4,4,1>UD    g7<4,4,1>UD { align16 2Q };

diff --git a/src/intel/tools/tests/gen7/bfi2.expected b/src/intel/tools/tests/gen7/bfi2.expected
new file mode 100644 (file)
index 0000000..c7efdcd
--- /dev/null
+++ b/src/intel/tools/tests/gen7/bfi2.expected
@@ -0,0 +1,2 @@
+1a 01 60 00 00 28 1e 17 c8 61 01 39 24 20 47 04
+1a 11 60 00 00 28 1e 13 c8 11 01 39 6c 20 c7 01

diff --git a/src/intel/tools/tests/gen7/bfrev.asm b/src/intel/tools/tests/gen7/bfrev.asm
new file mode 100644 (file)
index 0000000..101d2cc
--- /dev/null
+++ b/src/intel/tools/tests/gen7/bfrev.asm
@@ -0,0 +1,3 @@
+bfrev(8)        g5<1>UD         g5<8,8,1>UD                     { align1 1Q };
+bfrev(16)       g6<1>UD         g8<8,8,1>UD                     { align1 1H };
+bfrev(8)        g11<1>UD        g10<4>UD                        { align16 1Q };

diff --git a/src/intel/tools/tests/gen7/bfrev.expected b/src/intel/tools/tests/gen7/bfrev.expected
new file mode 100644 (file)
index 0000000..5dda563
--- /dev/null
+++ b/src/intel/tools/tests/gen7/bfrev.expected
@@ -0,0 +1,3 @@
+17 00 60 00 21 00 a0 20 a0 00 8d 00 00 00 00 00
+17 00 80 00 21 00 c0 20 00 01 8d 00 00 00 00 00
+17 01 60 00 21 00 6f 21 44 01 6e 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/break.asm b/src/intel/tools/tests/gen7/break.asm
new file mode 100644 (file)
index 0000000..5a51f7a
--- /dev/null
+++ b/src/intel/tools/tests/gen7/break.asm
@@ -0,0 +1,6 @@
+break(8)        JIP: 2          UIP: 40                         { align1 1Q };
+break(16)       JIP: 2          UIP: 48                         { align1 1H };
+(+f0.0.x) break(8) JIP: 110     UIP: 110                        { align16 1Q };
+(+f0.0) break(8) JIP: 2         UIP: 12                         { align1 1Q };
+(+f0.0) break(16) JIP: 2        UIP: 12                         { align1 1H };
+break(8)        JIP: 2          UIP: 38                         { align16 1Q };

diff --git a/src/intel/tools/tests/gen7/break.expected b/src/intel/tools/tests/gen7/break.expected
new file mode 100644 (file)
index 0000000..9cc7f8a
--- /dev/null
+++ b/src/intel/tools/tests/gen7/break.expected
@@ -0,0 +1,6 @@
+28 00 60 00 84 1c 00 20 00 00 8d 00 02 00 28 00
+28 00 80 00 84 1c 00 20 00 00 8d 00 02 00 30 00
+28 01 62 00 84 1c 0f 20 04 00 6e 00 6e 00 6e 00
+28 00 61 00 84 1c 00 20 00 00 8d 00 02 00 0c 00
+28 00 81 00 84 1c 00 20 00 00 8d 00 02 00 0c 00
+28 01 60 00 84 1c 0f 20 04 00 6e 00 02 00 26 00

diff --git a/src/intel/tools/tests/gen7/cbit.asm b/src/intel/tools/tests/gen7/cbit.asm
new file mode 100644 (file)
index 0000000..2a62b07
--- /dev/null
+++ b/src/intel/tools/tests/gen7/cbit.asm
@@ -0,0 +1,3 @@
+cbit(8)         g5<1>UD         g5<8,8,1>UD                     { align1 1Q };
+cbit(16)        g6<1>UD         g8<8,8,1>UD                     { align1 1H };
+cbit(8)         g11<1>UD        g10<4>UD                        { align16 1Q };

diff --git a/src/intel/tools/tests/gen7/cbit.expected b/src/intel/tools/tests/gen7/cbit.expected
new file mode 100644 (file)
index 0000000..e4560c3
--- /dev/null
+++ b/src/intel/tools/tests/gen7/cbit.expected
@@ -0,0 +1,3 @@
+4d 00 60 00 21 00 a0 20 a0 00 8d 00 00 00 00 00
+4d 00 80 00 21 00 c0 20 00 01 8d 00 00 00 00 00
+4d 01 60 00 21 00 6f 21 44 01 6e 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/cmp.asm b/src/intel/tools/tests/gen7/cmp.asm
new file mode 100644 (file)
index 0000000..3ac02d9
--- /dev/null
+++ b/src/intel/tools/tests/gen7/cmp.asm
@@ -0,0 +1,146 @@
+cmp.ge.f0.0(8)  null<1>F        g45<4>.xF       g43<4>.xF       { align16 1Q switch };
+cmp.g.f0.0(8)   g18<1>.xyF      g13<4>.zwwwF    0x3f800000F  /* 1F */ { align16 1Q };
+cmp.nz.f0.0(8)  null<1>D        g18<4>.xyyyD    0D              { align16 1Q switch };
+cmp.g.f0.0(8)   null<1>F        g14<4>F         0x3f800000F  /* 1F */ { align16 1Q switch };
+cmp.le.f0.0(8)  g24<1>.xyF      g13<4>.zwwwF    0x3f800000F  /* 1F */ { align16 1Q };
+cmp.nz.f0.0(8)  null<1>F        g3<0>.xyzzF     0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16 1Q switch };
+cmp.z.f0.0(8)   null<1>D        g13<4>.xyyyD    g6<0>.yzzzD     { align16 1Q switch };
+cmp.ge.f0.0(8)  g33<1>F         g32<8,8,1>F     0x3189705fF  /* 4e-09F */ { align1 1Q };
+cmp.l.f0.0(8)   g34<1>F         g32<8,8,1>F     0x3189705fF  /* 4e-09F */ { align1 1Q };
+cmp.ge.f0.0(8)  g2<1>F          g23<8,8,1>F     g51<0,1,0>F     { align1 1Q };
+cmp.l.f0.0(8)   g5<1>F          g23<8,8,1>F     g51<0,1,0>F     { align1 1Q };
+cmp.ge.f0.0(8)  g3<1>F          g4<8,8,1>F      g51<0,1,0>F     { align1 2Q };
+cmp.l.f0.0(8)   g6<1>F          g4<8,8,1>F      g51<0,1,0>F     { align1 2Q };
+cmp.z.f0.0(8)   null<1>D        g4<0>.xD        0D              { align16 1Q switch };
+cmp.l.f0.0(8)   null<1>F        g35<4>.xF       0x3189705fF  /* 4e-09F */ { align16 1Q switch };
+cmp.z.f0.0(8)   null<1>F        g3<0>.zwwwF     g3<0>.xyyyF     { align16 1Q switch };
+cmp.l.f0.0(8)   g12<1>.xF       g5.4<0>.zF      g5.4<0>.wF      { align16 1Q };
+cmp.ge.f0.0(8)  g9<1>.xF        g1<0>.xF        g1<0>.yF        { align16 1Q };
+cmp.nz.f0.0(8)  null<1>F        g42<4>F         g3<0>F          { align16 1Q switch };
+cmp.l.f0.0(8)   null<1>UD       g6<4>.xUD       0x00000003UD    { align16 1Q switch };
+cmp.l.f0.0(8)   null<1>D        g4<0,1,0>D      1D              { align1 1Q switch };
+cmp.z.f0.0(8)   g20<1>F         g3<8,8,1>F      g4.3<0,1,0>F    { align1 1Q };
+cmp.l.f0.0(16)  null<1>D        g6<0,1,0>D      1D              { align1 1H switch };
+cmp.z.f0.0(8)   g38<1>F         g5<8,8,1>F      g6.3<0,1,0>F    { align1 2Q };
+cmp.z.f0.0(8)   g5<1>D          g2.1<0,1,0>D    39D             { align1 1Q };
+cmp.z.f0.0(8)   g6<1>D          g2.1<0,1,0>D    39D             { align1 2Q };
+cmp.le.f0.0(8)  null<1>.zF      g7<4>.xF        0x0F  /* 0F */  { align16 1Q switch };
+cmp.z.f0.0(8)   g3<1>F          g2.1<0,1,0>F    0x41000000F  /* 8F */ { align1 1Q };
+cmp.z.f0.0(8)   g4<1>F          g2.1<0,1,0>F    0x41000000F  /* 8F */ { align1 2Q };
+cmp.z.f0.0(8)   null<1>D        g4<0,1,0>D      1D              { align1 1Q switch };
+cmp.z.f0.0(8)   null<1>F        g10<8,8,1>F     g4.1<0,1,0>F    { align1 1Q switch };
+cmp.z.f0.0(16)  null<1>D        g6<0,1,0>D      1D              { align1 1H switch };
+cmp.z.f0.0(16)  null<1>D        g17<8,8,1>F     g6.1<0,1,0>F    { align1 1H switch };
+cmp.z.f0.0(8)   g31<1>.yzwD     g3<0>.xD        g19<4>.yyzwD    { align16 1Q };
+cmp.nz.f0.0(8)  g8<1>D          g5<8,8,1>D      g3.1<0,1,0>D    { align1 1Q };
+cmp.nz.f0.0(8)  g13<1>D         g7<8,8,1>D      g3.1<0,1,0>D    { align1 2Q };
+cmp.nz.f0.0(8)  g6<1>F          g5<8,8,1>F      g2.2<0,1,0>F    { align1 1Q };
+cmp.nz.f0.0(8)  g9<1>F          g7<8,8,1>F      g2.2<0,1,0>F    { align1 2Q };
+cmp.ge.f0.0(8)  g12<1>.xD       g5.4<0>.zD      g5.4<0>.wD      { align16 1Q };
+cmp.nz.f0.0(8)  null<1>D        g4<0,1,0>D      0D              { align1 1Q switch };
+cmp.nz.f0.0(16) null<1>D        g6<0,1,0>D      0D              { align1 1H switch };
+cmp.nz.f0.0(8)  null<1>D        g3<0>.xyzzD     g33<4>.xyzzD    { align16 1Q switch };
+cmp.z.f0.0(8)   null<1>.xF      (abs)g13<4>.xF  0x7f800000F  /* infF */ { align16 1Q switch };
+cmp.nz.f0.0(8)  null<1>F        g13<4>.xF       0x0F  /* 0F */  { align16 1Q switch };
+cmp.l.f0.0(8)   null<1>.xF      g5<4>.xF        g13<4>.xF       { align16 1Q switch };
+cmp.l.f0.0(8)   g10<1>UD        g9<4>UD         g1<0>UD         { align16 1Q };
+cmp.g.f0.0(8)   g32<1>F         g31<8,8,1>F     0x3727c5acF  /* 1e-05F */ { align1 1Q };
+cmp.le.f0.0(8)  g33<1>F         g31<8,8,1>F     0x3727c5acF  /* 1e-05F */ { align1 1Q };
+cmp.g.f0.0(8)   g11<1>F         g9<8,8,1>F      g42<0,1,0>F     { align1 1Q };
+cmp.g.f0.0(8)   g12<1>F         g10<8,8,1>F     g42<0,1,0>F     { align1 2Q };
+cmp.le.f0.0(8)  g13<1>F         g9<8,8,1>F      g42<0,1,0>F     { align1 1Q };
+cmp.le.f0.0(8)  g14<1>F         g10<8,8,1>F     g42<0,1,0>F     { align1 2Q };
+cmp.z.f0.0(8)   g11<1>F         g9<4>.xF        g2<4>F          { align16 1Q };
+cmp.nz.f0.0(8)  g4<1>D          g2.3<0,1,0>D    0D              { align1 1Q };
+cmp.nz.f0.0(8)  g6<1>D          g2.3<0,1,0>D    0D              { align1 2Q };
+cmp.z.f0.0(8)   null<1>F        g4.1<0,1,0>F    0x3f800000F  /* 1F */ { align1 1Q switch };
+cmp.z.f0.0(16)  null<1>D        g6.1<0,1,0>F    0x3f800000F  /* 1F */ { align1 1H switch };
+cmp.l.f0.0(8)   null<1>F        g4.4<0,1,0>F    0x0F  /* 0F */  { align1 1Q switch };
+cmp.l.f0.0(16)  null<1>D        g6.4<0,1,0>F    0x0F  /* 0F */  { align1 1H switch };
+cmp.ge.f0.0(8)  g9<1>F          g6.4<0,1,0>F    0x0F  /* 0F */  { align1 2Q };
+cmp.nz.f0.0(8)  null<1>F        g124<8,8,1>F    g124<8,8,1>F    { align1 1Q switch };
+cmp.nz.f0.0(8)  null<1>F        g124<8,8,1>F    0x0F  /* 0F */  { align1 1Q switch };
+cmp.g.f0.0(8)   null<1>F        g124<8,8,1>F    0x0F  /* 0F */  { align1 1Q switch };
+cmp.nz.f0.0(16) null<1>D        g120<8,8,1>F    g120<8,8,1>F    { align1 1H switch };
+cmp.nz.f0.0(16) null<1>D        g120<8,8,1>F    0x0F  /* 0F */  { align1 1H switch };
+cmp.g.f0.0(16)  null<1>D        g120<8,8,1>F    0x0F  /* 0F */  { align1 1H switch };
+cmp.z.f0.0(8)   g5<1>D          g4<8,8,1>D      g2.5<0,1,0>D    { align1 1Q };
+cmp.z.f0.0(8)   g8<1>D          g6<8,8,1>D      g2.5<0,1,0>D    { align1 2Q };
+cmp.ge.f0.0(8)  null<1>D        g20<8,8,1>D     g4<0,1,0>D      { align1 1Q switch };
+cmp.ge.f0.0(16) null<1>D        g13<8,8,1>D     g6<0,1,0>D      { align1 1H switch };
+(+f0.1) cmp.z.f0.1(8) null<1>D  g2<8,8,1>D      0D              { align1 1Q switch };
+(+f0.1) cmp.z.f0.1(16) null<1>D g2<8,8,1>D      0D              { align1 1H switch };
+cmp.ge.f0.0(8)  g74<1>.xD       g1<0>.xD        16D             { align16 1Q };
+cmp.ge.f0.0(8)  g56<1>D         g3<0,1,0>D      1D              { align1 1Q };
+cmp.l.f0.0(8)   g57<1>D         g3<0,1,0>D      1D              { align1 1Q };
+cmp.ge.f0.0(8)  g109<1>D        g3<0,1,0>D      1D              { align1 2Q };
+cmp.l.f0.0(8)   g111<1>D        g3<0,1,0>D      1D              { align1 2Q };
+cmp.z.f0.0(8)   g48<1>.xD       g3.4<0>.xD      0D              { align16 1Q };
+cmp.ge.f0.0(8)  g9<1>UD         g6<0>UD         g6.4<0>UD       { align16 1Q };
+cmp.nz.f0.0(8)  g9<1>.xD        g1<0>.xD        g1<0>.yD        { align16 1Q };
+cmp.nz.f0.0(8)  g8<1>.xyzF      g1<0>.xyzzF     g1.4<0>.xyzzF   { align16 1Q };
+cmp.l.f0.0(8)   g3<1>D          g2.1<0,1,0>D    g2<0,1,0>D      { align1 1Q };
+cmp.l.f0.0(8)   g4<1>D          g2.1<0,1,0>D    g2<0,1,0>D      { align1 2Q };
+cmp.l.f0.0(8)   g70<1>.xD       g68<4>.xD       7D              { align16 1Q };
+cmp.l.f0.0(8)   null<1>.xD      g68<4>.xD       3D              { align16 1Q switch };
+cmp.le.f0.0(8)  g4<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1Q };
+cmp.g.f0.0(8)   g5<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1Q };
+cmp.le.f0.0(8)  g6<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 2Q };
+cmp.g.f0.0(8)   g8<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 2Q };
+cmp.le.f0.0(8)  null<1>F        g63<8,8,1>F     g2.1<0,1,0>F    { align1 1Q switch };
+cmp.le.f0.0(8)  null<1>F        g79<8,8,1>F     0x3fc00000F  /* 1.5F */ { align1 1Q switch };
+cmp.le.f0.0(16) null<1>D        g116<8,8,1>F    g2.2<0,1,0>F    { align1 1H switch };
+cmp.le.f0.0(16) null<1>D        g98<8,8,1>F     0x3fc00000F  /* 1.5F */ { align1 1H switch };
+cmp.z.f0.0(8)   null<1>F        g3<0>.xyzzF     0x6e6e6c6aVF /* [13F, 14F, 15F, 15F]VF */ { align16 1Q switch };
+cmp.ge.f0.0(8)  g3<1>D          g2<0,1,0>D      g2.1<0,1,0>D    { align1 1Q };
+cmp.ge.f0.0(8)  g4<1>D          g2<0,1,0>D      g2.1<0,1,0>D    { align1 2Q };
+cmp.ge.f0.0(8)  g31<1>UD        g30<8,8,1>UD    g5.7<0,1,0>UD   { align1 1Q };
+cmp.l.f0.0(8)   g32<1>UD        g30<8,8,1>UD    g5.3<0,1,0>UD   { align1 1Q };
+cmp.ge.f0.0(8)  g50<1>UD        g48<8,8,1>UD    g7.7<0,1,0>UD   { align1 2Q };
+cmp.l.f0.0(8)   g52<1>UD        g48<8,8,1>UD    g7.3<0,1,0>UD   { align1 2Q };
+cmp.ge.f0.0(8)  null<1>F        g13<8,8,1>F     0x38d1b717F  /* 0.0001F */ { align1 1Q switch };
+cmp.ge.f0.0(16) null<1>D        g24<8,8,1>F     0x38d1b717F  /* 0.0001F */ { align1 1H switch };
+cmp.l.f0.0(8)   g13<1>.xyD      g5.4<0>.zwwwD   g6<0>.xyyyD     { align16 1Q };
+cmp.nz.f0.0(8)  g22<1>F         g8.7<0,1,0>F    0x442f0000F  /* 700F */ { align1 1Q };
+cmp.nz.f0.0(8)  g32<1>F         g8.7<0,1,0>F    0x442f0000F  /* 700F */ { align1 2Q };
+cmp.g.f0.0(8)   g5<1>F          (abs)g3<8,8,1>F 0x3b808081F  /* 0.00392157F */ { align1 2Q };
+cmp.g.f0.0(8)   g30<1>D         g5.1<0,1,0>D    4D              { align1 1Q };
+cmp.g.f0.0(8)   g56<1>D         g7.1<0,1,0>D    4D              { align1 2Q };
+cmp.ge.f0.0(8)  g30<1>.xyF      (abs)g29<4>.xyyyF 0x5d5e0b6bF  /* 1e+18F */ { align16 1Q };
+cmp.l.f0.0(8)   g61<1>.xyF      g59<4>.xyyyF    0x0F  /* 0F */  { align16 1Q };
+cmp.l.f0.0(8)   null<1>UD       g5.4<0>.zUD     g5.4<0>.wUD     { align16 1Q switch };
+cmp.ge.f0.0(8)  null<1>UD       g5.4<0>.wUD     g5.4<0>.zUD     { align16 1Q switch };
+cmp.l.f0.0(8)   null<1>D        g1<0>.yD        g1<0>.xD        { align16 1Q switch };
+cmp.ge.f0.0(8)  null<1>D        g5.4<0>.wD      g5.4<0>.zD      { align16 1Q switch };
+cmp.ge.f0.0(8)  null<1>D        g2<0,1,0>D      1D              { align1 1Q switch };
+cmp.ge.f0.0(16) null<1>D        g2<0,1,0>D      1D              { align1 1H switch };
+cmp.l.f0.0(8)   null<1>F        g12<8,8,1>F     g38<0,1,0>F     { align1 1Q switch };
+cmp.l.f0.0(16)  null<1>D        g19<8,8,1>F     g60<0,1,0>F     { align1 1H switch };
+cmp.g.f0.0(8)   null<1>.xD      g1<0>.xD        0D              { align16 1Q switch };
+cmp.ge.f0.0(8)  null<1>.xD      g7<4>.xD        4096D           { align16 1Q switch };
+cmp.z.f0.0(8)   g14<1>.xF       g1<0>.xF        0x40b79581F  /* 5.737F */ { align16 1Q };
+cmp.nz.f0.0(8)  null<1>UD       g9<4>.xUD       0x00000000UD    { align16 1Q switch };
+cmp.nz.f0.0(8)  null<1>D        g3<8,8,1>D      g2<0,1,0>D      { align1 1Q switch };
+cmp.nz.f0.0(16) null<1>D        g3<8,8,1>D      g2<0,1,0>D      { align1 1H switch };
+cmp.z.f0.0(8)   null<1>UD       g5<8,8,1>UD     0x00000000UD    { align1 1Q switch };
+cmp.z.f0.0(16)  null<1>D        g15<8,8,1>UD    0x00000000UD    { align1 1H switch };
+cmp.g.f0.0(8)   null<1>UD       g1<0>.zUD       0x0000001fUD    { align16 1Q switch };
+cmp.g.f0.0(8)   null<1>F        (abs)g14<8,8,1>F g45<0,1,0>F    { align1 1Q switch };
+cmp.g.f0.0(16)  null<1>D        (abs)g21<8,8,1>F g6<0,1,0>F     { align1 1H switch };
+cmp.ge.f0.0(8)  null<1>F        (abs)g30<4>F    0x5d5e0b6bF  /* 1e+18F */ { align16 1Q switch };
+(+f0.1) cmp.nz.f0.1(8) null<1>UW g0<8,8,1>UW    g0<8,8,1>UW     { align1 1Q switch };
+(+f0.1) cmp.nz.f0.1(16) null<1>D g0<8,8,1>UW    g0<8,8,1>UW     { align1 1H switch };
+cmp.l.f0.0(8)   null<1>UD       g2<8,8,1>UD     g18<8,8,1>UD    { align1 1Q switch };
+cmp.l.f0.0(16)  null<1>D        g32<8,8,1>UD    g29<8,8,1>UD    { align1 1H switch };
+cmp.ge.f0.0(8)  null<1>F        g30<8,8,1>F     g4.4<0,1,0>F    { align1 1Q switch };
+cmp.ge.f0.0(16) null<1>D        g28<8,8,1>F     g6.4<0,1,0>F    { align1 1H switch };
+cmp.le.f0.0(8)  g9<1>F          g7<8,8,1>F      0x3727c5acF  /* 1e-05F */ { align1 2Q };
+cmp.g.f0.0(8)   null<1>D        g44<8,8,1>D     8D              { align1 1Q switch };
+cmp.g.f0.0(16)  null<1>D        g72<8,8,1>D     8D              { align1 1H switch };
+cmp.ge.f0.0(8)  null<1>UD       g4<8,8,1>UD     g2.3<0,1,0>UD   { align1 1Q switch };
+cmp.ge.f0.0(16) null<1>D        g5<8,8,1>UD     g2.3<0,1,0>UD   { align1 1H switch };
+cmp.l.f0.0(8)   g11<1>F         g9<8,8,1>F      0x3e800000F  /* 0.25F */ { align1 2Q };
+cmp.z.f0.0(8)   null<1>D        g33<8,8,1>D     g37<8,8,1>D     { align1 1Q switch };
+cmp.z.f0.0(16)  null<1>D        g58<8,8,1>D     g66<8,8,1>D     { align1 1H switch };
+cmp.g.f0.0(8)   null<1>UD       g4.2<0,1,0>UD   0x0000001fUD    { align1 1Q switch };
+cmp.g.f0.0(16)  null<1>D        g4.2<0,1,0>UD   0x0000001fUD    { align1 1H switch };

diff --git a/src/intel/tools/tests/gen7/cmp.expected b/src/intel/tools/tests/gen7/cmp.expected
new file mode 100644 (file)
index 0000000..ade2531
--- /dev/null
+++ b/src/intel/tools/tests/gen7/cmp.expected
@@ -0,0 +1,146 @@
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+10 80 80 03 a4 1c 00 20 00 09 8d 00 08 00 00 00
+10 80 60 04 20 04 00 20 80 00 8d 00 4c 00 00 00
+10 80 80 04 24 04 00 20 a0 00 8d 00 4c 00 00 00
+10 10 60 05 bd 7f 60 21 20 01 8d 00 00 00 80 3e
+10 80 60 01 a4 14 00 20 20 04 8d 00 a0 04 8d 00
+10 80 80 01 a4 14 00 20 40 07 8d 00 40 08 8d 00
+10 80 60 03 20 0c 00 20 88 00 00 00 1f 00 00 00
+10 80 80 03 24 0c 00 20 88 00 00 00 1f 00 00 00

diff --git a/src/intel/tools/tests/gen7/dp2.asm b/src/intel/tools/tests/gen7/dp2.asm
new file mode 100644 (file)
index 0000000..b615d1a
--- /dev/null
+++ b/src/intel/tools/tests/gen7/dp2.asm
@@ -0,0 +1,4 @@
+dp2(8)          g35<1>.xF       g34<4>.xyyyF    g34<4>.xyyyF    { align16 1Q };
+dp2(8)          g4<1>.yF        g1<0>.xyyyF     g1.4<0>.xyyyF   { align16 NoDDClr 1Q };
+dp2(8)          g4<1>.zF        g1<0>.xyyyF     g1.4<0>.zwwwF   { align16 NoDDClr,NoDDChk 1Q };
+dp2(8)          g4<1>.wF        g1<0>.xyyyF     g2<0>.xyyyF     { align16 NoDDChk 1Q };

diff --git a/src/intel/tools/tests/gen7/dp2.expected b/src/intel/tools/tests/gen7/dp2.expected
new file mode 100644 (file)
index 0000000..ff567fe
--- /dev/null
+++ b/src/intel/tools/tests/gen7/dp2.expected
@@ -0,0 +1,4 @@
+57 01 60 00 bd 77 61 24 44 04 65 00 44 04 65 00
+57 05 60 00 bd 77 82 20 24 00 05 00 34 00 05 00
+57 0d 60 00 bd 77 84 20 24 00 05 00 3e 00 0f 00
+57 09 60 00 bd 77 88 20 24 00 05 00 44 00 05 00

diff --git a/src/intel/tools/tests/gen7/dp3.asm b/src/intel/tools/tests/gen7/dp3.asm
new file mode 100644 (file)
index 0000000..3f7a6ae
--- /dev/null
+++ b/src/intel/tools/tests/gen7/dp3.asm
@@ -0,0 +1,6 @@
+dp3(8)          g12<1>.xF       g11<4>.xyzzF    g11<4>.xyzzF    { align16 1Q };
+dp3(8)          g116<1>.xF      g3<0>.xyzzF     g6<4>.xyzzF     { align16 NoDDClr 1Q };
+dp3(8)          g116<1>.yF      g3.4<0>.xyzzF   g6<4>.xyzzF     { align16 NoDDClr,NoDDChk 1Q };
+dp3(8)          g10<1>.yF       g6<0>.xyzzF     g7<0>.xyzzF     { align16 NoDDChk 1Q };
+dp3.le.f0.0(8)  g40<1>.xF       g31<4>.xyzzF    g3.4<0>.xyzzF   { align16 1Q };
+dp3.sat(8)      g37<1>.xF       g31<4>.xyzzF    g35<4>.xyzzF    { align16 1Q };

diff --git a/src/intel/tools/tests/gen7/dp3.expected b/src/intel/tools/tests/gen7/dp3.expected
new file mode 100644 (file)
index 0000000..ada1cc3
--- /dev/null
+++ b/src/intel/tools/tests/gen7/dp3.expected
@@ -0,0 +1,6 @@
+56 01 60 00 bd 77 81 21 64 01 6a 00 64 01 6a 00
+56 05 60 00 bd 77 81 2e 64 00 0a 00 c4 00 6a 00
+56 0d 60 00 bd 77 82 2e 74 00 0a 00 c4 00 6a 00
+56 09 60 00 bd 77 42 21 c4 00 0a 00 e4 00 0a 00
+56 01 60 06 bd 77 01 25 e4 03 6a 00 74 00 0a 00
+56 01 60 80 bd 77 a1 24 e4 03 6a 00 64 04 6a 00

diff --git a/src/intel/tools/tests/gen7/dp4.asm b/src/intel/tools/tests/gen7/dp4.asm
new file mode 100644 (file)
index 0000000..51a943a
--- /dev/null
+++ b/src/intel/tools/tests/gen7/dp4.asm
@@ -0,0 +1,6 @@
+dp4(8)          g115<1>.xF      g3<4>F          g1<0>F          { align16 NoDDClr 1Q };
+dp4(8)          g115<1>.yF      g3<4>F          g1.4<0>F        { align16 NoDDClr,NoDDChk 1Q };
+dp4(8)          g115<1>.wF      g3<4>F          g2.4<0>F        { align16 NoDDChk 1Q };
+dp4(8)          g115<1>.wF      g5<4>F          g2.4<0>F        { align16 1Q };
+dp4.sat(8)      g116<1>F        g2<4>.xF        g2<4>F          { align16 1Q };
+dp4(8)          g15<1>.xF       g2<4>F          0x3f800000F  /* 1F */ { align16 1Q };

diff --git a/src/intel/tools/tests/gen7/dp4.expected b/src/intel/tools/tests/gen7/dp4.expected
new file mode 100644 (file)
index 0000000..bdf10ad
--- /dev/null
+++ b/src/intel/tools/tests/gen7/dp4.expected
@@ -0,0 +1,6 @@
+54 05 60 00 bd 77 61 2e 64 00 6e 00 24 00 0e 00
+54 0d 60 00 bd 77 62 2e 64 00 6e 00 34 00 0e 00
+54 09 60 00 bd 77 68 2e 64 00 6e 00 54 00 0e 00
+54 01 60 00 bd 77 68 2e a4 00 6e 00 54 00 0e 00
+54 01 60 80 bd 77 8f 2e 40 00 60 00 44 00 6e 00
+54 01 60 00 bd 7f e1 21 44 00 6e 00 00 00 80 3f

diff --git a/src/intel/tools/tests/gen7/dph.asm b/src/intel/tools/tests/gen7/dph.asm
new file mode 100644 (file)
index 0000000..c28a841
--- /dev/null
+++ b/src/intel/tools/tests/gen7/dph.asm
@@ -0,0 +1,5 @@
+dph(8)          g116<1>.xF      g4<4>.xyzxF     g5<4>F          { align16 1Q };
+dph.sat(8)      g116<1>F        g1<0>.xyzxF     g3<4>F          { align16 1Q };
+dph(8)          g115<1>.xF      g5<4>.xyzxF     g1<0>F          { align16 NoDDClr 1Q };
+dph(8)          g115<1>.yF      g5<4>.xyzxF     g1.4<0>F        { align16 NoDDClr,NoDDChk 1Q };
+dph(8)          g115<1>.wF      g5<4>.xyzxF     g2.4<0>F        { align16 NoDDChk 1Q };

diff --git a/src/intel/tools/tests/gen7/dph.expected b/src/intel/tools/tests/gen7/dph.expected
new file mode 100644 (file)
index 0000000..02bd5f6
--- /dev/null
+++ b/src/intel/tools/tests/gen7/dph.expected
@@ -0,0 +1,5 @@
+55 01 60 00 bd 77 81 2e 84 00 62 00 a4 00 6e 00
+55 01 60 80 bd 77 8f 2e 24 00 02 00 64 00 6e 00
+55 05 60 00 bd 77 61 2e a4 00 62 00 24 00 0e 00
+55 0d 60 00 bd 77 62 2e a4 00 62 00 34 00 0e 00
+55 09 60 00 bd 77 68 2e a4 00 62 00 54 00 0e 00

diff --git a/src/intel/tools/tests/gen7/else.asm b/src/intel/tools/tests/gen7/else.asm
new file mode 100644 (file)
index 0000000..71a09a3
--- /dev/null
+++ b/src/intel/tools/tests/gen7/else.asm
@@ -0,0 +1,3 @@
+else(8)         JIP: 12                                         { align1 1Q };
+else(16)        JIP: 12                                         { align1 1H };
+else(8)         JIP: 18                                         { align16 1Q };

diff --git a/src/intel/tools/tests/gen7/else.expected b/src/intel/tools/tests/gen7/else.expected
new file mode 100644 (file)
index 0000000..86cf63f
--- /dev/null
+++ b/src/intel/tools/tests/gen7/else.expected
@@ -0,0 +1,3 @@
+24 00 60 00 84 3c 00 20 00 00 8d 00 0c 00 00 00
+24 00 80 00 84 3c 00 20 00 00 8d 00 0c 00 00 00
+24 01 60 00 84 3c 0f 20 04 00 6e 00 12 00 00 00

diff --git a/src/intel/tools/tests/gen7/endif.asm b/src/intel/tools/tests/gen7/endif.asm
new file mode 100644 (file)
index 0000000..b3a5066
--- /dev/null
+++ b/src/intel/tools/tests/gen7/endif.asm
@@ -0,0 +1,3 @@
+endif(8)        JIP: 2                                          { align16 1Q };
+endif(8)        JIP: 2                                          { align1 1Q };
+endif(16)       JIP: 2                                          { align1 1H };

diff --git a/src/intel/tools/tests/gen7/endif.expected b/src/intel/tools/tests/gen7/endif.expected
new file mode 100644 (file)
index 0000000..e646da6
--- /dev/null
+++ b/src/intel/tools/tests/gen7/endif.expected
@@ -0,0 +1,3 @@
+25 01 60 00 84 3c 0f 20 04 00 6e 00 02 00 00 00
+25 00 60 00 84 3c 00 20 00 00 8d 00 02 00 00 00
+25 00 80 00 84 3c 00 20 00 00 8d 00 02 00 00 00

diff --git a/src/intel/tools/tests/gen7/f16to32.asm b/src/intel/tools/tests/gen7/f16to32.asm
new file mode 100644 (file)
index 0000000..29de37d
--- /dev/null
+++ b/src/intel/tools/tests/gen7/f16to32.asm
@@ -0,0 +1,2 @@
+f16to32(8)      g19<1>F         g2<16,8,2>UW                    { align1 1Q };
+f16to32(16)     g21<1>F         g6<16,8,2>UW                    { align1 1H };

diff --git a/src/intel/tools/tests/gen7/f16to32.expected b/src/intel/tools/tests/gen7/f16to32.expected
new file mode 100644 (file)
index 0000000..3c22d54
--- /dev/null
+++ b/src/intel/tools/tests/gen7/f16to32.expected
@@ -0,0 +1,2 @@
+14 00 60 00 3d 01 60 22 40 00 ae 00 00 00 00 00
+14 00 80 00 3d 01 a0 22 c0 00 ae 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/f32to16.asm b/src/intel/tools/tests/gen7/f32to16.asm
new file mode 100644 (file)
index 0000000..4d6764d
--- /dev/null
+++ b/src/intel/tools/tests/gen7/f32to16.asm
@@ -0,0 +1,2 @@
+f32to16(8)      g38<2>W         g13<8,8,1>F                     { align1 1Q };
+f32to16(16)     g76<2>W         g91<8,8,1>F                     { align1 1H };

diff --git a/src/intel/tools/tests/gen7/f32to16.expected b/src/intel/tools/tests/gen7/f32to16.expected
new file mode 100644 (file)
index 0000000..d9ab85d
--- /dev/null
+++ b/src/intel/tools/tests/gen7/f32to16.expected
@@ -0,0 +1,2 @@
+13 00 60 00 ad 03 c0 44 a0 01 8d 00 00 00 00 00
+13 00 80 00 ad 03 80 49 60 0b 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/fbh.asm b/src/intel/tools/tests/gen7/fbh.asm
new file mode 100644 (file)
index 0000000..f54933b
--- /dev/null
+++ b/src/intel/tools/tests/gen7/fbh.asm
@@ -0,0 +1,3 @@
+fbh(8)          g16<1>D         g15<4>D                         { align16 1Q };
+fbh(8)          g7<1>D          g4<8,8,1>D                      { align1 1Q };
+fbh(16)         g8<1>D          g4<8,8,1>D                      { align1 1H };

diff --git a/src/intel/tools/tests/gen7/fbh.expected b/src/intel/tools/tests/gen7/fbh.expected
new file mode 100644 (file)
index 0000000..72fad95
--- /dev/null
+++ b/src/intel/tools/tests/gen7/fbh.expected
@@ -0,0 +1,3 @@
+4b 01 60 00 a5 00 0f 22 e4 01 6e 00 00 00 00 00
+4b 00 60 00 a5 00 e0 20 80 00 8d 00 00 00 00 00
+4b 00 80 00 a5 00 00 21 80 00 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/fbl.asm b/src/intel/tools/tests/gen7/fbl.asm
new file mode 100644 (file)
index 0000000..844976d
--- /dev/null
+++ b/src/intel/tools/tests/gen7/fbl.asm
@@ -0,0 +1,5 @@
+fbl(8)          g5<1>UD         g5<8,8,1>UD                     { align1 1Q };
+fbl(16)         g6<1>UD         g8<8,8,1>UD                     { align1 1H };
+fbl(8)          g11<1>UD        g10<4>UD                        { align16 1Q };
+fbl(1)          g6<1>UD         f1<0,1,0>UB                     { align1 WE_all 1N };
+fbl(1)          g9<1>UD         f1<0,1,0>UW                     { align1 WE_all 1N };

diff --git a/src/intel/tools/tests/gen7/fbl.expected b/src/intel/tools/tests/gen7/fbl.expected
new file mode 100644 (file)
index 0000000..ded84ca
--- /dev/null
+++ b/src/intel/tools/tests/gen7/fbl.expected
@@ -0,0 +1,5 @@
+4c 00 60 00 21 00 a0 20 a0 00 8d 00 00 00 00 00
+4c 00 80 00 21 00 c0 20 00 01 8d 00 00 00 00 00
+4c 01 60 00 21 00 6f 21 44 01 6e 00 00 00 00 00
+4c 02 00 00 01 02 c0 20 20 06 00 00 00 00 00 00
+4c 02 00 00 01 01 20 21 20 06 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/frc.asm b/src/intel/tools/tests/gen7/frc.asm
new file mode 100644 (file)
index 0000000..60d2ae7
--- /dev/null
+++ b/src/intel/tools/tests/gen7/frc.asm
@@ -0,0 +1,4 @@
+frc(8)          g19<1>.xF       (abs)g1<0>.xF                   { align16 1Q };
+frc.sat(8)      g116<1>F        g6<4>F                          { align16 1Q };
+frc(8)          g3<1>F          g2<0,1,0>F                      { align1 1Q };
+frc(16)         g3<1>F          g2<0,1,0>F                      { align1 1H };

diff --git a/src/intel/tools/tests/gen7/frc.expected b/src/intel/tools/tests/gen7/frc.expected
new file mode 100644 (file)
index 0000000..36265f5
--- /dev/null
+++ b/src/intel/tools/tests/gen7/frc.expected
@@ -0,0 +1,4 @@
+43 01 60 00 bd 03 61 22 20 20 00 00 00 00 00 00
+43 01 60 80 bd 03 8f 2e c4 00 6e 00 00 00 00 00
+43 00 60 00 bd 03 60 20 40 00 00 00 00 00 00 00
+43 00 80 00 bd 03 60 20 40 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/halt.asm b/src/intel/tools/tests/gen7/halt.asm
new file mode 100644 (file)
index 0000000..0a06cc5
--- /dev/null
+++ b/src/intel/tools/tests/gen7/halt.asm
@@ -0,0 +1,4 @@
+(-f0.1.any4h) halt(8) JIP: 72   UIP: 74                         { align1 1Q };
+halt(8)         JIP: 2          UIP: 2                          { align1 1Q };
+(-f0.1.any4h) halt(16) JIP: 76  UIP: 78                         { align1 1H };
+halt(16)        JIP: 2          UIP: 2                          { align1 1H };

diff --git a/src/intel/tools/tests/gen7/halt.expected b/src/intel/tools/tests/gen7/halt.expected
new file mode 100644 (file)
index 0000000..edc7d9e
--- /dev/null
+++ b/src/intel/tools/tests/gen7/halt.expected
@@ -0,0 +1,4 @@
+2a 00 76 00 84 1c 00 20 00 00 8d 02 48 00 4a 00
+2a 00 60 00 84 1c 00 20 00 00 8d 00 02 00 02 00
+2a 00 96 00 84 1c 00 20 00 00 8d 02 4c 00 4e 00
+2a 00 80 00 84 1c 00 20 00 00 8d 00 02 00 02 00

diff --git a/src/intel/tools/tests/gen7/if.asm b/src/intel/tools/tests/gen7/if.asm
new file mode 100644 (file)
index 0000000..e6d096d
--- /dev/null
+++ b/src/intel/tools/tests/gen7/if.asm
@@ -0,0 +1,6 @@
+(+f0.0.x) if(8) JIP: 18         UIP: 18                         { align16 1Q };
+(+f0.0) if(8)   JIP: 14         UIP: 14                         { align16 1Q };
+(+f0.0) if(8)   JIP: 32         UIP: 96                         { align1 1Q };
+(+f0.0) if(16)  JIP: 32         UIP: 96                         { align1 1H };
+(-f0.0) if(8)   JIP: 10         UIP: 10                         { align1 1Q };
+(-f0.0) if(16)  JIP: 10         UIP: 10                         { align1 1H };

diff --git a/src/intel/tools/tests/gen7/if.expected b/src/intel/tools/tests/gen7/if.expected
new file mode 100644 (file)
index 0000000..c08f2ff
--- /dev/null
+++ b/src/intel/tools/tests/gen7/if.expected
@@ -0,0 +1,6 @@
+22 01 62 00 84 3c 0f 20 04 00 0e 00 12 00 12 00
+22 01 61 00 84 3c 0f 20 04 00 0e 00 0e 00 0e 00
+22 00 61 00 84 3c 00 20 00 00 00 00 20 00 60 00
+22 00 81 00 84 3c 00 20 00 00 00 00 20 00 60 00
+22 00 71 00 84 3c 00 20 00 00 00 00 0a 00 0a 00
+22 00 91 00 84 3c 00 20 00 00 00 00 0a 00 0a 00

diff --git a/src/intel/tools/tests/gen7/lrp.asm b/src/intel/tools/tests/gen7/lrp.asm
new file mode 100644 (file)
index 0000000..6b20c7c
--- /dev/null
+++ b/src/intel/tools/tests/gen7/lrp.asm
@@ -0,0 +1,4 @@
+lrp(8)          g42<1>F         g41<4,4,1>.xF   g40<4,4,1>F     g39<4,4,1>F { align16 1Q };
+lrp(8)          g5<1>F          g2.4<0,1,0>F    g2.2<0,1,0>F    g2.0<0,1,0>F { align16 2Q };
+lrp.sat(8)      g7<1>F          g10<4,4,1>F     g13<4,4,1>F     g16<4,4,1>F { align16 1Q };
+lrp.sat(8)      g19<1>F         g21<4,4,1>F     g27<4,4,1>F     g33<4,4,1>F { align16 2Q };

diff --git a/src/intel/tools/tests/gen7/lrp.expected b/src/intel/tools/tests/gen7/lrp.expected
new file mode 100644 (file)
index 0000000..7c80f06
--- /dev/null
+++ b/src/intel/tools/tests/gen7/lrp.expected
@@ -0,0 +1,4 @@
+5c 01 60 00 00 00 1e 2a 00 90 02 39 50 20 c7 09
+5c 11 60 00 00 00 1e 05 01 28 20 80 04 04 80 00
+5c 01 60 80 00 00 1e 07 c8 a1 00 39 1a 20 07 04
+5c 11 60 80 00 00 1e 13 c8 51 01 39 36 20 47 08

diff --git a/src/intel/tools/tests/gen7/lzd.asm b/src/intel/tools/tests/gen7/lzd.asm
new file mode 100644 (file)
index 0000000..da2da08
--- /dev/null
+++ b/src/intel/tools/tests/gen7/lzd.asm
@@ -0,0 +1,3 @@
+lzd(8)          g20<1>UD        g2.4<0>UD                       { align16 1Q };
+lzd(8)          g17<1>UD        g3.1<0,1,0>UD                   { align1 1Q };
+lzd(16)         g27<1>UD        g3.1<0,1,0>UD                   { align1 1H };

diff --git a/src/intel/tools/tests/gen7/lzd.expected b/src/intel/tools/tests/gen7/lzd.expected
new file mode 100644 (file)
index 0000000..429bf45
--- /dev/null
+++ b/src/intel/tools/tests/gen7/lzd.expected
@@ -0,0 +1,3 @@
+4a 01 60 00 21 00 8f 22 54 00 0e 00 00 00 00 00
+4a 00 60 00 21 00 20 22 64 00 00 00 00 00 00 00
+4a 00 80 00 21 00 60 23 64 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/mach.asm b/src/intel/tools/tests/gen7/mach.asm
new file mode 100644 (file)
index 0000000..f0a04c5
--- /dev/null
+++ b/src/intel/tools/tests/gen7/mach.asm
@@ -0,0 +1,13 @@
+mach(8)         null<1>D        g5.4<0>.zwwwD   g6<0>.xyyyD     { align16 1Q AccWrEnable };
+mach(8)         g12<1>UD        g10<8,8,1>UD    0xaaaaaaabUD    { align1 1Q AccWrEnable };
+mach(8)         g16<1>D         g10<8,8,1>D     1431655766D     { align1 1Q AccWrEnable };
+mach(8)         g2<1>UD         g23<8,8,1>UD    0xaaaaaaabUD    { align1 WE_all 1Q AccWrEnable };
+mach(8)         g3<1>D          g23<8,8,1>D     1431655766D     { align1 WE_all 1Q AccWrEnable };
+mach(8)         g9<1>D          g1<0>D          g1.4<0>D        { align16 1Q AccWrEnable };
+mach(8)         null<1>D        g1<4>.xD        741092396D      { align16 1Q AccWrEnable };
+mach(8)         g12<1>UD        g4<8,8,1>UD     g8<8,8,1>UD     { align1 1Q AccWrEnable };
+mach(8)         g5<1>UD         g5<8,8,1>UD     g13<8,8,1>UD    { align1 WE_all 1Q AccWrEnable };
+mach(8)         g13<1>D         g5<8,8,1>D      g9<8,8,1>D      { align1 1Q AccWrEnable };
+mach(8)         g2<1>D          g6<8,8,1>D      g14<8,8,1>D     { align1 WE_all 1Q AccWrEnable };
+mach(8)         g24<1>.xUD      g22<4>.xUD      0x80000001UD    { align16 1Q AccWrEnable };
+mach(8)         g12<1>UD        g9<4>UD         g11<4>UD        { align16 1Q AccWrEnable };

diff --git a/src/intel/tools/tests/gen7/mach.expected b/src/intel/tools/tests/gen7/mach.expected
new file mode 100644 (file)
index 0000000..3da50e3
--- /dev/null
+++ b/src/intel/tools/tests/gen7/mach.expected
@@ -0,0 +1,13 @@
+49 01 60 10 a4 14 0f 20 be 00 0f 00 c4 00 05 00
+49 00 60 10 21 0c 80 21 40 01 8d 00 ab aa aa aa
+49 00 60 10 a5 1c 00 22 40 01 8d 00 56 55 55 55
+49 02 60 10 21 0c 40 20 e0 02 8d 00 ab aa aa aa
+49 02 60 10 a5 1c 60 20 e0 02 8d 00 56 55 55 55
+49 01 60 10 a5 14 2f 21 24 00 0e 00 34 00 0e 00
+49 01 60 10 a4 1c 0f 20 20 00 60 00 2c 2c 2c 2c
+49 00 60 10 21 04 80 21 80 00 8d 00 00 01 8d 00
+49 02 60 10 21 04 a0 20 a0 00 8d 00 a0 01 8d 00
+49 00 60 10 a5 14 a0 21 a0 00 8d 00 20 01 8d 00
+49 02 60 10 a5 14 40 20 c0 00 8d 00 c0 01 8d 00
+49 01 60 10 21 0c 01 23 c0 02 60 00 01 00 00 80
+49 01 60 10 21 04 8f 21 24 01 6e 00 64 01 6e 00

diff --git a/src/intel/tools/tests/gen7/mad.asm b/src/intel/tools/tests/gen7/mad.asm
new file mode 100644 (file)
index 0000000..4494536
--- /dev/null
+++ b/src/intel/tools/tests/gen7/mad.asm
@@ -0,0 +1,38 @@
+mad(8)          g11<1>F         g4.7<0,1,0>F    g4.3<0,1,0>F    g9<4,4,1>F { align16 1Q };
+mad(8)          g25<1>F         g6.7<0,1,0>F    g6.3<0,1,0>F    g21<4,4,1>F { align16 2Q };
+mad(8)          g18<1>.xyzF     -g16<4,4,1>.xyzzF g11<4,4,1>.xyzzF g9<4,4,1>.xyzzF { align16 1Q };
+mad(8)          g3<1>F          -g2.4<0,1,0>F   g6.0<0,1,0>F    g2.0<0,1,0>F { align16 2Q };
+mad(8)          g116<1>.xyzF    g9<4,4,1>.xyzzF g6<4,4,1>.xyzzF g30<4,4,1>.xyzzF { align16 NoDDClr 1Q };
+mad.le.f0.0(8)  g9<1>F          g3<4,4,1>F      g4.2<0,1,0>F    g15<4,4,1>F { align16 1Q };
+mad.le.f0.0(8)  g4<1>F          g2<4,4,1>F      g6.2<0,1,0>F    g20<4,4,1>F { align16 2Q };
+mad(8)          g20<1>.xyzF     g8<4,4,1>.xF    g19<4,4,1>.xyzzF -g9<4,4,1>.xF { align16 1Q };
+mad(8)          g22<1>.xF       g10<4,4,1>.xF   g21<4,4,1>.xF   (abs)g5.6<0,1,0>F { align16 1Q };
+mad.sat(8)      g116<1>.xyzF    g95<4,4,1>.xyzzF g89<4,4,1>.xyzzF g93<4,4,1>.zF { align16 NoDDClr 1Q };
+mad(8)          g53<1>F         -g52<4,4,1>F    g21<4,4,1>F     -g21<4,4,1>F { align16 1Q };
+mad(8)          g71<1>F         -g8<4,4,1>F     -g2.4<0,1,0>F   -g21<4,4,1>F { align16 1Q };
+mad.sat(8)      g40<1>F         g39<4,4,1>F     g37<4,4,1>F     g10<4,4,1>F { align16 1Q };
+mad(8)          g67<1>F         g65<4,4,1>F     g6.2<0,1,0>F    -g2.2<0,1,0>F { align16 2Q };
+mad(8)          g37<1>F         -g35<4,4,1>F    g87<4,4,1>F     -g87<4,4,1>F { align16 2Q };
+mad(8)          g6<1>F          -g93<4,4,1>F    -g2.5<0,1,0>F   -g87<4,4,1>F { align16 2Q };
+mad.sat(8)      g9<1>F          g7<4,4,1>F      g118<4,4,1>F    g105<4,4,1>F { align16 2Q };
+mad.ge.f0.0(8)  g19<1>.xF       g9<4,4,1>.xF    g18<4,4,1>.xF   -g6.0<0,1,0>F { align16 1Q };
+mad(8)          g115<1>.xF      g1<4,4,1>.xF    g9<4,4,1>.xF    g2<4,4,1>.xF { align16 NoDDChk 1Q };
+mad.sat(8)      g116<1>.xyzF    -g9<4,4,1>.xyzzF g8<4,4,1>.zxyyF g6<4,4,1>.yzxxF { align16 NoDDClr 1Q };
+mad(8)          g125<1>F        g11<4,4,1>F     -g13.0<0,1,0>F  g6<4,4,1>F { align16 1Q };
+mad(8)          g123<1>F        g2<4,4,1>F      -g64.0<0,1,0>F  g11<4,4,1>F { align16 2Q };
+mad(8)          g2<1>F          -g6<4,4,1>F     (abs)g5<4,4,1>F g14.0<0,1,0>F { align16 1Q };
+mad(8)          g2<1>F          -g9<4,4,1>F     (abs)g7<4,4,1>F g64.0<0,1,0>F { align16 2Q };
+mad(8)          g11<1>.yF       -g27<4,4,1>.xF  g7.2<0,1,0>F    g6.0<0,1,0>F { align16 NoDDClr,NoDDChk 1Q };
+mad(8)          g10<1>.zF       -g30<4,4,1>.xF  g6.6<0,1,0>F    g6.1<0,1,0>F { align16 NoDDChk 1Q };
+mad(8)          g5<1>F          -g18.1<0,1,0>F  g7<4,4,1>F      (abs)g2.0<0,1,0>F { align16 1Q };
+mad(8)          g5<1>F          -g13.1<0,1,0>F  g12<4,4,1>F     (abs)g2.0<0,1,0>F { align16 2Q };
+mad(8)          g6<1>F          g13.0<0,1,0>F   g5<4,4,1>F      (abs)g2.0<0,1,0>F { align16 2Q };
+mad.ge.f0.0(8)  g9<1>F          g21.0<0,1,0>F   g7<4,4,1>F      -g2.4<0,1,0>F { align16 2Q };
+mad(8)          g13<1>F         g51.2<0,1,0>F   -g51.3<0,1,0>F  (abs)g2.0<0,1,0>F { align16 1Q };
+mad(8)          g12<1>F         g31.2<0,1,0>F   -g31.3<0,1,0>F  (abs)g2.0<0,1,0>F { align16 2Q };
+mad.l.f0.0(8)   g18<1>F         g4<4,4,1>F      g2.2<0,1,0>F    g2.4<0,1,0>F { align16 1Q };
+mad.l.f0.0(8)   g7<1>F          g5<4,4,1>F      g2.2<0,1,0>F    g2.4<0,1,0>F { align16 2Q };
+mad(8)          g9<1>.zF        g36<4,4,1>.xF   g27<4,4,1>.xF   g6.7<0,1,0>F { align16 NoDDClr,NoDDChk 1Q };
+mad(8)          g5<1>.xF        -g16<4,4,1>.xF  g2.2<0,1,0>F    g1.5<0,1,0>F { align16 NoDDClr 1Q };
+mad.nz.f0.0(8)  g10<1>F         -g12.0<0,1,0>F  g7<4,4,1>F      g10<4,4,1>F { align16 1Q };
+mad.nz.f0.0(8)  g16<1>F         -g33.0<0,1,0>F  g10<4,4,1>F     g18<4,4,1>F { align16 2Q };

diff --git a/src/intel/tools/tests/gen7/mad.expected b/src/intel/tools/tests/gen7/mad.expected
new file mode 100644 (file)
index 0000000..dea1096
--- /dev/null
+++ b/src/intel/tools/tests/gen7/mad.expected
@@ -0,0 +1,38 @@
+5b 01 60 00 00 00 1e 0b 01 4e 20 c0 08 20 47 02
+5b 11 60 00 00 00 1e 19 01 6e 20 c0 0c 20 47 05
+5b 01 60 00 20 00 0e 12 48 01 01 29 16 20 45 02
+5b 11 60 00 20 00 1e 03 01 28 20 00 0c 04 80 00
+5b 05 60 00 00 00 0e 74 48 91 00 29 0c 20 85 07
+5b 01 60 06 00 00 1e 09 c8 31 20 80 08 20 c7 03
+5b 11 60 06 00 00 1e 04 c8 21 20 80 0c 20 07 05
+5b 01 60 00 00 02 0e 14 00 80 00 29 26 00 40 02
+5b 01 60 00 00 01 02 16 00 a0 00 00 2a 04 70 01
+5b 05 60 80 00 00 0e 74 48 f1 05 29 b2 50 45 17
+5b 01 60 00 20 02 1e 35 c8 41 03 39 2a 20 47 05
+5b 01 60 00 a0 02 1e 47 c8 81 20 00 05 20 47 05
+5b 01 60 80 00 00 1e 28 c8 71 02 39 4a 20 87 02
+5b 11 60 00 00 02 1e 43 c8 11 24 80 0c 04 90 00
+5b 11 60 00 20 02 1e 25 c8 31 02 39 ae 20 c7 15
+5b 11 60 00 a0 02 1e 06 c8 d1 25 40 05 20 c7 15
+5b 11 60 80 00 00 1e 09 c8 71 00 39 ec 20 47 1a
+5b 01 60 04 00 02 02 13 00 90 00 00 24 04 80 01
+5b 09 60 00 00 00 02 73 00 10 00 00 12 00 80 00
+5b 05 60 80 20 00 0e 74 48 91 80 14 10 48 80 01
+5b 01 60 00 80 00 1e 7d c8 b1 20 00 1a 20 87 01
+5b 11 60 00 80 00 1e 7b c8 21 20 00 80 20 c7 02
+5b 01 60 00 60 00 1e 02 c8 61 00 39 0a 04 80 03
+5b 11 60 00 60 00 1e 02 c8 91 00 39 0e 04 00 10
+5b 0d 60 00 20 00 04 0b 00 b0 21 80 0e 04 80 01
+5b 09 60 00 20 00 08 0a 00 e0 21 80 0d 04 88 01
+5b 01 60 00 20 01 1e 05 01 22 01 39 0e 04 80 00
+5b 11 60 00 20 01 1e 05 01 d2 00 39 18 04 80 00
+5b 11 60 00 00 01 1e 06 01 d0 00 39 0a 04 80 00
+5b 11 60 04 00 02 1e 09 01 50 01 39 0e 04 a0 00
+5b 01 60 00 80 01 1e 0d 01 34 23 c0 66 04 80 00
+5b 11 60 00 80 01 1e 0c 01 f4 21 c0 3e 04 80 00
+5b 01 60 05 00 00 1e 12 c8 41 20 80 04 04 a0 00
+5b 11 60 05 00 00 1e 07 c8 51 20 80 04 04 a0 00
+5b 0d 60 00 00 00 08 09 00 40 02 00 36 04 b8 01
+5b 05 60 00 20 00 02 05 00 00 21 80 04 04 68 00
+5b 01 60 02 20 00 1e 0a 01 c0 00 39 0e 20 87 02
+5b 11 60 02 20 00 1e 10 01 10 02 39 14 20 87 04

diff --git a/src/intel/tools/tests/gen7/math.asm b/src/intel/tools/tests/gen7/math.asm
new file mode 100644 (file)
index 0000000..6e181a6
--- /dev/null
+++ b/src/intel/tools/tests/gen7/math.asm
@@ -0,0 +1,39 @@
+math inv(8)     g6<1>F          g2<0,1,0>F      null<8,8,1>F    { align1 1Q };
+math inv(16)    g10<1>F         g2<0,1,0>F      null<8,8,1>F    { align1 1H };
+math inv(8)     g11<1>.xyzF     g2<0>.xyzzF     null<4>F        { align16 1Q };
+math sqrt(8)    g13<1>.xF       g12<4>.xF       null<4>F        { align16 1Q };
+math sqrt(8)    g9<1>F          g8<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math sqrt(16)   g6<1>F          g4<8,8,1>F      null<8,8,1>F    { align1 1H };
+math pow(8)     g20<1>F         g14<8,8,1>F     g20<0,1,0>F     { align1 1Q };
+math pow(16)    g21<1>F         g19<8,8,1>F     g25<0,1,0>F     { align1 1H };
+math intmod(8)  g13<1>UD        g6<0>UD         g5.4<0>.zUD     { align16 1Q };
+math pow(8)     g14<1>.xF       g13<4>.xF       g12<4>.xF       { align16 1Q };
+math log(8)     g22<1>F         g20<8,8,1>F     null<8,8,1>F    { align1 1Q };
+math log(16)    g4<1>F          g44<8,8,1>F     null<8,8,1>F    { align1 1H };
+math cos(8)     g5<1>.yF        g14<4>.xF       null<4>F        { align16 1Q };
+math sin(8)     g21<1>.xF       g16<4>.xF       null<4>F        { align16 1Q };
+math exp(8)     g16<1>.xF       g15<4>.xF       null<4>F        { align16 1Q };
+math log(8)     g15<1>.xF       g14<4>.xF       null<4>F        { align16 1Q };
+math intdiv(8)  g9<1>.xyD       g1<0>.xD        g1<0>.yzzzD     { align16 1Q };
+math exp(8)     g124<1>F        g5<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math exp(16)    g120<1>F        g7<8,8,1>F      null<8,8,1>F    { align1 1H };
+math intdiv(8)  g14<1>.xyzUD    g6<0>.xyzzUD    g6.4<0>.xyzzUD  { align16 1Q };
+math cos(8)     g127<1>F        g5<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math cos(16)    g126<1>F        g7<8,8,1>F      null<8,8,1>F    { align1 1H };
+math intdiv(8)  g4<1>D          g2<0,1,0>D      g2.4<0,1,0>D    { align1 1Q };
+math intdiv(8)  g4<1>D          g2<0,1,0>D      g2.4<0,1,0>D    { align1 2Q };
+math rsq(8)     g69<1>.xF       (abs)g68<4>.xF  null<4>F        { align16 1Q };
+math rsq(8)     g47<1>F         g46<8,8,1>F     null<8,8,1>F    { align1 1Q };
+math rsq(16)    g84<1>F         g82<8,8,1>F     null<8,8,1>F    { align1 1H };
+math.sat exp(8) g3<1>F          g2<0,1,0>F      null<8,8,1>F    { align1 1Q };
+math.sat exp(16) g3<1>F         g2<0,1,0>F      null<8,8,1>F    { align1 1H };
+math sin(8)     g3<1>F          g2<0,1,0>F      null<8,8,1>F    { align1 1Q };
+math sin(16)    g3<1>F          g2<0,1,0>F      null<8,8,1>F    { align1 1H };
+math intdiv(8)  g126<1>UD       g4<0,1,0>UD     g6<8,8,1>UD     { align1 1Q };
+math intdiv(8)  g125<1>UD       g4<0,1,0>UD     g7<8,8,1>UD     { align1 2Q };
+math.sat rsq(8) g116<1>F        (abs)g6<4>.xF   null<4>F        { align16 1Q };
+math.sat pow(8) g116<1>F        g2<4>.xF        g2<4>.yF        { align16 1Q };
+math intmod(8)  g44<1>UD        g43<8,8,1>UD    g12<8,8,1>UD    { align1 1Q };
+math intmod(8)  g73<1>UD        g71<8,8,1>UD    g13<8,8,1>UD    { align1 2Q };
+math.sat inv(8) g116<1>.xF      g1<0>.xF        null<4>F        { align16 1Q };
+math.sat log(8) g116<1>F        g6<4>.xF        null<4>F        { align16 1Q };

diff --git a/src/intel/tools/tests/gen7/math.expected b/src/intel/tools/tests/gen7/math.expected
new file mode 100644 (file)
index 0000000..f7c1eb6
--- /dev/null
+++ b/src/intel/tools/tests/gen7/math.expected
@@ -0,0 +1,39 @@
+38 00 60 01 bd 73 c0 20 40 00 00 00 00 00 8d 00
+38 00 80 01 bd 73 40 21 40 00 00 00 00 00 8d 00
+38 01 60 01 bd 73 67 21 44 00 0a 00 04 00 6e 00
+38 01 60 04 bd 73 a1 21 80 01 60 00 04 00 6e 00
+38 00 60 04 bd 73 20 21 00 01 8d 00 00 00 8d 00
+38 00 80 04 bd 73 c0 20 80 00 8d 00 00 00 8d 00
+38 00 60 0a bd 77 80 22 c0 01 8d 00 80 02 00 00
+38 00 80 0a bd 77 a0 22 60 02 8d 00 20 03 00 00
+38 01 60 0d 21 04 af 21 c4 00 0e 00 ba 00 0a 00
+38 01 60 0a bd 77 c1 21 a0 01 60 00 80 01 60 00
+38 00 60 02 bd 73 c0 22 80 02 8d 00 00 00 8d 00
+38 00 80 02 bd 73 80 20 80 05 8d 00 00 00 8d 00
+38 01 60 07 bd 73 a2 20 c0 01 60 00 04 00 6e 00
+38 01 60 06 bd 73 a1 22 00 02 60 00 04 00 6e 00
+38 01 60 03 bd 73 01 22 e0 01 60 00 04 00 6e 00
+38 01 60 02 bd 73 e1 21 c0 01 60 00 04 00 6e 00
+38 01 60 0c a5 14 23 21 20 00 00 00 29 00 0a 00
+38 00 60 03 bd 73 80 2f a0 00 8d 00 00 00 8d 00
+38 00 80 03 bd 73 00 2f e0 00 8d 00 00 00 8d 00
+38 01 60 0c 21 04 c7 21 c4 00 0a 00 d4 00 0a 00
+38 00 60 07 bd 73 e0 2f a0 00 8d 00 00 00 8d 00
+38 00 80 07 bd 73 c0 2f e0 00 8d 00 00 00 8d 00
+38 00 60 0c a5 14 80 20 40 00 00 00 50 00 00 00
+38 10 60 0c a5 14 80 20 40 00 00 00 50 00 00 00
+38 01 60 05 bd 73 a1 28 80 28 60 00 04 00 6e 00
+38 00 60 05 bd 73 e0 25 c0 05 8d 00 00 00 8d 00
+38 00 80 05 bd 73 80 2a 40 0a 8d 00 00 00 8d 00
+38 00 60 83 bd 73 60 20 40 00 00 00 00 00 8d 00
+38 00 80 83 bd 73 60 20 40 00 00 00 00 00 8d 00
+38 00 60 06 bd 73 60 20 40 00 00 00 00 00 8d 00
+38 00 80 06 bd 73 60 20 40 00 00 00 00 00 8d 00
+38 00 60 0c 21 04 c0 2f 80 00 00 00 c0 00 8d 00
+38 10 60 0c 21 04 a0 2f 80 00 00 00 e0 00 8d 00
+38 01 60 85 bd 73 8f 2e c0 20 60 00 04 00 6e 00
+38 01 60 8a bd 77 8f 2e 40 00 60 00 45 00 65 00
+38 00 60 0d 21 04 80 25 60 05 8d 00 80 01 8d 00
+38 10 60 0d 21 04 20 29 e0 08 8d 00 a0 01 8d 00
+38 01 60 81 bd 73 81 2e 20 00 00 00 04 00 6e 00
+38 01 60 82 bd 73 8f 2e c0 00 60 00 04 00 6e 00

diff --git a/src/intel/tools/tests/gen7/mov.asm b/src/intel/tools/tests/gen7/mov.asm
new file mode 100644 (file)
index 0000000..ef36ad8
--- /dev/null
+++ b/src/intel/tools/tests/gen7/mov.asm
@@ -0,0 +1,147 @@
+mov(8)          g126<1>F        g4<8,8,1>D                      { align1 1Q };
+mov(8)          g124<1>F        g126<8,8,1>F                    { align1 1Q };
+mov(16)         g124<1>F        g4<8,8,1>D                      { align1 1H };
+mov(16)         g120<1>F        g124<8,8,1>F                    { align1 1H };
+mov(8)          g114<1>D        0D                              { align16 1Q };
+mov(8)          g115<1>F        0x41880000F      /* 17F */      { align16 1Q };
+mov(8)          g113<1>UD       g0<4>UD                         { align16 WE_all 1Q };
+mov.sat(8)      g116<1>F        g4<4>F                          { align16 1Q };
+mov(8)          g114<1>.wF      g5<4>.xF                        { align16 1Q };
+mov(4)          g114<1>F        g2.3<8,2,4>F                    { align1 WE_all 1N };
+mov(8)          g125<1>F        0x0F             /* 0F */       { align1 1Q };
+mov(16)         g122<1>F        0x0F             /* 0F */       { align1 1H };
+mov(8)          g2<1>F          g6<8,4,1>UW                     { align1 1Q };
+mov(8)          g7<1>D          g2<8,8,1>F                      { align1 1Q };
+mov(16)         g2<1>F          g4<8,8,1>UW                     { align1 1H };
+mov(16)         g8<1>D          g2<8,8,1>F                      { align1 1H };
+mov(8)          g39<1>D         g3.4<0>D                        { align16 1Q };
+mov(8)          g12<1>F         0x30003000VF    /* [0F, 1F, 0F, 1F]VF */ { align16 1Q };
+mov(8)          g51<1>UD        0x00000000UD                    { align1 WE_all 1Q };
+mov(1)          g51.5<1>UD      0x0000ff00UD                    { align1 WE_all 1N };
+mov(1)          g51<1>UD        g[a0]<0,1,0>UD                  { align1 WE_all 1N };
+mov(2)          g12<1>UD        g0<0,1,0>UD                     { align1 WE_all 1N };
+mov(8)          g13<1>D         g50<4>D                         { align16 WE_all 1Q };
+mov(8)          g15<1>.xUD      g5<0>.wUD                       { align16 1Q };
+(+f0.0.any4h) mov(8) g19<1>.xD  -1D                             { align16 1Q };
+mov.z.f0.0(8)   null<1>F        g11<0>.xUD                      { align16 1Q };
+mov(8)          g126<1>F        0x00000000UD                    { align1 WE_all 1Q };
+mov(1)          g51<1>F         0x3189705fF      /* 4e-09F */   { align1 WE_all 1N };
+mov(1)          g126<1>D        0D                              { align1 WE_all 1N };
+mov(1)          g126<1>D        g39<0,1,0>D                     { align1 WE_all 1N };
+mov(8)          g116<1>.xD      1059749626D                     { align16 NoDDClr 1Q };
+mov(8)          g116<1>.yD      1143373824D                     { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g117<1>.yD      -1093874483D                    { align16 NoDDChk 1Q };
+mov(8)          g117<1>.xzF     0x7e0020VF      /* [0.5F, 0F, 30F, 0F]VF */ { align16 NoDDChk 1Q };
+mov(8)          g7<1>UD         g0<8,8,1>UD                     { align1 WE_all 1Q };
+mov(8)          g21<1>UD        g0<8,8,1>UD                     { align1 WE_all 2Q };
+mov(8)          g23<1>F         g6<0,1,0>F                      { align1 2Q };
+mov(1)          g21.2<1>UD      0x000003f2UD                    { align1 WE_all 3N };
+mov(8)          g8<1>.xD        g27<4>.xD                       { align16 NoDDClr 1Q };
+mov(8)          g8<1>.yD        g4<0>.yD                        { align16 NoDDChk 1Q };
+mov(8)          g10<1>.xF       -g12<4>.xD                      { align16 1Q };
+mov(8)          g13<1>.xyD      acc0<4>D                        { align16 1Q };
+mov(8)          g116<1>.xF      -g9<4>.xD                       { align16 NoDDClr 1Q };
+mov(8)          g115<1>.yUD     0x00000000UD                    { align16 NoDDChk 1Q };
+mov(2)          g113.3<1>UD     0x00000000UD                    { align1 WE_all 1N };
+mov(2)          g113.4<1>UW     g12<8,1,0>UW                    { align1 WE_all 1N };
+mov(8)          g38<1>UD        g1.7<0,1,0>D                    { align1 1Q };
+mov(8)          g7<1>UD         g0.1<0,1,0>UD                   { align1 1Q };
+mov(8)          g19<1>.xD       g18<4>.xF                       { align16 1Q };
+mov(8)          g8<1>D          1065353216D                     { align16 WE_all 1Q };
+mov(8)          g5<1>F          g3.3<0,1,0>UD                   { align1 1Q };
+mov(16)         g5<1>F          g3.3<0,1,0>UD                   { align1 1H };
+mov.sat(8)      g116<1>.xF      0x3f800000F      /* 1F */       { align16 NoDDClr 1Q };
+mov.sat(8)      g116<1>.yF      0x3f666666F      /* 0.9F */     { align16 NoDDClr,NoDDChk 1Q };
+mov.sat(8)      g116<1>.wF      0x3f333333F      /* 0.7F */     { align16 NoDDChk 1Q };
+mov(8)          g19<1>.yzwD     0x48403000VF    /* [0F, 1F, 2F, 3F]VF */ { align16 1Q };
+mov(8)          g12<1>F         g11<4>UD                        { align16 1Q };
+(+f0.0.all4h) mov(8) g13<1>.xD  -1D                             { align16 1Q };
+mov(16)         g122<1>UD       g0<8,8,1>UD                     { align1 WE_all 1H };
+mov(8)          g116<1>.yF      g56<4>.xD                       { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g116<1>.wF      g58<4>.xD                       { align16 NoDDChk 1Q };
+mov(8)          g115<1>.zwF     0x30000000VF    /* [0F, 0F, 0F, 1F]VF */ { align16 NoDDClr 1Q };
+mov(8)          g26<1>.xUD      0x00000001UD                    { align16 1Q };
+mov(8)          g116<1>.xyD     g4<4>.xyyyD                     { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g14<1>D         0D                              { align1 1Q };
+mov(16)         g20<1>D         0D                              { align1 1H };
+mov(8)          g3<1>.xF        -g16<4>.xF                      { align16 NoDDChk 1Q };
+mov(8)          g115<1>.wF      0D                              { align16 NoDDChk 1Q };
+mov(8)          g8<1>.xUD       g1<0>.xF                        { align16 1Q };
+mov(8)          g3<1>.xyzF      g1.4<0>.xyzzUD                  { align16 NoDDClr 1Q };
+mov(8)          g3<1>.wF        g1<0>.xUD                       { align16 NoDDChk 1Q };
+mov(8)          g3<1>D          -g2<0,1,0>D                     { align1 1Q };
+mov(16)         g3<1>D          -g2<0,1,0>D                     { align1 1H };
+mov.nz.f0.0(8)  null<1>.xD      g1<0>.xD                        { align16 1Q };
+mov.sat(8)      g124<1>F        g2.2<0,1,0>F                    { align1 1Q };
+mov.sat(16)     g120<1>F        g2.2<0,1,0>F                    { align1 1H };
+mov(8)          g124<1>UD       g15<8,8,1>F                     { align1 1Q };
+mov(16)         g120<1>UD       g28<8,8,1>F                     { align1 1H };
+mov(8)          g7<1>.xF        -g6<4>.yF                       { align16 NoDDClr 1Q };
+mov(16)         g18<1>UD        g2<8,8,1>D                      { align1 1H };
+mov(1)          f0.1<1>UW       g1.14<0,1,0>UW                  { align1 WE_all 1N };
+mov(1)          g123.14<1>UW    f0.1<0,1,0>UW                   { align1 WE_all 1N };
+mov.nz.f0.0(8)  null<1>D        g2<8,8,1>D                      { align1 1Q };
+mov.nz.f0.0(16) null<1>D        g89<8,8,1>D                     { align1 1H };
+mov.sat(8)      g116<1>.wF      g20<4>.wF                       { align16 NoDDChk 1Q };
+mov.z.f0.0(8)   g29<1>.xD       g28<4>.xF                       { align16 1Q };
+mov(8)          g26<1>UD        g2<8,8,1>UD                     { align1 2Q };
+mov(8)          g34<1>D         g3<8,8,1>D                      { align1 2Q };
+mov.sat(8)      g116<1>F        0x3f800000F      /* 1F */       { align16 1Q };
+mov(8)          g7<1>.xUD       2D                              { align16 1Q };
+mov.sat(8)      g116<1>F        -g6<4>D                         { align16 1Q };
+mov(8)          g117<1>.yF      g4<4>.yF                        { align16 NoDDClr,NoDDChk 1Q };
+mov(1)          f1<1>UD         g1.7<0,1,0>UD                   { align1 WE_all 1N };
+mov(8)          g119<1>.zwD     0x706e0000VF    /* [0F, 0F, 15F, 16F]VF */ { align16 NoDDChk 1Q };
+mov.sat(8)      g116<1>.xyzF    -g11<4>.xyzzD                   { align16 NoDDClr 1Q };
+mov(8)          g26<1>UD        0D                              { align1 WE_all 1Q };
+mov(1)          g13.7<1>UD      65535D                          { align1 WE_all 1N };
+mov(1)          g26.7<1>UD      f0.1<0,1,0>UW                   { align1 WE_all 1N };
+mov(8)          g18<1>UD        0D                              { align1 WE_all 2Q };
+mov(1)          g18.7<1>UD      65535D                          { align1 WE_all 3N };
+mov(1)          g2.7<1>UD       f0.1<0,1,0>UW                   { align1 WE_all 3N };
+mov(1)          g2.7<1>UD       g1.7<0,1,0>UD                   { align1 WE_all 3N };
+mov(8)          g9<1>UD         0x00000000UD                    { align16 WE_all 1Q };
+mov(8)          g6<1>UD         0D                              { align1 1Q };
+mov(16)         g8<1>UD         0D                              { align1 1H };
+mov(8)          g8<1>UW         0x32103210V                     { align1 WE_all 1Q };
+mov(8)          g116<1>.yzF     0x484000VF      /* [0F, 2F, 3F, 0F]VF */ { align16 NoDDClr,NoDDChk 1Q };
+mov(8)          g22<1>.xUD      0D                              { align16 WE_all 1Q };
+mov(8)          g21<1>.xUD      g13<4>.xD                       { align16 1Q };
+mov.nz.f1.0(4)  null<1>F        g16<4>.xUD                      { align16 WE_all 1N };
+mov(1)          f1<1>UW         f0.1<0,1,0>UW                   { align1 WE_all 1N };
+mov(8)          g5<1>UD         0x00000000UD                    { align1 1Q };
+mov(16)         g7<1>UD         0x00000000UD                    { align1 1H };
+mov.nz.f0.0(8)  null<1>D        0x00000000UD                    { align1 1Q };
+mov.nz.f0.0(16) null<1>D        0x00000000UD                    { align1 1H };
+mov(1)          g2<1>UW         g3<0,1,0>UW                     { align1 WE_all 1N };
+mov(8)          g59<1>.xUD      0x00000020UD                    { align16 NoDDClr 1Q };
+mov(8)          g59<1>.yzwUD    0D                              { align16 NoDDChk 1Q };
+mov(8)          g11<1>D         16D                             { align1 2Q };
+mov.sat(8)      g116<1>.yzF     g1<0>.xxzzF                     { align16 NoDDClr,NoDDChk 1Q };
+mov.sat(8)      g116<1>.xF      -g1<0>.wF                       { align16 NoDDClr 1Q };
+mov.sat(8)      g116<1>.yF      -g11<4>.xD                      { align16 NoDDClr,NoDDChk 1Q };
+mov.sat(8)      g116<1>.wF      -g13<4>.xD                      { align16 NoDDChk 1Q };
+mov(8)          g2<1>UD         g11<16,8,2>UW                   { align1 1Q };
+mov(16)         g6<1>UD         g2<16,8,2>UW                    { align1 1H };
+mov(8)          g27<1>UD        g24.2<32,8,4>UB                 { align1 1Q };
+mov(16)         g38<1>UD        g36<32,8,4>UB                   { align1 1H };
+mov(8)          g19<1>D         g2<16,8,2>W                     { align1 1Q };
+mov(16)         g21<1>D         g6<16,8,2>W                     { align1 1H };
+mov(8)          g27<1>D         g24.2<32,8,4>B                  { align1 1Q };
+mov(16)         g38<1>D         g36<32,8,4>B                    { align1 1H };
+mov(8)          g27<1>F         g24.2<32,8,4>UB                 { align1 1Q };
+mov(16)         g39<1>F         g37<32,8,4>UB                   { align1 1H };
+mov(8)          g25<1>F         g2<16,8,2>W                     { align1 1Q };
+mov(16)         g21<1>F         g6<16,8,2>W                     { align1 1H };
+mov(8)          g27<1>F         g24.2<32,8,4>B                  { align1 1Q };
+mov(16)         g34<1>F         g32<32,8,4>B                    { align1 1H };
+mov(8)          g3<1>F          0x0F             /* 0F */       { align1 WE_all 1Q };
+mov(16)         g2<1>UD         0x00000000UD                    { align1 WE_all 1H };
+mov(8)          g2<1>D          0x00000000UD                    { align1 1Q };
+mov(16)         g2<1>D          0x00000000UD                    { align1 1H };
+mov(1)          g1<1>UW         g2<0>UW                         { align16 WE_all 1N };
+mov(1)          f1<1>UD         0x00000000UD                    { align1 WE_all 1N };
+mov.z.f1.0(8)   null<1>UW       0x0000UW                        { align1 1Q };
+mov.z.f1.0(16)  null<1>UW       0x0000UW                        { align1 1H };
+mov.z.f0.0(8)   null<1>D        g21<8,8,1>F                     { align1 1Q };
+mov.z.f0.0(16)  null<1>D        g86<8,8,1>F                     { align1 1H };

diff --git a/src/intel/tools/tests/gen7/mov.expected b/src/intel/tools/tests/gen7/mov.expected
new file mode 100644 (file)
index 0000000..94680fd
--- /dev/null
+++ b/src/intel/tools/tests/gen7/mov.expected
@@ -0,0 +1,147 @@
+01 00 60 00 bd 00 c0 2f 80 00 8d 00 00 00 00 00
+01 00 60 00 bd 03 80 2f c0 0f 8d 00 00 00 00 00
+01 00 80 00 bd 00 80 2f 80 00 8d 00 00 00 00 00
+01 00 80 00 bd 03 00 2f 80 0f 8d 00 00 00 00 00
+01 01 60 00 e5 10 4f 2e 00 00 00 00 00 00 00 00
+01 01 60 00 fd 73 6f 2e 00 00 00 00 00 00 88 41
+01 03 60 00 21 00 2f 2e 04 00 6e 00 00 00 00 00
+01 01 60 80 bd 03 8f 2e 84 00 6e 00 00 00 00 00
+01 01 60 00 bd 03 48 2e a0 00 60 00 00 00 00 00
+01 02 40 00 bd 03 40 2e 4c 00 87 00 00 00 00 00
+01 00 60 00 fd 73 a0 2f 00 00 00 00 00 00 00 00
+01 00 80 00 fd 73 40 2f 00 00 00 00 00 00 00 00
+01 00 60 00 3d 01 40 20 c0 00 89 00 00 00 00 00
+01 00 60 00 a5 03 e0 20 40 00 8d 00 00 00 00 00
+01 00 80 00 3d 01 40 20 80 00 8d 00 00 00 00 00
+01 00 80 00 a5 03 00 21 40 00 8d 00 00 00 00 00
+01 01 60 00 a5 00 ef 24 74 00 0e 00 00 00 00 00
+01 01 60 00 fd 52 8f 21 00 00 00 00 00 30 00 30
+01 02 60 00 61 00 60 26 00 00 00 00 00 00 00 00
+01 02 00 00 61 00 74 26 00 00 00 00 00 ff 00 00
+01 02 00 00 21 00 60 26 00 80 00 00 00 00 00 00
+01 02 20 00 21 00 80 21 00 00 00 00 00 00 00 00
+01 03 60 00 a5 00 af 21 44 06 6e 00 00 00 00 00
+01 01 60 00 21 00 e1 21 af 00 0f 00 00 00 00 00
+01 01 66 00 e5 10 61 22 00 00 00 00 ff ff ff ff
+01 01 60 01 3c 00 0f 20 60 01 00 00 00 00 00 00
+01 02 60 00 7d 00 c0 2f 00 00 00 00 00 00 00 00
+01 02 00 00 fd 73 60 26 00 00 00 00 5f 70 89 31
+01 02 00 00 e5 10 c0 2f 00 00 00 00 00 00 00 00
+01 02 00 00 a5 00 c0 2f e0 04 00 00 00 00 00 00
+01 05 60 00 e5 10 81 2e 00 00 00 00 fa 7e 2a 3f
+01 0d 60 00 e5 10 82 2e 00 00 00 00 00 80 26 44
+01 09 60 00 e5 10 a2 2e 00 00 00 00 cd cc cc be
+01 09 60 00 fd 52 a5 2e 00 00 00 00 20 00 7e 00
+01 02 60 00 21 00 e0 20 00 00 8d 00 00 00 00 00
+01 12 60 00 21 00 a0 22 00 00 8d 00 00 00 00 00
+01 10 60 00 bd 03 e0 22 c0 00 00 00 00 00 00 00
+01 12 00 00 61 00 a8 22 00 00 00 00 f2 03 00 00
+01 05 60 00 a5 00 01 21 60 03 60 00 00 00 00 00
+01 09 60 00 a5 00 02 21 85 00 05 00 00 00 00 00
+01 01 60 00 bd 00 41 21 80 41 60 00 00 00 00 00
+01 01 60 00 85 00 a3 21 04 04 6e 00 00 00 00 00
+01 05 60 00 bd 00 81 2e 20 41 60 00 00 00 00 00
+01 09 60 00 61 00 62 2e 00 00 00 00 00 00 00 00
+01 02 20 00 61 00 2c 2e 00 00 00 00 00 00 00 00
+01 02 20 00 29 01 28 2e 80 01 80 00 00 00 00 00
+01 00 60 00 a1 00 c0 24 3c 00 00 00 00 00 00 00
+01 00 60 00 21 00 e0 20 04 00 00 00 00 00 00 00
+01 01 60 00 a5 03 61 22 40 02 60 00 00 00 00 00
+01 03 60 00 e5 10 0f 21 00 00 00 00 00 00 80 3f
+01 00 60 00 3d 00 a0 20 6c 00 00 00 00 00 00 00
+01 00 80 00 3d 00 a0 20 6c 00 00 00 00 00 00 00
+01 05 60 80 fd 73 81 2e 00 00 00 00 00 00 80 3f
+01 0d 60 80 fd 73 82 2e 00 00 00 00 66 66 66 3f
+01 09 60 80 fd 73 88 2e 00 00 00 00 33 33 33 3f
+01 01 60 00 e5 52 6e 22 00 00 00 00 00 30 40 48
+01 01 60 00 3d 00 8f 21 64 01 6e 00 00 00 00 00
+01 01 67 00 e5 10 a1 21 00 00 00 00 ff ff ff ff
+01 02 80 00 21 00 40 2f 00 00 8d 00 00 00 00 00
+01 0d 60 00 bd 00 82 2e 00 07 60 00 00 00 00 00
+01 09 60 00 bd 00 88 2e 40 07 60 00 00 00 00 00
+01 05 60 00 fd 52 6c 2e 00 00 00 00 00 00 00 30
+01 01 60 00 61 00 41 23 00 00 00 00 01 00 00 00
+01 0d 60 00 a5 00 83 2e 84 00 65 00 00 00 00 00
+01 00 60 00 e5 10 c0 21 00 00 00 00 00 00 00 00
+01 00 80 00 e5 10 80 22 00 00 00 00 00 00 00 00
+01 09 60 00 bd 03 61 20 00 42 60 00 00 00 00 00
+01 09 60 00 fd 10 68 2e 00 00 00 00 00 00 00 00
+01 01 60 00 a1 03 01 21 20 00 00 00 00 00 00 00
+01 05 60 00 3d 00 67 20 34 00 0a 00 00 00 00 00
+01 09 60 00 3d 00 68 20 20 00 00 00 00 00 00 00
+01 00 60 00 a5 00 60 20 40 40 00 00 00 00 00 00
+01 00 80 00 a5 00 60 20 40 40 00 00 00 00 00 00
+01 01 60 02 a4 00 01 20 20 00 00 00 00 00 00 00
+01 00 60 80 bd 03 80 2f 48 00 00 00 00 00 00 00
+01 00 80 80 bd 03 00 2f 48 00 00 00 00 00 00 00
+01 00 60 00 a1 03 80 2f e0 01 8d 00 00 00 00 00
+01 00 80 00 a1 03 00 2f 80 03 8d 00 00 00 00 00
+01 05 60 00 bd 03 e1 20 c5 40 65 00 00 00 00 00
+01 00 80 00 a1 00 40 22 40 00 8d 00 00 00 00 00
+01 02 00 00 28 01 02 26 3c 00 00 00 00 00 00 00
+01 02 00 00 09 01 7c 2f 02 06 00 00 00 00 00 00
+01 00 60 02 a4 00 00 20 40 00 8d 00 00 00 00 00
+01 00 80 02 a4 00 00 20 20 0b 8d 00 00 00 00 00
+01 09 60 80 bd 03 88 2e 8f 02 6f 00 00 00 00 00
+01 01 60 01 a5 03 a1 23 80 03 60 00 00 00 00 00
+01 10 60 00 21 00 40 23 40 00 8d 00 00 00 00 00
+01 10 60 00 a5 00 40 24 60 00 8d 00 00 00 00 00
+01 01 60 80 fd 73 8f 2e 00 00 00 00 00 00 80 3f
+01 01 60 00 e1 10 e1 20 00 00 00 00 02 00 00 00
+01 01 60 80 bd 00 8f 2e c4 40 6e 00 00 00 00 00
+01 0d 60 00 bd 03 a2 2e 85 00 65 00 00 00 00 00
+01 02 00 00 20 00 20 26 3c 00 00 00 00 00 00 00
+01 09 60 00 e5 52 ec 2e 00 00 00 00 00 00 6e 70
+01 05 60 80 bd 00 87 2e 64 41 6a 00 00 00 00 00
+01 02 60 00 e1 10 40 23 00 00 00 00 00 00 00 00
+01 02 00 00 e1 10 bc 21 00 00 00 00 ff ff 00 00
+01 02 00 00 01 01 5c 23 02 06 00 00 00 00 00 00
+01 12 60 00 e1 10 40 22 00 00 00 00 00 00 00 00
+01 12 00 00 e1 10 5c 22 00 00 00 00 ff ff 00 00
+01 12 00 00 01 01 5c 20 02 06 00 00 00 00 00 00
+01 12 00 00 21 00 5c 20 3c 00 00 00 00 00 00 00
+01 03 60 00 61 00 2f 21 00 00 00 00 00 00 00 00
+01 00 60 00 e1 10 c0 20 00 00 00 00 00 00 00 00
+01 00 80 00 e1 10 00 21 00 00 00 00 00 00 00 00
+01 02 60 00 69 63 00 21 00 00 00 00 10 32 10 32
+01 0d 60 00 fd 52 86 2e 00 00 00 00 00 40 48 00
+01 03 60 00 e1 10 c1 22 00 00 00 00 00 00 00 00
+01 01 60 00 a1 00 a1 22 a0 01 60 00 00 00 00 00
+01 03 40 02 3c 00 0f 20 00 02 60 04 00 00 00 00
+01 02 00 00 08 01 20 26 02 06 00 00 00 00 00 00
+01 00 60 00 61 00 a0 20 00 00 00 00 00 00 00 00
+01 00 80 00 61 00 e0 20 00 00 00 00 00 00 00 00
+01 00 60 02 64 00 00 20 00 00 00 00 00 00 00 00
+01 00 80 02 64 00 00 20 00 00 00 00 00 00 00 00
+01 02 00 00 29 01 40 20 60 00 00 00 00 00 00 00
+01 05 60 00 61 00 61 27 00 00 00 00 20 00 00 00
+01 09 60 00 e1 10 6e 27 00 00 00 00 00 00 00 00
+01 10 60 00 e5 10 60 21 00 00 00 00 10 00 00 00
+01 0d 60 80 bd 03 86 2e 20 00 0a 00 00 00 00 00
+01 05 60 80 bd 03 81 2e 2f 40 0f 00 00 00 00 00
+01 0d 60 80 bd 00 82 2e 60 41 60 00 00 00 00 00
+01 09 60 80 bd 00 88 2e a0 41 60 00 00 00 00 00
+01 00 60 00 21 01 40 20 60 01 ae 00 00 00 00 00
+01 00 80 00 21 01 c0 20 40 00 ae 00 00 00 00 00
+01 00 60 00 21 02 60 23 02 03 cf 00 00 00 00 00
+01 00 80 00 21 02 c0 24 80 04 cf 00 00 00 00 00
+01 00 60 00 a5 01 60 22 40 00 ae 00 00 00 00 00
+01 00 80 00 a5 01 a0 22 c0 00 ae 00 00 00 00 00
+01 00 60 00 a5 02 60 23 02 03 cf 00 00 00 00 00
+01 00 80 00 a5 02 c0 24 80 04 cf 00 00 00 00 00
+01 00 60 00 3d 02 60 23 02 03 cf 00 00 00 00 00
+01 00 80 00 3d 02 e0 24 a0 04 cf 00 00 00 00 00
+01 00 60 00 bd 01 20 23 40 00 ae 00 00 00 00 00
+01 00 80 00 bd 01 a0 22 c0 00 ae 00 00 00 00 00
+01 00 60 00 bd 02 60 23 02 03 cf 00 00 00 00 00
+01 00 80 00 bd 02 40 24 00 04 cf 00 00 00 00 00
+01 02 60 00 fd 73 60 20 00 00 00 00 00 00 00 00
+01 02 80 00 61 00 40 20 00 00 00 00 00 00 00 00
+01 00 60 00 65 00 40 20 00 00 00 00 00 00 00 00
+01 00 80 00 65 00 40 20 00 00 00 00 00 00 00 00
+01 03 00 00 29 01 2f 20 44 00 0e 00 00 00 00 00
+01 02 00 00 60 00 20 26 00 00 00 00 00 00 00 00
+01 00 60 01 68 21 00 20 00 00 00 04 00 00 00 00
+01 00 80 01 68 21 00 20 00 00 00 04 00 00 00 00
+01 00 60 01 a4 03 00 20 a0 02 8d 00 00 00 00 00
+01 00 80 01 a4 03 00 20 c0 0a 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/mul.asm b/src/intel/tools/tests/gen7/mul.asm
new file mode 100644 (file)
index 0000000..d4fe5a5
--- /dev/null
+++ b/src/intel/tools/tests/gen7/mul.asm
@@ -0,0 +1,48 @@
+mul(8)          g124<1>F        g4<8,8,1>F      g6<8,8,1>F      { align1 1Q };
+mul(16)         g120<1>F        g6<8,8,1>F      g10<8,8,1>F     { align1 1H };
+mul(8)          g45<1>.xF       g5.4<0>.zF      g5.4<0>.zF      { align16 1Q };
+mul(8)          g39<1>.xD       g5<0>.xD        2D              { align16 1Q };
+mul(8)          acc0<1>D        g5.4<0>.zwwwD   g6<0>.xyyyD     { align16 1Q };
+mul(8)          g124<1>F        g4<8,8,1>F      0x3c23d70aF  /* 0.01F */ { align1 1Q };
+mul(16)         g120<1>F        g4<8,8,1>F      0x3c23d70aF  /* 0.01F */ { align1 1H };
+mul(8)          g9<1>.xyF       g8<4>.xyyyF     0x40000000F  /* 2F */ { align16 1Q };
+mul.sat(8)      g19<1>.xyzF     g15<4>.xyzzF    g18<4>.xF       { align16 1Q };
+mul(8)          g116<1>.xyF     g6<4>.xyyyF     0x3f000000F  /* 0.5F */ { align16 NoDDClr 1Q };
+mul.sat(8)      g2<1>F          g6<8,8,1>F      g5<8,8,1>F      { align1 1Q };
+mul.sat(16)     g16<1>F         g12<8,8,1>F     g10<8,8,1>F     { align1 1H };
+mul(8)          g3<1>D          g2<0,1,0>D      36W             { align1 1Q };
+mul(16)         g3<1>D          g2<0,1,0>D      36W             { align1 1H };
+mul(8)          g29<1>F         g28<4>.yF       0x3000VF /* [0F, 1F, 0F, 0F]VF */ { align16 1Q };
+mul(8)          g115<1>.xyzF    g2<4>.xyzzF     g8<4>.xF        { align16 NoDDClr 1Q };
+mul.l.f0.0(8)   null<1>.xF      g6<0>.xF        g5.4<0>.wF      { align16 1Q };
+mul.sat(8)      g10<1>F         g64<8,8,1>F     0x40a00001F  /* 5F */ { align1 1Q };
+mul.sat(16)     g13<1>F         g11<8,8,1>F     0x40a00001F  /* 5F */ { align1 1H };
+mul(2)          g113.3<1>UD     g35<8,2,4>UD    0x0005UW        { align1 WE_all 1N };
+mul(8)          acc0<1>UD       g10<8,8,1>UD    0xaaaaaaabUD    { align1 1Q };
+mul(8)          acc0<1>D        g10<8,8,1>D     1431655766D     { align1 1Q };
+mul(8)          acc0<1>UD       g23<8,8,1>UD    0xaaaaaaabUD    { align1 2Q };
+mul(8)          acc0<1>D        g23<8,8,1>D     1431655766D     { align1 2Q };
+mul(8)          g116<1>.yF      g12<4>.xF       0x3b800000F  /* 0.00390625F */ { align16 NoDDChk 1Q };
+mul(8)          g4<1>D          g2<0,1,0>D      g2.6<0,1,0>UW   { align1 1Q };
+mul(16)         g4<1>D          g2<0,1,0>D      g2.6<0,1,0>UW   { align1 1H };
+mul.l.f0.0(8)   g20<1>F         g2<8,8,1>F      0x42700000F  /* 60F */ { align1 1Q };
+mul.l.f0.0(16)  g32<1>F         g2<8,8,1>F      0x42700000F  /* 60F */ { align1 1H };
+mul(8)          g115<1>.xF      g15<4>.xF       0x40a66666F  /* 5.2F */ { align16 NoDDClr,NoDDChk 1Q };
+mul.sat(8)      g116<1>F        g6<4>F          0x3b800000F  /* 0.00390625F */ { align16 1Q };
+mul(8)          acc0<1>D        g1<4>.xD        741092396D      { align16 1Q };
+mul(8)          acc0<1>UD       g4<8,8,1>UD     g8<8,8,1>UD     { align1 1Q };
+mul(8)          acc0<1>UD       g5<8,8,1>UD     g13<8,8,1>UD    { align1 2Q };
+mul(8)          acc0<1>D        g5<8,8,1>D      g9<8,8,1>D      { align1 1Q };
+mul(8)          acc0<1>D        g6<8,8,1>D      g14<8,8,1>D     { align1 2Q };
+mul(8)          g3<1>D          g2<0,1,0>D      0x77b9UW        { align1 1Q };
+mul(16)         g3<1>D          g2<0,1,0>D      0x77b9UW        { align1 1H };
+mul(8)          acc0<1>UD       g8<4>.xUD       0xaaaaaaabUD    { align16 1Q };
+mul(8)          g17<1>.xD       g3<4>.xD        g11<4>.xD       { align16 1Q };
+mul.sat(8)      g116<1>.xyF     g1<0>.wzzzF     g3<4>.wzzzF     { align16 NoDDClr 1Q };
+mul.sat(8)      g116<1>.zwF     g1<0>.yyyxF     g3<4>.yyyxF     { align16 NoDDChk 1Q };
+mul.sat(8)      g116<1>F        g4<4>F          0x20303030VF /* [1F, 1F, 1F, 0.5F]VF */ { align16 1Q };
+mul(8)          acc0<1>UD       g9<4>UD         g11<4>UD        { align16 1Q };
+mul(1)          g3<1>UD         g15<0,1,0>UD    0x0101UW        { align1 WE_all 1N };
+mul(8)          g3<1>.wF        g1<0>.zF        g9<4>.xF        { align16 NoDDClr,NoDDChk 1Q };
+mul(8)          g117<1>.yF      g36<4>.xF       g19<4>.xF       { align16 NoDDChk 1Q };
+mul.sat(8)      g116<1>.xyzF    g12<4>.xF       0x3030VF /* [1F, 1F, 0F, 0F]VF */ { align16 NoDDClr 1Q };

diff --git a/src/intel/tools/tests/gen7/mul.expected b/src/intel/tools/tests/gen7/mul.expected
new file mode 100644 (file)
index 0000000..9e29bdb
--- /dev/null
+++ b/src/intel/tools/tests/gen7/mul.expected
@@ -0,0 +1,48 @@
+41 00 60 00 bd 77 80 2f 80 00 8d 00 c0 00 8d 00
+41 00 80 00 bd 77 00 2f c0 00 8d 00 40 01 8d 00
+41 01 60 00 bd 77 a1 25 ba 00 0a 00 ba 00 0a 00
+41 01 60 00 a5 1c e1 24 a0 00 00 00 02 00 00 00
+41 01 60 00 a4 14 0f 24 be 00 0f 00 c4 00 05 00
+41 00 60 00 bd 7f 80 2f 80 00 8d 00 0a d7 23 3c
+41 00 80 00 bd 7f 00 2f 80 00 8d 00 0a d7 23 3c
+41 01 60 00 bd 7f 23 21 04 01 65 00 00 00 00 40
+41 01 60 80 bd 77 67 22 e4 01 6a 00 40 02 60 00
+41 05 60 00 bd 7f 83 2e c4 00 65 00 00 00 00 3f
+41 00 60 80 bd 77 40 20 c0 00 8d 00 a0 00 8d 00
+41 00 80 80 bd 77 00 22 80 01 8d 00 40 01 8d 00
+41 00 60 00 a5 3c 60 20 40 00 00 00 24 00 24 00
+41 00 80 00 a5 3c 60 20 40 00 00 00 24 00 24 00
+41 01 60 00 bd 5f af 23 85 03 65 00 00 30 00 00
+41 05 60 00 bd 77 67 2e 44 00 6a 00 00 01 60 00
+41 01 60 05 bc 77 01 20 c0 00 00 00 bf 00 0f 00
+41 00 60 80 bd 7f 40 21 00 08 8d 00 01 00 a0 40
+41 00 80 80 bd 7f a0 21 60 01 8d 00 01 00 a0 40
+41 02 20 00 21 2c 2c 2e 60 04 87 00 05 00 05 00
+41 00 60 00 20 0c 00 24 40 01 8d 00 ab aa aa aa
+41 00 60 00 a4 1c 00 24 40 01 8d 00 56 55 55 55
+41 10 60 00 20 0c 00 24 e0 02 8d 00 ab aa aa aa
+41 10 60 00 a4 1c 00 24 e0 02 8d 00 56 55 55 55
+41 09 60 00 bd 7f 82 2e 80 01 60 00 00 00 80 3b
+41 00 60 00 a5 24 80 20 40 00 00 00 4c 00 00 00
+41 00 80 00 a5 24 80 20 40 00 00 00 4c 00 00 00
+41 00 60 05 bd 7f 80 22 40 00 8d 00 00 00 70 42
+41 00 80 05 bd 7f 00 24 40 00 8d 00 00 00 70 42
+41 0d 60 00 bd 7f 61 2e e0 01 60 00 66 66 a6 40
+41 01 60 80 bd 7f 8f 2e c4 00 6e 00 00 00 80 3b
+41 01 60 00 a4 1c 0f 24 20 00 60 00 2c 2c 2c 2c
+41 00 60 00 20 04 00 24 80 00 8d 00 00 01 8d 00
+41 10 60 00 20 04 00 24 a0 00 8d 00 a0 01 8d 00
+41 00 60 00 a4 14 00 24 a0 00 8d 00 20 01 8d 00
+41 10 60 00 a4 14 00 24 c0 00 8d 00 c0 01 8d 00
+41 00 60 00 a5 2c 60 20 40 00 00 00 b9 77 b9 77
+41 00 80 00 a5 2c 60 20 40 00 00 00 b9 77 b9 77
+41 01 60 00 20 0c 0f 24 00 01 60 00 ab aa aa aa
+41 01 60 00 a5 14 21 22 60 00 60 00 60 01 60 00
+41 05 60 80 bd 77 83 2e 2b 00 0a 00 6b 00 6a 00
+41 09 60 80 bd 77 8c 2e 25 00 01 00 65 00 61 00
+41 01 60 80 bd 5f 8f 2e 84 00 6e 00 30 30 30 20
+41 01 60 00 20 04 0f 24 24 01 6e 00 64 01 6e 00
+41 02 00 00 21 2c 60 20 e0 01 00 00 01 01 01 01
+41 0d 60 00 bd 77 68 20 2a 00 0a 00 20 01 60 00
+41 09 60 00 bd 77 a2 2e 80 04 60 00 60 02 60 00
+41 05 60 80 bd 5f 87 2e 80 01 60 00 30 30 00 00

diff --git a/src/intel/tools/tests/gen7/not.asm b/src/intel/tools/tests/gen7/not.asm
new file mode 100644 (file)
index 0000000..f5106c4
--- /dev/null
+++ b/src/intel/tools/tests/gen7/not.asm
@@ -0,0 +1,4 @@
+not(8)          g13<1>.xD       g5.4<0>.wD                      { align16 1Q };
+not.nz.f0.0(8)  null<1>.xD      g13<4>.xD                       { align16 1Q };
+not(8)          g20<1>D         g19<8,8,1>D                     { align1 1Q };
+not(16)         g27<1>D         g25<8,8,1>D                     { align1 1H };

diff --git a/src/intel/tools/tests/gen7/not.expected b/src/intel/tools/tests/gen7/not.expected
new file mode 100644 (file)
index 0000000..5a7df37
--- /dev/null
+++ b/src/intel/tools/tests/gen7/not.expected
@@ -0,0 +1,4 @@
+04 01 60 00 a5 00 a1 21 bf 00 0f 00 00 00 00 00
+04 01 60 02 a4 00 01 20 a0 01 60 00 00 00 00 00
+04 00 60 00 a5 00 80 22 60 02 8d 00 00 00 00 00
+04 00 80 00 a5 00 60 23 20 03 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/or.asm b/src/intel/tools/tests/gen7/or.asm
new file mode 100644 (file)
index 0000000..513eeba
--- /dev/null
+++ b/src/intel/tools/tests/gen7/or.asm
@@ -0,0 +1,20 @@
+or(1)           g113.5<1>UD     g0.5<0,1,0>UD   0x0000ff00UD    { align1 WE_all 1N };
+or.nz.f0.0(8)   null<1>.xUD     g21<4>.xUD      g19<4>.xUD      { align16 1Q };
+or(8)           g13<1>.xyUD     g5.4<0>.zwwwUD  g6<0>.xUD       { align16 1Q };
+or(8)           g10<1>UD        g9<8,8,1>UD     g8<8,8,1>UD     { align1 1Q };
+or(16)          g16<1>UD        g14<8,8,1>UD    g12<8,8,1>UD    { align1 1H };
+(+f0.0) or(8)   g22<1>.xUD      g22<4>.xUD      0x3f800000UD    { align16 1Q };
+or.nz.f0.0(8)   g8<1>UD         g4<8,8,1>UD     g7<8,8,1>UD     { align1 1Q };
+or.nz.f0.0(8)   null<1>UD       g12<8,8,1>UD    g15<8,8,1>UD    { align1 1Q };
+or.nz.f0.0(16)  g12<1>UD        g5<8,8,1>UD     g10<8,8,1>UD    { align1 1H };
+or.nz.f0.0(16)  null<1>UD       g20<8,8,1>UD    g26<8,8,1>UD    { align1 1H };
+(+f0.0) or(8)   g6<1>UD         g6<8,8,1>UD     0x3f800000UD    { align1 1Q };
+(+f0.0) or(16)  g8<1>UD         g8<8,8,1>UD     0x3f800000UD    { align1 1H };
+or(1)           a0<1>UD         g8<0,1,0>UD     0x02427000UD    { align1 WE_all 1N };
+or(1)           a0<1>UD         a0<0,1,0>UD     0x02114000UD    { align1 WE_all 1N };
+or(1)           a0<1>UD         g2<0,1,0>UD     0x0e0b6000UD    { align1 WE_all 3N };
+or(1)           a0<1>UD         a0<0,1,0>UD     g17<0,1,0>UD    { align1 WE_all 1N };
+or(1)           g113.21<1>UB    g59<0,1,0>UB    g59.16<0,1,0>UB { align1 WE_all 1N };
+or(1)           g2<1>UD         g2<0,1,0>UD     g7<0,1,0>UD     { align1 WE_all 1N };
+or(8)           g32<1>UD        g24<8,8,1>UD    0x00281502UD    { align1 1Q };
+or(16)          g47<1>UD        g45<8,8,1>UD    0x00281502UD    { align1 1H };

diff --git a/src/intel/tools/tests/gen7/or.expected b/src/intel/tools/tests/gen7/or.expected
new file mode 100644 (file)
index 0000000..8673a5f
--- /dev/null
+++ b/src/intel/tools/tests/gen7/or.expected
@@ -0,0 +1,20 @@
+06 02 00 00 21 0c 34 2e 14 00 00 00 00 ff 00 00
+06 01 60 02 20 04 01 20 a0 02 60 00 60 02 60 00
+06 01 60 00 21 04 a3 21 be 00 0f 00 c0 00 00 00
+06 00 60 00 21 04 40 21 20 01 8d 00 00 01 8d 00
+06 00 80 00 21 04 00 22 c0 01 8d 00 80 01 8d 00
+06 01 61 00 21 0c c1 22 c0 02 60 00 00 00 80 3f
+06 00 60 02 21 04 00 21 80 00 8d 00 e0 00 8d 00
+06 00 60 02 20 04 00 20 80 01 8d 00 e0 01 8d 00
+06 00 80 02 21 04 80 21 a0 00 8d 00 40 01 8d 00
+06 00 80 02 20 04 00 20 80 02 8d 00 40 03 8d 00
+06 00 61 00 21 0c c0 20 c0 00 8d 00 00 00 80 3f
+06 00 81 00 21 0c 00 21 00 01 8d 00 00 00 80 3f
+06 02 00 00 20 0c 00 22 00 01 00 00 00 70 42 02
+06 02 00 00 00 0c 00 22 00 02 00 00 00 40 11 02
+06 12 00 00 20 0c 00 22 40 00 00 00 00 60 0b 0e
+06 02 00 00 00 04 00 22 00 02 00 00 20 02 00 00
+06 02 00 00 31 46 35 2e 60 07 00 00 70 07 00 00
+06 02 00 00 21 04 40 20 40 00 00 00 e0 00 00 00
+06 00 60 00 21 0c 00 24 00 03 8d 00 02 15 28 00
+06 00 80 00 21 0c e0 25 a0 05 8d 00 02 15 28 00

diff --git a/src/intel/tools/tests/gen7/pln.asm b/src/intel/tools/tests/gen7/pln.asm
new file mode 100644 (file)
index 0000000..1353e70
--- /dev/null
+++ b/src/intel/tools/tests/gen7/pln.asm
@@ -0,0 +1,2 @@
+pln(8)          g124<1>F        g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln(16)         g120<1>F        g6<0,1,0>F      g2<8,8,1>F      { align1 1H };

diff --git a/src/intel/tools/tests/gen7/pln.expected b/src/intel/tools/tests/gen7/pln.expected
new file mode 100644 (file)
index 0000000..17ef47c
--- /dev/null
+++ b/src/intel/tools/tests/gen7/pln.expected
@@ -0,0 +1,2 @@
+5a 00 60 00 bd 77 80 2f 80 00 00 00 40 00 8d 00
+5a 00 80 00 bd 77 00 2f c0 00 00 00 40 00 8d 00

diff --git a/src/intel/tools/tests/gen7/rndd.asm b/src/intel/tools/tests/gen7/rndd.asm
new file mode 100644 (file)
index 0000000..b8dbada
--- /dev/null
+++ b/src/intel/tools/tests/gen7/rndd.asm
@@ -0,0 +1,7 @@
+rndd(8)         g18<1>.xF       g1<0>.xF                        { align16 1Q };
+rndd(8)         g4<1>F          -g2<0,1,0>F                     { align1 1Q };
+rndd(16)        g4<1>F          -g2<0,1,0>F                     { align1 1H };
+rndd(8)         g6<1>.zF        g22<4>.xF                       { align16 NoDDClr 1Q };
+rndd.z.f0.0(8)  null<1>F        g17<8,8,1>F                     { align1 1Q };
+rndd.z.f0.0(16) null<1>F        g38<8,8,1>F                     { align1 1H };
+rndd.sat(8)     g116<1>F        g6<4>F                          { align16 1Q };

diff --git a/src/intel/tools/tests/gen7/rndd.expected b/src/intel/tools/tests/gen7/rndd.expected
new file mode 100644 (file)
index 0000000..e20ac29
--- /dev/null
+++ b/src/intel/tools/tests/gen7/rndd.expected
@@ -0,0 +1,7 @@
+45 01 60 00 bd 03 41 22 20 00 00 00 00 00 00 00
+45 00 60 00 bd 03 80 20 40 40 00 00 00 00 00 00
+45 00 80 00 bd 03 80 20 40 40 00 00 00 00 00 00
+45 05 60 00 bd 03 c4 20 c0 02 60 00 00 00 00 00
+45 00 60 01 bc 03 00 20 20 02 8d 00 00 00 00 00
+45 00 80 01 bc 03 00 20 c0 04 8d 00 00 00 00 00
+45 01 60 80 bd 03 8f 2e c4 00 6e 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/rnde.asm b/src/intel/tools/tests/gen7/rnde.asm
new file mode 100644 (file)
index 0000000..9aeec4a
--- /dev/null
+++ b/src/intel/tools/tests/gen7/rnde.asm
@@ -0,0 +1,3 @@
+rnde(8)         g6<1>F          g3<8,8,1>F                      { align1 1Q };
+rnde(16)        g8<1>F          g4<8,8,1>F                      { align1 1H };
+rnde(8)         g12<1>.xyzF     g6<0>.xyzzF                     { align16 1Q };

diff --git a/src/intel/tools/tests/gen7/rnde.expected b/src/intel/tools/tests/gen7/rnde.expected
new file mode 100644 (file)
index 0000000..a2bed50
--- /dev/null
+++ b/src/intel/tools/tests/gen7/rnde.expected
@@ -0,0 +1,3 @@
+46 00 60 00 bd 03 c0 20 60 00 8d 00 00 00 00 00
+46 00 80 00 bd 03 00 21 80 00 8d 00 00 00 00 00
+46 01 60 00 bd 03 87 21 c4 00 0a 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/rndz.asm b/src/intel/tools/tests/gen7/rndz.asm
new file mode 100644 (file)
index 0000000..c1fa156
--- /dev/null
+++ b/src/intel/tools/tests/gen7/rndz.asm
@@ -0,0 +1,3 @@
+rndz(8)         g9<1>.xyzF      g1<0>.xyzzF                     { align16 1Q };
+rndz(8)         g3<1>F          g2<0,1,0>F                      { align1 1Q };
+rndz(16)        g3<1>F          g2<0,1,0>F                      { align1 1H };

diff --git a/src/intel/tools/tests/gen7/rndz.expected b/src/intel/tools/tests/gen7/rndz.expected
new file mode 100644 (file)
index 0000000..6079a40
--- /dev/null
+++ b/src/intel/tools/tests/gen7/rndz.expected
@@ -0,0 +1,3 @@
+47 01 60 00 bd 03 27 21 24 00 0a 00 00 00 00 00
+47 00 60 00 bd 03 60 20 40 00 00 00 00 00 00 00
+47 00 80 00 bd 03 60 20 40 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen7/sel.asm b/src/intel/tools/tests/gen7/sel.asm
new file mode 100644 (file)
index 0000000..7e31e63
--- /dev/null
+++ b/src/intel/tools/tests/gen7/sel.asm
@@ -0,0 +1,56 @@
+(+f0.0) sel(8)  g47<1>UD        g12<4>UD        g13<4>UD        { align16 1Q };
+(-f0.0) sel(8)  g25<1>.xyUD     g13<4>.zwwwUD   0x40000000UD    { align16 1Q };
+(+f0.0.any4h) sel(8) g30<1>UD   g13<4>UD        g12<4>UD        { align16 1Q };
+(+f0.0.all4h) sel(8) g16<1>UD   g8<4>UD         g9<4>UD         { align16 1Q };
+(+f0.0) sel(8)  g2<1>UD         g31<8,8,1>UD    g34<8,8,1>UD    { align1 1Q };
+(+f0.0) sel(8)  g124<1>UD       g67<8,8,1>UD    0x3f800000UD    { align1 1Q };
+(+f0.0) sel(16) g2<1>UD         g35<8,8,1>UD    g41<8,8,1>UD    { align1 1H };
+(+f0.0) sel(16) g120<1>UD       g27<8,8,1>UD    0x3f800000UD    { align1 1H };
+sel.ge(8)       g64<1>F         g9<8,8,1>F      0x0F  /* 0F */  { align1 1Q };
+(-f0.0) sel(8)  g16<1>UD        g20<8,8,1>UD    0x00000000UD    { align1 1Q };
+sel.ge(16)      g17<1>F         g3<8,8,1>F      0x0F  /* 0F */  { align1 1H };
+(-f0.0) sel(16) g23<1>UD        g21<8,8,1>UD    0x00000000UD    { align1 1H };
+sel.l(8)        g13<1>.xyzD     g6<0>.xyzzD     g5.4<0>.zD      { align16 1Q };
+sel.ge(8)       g3<1>.yF        g7<4>.xF        0x0F  /* 0F */  { align16 1Q };
+sel.l(8)        g11<1>.xF       g7<4>.wF        0x43000000F  /* 128F */ { align16 1Q };
+(-f0.0.z) sel(8) g3<1>.zUD      g14<4>.xUD      0x00000000UD    { align16 1Q };
+sel.l(8)        g14<1>UD        g6<0>UD         g6.4<0>UD       { align16 1Q };
+(+f0.0.x) sel(8) g32<1>.xUD     g12<4>.yUD      0x41a80000UD    { align16 1Q };
+(-f0.0.x) sel(8) g33<1>.xUD     g32<4>.xUD      0x41b80000UD    { align16 1Q };
+sel.ge(8)       g2<1>F          (abs)g7<8,8,1>F (abs)g8<8,8,1>F { align1 1Q };
+sel.ge(16)      g2<1>F          (abs)g10<8,8,1>F (abs)g12<8,8,1>F { align1 1H };
+(+f0.0.x) sel(8) g25<1>.xUD     g23<4>.yUD      g23<4>.xUD      { align16 1Q };
+sel.sat.l(8)    g116<1>F        g2<4>F          0x3f000000F  /* 0.5F */ { align16 1Q };
+sel.l(8)        g13<1>.xF       g1<0>.wF        g1<0>.zF        { align16 1Q };
+sel.ge(8)       g13<1>.xF       g1<0>.wF        g1<0>.zF        { align16 1Q };
+(-f0.0.any4h) sel(8) g67<1>.xUD g63<4>.xUD      0x00000000UD    { align16 1Q };
+(+f0.0.x) sel(8) g17<1>.xF      g5.4<0>.zF      -g5.4<0>.zF     { align16 1Q };
+sel.l(8)        g124<1>F        g2.3<0,1,0>F    g2.2<0,1,0>F    { align1 1Q };
+sel.l(16)       g120<1>F        g2.3<0,1,0>F    g2.2<0,1,0>F    { align1 1H };
+sel.ge(8)       g13<1>.xyzD     g6<0>.xyzzD     g5.4<0>.zD      { align16 1Q };
+sel.ge(8)       g13<1>.xyUD     g5.4<0>.zwwwUD  g6<0>.xyyyUD    { align16 1Q };
+(+f0.0.any4h) sel(8) g17<1>.xUD g8<4>.xUD       0x00000001UD    { align16 1Q };
+sel.ge(8)       g12<1>.xD       g5.4<0>.zD      -1D             { align16 1Q };
+sel.l(8)        g14<1>.xD       g12<4>.xD       1D              { align16 1Q };
+sel.l(8)        g3<1>UD         g2.1<0,1,0>UD   0x00000001UD    { align1 1Q };
+sel.l(16)       g3<1>UD         g2.1<0,1,0>UD   0x00000001UD    { align1 1H };
+sel.ge(8)       g4<1>D          g3<0,1,0>D      -252D           { align1 1Q };
+sel.l(8)        g5<1>D          g4<8,8,1>D      254D            { align1 1Q };
+sel.ge(16)      g4<1>D          g3<0,1,0>D      -252D           { align1 1H };
+sel.l(16)       g6<1>D          g4<8,8,1>D      254D            { align1 1H };
+sel.sat.l(8)    g116<1>F        g1<0>F          g3<4>F          { align16 1Q };
+sel.l(8)        g6<1>F          g3<8,8,1>F      0x40400000F  /* 3F */ { align1 1Q };
+sel.l(16)       g2<1>F          g20<8,8,1>F     0x40400000F  /* 3F */ { align1 1H };
+(+f0.0) sel(8)  g28<1>.xyF      (abs)g6<0>.xyyyF g5.4<0>.zwwwF  { align16 1Q };
+(+f0.0) sel(8)  g31<1>.xyUD     g10<4>.xyyyUD   0x3f800000UD    { align16 1Q };
+(-f0.0) sel(8)  g38<1>.xyF      (abs)g35<4>.xyyyF 0x3f800000F  /* 1F */ { align16 1Q };
+sel.l(8)        g13<1>.xUD      g11<4>.xUD      0x00000007UD    { align16 1Q };
+(+f1.0) sel(4)  g17<1>.xUD      g15.4<4>.xUD    g15<4>.xUD      { align16 WE_all 1N };
+(+f0.0) sel(8)  g57<1>F         (abs)g2.3<0,1,0>F g2<0,1,0>F    { align1 1Q };
+(-f0.0) sel(8)  g29<1>F         (abs)g26<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
+(+f0.0) sel(16) g8<1>F          (abs)g2.3<0,1,0>F g2<0,1,0>F    { align1 1H };
+(-f0.0) sel(16) g55<1>F         (abs)g14<8,8,1>F 0x3f800000F  /* 1F */ { align1 1H };
+(-f0.0.x) sel(8) g32<1>.xF      (abs)g29<4>.xF  0x3f800000F  /* 1F */ { align16 1Q };
+sel.sat.ge(8)   g116<1>F        g25<4>F         0xbf800000F  /* -1F */ { align16 1Q };
+sel.sat.l(8)    g46<1>F         g45<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
+sel.sat.l(16)   g8<1>F          g83<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1H };

diff --git a/src/intel/tools/tests/gen7/sel.expected b/src/intel/tools/tests/gen7/sel.expected
new file mode 100644 (file)
index 0000000..e0d0a23
--- /dev/null
+++ b/src/intel/tools/tests/gen7/sel.expected
@@ -0,0 +1,56 @@
+02 01 61 00 21 04 ef 25 84 01 6e 00 a4 01 6e 00
+02 01 71 00 21 0c 23 23 ae 01 6f 00 00 00 00 40
+02 01 66 00 21 04 cf 23 a4 01 6e 00 84 01 6e 00
+02 01 67 00 21 04 0f 22 04 01 6e 00 24 01 6e 00
+02 00 61 00 21 04 40 20 e0 03 8d 00 40 04 8d 00
+02 00 61 00 21 0c 80 2f 60 08 8d 00 00 00 80 3f
+02 00 81 00 21 04 40 20 60 04 8d 00 20 05 8d 00
+02 00 81 00 21 0c 00 2f 60 03 8d 00 00 00 80 3f
+02 00 60 04 bd 7f 00 28 20 01 8d 00 00 00 00 00
+02 00 71 00 21 0c 00 22 80 02 8d 00 00 00 00 00
+02 00 80 04 bd 7f 20 22 60 00 8d 00 00 00 00 00
+02 00 91 00 21 0c e0 22 a0 02 8d 00 00 00 00 00
+02 01 60 05 a5 14 a7 21 c4 00 0a 00 ba 00 0a 00
+02 01 60 04 bd 7f 62 20 e0 00 60 00 00 00 00 00
+02 01 60 05 bd 7f 61 21 ef 00 6f 00 00 00 00 43
+02 01 74 00 21 0c 64 20 c0 01 60 00 00 00 00 00
+02 01 60 05 21 04 cf 21 c4 00 0e 00 d4 00 0e 00
+02 01 62 00 21 0c 01 24 85 01 65 00 00 00 a8 41
+02 01 72 00 21 0c 21 24 00 04 60 00 00 00 b8 41
+02 00 60 04 bd 77 40 20 e0 20 8d 00 00 21 8d 00
+02 00 80 04 bd 77 40 20 40 21 8d 00 80 21 8d 00
+02 01 62 00 21 04 21 23 e5 02 65 00 e0 02 60 00
+02 01 60 85 bd 7f 8f 2e 44 00 6e 00 00 00 00 3f
+02 01 60 05 bd 77 a1 21 2f 00 0f 00 2a 00 0a 00
+02 01 60 04 bd 77 a1 21 2f 00 0f 00 2a 00 0a 00
+02 01 76 00 21 0c 61 28 e0 07 60 00 00 00 00 00
+02 01 62 00 bd 77 21 22 ba 00 0a 00 ba 40 0a 00
+02 00 60 05 bd 77 80 2f 4c 00 00 00 48 00 00 00
+02 00 80 05 bd 77 00 2f 4c 00 00 00 48 00 00 00
+02 01 60 04 a5 14 a7 21 c4 00 0a 00 ba 00 0a 00
+02 01 60 04 21 04 a3 21 be 00 0f 00 c4 00 05 00
+02 01 66 00 21 0c 21 22 00 01 60 00 01 00 00 00
+02 01 60 04 a5 1c 81 21 ba 00 0a 00 ff ff ff ff
+02 01 60 05 a5 1c c1 21 80 01 60 00 01 00 00 00
+02 00 60 05 21 0c 60 20 44 00 00 00 01 00 00 00
+02 00 80 05 21 0c 60 20 44 00 00 00 01 00 00 00
+02 00 60 04 a5 1c 80 20 60 00 00 00 04 ff ff ff
+02 00 60 05 a5 1c a0 20 80 00 8d 00 fe 00 00 00
+02 00 80 04 a5 1c 80 20 60 00 00 00 04 ff ff ff
+02 00 80 05 a5 1c c0 20 80 00 8d 00 fe 00 00 00
+02 01 60 85 bd 77 8f 2e 24 00 0e 00 64 00 6e 00
+02 00 60 05 bd 7f c0 20 60 00 8d 00 00 00 40 40
+02 00 80 05 bd 7f 40 20 80 02 8d 00 00 00 40 40
+02 01 61 00 bd 77 83 23 c4 20 05 00 be 00 0f 00
+02 01 61 00 21 0c e3 23 44 01 65 00 00 00 80 3f
+02 01 71 00 bd 7f c3 24 64 24 65 00 00 00 80 3f
+02 01 60 05 21 0c a1 21 60 01 60 00 07 00 00 00
+02 03 41 00 21 04 21 22 f0 01 60 04 e0 01 60 00
+02 00 61 00 bd 77 20 27 4c 20 00 00 40 00 00 00
+02 00 71 00 bd 7f a0 23 40 23 8d 00 00 00 80 3f
+02 00 81 00 bd 77 00 21 4c 20 00 00 40 00 00 00
+02 00 91 00 bd 7f e0 26 c0 21 8d 00 00 00 80 3f
+02 01 72 00 bd 7f 01 24 a0 23 60 00 00 00 80 3f
+02 01 60 84 bd 7f 8f 2e 24 03 6e 00 00 00 80 bf
+02 00 60 85 bd 7f c0 25 a0 05 8d 00 00 00 00 3f
+02 00 80 85 bd 7f 00 21 60 0a 8d 00 00 00 00 3f

diff --git a/src/intel/tools/tests/gen7/send.asm b/src/intel/tools/tests/gen7/send.asm
new file mode 100644 (file)
index 0000000..6345a9c
--- /dev/null
+++ b/src/intel/tools/tests/gen7/send.asm
@@ -0,0 +1,1170 @@
+send(8)         null<1>F        g113<4>F        0x8608c000
+                            urb MsgDesc: 0 write HWord interleave complete mlen 3 rlen 0 { align16 1Q EOT };
+send(8)         null<1>F        g113<4>F        0x8a08c000
+                            urb MsgDesc: 0 write HWord interleave complete mlen 5 rlen 0 { align16 1Q EOT };
+send(8)         g2<1>UW         g8<8,8,1>UD     0x08427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g14<8,8,1>UD    0x10847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g50<1>D         g51<4>UD        0x02194013
+                            urb MsgDesc: 2 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>F        g12<4>UD        0x04094019
+                            urb MsgDesc: 3 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g13<4>UD        0x04094011
+                            urb MsgDesc: 2 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g12<4>UD        0x04094009
+                            urb MsgDesc: 1 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g12<4>UD        0x04094001
+                            urb MsgDesc: 0 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         g14<1>D         g15<4>UD        0x0219400b
+                            urb MsgDesc: 1 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g13<1>D         g12<4>UD        0x02194003
+                            urb MsgDesc: 0 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>UW       g12<4,4,1>UD    0x02008004
+                            gateway MsgDesc: (barrier msg) mlen 1 rlen 0    { align1 WE_all 1Q };
+send(8)         null<1>F        g13<4>UD        0x0208c003
+                            urb MsgDesc: 0 read OWord interleave complete mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        g126<4>F        0x84080001
+                            urb MsgDesc: 0 write OWord mlen 2 rlen 0        { align16 1Q EOT };
+send(8)         g0<1>F          g125<4>F        0x060a80ff
+                            data MsgDesc: ( DC OWORD dual block write, 255, 0) mlen 3 rlen 0 { align16 1Q };
+send(8)         g41<1>F         g126<4>F        0x041880ff
+                            data MsgDesc: ( DC OWORD dual block read, 255, 0) mlen 2 rlen 1 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x8e08c000
+                            urb MsgDesc: 0 write HWord interleave complete mlen 7 rlen 0 { align16 1Q EOT };
+send(8)         g124<1>UW       g11<8,8,1>UD    0x06420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g16<8,8,1>UD    0x0c840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x08840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x144a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g8<8,8,1>UD     0x084a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g38<1>UD        g87<4>.xUD      0x02107000
+                            sampler MsgDesc: ld SIMD4x2 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x0a4a6001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g12<8,8,1>UD    0x0a4a6102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x128c6001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g20<8,8,1>UD    0x128c6102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 8 { align1 1H };
+send(8)         g10<1>D         g114<4>F        0x0411e000
+                            sampler MsgDesc: ld2dms SIMD4x2 Surface = 0 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x0a094000
+                            urb MsgDesc: 0 write HWord per-slot interleave mlen 5 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x82084000
+                            urb MsgDesc: 0 write HWord interleave mlen 1 rlen 0 { align16 1Q EOT };
+send(8)         null<1>F        g9<4>UD         0x04094021
+                            urb MsgDesc: 4 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g9<4>UD         0x02088003
+                            urb MsgDesc: 0 read OWord complete mlen 1 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x06094000
+                            urb MsgDesc: 0 write HWord per-slot interleave mlen 3 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x1a084000
+                            urb MsgDesc: 0 write HWord interleave mlen 13 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x8a08c030
+                            urb MsgDesc: 6 write HWord interleave complete mlen 5 rlen 0 { align16 1Q EOT };
+send(8)         g5<1>UW         g21<8,8,1>UD    0x02420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g21<8,8,1>UD    0x04840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g12<1>D         g114<4>F        0x0210a000
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>F        g9<4>UD         0x04094029
+                            urb MsgDesc: 5 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x06427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g18<8,8,1>UD    0x0c847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x0c424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g3<1>D          g114<4>F        0x0210a101
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 1 Sampler = 1 mlen 1 rlen 1 { align16 1Q };
+send(8)         g5<1>D          g114<4>F        0x0210a202
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 2 Sampler = 2 mlen 1 rlen 1 { align16 1Q };
+send(8)         g7<1>D          g114<4>F        0x0210a303
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 3 Sampler = 3 mlen 1 rlen 1 { align16 1Q };
+send(8)         g9<1>D          g114<4>F        0x0210a404
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 4 Sampler = 4 mlen 1 rlen 1 { align16 1Q };
+send(8)         g11<1>D         g114<4>F        0x0210a505
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 5 Sampler = 5 mlen 1 rlen 1 { align16 1Q };
+send(8)         g13<1>D         g114<4>F        0x0210a606
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 6 Sampler = 6 mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x9208c000
+                            urb MsgDesc: 0 write HWord interleave complete mlen 9 rlen 0 { align16 1Q EOT };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x04429001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08849001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g13<1>UD        g3<8,8,1>UD     0x02280301
+                            const MsgDesc: (1, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g11<1>D         g114<4>F        0x06191001
+                            sampler MsgDesc: gather4_po SIMD4x2 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align16 1Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x08842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g5<1>UW         g3<8,8,1>UD     0x02427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g8<1>UW         g5<8,8,1>UD     0x04847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g9<8,8,1>UD     0x08421001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g14<8,8,1>UD    0x10841001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x02429001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x04849001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g9<8,8,1>UD     0x0242a001
+                            sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0484a001
+                            sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g21<8,8,1>UD    0x08426001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g2<8,8,1>UD     0x10846001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g8<8,8,1>UD     0x06426001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g20<8,8,1>UD    0x0c846001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x1a084030
+                            urb MsgDesc: 6 write HWord interleave mlen 13 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x9608c060
+                            urb MsgDesc: 12 write HWord interleave complete mlen 11 rlen 0 { align16 1Q EOT };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x06423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0c843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x0a094008
+                            urb MsgDesc: 1 write HWord per-slot interleave mlen 5 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x04084001
+                            urb MsgDesc: 0 write OWord interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         g9<1>F          g114<4>F        0x04188001
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x8608c030
+                            urb MsgDesc: 6 write HWord interleave complete mlen 3 rlen 0 { align16 1Q EOT };
+send(8)         g124<1>UW       g11<8,8,1>UD    0x0a4a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g19<8,8,1>UD    0x128c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x9608c000
+                            urb MsgDesc: 0 write HWord interleave complete mlen 11 rlen 0 { align16 1Q EOT };
+send(8)         g9<1>UW         g2<8,8,1>UD     0x0242a102
+                            sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g16<8,8,1>UD    0x06426102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g29<1>UW        g37<8,8,1>UD    0x0484a102
+                            sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g15<8,8,1>UD    0x0c846102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         g5<1>UW         g17<8,8,1>UD    0x06427102
+                            sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(8)         g9<1>UW         g20<8,8,1>UD    0x0843e001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g21<1>UW        g7<8,8,1>UD     0x0c847102
+                            sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(16)        g29<1>UW        g13<8,8,1>UD    0x1085e001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g13<8,8,1>UD    0x0a43e001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g10<8,8,1>UD    0x1485e001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x0643d001
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0c85d001
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g9<1>UW         g19<8,8,1>UD    0x0443d001
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g23<1>UW        g11<8,8,1>UD    0x0885d001
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g16<1>.xD       g114<4>F        0x0218b000
+                            sampler MsgDesc: sampleinfo SIMD4x2 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x16094000
+                            urb MsgDesc: 0 write HWord per-slot interleave mlen 11 rlen 0 { align16 1Q };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x064a3001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g9<8,8,1>UD     0x064a3102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0a8c3001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0a8c3102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 5 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x06421001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x0c841001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g11<8,8,1>UD    0x06425001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g14<8,8,1>UD    0x06425102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g21<8,8,1>UD    0x0c845001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g27<8,8,1>UD    0x0c845102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g9<8,8,1>UD     0x08420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x10840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g11<1>UD        g114<4>F        0x0211d000
+                            sampler MsgDesc: ld_mcs SIMD4x2 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x0e424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g16<1>F         g17<4>.xUD      0x02107001
+                            sampler MsgDesc: ld SIMD4x2 Surface = 1 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g6<1>UW         g9<8,8,1>UD     0x08426102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g15<8,8,1>UD    0x10846102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+send(8)         g4<1>D          g114<4>F        0x04188003
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 3 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         g5<1>D          g114<4>F        0x04188104
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 4 Sampler = 1 mlen 2 rlen 1 { align16 1Q };
+send(8)         g8<1>D          g114<4>F        0x04188205
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 5 Sampler = 2 mlen 2 rlen 1 { align16 1Q };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x08422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g15<8,8,1>UD    0x10842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g7<8,8,1>UD     a0<0,1,0>UD     0x00000200
+                            sampler MsgDesc: indirect                       { align1 1Q };
+send(8)         g28<1>D         g29<4>UD        0x0219401b
+                            urb MsgDesc: 3 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g36<1>D         g37<4>UD        0x02194023
+                            urb MsgDesc: 4 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g43<1>D         g44<4>UD        0x0219402b
+                            urb MsgDesc: 5 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g3<1>.xUW       g1<4>UD         0x0411bb00
+                            data MsgDesc: ( DC untyped atomic, 0,  imin) mlen 2 rlen 1 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x1a094000
+                            urb MsgDesc: 0 write HWord per-slot interleave mlen 13 rlen 0 { align16 1Q };
+send(8)         g124<1>UW       g5<8,8,1>UD     0x04420304
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x08840304
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g9<8,8,1>UD     0x08423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g16<1>UW        g8<8,8,1>UD     0x10843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x0a421001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g9<8,8,1>UD     0x14841001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x06422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g14<1>UW        g8<8,8,1>UD     0x0c842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x0e094000
+                            urb MsgDesc: 0 write HWord per-slot interleave mlen 7 rlen 0 { align16 1Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x06424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x06429001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g12<8,8,1>UD    0x0c849001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x08847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x064a8006
+                            sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g14<8,8,1>UD    0x064a840a
+                            sampler MsgDesc: gather4 SIMD8 Surface = 10 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x084a8107
+                            sampler MsgDesc: gather4 SIMD8 Surface = 7 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g10<8,8,1>UD    0x084a8208
+                            sampler MsgDesc: gather4 SIMD8 Surface = 8 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g26<8,8,1>UD    0x0a4a8309
+                            sampler MsgDesc: gather4 SIMD8 Surface = 9 Sampler = 3 mlen 5 rlen 4 { align1 1Q };
+send(16)        g35<1>UW        g2<8,8,1>UD     0x0a8c8006
+                            sampler MsgDesc: gather4 SIMD16 Surface = 6 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(16)        g18<1>UW        g43<8,8,1>UD    0x0a8c840a
+                            sampler MsgDesc: gather4 SIMD16 Surface = 10 Sampler = 4 mlen 5 rlen 8 { align1 1H };
+send(16)        g43<1>UW        g7<8,8,1>UD     0x0e8c8107
+                            sampler MsgDesc: gather4 SIMD16 Surface = 7 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g51<8,8,1>UD    0x0e8c8208
+                            sampler MsgDesc: gather4 SIMD16 Surface = 8 Sampler = 2 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g26<8,8,1>UD    0x128c8309
+                            sampler MsgDesc: gather4 SIMD16 Surface = 9 Sampler = 3 mlen 9 rlen 8 { align1 1H };
+(+f1.0) send(8) null<1>UW       g7<8,8,1>UD     0x0a036001
+                            data MsgDesc: ( DC untyped surface write, 1, 32) mlen 5 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g9<8,8,1>UD     0x14035001
+                            data MsgDesc: ( DC untyped surface write, 1, 16) mlen 10 rlen 0 { align1 1H };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x0e4a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x084a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g17<8,8,1>UD    0x0e8c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g9<8,8,1>UD     0x0a422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x14842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(16)        g3<1>UD         g5<8,8,1>UD     0x02280302
+                            const MsgDesc: (2, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g25<1>UW        g13<8,8,1>UD    0x06194e01
+                            render MsgDesc: typed surface read MsgCtrl = 0x14 Surface = 1 mlen 3 rlen 1 { align1 1Q };
+send(8)         null<1>UW       g26<8,8,1>UD    0x080b4e01
+                            render MsgDesc: typed surface write MsgCtrl = 0x14 Surface = 1 mlen 4 rlen 0 { align1 1Q };
+send(8)         g40<1>UW        g18<8,8,1>UD    0x06196e01
+                            render MsgDesc: typed surface read MsgCtrl = 0x46 Surface = 1 mlen 3 rlen 1 { align1 2Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x080b6e01
+                            render MsgDesc: typed surface write MsgCtrl = 0x46 Surface = 1 mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06098501
+                            render MsgDesc: typed atomic op MsgCtrl = 0x5 Surface = 1 mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06099501
+                            render MsgDesc: typed atomic op MsgCtrl = 0x21 Surface = 1 mlen 3 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x08098c01
+                            render MsgDesc: typed atomic op MsgCtrl = 0x12 Surface = 1 mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099c01
+                            render MsgDesc: typed atomic op MsgCtrl = 0x28 Surface = 1 mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x08098401
+                            render MsgDesc: typed atomic op MsgCtrl = 0x4 Surface = 1 mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099401
+                            render MsgDesc: typed atomic op MsgCtrl = 0x20 Surface = 1 mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x0a098e01
+                            render MsgDesc: typed atomic op MsgCtrl = 0x14 Surface = 1 mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g16<8,8,1>UD    0x0a099e01
+                            render MsgDesc: typed atomic op MsgCtrl = 0x30 Surface = 1 mlen 5 rlen 0 { align1 2Q };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x04423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g8<8,8,1>UD     0x04423102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x08843102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g5<8,8,1>UD     0x064a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x0a8c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06423102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g26<8,8,1>UD    0x0c843102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         g5<1>UW         g15<8,8,1>UD    0x04420203
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 4 { align1 1Q };
+send(8)         g9<1>UW         g15<8,8,1>UD    0x04420102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g27<8,8,1>UD    0x08840203
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 8 { align1 1H };
+send(16)        g15<1>UW        g27<8,8,1>UD    0x08840102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(8)         g22<1>UW        g22<8,8,1>UD    0x0242a203
+                            sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g26<8,8,1>UD    0x0242a304
+                            sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 4 { align1 1Q };
+send(8)         g30<1>UW        g30<8,8,1>UD    0x0242a405
+                            sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 4 { align1 1Q };
+send(8)         g34<1>UW        g34<8,8,1>UD    0x0242a506
+                            sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 4 { align1 1Q };
+send(8)         g38<1>UW        g38<8,8,1>UD    0x0242a607
+                            sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 6 mlen 1 rlen 4 { align1 1Q };
+send(8)         g42<1>UW        g42<8,8,1>UD    0x0242a708
+                            sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 7 mlen 1 rlen 4 { align1 1Q };
+send(8)         g46<1>UW        g46<8,8,1>UD    0x0242a809
+                            sampler MsgDesc: resinfo SIMD8 Surface = 9 Sampler = 8 mlen 1 rlen 4 { align1 1Q };
+send(8)         g50<1>UW        g50<8,8,1>UD    0x0242a90a
+                            sampler MsgDesc: resinfo SIMD8 Surface = 10 Sampler = 9 mlen 1 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g54<8,8,1>UD    0x0242aa0b
+                            sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 10 mlen 1 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g55<8,8,1>UD    0x0242ab0c
+                            sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 11 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g56<8,8,1>UD    0x0242ac0d
+                            sampler MsgDesc: resinfo SIMD8 Surface = 13 Sampler = 12 mlen 1 rlen 4 { align1 1Q };
+send(16)        g82<1>UW        g110<8,8,1>UD   0x0484aa0b
+                            sampler MsgDesc: resinfo SIMD16 Surface = 11 Sampler = 10 mlen 2 rlen 8 { align1 1H };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x0484a203
+                            sampler MsgDesc: resinfo SIMD16 Surface = 3 Sampler = 2 mlen 2 rlen 8 { align1 1H };
+send(16)        g90<1>UW        g112<8,8,1>UD   0x0484ab0c
+                            sampler MsgDesc: resinfo SIMD16 Surface = 12 Sampler = 11 mlen 2 rlen 8 { align1 1H };
+send(16)        g98<1>UW        g106<8,8,1>UD   0x0484ac0d
+                            sampler MsgDesc: resinfo SIMD16 Surface = 13 Sampler = 12 mlen 2 rlen 8 { align1 1H };
+send(16)        g26<1>UW        g34<8,8,1>UD    0x0484a304
+                            sampler MsgDesc: resinfo SIMD16 Surface = 4 Sampler = 3 mlen 2 rlen 8 { align1 1H };
+send(16)        g34<1>UW        g42<8,8,1>UD    0x0484a405
+                            sampler MsgDesc: resinfo SIMD16 Surface = 5 Sampler = 4 mlen 2 rlen 8 { align1 1H };
+send(16)        g42<1>UW        g50<8,8,1>UD    0x0484a506
+                            sampler MsgDesc: resinfo SIMD16 Surface = 6 Sampler = 5 mlen 2 rlen 8 { align1 1H };
+send(16)        g50<1>UW        g58<8,8,1>UD    0x0484a607
+                            sampler MsgDesc: resinfo SIMD16 Surface = 7 Sampler = 6 mlen 2 rlen 8 { align1 1H };
+send(16)        g58<1>UW        g66<8,8,1>UD    0x0484a708
+                            sampler MsgDesc: resinfo SIMD16 Surface = 8 Sampler = 7 mlen 2 rlen 8 { align1 1H };
+send(16)        g66<1>UW        g74<8,8,1>UD    0x0484a809
+                            sampler MsgDesc: resinfo SIMD16 Surface = 9 Sampler = 8 mlen 2 rlen 8 { align1 1H };
+send(16)        g74<1>UW        g108<8,8,1>UD   0x0484a90a
+                            sampler MsgDesc: resinfo SIMD16 Surface = 10 Sampler = 9 mlen 2 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g11<8,8,1>UD    0x12424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 4 { align1 1Q };
+send(8)         g17<1>F         g114<4>F        0x04102000
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 0 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         g10<1>UW        g10<8,8,1>UD    0x04420405
+                            sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g14<8,8,1>UD    0x04420506
+                            sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 2 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x04420607
+                            sampler MsgDesc: sample SIMD8 Surface = 7 Sampler = 6 mlen 2 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g22<8,8,1>UD    0x04420708
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 2 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g26<8,8,1>UD    0x04420809
+                            sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 8 mlen 2 rlen 4 { align1 1Q };
+send(8)         g30<1>UW        g30<8,8,1>UD    0x0442090a
+                            sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 9 mlen 2 rlen 4 { align1 1Q };
+send(8)         g34<1>UW        g34<8,8,1>UD    0x04420a0b
+                            sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 10 mlen 2 rlen 4 { align1 1Q };
+send(8)         g38<1>UW        g38<8,8,1>UD    0x04420b0c
+                            sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 11 mlen 2 rlen 4 { align1 1Q };
+send(8)         g42<1>UW        g42<8,8,1>UD    0x04420c0d
+                            sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 12 mlen 2 rlen 4 { align1 1Q };
+send(8)         g46<1>UW        g46<8,8,1>UD    0x04420d0e
+                            sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 13 mlen 2 rlen 4 { align1 1Q };
+send(8)         g50<1>UW        g50<8,8,1>UD    0x04420e0f
+                            sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 14 mlen 2 rlen 4 { align1 1Q };
+send(8)         g54<1>UW        g54<8,8,1>UD    0x04420f10
+                            sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08840405
+                            sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g18<8,8,1>UD    0x08840506
+                            sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08840607
+                            sampler MsgDesc: sample SIMD16 Surface = 7 Sampler = 6 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g18<8,8,1>UD    0x08840708
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08840809
+                            sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 8 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g18<8,8,1>UD    0x0884090a
+                            sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 9 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08840a0b
+                            sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 10 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g18<8,8,1>UD    0x08840b0c
+                            sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 11 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08840c0d
+                            sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 12 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g18<8,8,1>UD    0x08840d0e
+                            sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 13 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08840e0f
+                            sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 14 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g18<8,8,1>UD    0x08840f10
+                            sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 4 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g2<8,8,1>UD     0x02420102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g2<8,8,1>UD     0x04840102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x02416001
+                            data MsgDesc: ( DC untyped surface read, 1, 32) mlen 1 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x04815001
+                            data MsgDesc: ( DC untyped surface read, 1, 16) mlen 2 rlen 8 { align1 1H };
+send(8)         null<1>F        g11<4>UD        0x04094031
+                            urb MsgDesc: 6 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g9<4>UD         0x04094039
+                            urb MsgDesc: 7 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         g52<1>D         g53<4>UD        0x02194033
+                            urb MsgDesc: 6 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g59<1>D         g60<4>UD        0x0219403b
+                            urb MsgDesc: 7 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g66<1>D         g67<4>UD        0x02194043
+                            urb MsgDesc: 8 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g73<1>D         g74<4>UD        0x0219404b
+                            urb MsgDesc: 9 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x084a2001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x0e8c2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g5<8,8,1>UD     0x0a426001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g10<8,8,1>UD    0x0a426102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g15<8,8,1>UD    0x14846001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g25<8,8,1>UD    0x14846102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x084a5001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x084a5102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x0e8c5001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0e8c5102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x084a3001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g10<8,8,1>UD    0x084a3102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0e8c3001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0e8c3102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x044a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g4<8,8,1>UD     0x068c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 8 { align1 1H };
+send(8)         g17<1>UW        g12<8,8,1>UD    0x04420003
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g37<8,8,1>UD    0x08840003
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g11<1>UW        g39<8,8,1>UD    0x06427008
+                            sampler MsgDesc: ld SIMD8 Surface = 8 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g15<1>UW        g39<8,8,1>UD    0x06427109
+                            sampler MsgDesc: ld SIMD8 Surface = 9 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(8)         g19<1>UW        g39<8,8,1>UD    0x0642720a
+                            sampler MsgDesc: ld SIMD8 Surface = 10 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(8)         g23<1>UW        g39<8,8,1>UD    0x0642730b
+                            sampler MsgDesc: ld SIMD8 Surface = 11 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(8)         g27<1>UW        g39<8,8,1>UD    0x0642740c
+                            sampler MsgDesc: ld SIMD8 Surface = 12 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
+send(8)         g31<1>UW        g39<8,8,1>UD    0x0642750d
+                            sampler MsgDesc: ld SIMD8 Surface = 13 Sampler = 5 mlen 3 rlen 4 { align1 1Q };
+send(8)         g35<1>UW        g39<8,8,1>UD    0x0642760e
+                            sampler MsgDesc: ld SIMD8 Surface = 14 Sampler = 6 mlen 3 rlen 4 { align1 1Q };
+send(8)         g39<1>UW        g39<8,8,1>UD    0x0642770f
+                            sampler MsgDesc: ld SIMD8 Surface = 15 Sampler = 7 mlen 3 rlen 4 { align1 1Q };
+send(16)        g67<1>UW        g93<8,8,1>UD    0x0c847008
+                            sampler MsgDesc: ld SIMD16 Surface = 8 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        g27<1>UW        g93<8,8,1>UD    0x0c847109
+                            sampler MsgDesc: ld SIMD16 Surface = 9 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(16)        g37<1>UW        g93<8,8,1>UD    0x0c84720a
+                            sampler MsgDesc: ld SIMD16 Surface = 10 Sampler = 2 mlen 6 rlen 8 { align1 1H };
+send(16)        g47<1>UW        g93<8,8,1>UD    0x0c84730b
+                            sampler MsgDesc: ld SIMD16 Surface = 11 Sampler = 3 mlen 6 rlen 8 { align1 1H };
+send(16)        g57<1>UW        g93<8,8,1>UD    0x0c84740c
+                            sampler MsgDesc: ld SIMD16 Surface = 12 Sampler = 4 mlen 6 rlen 8 { align1 1H };
+send(16)        g17<1>UW        g93<8,8,1>UD    0x0c84750d
+                            sampler MsgDesc: ld SIMD16 Surface = 13 Sampler = 5 mlen 6 rlen 8 { align1 1H };
+send(16)        g85<1>UW        g93<8,8,1>UD    0x0c84760e
+                            sampler MsgDesc: ld SIMD16 Surface = 14 Sampler = 6 mlen 6 rlen 8 { align1 1H };
+send(16)        g77<1>UW        g93<8,8,1>UD    0x0c84770f
+                            sampler MsgDesc: ld SIMD16 Surface = 15 Sampler = 7 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g8<8,8,1>UD     0x064a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g15<8,8,1>UD    0x0a8c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         g5<1>F          g114<4>F        0x06190003
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 3 Sampler = 0 mlen 3 rlen 1 { align16 1Q };
+send(8)         g6<1>F          g114<4>F        0x06190104
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 4 Sampler = 1 mlen 3 rlen 1 { align16 1Q };
+send(8)         g9<1>F          g114<4>F        0x06190205
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 5 Sampler = 2 mlen 3 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x084a6001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x084a6102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x0e8c6001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0e8c6102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x0a4a5001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g17<8,8,1>UD    0x0a4a5102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g25<1>UW        g7<8,8,1>UD     0x128c5001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(16)        g33<1>UW        g16<8,8,1>UD    0x128c5102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 8 { align1 1H };
+send(8)         g69<1>.xUW      g66<4>UD        0x0211b500
+                            data MsgDesc: ( DC untyped atomic, 0,  inc) mlen 1 rlen 1 { align16 1Q };
+send(8)         g3<1>D          g114<4>F        0x04188005
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 5 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         g4<1>D          g114<4>F        0x04188106
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 6 Sampler = 1 mlen 2 rlen 1 { align16 1Q };
+send(8)         g6<1>D          g114<4>F        0x04188207
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 7 Sampler = 2 mlen 2 rlen 1 { align16 1Q };
+send(8)         g9<1>D          g114<4>F        0x04188308
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 8 Sampler = 3 mlen 2 rlen 1 { align16 1Q };
+send(8)         g11<1>D         g114<4>F        0x04188409
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 9 Sampler = 4 mlen 2 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x0c4a6001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g13<8,8,1>UD    0x0c4a6102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 1Q };
+send(16)        g31<1>UW        g9<8,8,1>UD     0x168c6001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g20<8,8,1>UD    0x168c6102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 11 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x064a8004
+                            sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x084a8105
+                            sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g10<8,8,1>UD    0x064a8206
+                            sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0a8c8004
+                            sampler MsgDesc: gather4 SIMD16 Surface = 4 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0e8c8105
+                            sampler MsgDesc: gather4 SIMD16 Surface = 5 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(16)        g26<1>UW        g34<8,8,1>UD    0x0a8c8206
+                            sampler MsgDesc: gather4 SIMD16 Surface = 6 Sampler = 2 mlen 5 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x0a4a2001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g9<8,8,1>UD     0x128c2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         g24<1>F         g25<4>.xUD      0x02107002
+                            sampler MsgDesc: ld SIMD4x2 Surface = 2 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g30<1>F         g31<4>.xUD      0x02107003
+                            sampler MsgDesc: ld SIMD4x2 Surface = 3 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g35<1>F         g36<4>.xUD      0x02107004
+                            sampler MsgDesc: ld SIMD4x2 Surface = 4 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g41<1>F         g42<4>.xUD      0x02107005
+                            sampler MsgDesc: ld SIMD4x2 Surface = 5 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g47<1>F         g48<4>.xUD      0x02107006
+                            sampler MsgDesc: ld SIMD4x2 Surface = 6 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g53<1>F         g54<4>.xUD      0x02107007
+                            sampler MsgDesc: ld SIMD4x2 Surface = 7 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g59<1>F         g60<4>.xUD      0x02107008
+                            sampler MsgDesc: ld SIMD4x2 Surface = 8 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g65<1>F         g66<4>.xUD      0x02107009
+                            sampler MsgDesc: ld SIMD4x2 Surface = 9 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g71<1>F         g72<4>.xUD      0x0210700a
+                            sampler MsgDesc: ld SIMD4x2 Surface = 10 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g77<1>F         g78<4>.xUD      0x0210700b
+                            sampler MsgDesc: ld SIMD4x2 Surface = 11 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g83<1>F         g84<4>.xUD      0x0210700c
+                            sampler MsgDesc: ld SIMD4x2 Surface = 12 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g89<1>F         g90<4>.xUD      0x0210700d
+                            sampler MsgDesc: ld SIMD4x2 Surface = 13 Sampler = 0 mlen 1 rlen 1 { align16 1Q };
+send(8)         g5<1>F          g114<4>F        0x04102505
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 5 Sampler = 5 mlen 2 rlen 1 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x06094008
+                            urb MsgDesc: 1 write HWord per-slot interleave mlen 3 rlen 0 { align16 1Q };
+(+f1.0) send(8) g2<1>UW         g6<8,8,1>UD     0x0211b501
+                            data MsgDesc: ( DC untyped atomic, 1,  inc) mlen 1 rlen 1 { align1 1Q };
+(+f1.0) send(16) g2<1>UW        g8<8,8,1>UD     0x0421a501
+                            data MsgDesc: ( DC untyped atomic, 1,  inc) mlen 2 rlen 2 { align1 1H };
+(+f1.0) send(8) null<1>UW       g2<8,8,1>UD     0x02019501
+                            data MsgDesc: ( DC untyped atomic, 1,  inc) mlen 1 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g2<8,8,1>UD     0x04018501
+                            data MsgDesc: ( DC untyped atomic, 1,  inc) mlen 2 rlen 0 { align1 1H };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x0a423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g15<8,8,1>UD    0x0a423102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g29<1>UW        g9<8,8,1>UD     0x14843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(16)        g37<1>UW        g19<8,8,1>UD    0x14843102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H };
+(+f1.0) send(8) g4<1>UW         g12<8,8,1>UD    0x0211b502
+                            data MsgDesc: ( DC untyped atomic, 2,  inc) mlen 1 rlen 1 { align1 1Q };
+(+f1.0) send(16) g5<1>UW        g17<8,8,1>UD    0x0421a502
+                            data MsgDesc: ( DC untyped atomic, 2,  inc) mlen 2 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g9<8,8,1>UD     0x024ab001
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x028cb001
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 1 Sampler = 0 mlen 1 rlen 8 { align1 1H };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04036e01
+                            data MsgDesc: ( DC untyped surface write, 1, 46) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x06036c01
+                            data MsgDesc: ( DC untyped surface write, 1, 44) mlen 3 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g4<8,8,1>UD     0x08035e01
+                            data MsgDesc: ( DC untyped surface write, 1, 30) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g4<8,8,1>UD     0x0c035c01
+                            data MsgDesc: ( DC untyped surface write, 1, 28) mlen 6 rlen 0 { align1 1H };
+send(1)         g2<1>UW         g2<0,1,0>UW     0x0219e000
+                            data MsgDesc: ( DC mfence, 0, 32) mlen 1 rlen 1 { align1 WE_all 1N };
+send(8)         g2<1>UW         g94<8,8,1>UD    0x02116e01
+                            data MsgDesc: ( DC untyped surface read, 1, 46) mlen 1 rlen 1 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g119<8,8,1>UD   0x02019601
+                            data MsgDesc: ( DC untyped atomic, 1,  dec) mlen 1 rlen 0 { align1 1Q };
+(+f1.0) send(8) g48<1>UW        g119<8,8,1>UD   0x0211b601
+                            data MsgDesc: ( DC untyped atomic, 1,  dec) mlen 1 rlen 1 { align1 1Q };
+send(16)        g5<1>UW         g23<8,8,1>UD    0x04215e01
+                            data MsgDesc: ( DC untyped surface read, 1, 30) mlen 2 rlen 2 { align1 1H };
+(+f1.0) send(16) null<1>UW      g3<8,8,1>UD     0x04018601
+                            data MsgDesc: ( DC untyped atomic, 1,  dec) mlen 2 rlen 0 { align1 1H };
+(+f1.0) send(16) g97<1>UW       g3<8,8,1>UD     0x0421a601
+                            data MsgDesc: ( DC untyped atomic, 1,  dec) mlen 2 rlen 2 { align1 1H };
+send(8)         g47<1>.xUW      g44<4>UD        0x0211b600
+                            data MsgDesc: ( DC untyped atomic, 0,  dec) mlen 1 rlen 1 { align16 1Q };
+send(8)         g101<1>D        g99<4>UD        0x021940c3
+                            urb MsgDesc: 24 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         g110<1>D        g99<4>UD        0x021940cb
+                            urb MsgDesc: 25 read OWord per-slot interleave mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>F        g9<4>UD         0x04094041
+                            urb MsgDesc: 8 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         null<1>F        g9<4>UD         0x04094049
+                            urb MsgDesc: 9 write OWord per-slot interleave mlen 2 rlen 0 { align16 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x04421001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x08841001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06420102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0c840102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x8e08c030
+                            urb MsgDesc: 6 write HWord interleave complete mlen 7 rlen 0 { align16 1Q EOT };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x02416002
+                            data MsgDesc: ( DC untyped surface read, 2, 32) mlen 1 rlen 4 { align1 1Q };
+send(16)        g19<1>UW        g17<8,8,1>UD    0x04815002
+                            data MsgDesc: ( DC untyped surface read, 2, 16) mlen 2 rlen 8 { align1 1H };
+send(8)         g2<1>.xD        g114<4>F        0x0218b101
+                            sampler MsgDesc: sampleinfo SIMD4x2 Surface = 1 Sampler = 1 mlen 1 rlen 1 { align16 1Q };
+send(8)         g4<1>.xD        g114<4>F        0x0218b202
+                            sampler MsgDesc: sampleinfo SIMD4x2 Surface = 2 Sampler = 2 mlen 1 rlen 1 { align16 1Q };
+send(8)         g6<1>.xD        g114<4>F        0x0218b303
+                            sampler MsgDesc: sampleinfo SIMD4x2 Surface = 3 Sampler = 3 mlen 1 rlen 1 { align16 1Q };
+send(8)         g8<1>.xD        g114<4>F        0x0218b404
+                            sampler MsgDesc: sampleinfo SIMD4x2 Surface = 4 Sampler = 4 mlen 1 rlen 1 { align16 1Q };
+send(8)         g10<1>.xD       g114<4>F        0x0218b505
+                            sampler MsgDesc: sampleinfo SIMD4x2 Surface = 5 Sampler = 5 mlen 1 rlen 1 { align16 1Q };
+send(8)         g124<1>UW       g8<8,8,1>UD     0x064a2001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g12<8,8,1>UD    0x0a8c2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g15<8,8,1>UD    0x08423102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g2<8,8,1>UD     0x10843102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+send(8)         g5<1>UW         g5<8,8,1>UD     0x04194e01
+                            render MsgDesc: typed surface read MsgCtrl = 0x14 Surface = 1 mlen 2 rlen 1 { align1 1Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x060b4e02
+                            render MsgDesc: typed surface write MsgCtrl = 0x14 Surface = 2 mlen 3 rlen 0 { align1 1Q };
+send(8)         g7<1>UW         g10<8,8,1>UD    0x04196e01
+                            render MsgDesc: typed surface read MsgCtrl = 0x46 Surface = 1 mlen 2 rlen 1 { align1 2Q };
+send(8)         null<1>UW       g12<8,8,1>UD    0x060b6e02
+                            render MsgDesc: typed surface write MsgCtrl = 0x46 Surface = 2 mlen 3 rlen 0 { align1 2Q };
+send(8)         null<1>F        g113<4>F        0x1a094030
+                            urb MsgDesc: 6 write HWord per-slot interleave mlen 13 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x06094060
+                            urb MsgDesc: 12 write HWord per-slot interleave mlen 3 rlen 0 { align16 1Q };
+send(8)         null<1>F        g113<4>F        0x9a08c000
+                            urb MsgDesc: 0 write HWord interleave complete mlen 13 rlen 0 { align16 1Q EOT };
+send(8)         g14<1>UW        g11<8,8,1>UD    0x084b0206
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 6 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x084b0004
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 4 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x0a4b0105
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 5 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g26<1>UW        g2<8,8,1>UD     0x0e8d0206
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 6 Sampler = 2 mlen 7 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0e8d0004
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 4 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g34<8,8,1>UD    0x128d0105
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 5 Sampler = 1 mlen 9 rlen 8 { align1 1H };
+send(16)        g52<1>UD        g6<8,8,1>UD     0x02280304
+                            const MsgDesc: (4, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g30<1>UD        g11<8,8,1>UD    0x02280303
+                            const MsgDesc: (3, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g32<1>UD        g14<8,8,1>UD    0x02280306
+                            const MsgDesc: (6, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g34<1>UD        g16<8,8,1>UD    0x02280305
+                            const MsgDesc: (5, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g7<1>UW         g24<8,8,1>UD    0x02116e02
+                            data MsgDesc: ( DC untyped surface read, 2, 46) mlen 1 rlen 1 { align1 1Q };
+send(8)         g8<1>UW         g24<8,8,1>UD    0x02116e04
+                            data MsgDesc: ( DC untyped surface read, 4, 46) mlen 1 rlen 1 { align1 1Q };
+send(8)         g5<1>UW         g21<8,8,1>UD    0x02116e03
+                            data MsgDesc: ( DC untyped surface read, 3, 46) mlen 1 rlen 1 { align1 1Q };
+send(16)        g12<1>UW        g40<8,8,1>UD    0x04215e02
+                            data MsgDesc: ( DC untyped surface read, 2, 30) mlen 2 rlen 2 { align1 1H };
+send(16)        g14<1>UW        g40<8,8,1>UD    0x04215e04
+                            data MsgDesc: ( DC untyped surface read, 4, 30) mlen 2 rlen 2 { align1 1H };
+send(16)        g8<1>UW         g36<8,8,1>UD    0x04215e03
+                            data MsgDesc: ( DC untyped surface read, 3, 30) mlen 2 rlen 2 { align1 1H };
+(+f1.0) send(8) null<1>UW       g11<8,8,1>UD    0x0a036002
+                            data MsgDesc: ( DC untyped surface write, 2, 32) mlen 5 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g13<8,8,1>UD    0x14035002
+                            data MsgDesc: ( DC untyped surface write, 2, 16) mlen 10 rlen 0 { align1 1H };
+send(8)         g15<1>D         g114<4>F        0x0210a707
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 7 Sampler = 7 mlen 1 rlen 1 { align16 1Q };
+send(8)         g17<1>D         g114<4>F        0x0210a808
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 8 Sampler = 8 mlen 1 rlen 1 { align16 1Q };
+send(8)         g19<1>D         g114<4>F        0x0210a909
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 9 Sampler = 9 mlen 1 rlen 1 { align16 1Q };
+send(8)         g21<1>D         g114<4>F        0x0210aa0a
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 10 Sampler = 10 mlen 1 rlen 1 { align16 1Q };
+send(8)         g23<1>D         g114<4>F        0x0210ab0b
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 11 Sampler = 11 mlen 1 rlen 1 { align16 1Q };
+send(8)         g25<1>D         g114<4>F        0x0210ac0c
+                            sampler MsgDesc: resinfo SIMD4x2 Surface = 12 Sampler = 12 mlen 1 rlen 1 { align16 1Q };
+send(8)         null<1>UW       g126<8,8,1>UD   0x040a02ff
+                            data MsgDesc: ( DC OWORD block write, 255, 2) mlen 2 rlen 0 { align1 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0009
+                            data MsgDesc: ( DC OWORD block read, 9, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0001
+                            data MsgDesc: ( DC OWORD block read, 1, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0008
+                            data MsgDesc: ( DC OWORD block read, 8, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0002
+                            data MsgDesc: ( DC OWORD block read, 2, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0007
+                            data MsgDesc: ( DC OWORD block read, 7, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0000
+                            data MsgDesc: ( DC OWORD block read, 0, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g68<1>UW        g0<8,8,1>F      0x021c0005
+                            data MsgDesc: ( DC OWORD block read, 5, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c0004
+                            data MsgDesc: ( DC OWORD block read, 4, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g64<1>UW        g0<8,8,1>F      0x021c0006
+                            data MsgDesc: ( DC OWORD block read, 6, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         g64<1>UW        g0<8,8,1>F      0x021c0003
+                            data MsgDesc: ( DC OWORD block read, 3, 0) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         null<1>F        g113<4>F        0x16094060
+                            urb MsgDesc: 12 write HWord per-slot interleave mlen 11 rlen 0 { align16 1Q };
+send(8)         null<1>UW       g9<8,8,1>UD     0x0e0b4002
+                            render MsgDesc: typed surface write MsgCtrl = 0x0 Surface = 2 mlen 7 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g21<8,8,1>UD    0x0e0b6002
+                            render MsgDesc: typed surface write MsgCtrl = 0x32 Surface = 2 mlen 7 rlen 0 { align1 2Q };
+send(8)         g2<1>UW         g50<8,8,1>UD    0x02216c01
+                            data MsgDesc: ( DC untyped surface read, 1, 44) mlen 1 rlen 2 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g2<8,8,1>UD     0x06036c02
+                            data MsgDesc: ( DC untyped surface write, 2, 44) mlen 3 rlen 0 { align1 1Q };
+send(16)        g15<1>UW        g85<8,8,1>UD    0x04415c01
+                            data MsgDesc: ( DC untyped surface read, 1, 28) mlen 2 rlen 4 { align1 1H };
+(+f1.0) send(16) null<1>UW      g2<8,8,1>UD     0x0c035c02
+                            data MsgDesc: ( DC untyped surface write, 2, 28) mlen 6 rlen 0 { align1 1H };
+send(8)         null<1>UW       g7<8,8,1>UD     0x080b4e02
+                            render MsgDesc: typed surface write MsgCtrl = 0x14 Surface = 2 mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x080b6e02
+                            render MsgDesc: typed surface write MsgCtrl = 0x46 Surface = 2 mlen 4 rlen 0 { align1 2Q };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x104a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x084a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x0e8c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g4<1>UW         g16<8,8,1>UD    0x04194e02
+                            render MsgDesc: typed surface read MsgCtrl = 0x14 Surface = 2 mlen 2 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x0619a701
+                            render MsgDesc: typed atomic op MsgCtrl = 0x39 Surface = 1 mlen 3 rlen 1 { align1 1Q };
+send(8)         g7<1>UW         g31<8,8,1>UD    0x04196e02
+                            render MsgDesc: typed surface read MsgCtrl = 0x46 Surface = 2 mlen 2 rlen 1 { align1 2Q };
+send(8)         g121<1>UW       g5<8,8,1>UD     0x0619b701
+                            render MsgDesc: typed atomic op MsgCtrl = 0x55 Surface = 1 mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x0619ad01
+                            render MsgDesc: typed atomic op MsgCtrl = 0x45 Surface = 1 mlen 3 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g5<8,8,1>UD     0x0619bd01
+                            render MsgDesc: typed atomic op MsgCtrl = 0x61 Surface = 1 mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x0619ac01
+                            render MsgDesc: typed atomic op MsgCtrl = 0x44 Surface = 1 mlen 3 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g5<8,8,1>UD     0x0619bc01
+                            render MsgDesc: typed atomic op MsgCtrl = 0x60 Surface = 1 mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x0619a101
+                            render MsgDesc: typed atomic op MsgCtrl = 0x33 Surface = 1 mlen 3 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g5<8,8,1>UD     0x0619b101
+                            render MsgDesc: typed atomic op MsgCtrl = 0x49 Surface = 1 mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x0619a201
+                            render MsgDesc: typed atomic op MsgCtrl = 0x34 Surface = 1 mlen 3 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g5<8,8,1>UD     0x0619b201
+                            render MsgDesc: typed atomic op MsgCtrl = 0x50 Surface = 1 mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x0619a301
+                            render MsgDesc: typed atomic op MsgCtrl = 0x35 Surface = 1 mlen 3 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g5<8,8,1>UD     0x0619b301
+                            render MsgDesc: typed atomic op MsgCtrl = 0x51 Surface = 1 mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x0619a401
+                            render MsgDesc: typed atomic op MsgCtrl = 0x36 Surface = 1 mlen 3 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g5<8,8,1>UD     0x0619b401
+                            render MsgDesc: typed atomic op MsgCtrl = 0x52 Surface = 1 mlen 3 rlen 1 { align1 2Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x0819ae01
+                            render MsgDesc: typed atomic op MsgCtrl = 0x46 Surface = 1 mlen 4 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g2<8,8,1>UD     0x0819be01
+                            render MsgDesc: typed atomic op MsgCtrl = 0x62 Surface = 1 mlen 4 rlen 1 { align1 2Q };
+send(8)         null<1>F        g113<4>F        0x8608c060
+                            urb MsgDesc: 12 write HWord interleave complete mlen 3 rlen 0 { align16 1Q EOT };
+send(8)         g9<1>UW         g19<8,8,1>UD    0x0843e102
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g23<1>UW        g7<8,8,1>UD     0x1085e102
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+send(8)         g9<1>UW         g21<8,8,1>UD    0x0443d002
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g23<1>UW        g11<8,8,1>UD    0x0885d002
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         null<1>UW       g2<8,8,1>UD     0x060b4e01
+                            render MsgDesc: typed surface write MsgCtrl = 0x14 Surface = 1 mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x060b6e01
+                            render MsgDesc: typed surface write MsgCtrl = 0x46 Surface = 1 mlen 3 rlen 0 { align1 2Q };
+(+f1.0) send(8) null<1>UW       g11<8,8,1>UD    0x0a036003
+                            data MsgDesc: ( DC untyped surface write, 3, 32) mlen 5 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g11<8,8,1>UD    0x14035003
+                            data MsgDesc: ( DC untyped surface write, 3, 16) mlen 10 rlen 0 { align1 1H };
+send(8)         g3<1>UW         g4<8,8,1>UD     0x02427002
+                            sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g4<1>UW         g12<8,8,1>UD    0x04847002
+                            sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x0a4a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x08425001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x08425102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x10845001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g19<8,8,1>UD    0x10845102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+send(16)        g2<1>UD         g4<8,8,1>UD     0x02280307
+                            const MsgDesc: (7, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x064a8002
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0a8c8002
+                            sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+(+f1.0) send(8) null<1>UW       g9<8,8,1>UD     a0<0,1,0>UD     0x00000200
+                            data MsgDesc: indirect                          { align1 1Q };
+send(8)         g10<1>UW        g10<8,8,1>UD    0x04420004
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x08840004
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g22<1>UW        g22<8,8,1>UD    0x064a800d
+                            sampler MsgDesc: gather4 SIMD8 Surface = 13 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g38<1>UW        g38<8,8,1>UD    0x084a810e
+                            sampler MsgDesc: gather4 SIMD8 Surface = 14 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(8)         g5<1>UW         g19<8,8,1>UD    0x064a820f
+                            sampler MsgDesc: gather4 SIMD8 Surface = 15 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(8)         g47<1>UW        g41<8,8,1>UD    0x064a8310
+                            sampler MsgDesc: gather4 SIMD8 Surface = 16 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g14<8,8,1>UD    0x084a8411
+                            sampler MsgDesc: gather4 SIMD8 Surface = 17 Sampler = 4 mlen 4 rlen 4 { align1 1Q };
+send(8)         g47<1>UW        g7<8,8,1>UD     0x064a8512
+                            sampler MsgDesc: gather4 SIMD8 Surface = 18 Sampler = 5 mlen 3 rlen 4 { align1 1Q };
+send(8)         g25<1>UW        g25<8,8,1>UD    0x064a8613
+                            sampler MsgDesc: gather4 SIMD8 Surface = 19 Sampler = 6 mlen 3 rlen 4 { align1 1Q };
+send(8)         g29<1>UW        g45<8,8,1>UD    0x084a8714
+                            sampler MsgDesc: gather4 SIMD8 Surface = 20 Sampler = 7 mlen 4 rlen 4 { align1 1Q };
+send(8)         g11<1>UW        g8<8,8,1>UD     0x064a8815
+                            sampler MsgDesc: gather4 SIMD8 Surface = 21 Sampler = 8 mlen 3 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g26<8,8,1>UD    0x084b0916
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 22 Sampler = 9 mlen 4 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x0a4b0a17
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 23 Sampler = 10 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x084b0b18
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 24 Sampler = 11 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0a8c800d
+                            sampler MsgDesc: gather4 SIMD16 Surface = 13 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(16)        g34<1>UW        g42<8,8,1>UD    0x0e8c810e
+                            sampler MsgDesc: gather4 SIMD16 Surface = 14 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(16)        g34<1>UW        g89<8,8,1>UD    0x0a8c820f
+                            sampler MsgDesc: gather4 SIMD16 Surface = 15 Sampler = 2 mlen 5 rlen 8 { align1 1H };
+send(16)        g30<1>UW        g73<8,8,1>UD    0x0a8c8310
+                            sampler MsgDesc: gather4 SIMD16 Surface = 16 Sampler = 3 mlen 5 rlen 8 { align1 1H };
+send(16)        g30<1>UW        g23<8,8,1>UD    0x0e8c8411
+                            sampler MsgDesc: gather4 SIMD16 Surface = 17 Sampler = 4 mlen 7 rlen 8 { align1 1H };
+send(16)        g5<1>UW         g33<8,8,1>UD    0x0a8c8512
+                            sampler MsgDesc: gather4 SIMD16 Surface = 18 Sampler = 5 mlen 5 rlen 8 { align1 1H };
+send(16)        g33<1>UW        g56<8,8,1>UD    0x0a8c8613
+                            sampler MsgDesc: gather4 SIMD16 Surface = 19 Sampler = 6 mlen 5 rlen 8 { align1 1H };
+send(16)        g34<1>UW        g23<8,8,1>UD    0x0e8c8714
+                            sampler MsgDesc: gather4 SIMD16 Surface = 20 Sampler = 7 mlen 7 rlen 8 { align1 1H };
+send(16)        g5<1>UW         g34<8,8,1>UD    0x0a8c8815
+                            sampler MsgDesc: gather4 SIMD16 Surface = 21 Sampler = 8 mlen 5 rlen 8 { align1 1H };
+send(16)        g38<1>UW        g67<8,8,1>UD    0x0e8d0916
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 22 Sampler = 9 mlen 7 rlen 8 { align1 1H };
+send(16)        g38<1>UW        g2<8,8,1>UD     0x128d0a17
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 23 Sampler = 10 mlen 9 rlen 8 { align1 1H };
+send(16)        g18<1>UW        g33<8,8,1>UD    0x0e8d0b18
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 24 Sampler = 11 mlen 7 rlen 8 { align1 1H };
+(+f1.0) send(8) g3<1>UW         g10<8,8,1>UD    0x0411b701
+                            data MsgDesc: ( DC untyped atomic, 1,  add) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g5<1>UW         g10<8,8,1>UD    0x0411bd01
+                            data MsgDesc: ( DC untyped atomic, 1,  umin) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g6<1>UW         g10<8,8,1>UD    0x0411bc01
+                            data MsgDesc: ( DC untyped atomic, 1,  umax) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g7<1>UW         g10<8,8,1>UD    0x0411b101
+                            data MsgDesc: ( DC untyped atomic, 1,  and) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g8<1>UW         g10<8,8,1>UD    0x0411b201
+                            data MsgDesc: ( DC untyped atomic, 1,  or) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g9<1>UW         g10<8,8,1>UD    0x0411b301
+                            data MsgDesc: ( DC untyped atomic, 1,  xor) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g10<1>UW        g10<8,8,1>UD    0x0411b401
+                            data MsgDesc: ( DC untyped atomic, 1,  mov) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g11<1>UW        g11<8,8,1>UD    0x0611be01
+                            data MsgDesc: ( DC untyped atomic, 1,  cmpwr) mlen 3 rlen 1 { align1 1Q };
+(+f1.0) send(16) g3<1>UW        g19<8,8,1>UD    0x0821a701
+                            data MsgDesc: ( DC untyped atomic, 1,  add) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g7<1>UW        g19<8,8,1>UD    0x0821ad01
+                            data MsgDesc: ( DC untyped atomic, 1,  umin) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g9<1>UW        g19<8,8,1>UD    0x0821ac01
+                            data MsgDesc: ( DC untyped atomic, 1,  umax) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g11<1>UW       g19<8,8,1>UD    0x0821a101
+                            data MsgDesc: ( DC untyped atomic, 1,  and) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g13<1>UW       g19<8,8,1>UD    0x0821a201
+                            data MsgDesc: ( DC untyped atomic, 1,  or) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g15<1>UW       g19<8,8,1>UD    0x0821a301
+                            data MsgDesc: ( DC untyped atomic, 1,  xor) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g17<1>UW       g19<8,8,1>UD    0x0821a401
+                            data MsgDesc: ( DC untyped atomic, 1,  mov) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g19<1>UW       g21<8,8,1>UD    0x0c21ae01
+                            data MsgDesc: ( DC untyped atomic, 1,  cmpwr) mlen 6 rlen 2 { align1 1H };
+send(8)         g26<1>F         g114<4>F        0x0418800c
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 12 Sampler = 0 mlen 2 rlen 1 { align16 1Q };
+send(8)         g30<1>F         g114<4>F        0x0418810d
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 13 Sampler = 1 mlen 2 rlen 1 { align16 1Q };
+send(8)         g36<1>F         g114<4>F        0x0418820e
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 14 Sampler = 2 mlen 2 rlen 1 { align16 1Q };
+send(8)         g55<1>D         g114<4>F        0x0418830f
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 15 Sampler = 3 mlen 2 rlen 1 { align16 1Q };
+send(8)         g61<1>D         g114<4>F        0x04188410
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 16 Sampler = 4 mlen 2 rlen 1 { align16 1Q };
+send(8)         g67<1>D         g114<4>F        0x04188511
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 17 Sampler = 5 mlen 2 rlen 1 { align16 1Q };
+send(8)         g86<1>UD        g114<4>F        0x04188612
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 18 Sampler = 6 mlen 2 rlen 1 { align16 1Q };
+send(8)         g92<1>UD        g114<4>F        0x04188713
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 19 Sampler = 7 mlen 2 rlen 1 { align16 1Q };
+send(8)         g98<1>UD        g114<4>F        0x04188814
+                            sampler MsgDesc: gather4 SIMD4x2 Surface = 20 Sampler = 8 mlen 2 rlen 1 { align16 1Q };
+send(8)         g6<1>F          g114<4>F        0x06190915
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 21 Sampler = 9 mlen 3 rlen 1 { align16 1Q };
+send(8)         g11<1>F         g114<4>F        0x06190a16
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 22 Sampler = 10 mlen 3 rlen 1 { align16 1Q };
+send(8)         g16<1>F         g114<4>F        0x06190b17
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 23 Sampler = 11 mlen 3 rlen 1 { align16 1Q };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x0a4b1002
+                            sampler MsgDesc: gather4_po SIMD8 Surface = 2 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g3<8,8,1>UD     0x128d1002
+                            sampler MsgDesc: gather4_po SIMD16 Surface = 2 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         g4<1>F          g114<4>F        0x06190005
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 5 Sampler = 0 mlen 3 rlen 1 { align16 1Q };
+send(8)         g5<1>F          g114<4>F        0x06190106
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 6 Sampler = 1 mlen 3 rlen 1 { align16 1Q };
+send(8)         g7<1>F          g114<4>F        0x06190207
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 7 Sampler = 2 mlen 3 rlen 1 { align16 1Q };
+send(8)         g10<1>F         g114<4>F        0x06190308
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 8 Sampler = 3 mlen 3 rlen 1 { align16 1Q };
+send(8)         g12<1>F         g114<4>F        0x06190409
+                            sampler MsgDesc: gather4_c SIMD4x2 Surface = 9 Sampler = 4 mlen 3 rlen 1 { align16 1Q };
+send(8)         g24<1>UW        g2<8,8,1>UD     0x06423203
+                            sampler MsgDesc: sample_c SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(16)        g19<1>UW        g27<8,8,1>UD    0x0c843203
+                            sampler MsgDesc: sample_c SIMD16 Surface = 3 Sampler = 2 mlen 6 rlen 8 { align1 1H };
+send(8)         g5<1>F          g114<4>F        0x04102303
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 3 Sampler = 3 mlen 2 rlen 1 { align16 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x08424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g9<1>UW         g5<8,8,1>UD     0x04420002
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g13<1>UW        g7<8,8,1>UD     0x08840002
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x0419a501
+                            render MsgDesc: typed atomic op MsgCtrl = 0x37 Surface = 1 mlen 2 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g2<8,8,1>UD     0x0419b501
+                            render MsgDesc: typed atomic op MsgCtrl = 0x53 Surface = 1 mlen 2 rlen 1 { align1 2Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06098101
+                            render MsgDesc: typed atomic op MsgCtrl = 0x1 Surface = 1 mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06099101
+                            render MsgDesc: typed atomic op MsgCtrl = 0x17 Surface = 1 mlen 3 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06098201
+                            render MsgDesc: typed atomic op MsgCtrl = 0x2 Surface = 1 mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06099201
+                            render MsgDesc: typed atomic op MsgCtrl = 0x18 Surface = 1 mlen 3 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06098301
+                            render MsgDesc: typed atomic op MsgCtrl = 0x3 Surface = 1 mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06099301
+                            render MsgDesc: typed atomic op MsgCtrl = 0x19 Surface = 1 mlen 3 rlen 0 { align1 2Q };
+send(8)         g29<1>UW        g18<8,8,1>UD    0x04420008
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g35<1>UW        g18<8,8,1>UD    0x04420109
+                            sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(8)         g41<1>UW        g18<8,8,1>UD    0x0442020a
+                            sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 2 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g18<8,8,1>UD    0x0442030b
+                            sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 3 mlen 2 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g18<8,8,1>UD    0x0442040c
+                            sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g18<8,8,1>UD    0x0442050d
+                            sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 5 mlen 2 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g18<8,8,1>UD    0x0442060e
+                            sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 6 mlen 2 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x0442070f
+                            sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 7 mlen 2 rlen 4 { align1 1Q };
+send(16)        g32<1>UW        g22<8,8,1>UD    0x08840008
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g42<1>UW        g22<8,8,1>UD    0x08840109
+                            sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(16)        g60<1>UW        g22<8,8,1>UD    0x0884020a
+                            sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 2 mlen 4 rlen 8 { align1 1H };
+send(16)        g70<1>UW        g22<8,8,1>UD    0x0884030b
+                            sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 3 mlen 4 rlen 8 { align1 1H };
+send(16)        g78<1>UW        g22<8,8,1>UD    0x0884040c
+                            sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 4 mlen 4 rlen 8 { align1 1H };
+send(16)        g86<1>UW        g22<8,8,1>UD    0x0884050d
+                            sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 5 mlen 4 rlen 8 { align1 1H };
+send(16)        g94<1>UW        g22<8,8,1>UD    0x0884060e
+                            sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 6 mlen 4 rlen 8 { align1 1H };
+send(16)        g52<1>UW        g22<8,8,1>UD    0x0884070f
+                            sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 7 mlen 4 rlen 8 { align1 1H };
+send(8)         g5<1>F          g114<4>F        0x04102101
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 1 Sampler = 1 mlen 2 rlen 1 { align16 1Q };
+send(8)         g6<1>F          g114<4>F        0x04102202
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 2 Sampler = 2 mlen 2 rlen 1 { align16 1Q };
+send(8)         g8<1>F          g114<4>F        0x04102404
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 4 Sampler = 4 mlen 2 rlen 1 { align16 1Q };
+send(8)         g10<1>F         g114<4>F        0x04102606
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 6 Sampler = 6 mlen 2 rlen 1 { align16 1Q };
+send(8)         g11<1>F         g114<4>F        0x04102707
+                            sampler MsgDesc: sample_l SIMD4x2 Surface = 7 Sampler = 7 mlen 2 rlen 1 { align16 1Q };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x0a425001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g17<8,8,1>UD    0x0a425102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g27<1>UW        g7<8,8,1>UD     0x14845001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(16)        g35<1>UW        g17<8,8,1>UD    0x14845102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H };
+send(8)         null<1>F        g113<4>F        0x0e094030
+                            urb MsgDesc: 6 write HWord per-slot interleave mlen 7 rlen 0 { align16 1Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x08098701
+                            render MsgDesc: typed atomic op MsgCtrl = 0x7 Surface = 1 mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099701
+                            render MsgDesc: typed atomic op MsgCtrl = 0x23 Surface = 1 mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x08098d01
+                            render MsgDesc: typed atomic op MsgCtrl = 0x13 Surface = 1 mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099d01
+                            render MsgDesc: typed atomic op MsgCtrl = 0x29 Surface = 1 mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x08098101
+                            render MsgDesc: typed atomic op MsgCtrl = 0x1 Surface = 1 mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099101
+                            render MsgDesc: typed atomic op MsgCtrl = 0x17 Surface = 1 mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x08098201
+                            render MsgDesc: typed atomic op MsgCtrl = 0x2 Surface = 1 mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099201
+                            render MsgDesc: typed atomic op MsgCtrl = 0x18 Surface = 1 mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x08098301
+                            render MsgDesc: typed atomic op MsgCtrl = 0x3 Surface = 1 mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099301
+                            render MsgDesc: typed atomic op MsgCtrl = 0x19 Surface = 1 mlen 4 rlen 0 { align1 2Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x024ab102
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g10<8,8,1>UD    0x024ab203
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g14<8,8,1>UD    0x024ab304
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x024ab405
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g22<8,8,1>UD    0x024ab506
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x028cb102
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 2 Sampler = 1 mlen 1 rlen 8 { align1 1H };
+send(16)        g28<1>UW        g27<8,8,1>UD    0x028cb203
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 3 Sampler = 2 mlen 1 rlen 8 { align1 1H };
+send(16)        g36<1>UW        g44<8,8,1>UD    0x028cb304
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 4 Sampler = 3 mlen 1 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g53<8,8,1>UD    0x028cb506
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 6 Sampler = 5 mlen 1 rlen 8 { align1 1H };
+send(16)        g44<1>UW        g52<8,8,1>UD    0x028cb405
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 5 Sampler = 4 mlen 1 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x084b0006
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 6 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x0a4b0107
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 7 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g11<8,8,1>UD    0x0a4b0208
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 8 Sampler = 2 mlen 5 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x0c4b0309
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 9 Sampler = 3 mlen 6 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g24<8,8,1>UD    0x084b040a
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 10 Sampler = 4 mlen 4 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x128d0208
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 8 Sampler = 2 mlen 9 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0e8d0006
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 6 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(16)        g26<1>UW        g35<8,8,1>UD    0x168d0309
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 9 Sampler = 3 mlen 11 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g53<8,8,1>UD    0x128d0107
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 7 Sampler = 1 mlen 9 rlen 8 { align1 1H };
+send(16)        g34<1>UW        g46<8,8,1>UD    0x0e8d040a
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 10 Sampler = 4 mlen 7 rlen 8 { align1 1H };
+send(8)         null<1>UW       g9<8,8,1>UD     0x0e0b4003
+                            render MsgDesc: typed surface write MsgCtrl = 0x0 Surface = 3 mlen 7 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g15<8,8,1>UD    0x0e0b6003
+                            render MsgDesc: typed surface write MsgCtrl = 0x32 Surface = 3 mlen 7 rlen 0 { align1 2Q };

diff --git a/src/intel/tools/tests/gen7/send.expected b/src/intel/tools/tests/gen7/send.expected
new file mode 100644 (file)
index 0000000..1ed520e
--- /dev/null
+++ b/src/intel/tools/tests/gen7/send.expected
@@ -0,0 +1,585 @@
+31 01 60 06 bc 0f 0f 20 24 0e 6e 00 00 c0 08 86
+31 01 60 06 bc 0f 0f 20 24 0e 6e 00 00 c0 08 8a
+31 00 60 02 29 0c 40 20 00 01 8d 00 01 70 42 08
+31 00 80 02 29 0c 40 20 c0 01 8d 00 01 70 84 10
+31 01 60 06 25 0c 4f 26 64 06 6e 00 13 40 19 02
+31 01 60 06 3c 0c 0f 20 84 01 6e 00 19 40 09 04
+31 01 60 06 3c 0c 0f 20 a4 01 6e 00 11 40 09 04
+31 01 60 06 3c 0c 0f 20 84 01 6e 00 09 40 09 04
+31 01 60 06 3c 0c 0f 20 84 01 6e 00 01 40 09 04
+31 01 60 06 25 0c cf 21 e4 01 6e 00 0b 40 19 02
+31 01 60 06 25 0c af 21 84 01 6e 00 03 40 19 02
+31 02 60 03 28 0c 00 20 80 01 69 00 04 80 00 02
+31 01 60 06 3c 0c 0f 20 a4 01 6e 00 03 c0 08 02
+31 01 60 06 bc 0f 0f 20 c4 0f 6e 00 01 00 08 84
+31 01 60 0a bd 0f 0f 20 a4 0f 6e 00 ff 80 0a 06
+31 01 60 0a bd 0f 2f 25 c4 0f 6e 00 ff 80 18 04
+31 01 60 06 bc 0f 0f 20 24 0e 6e 00 00 c0 08 8e
+31 00 60 02 29 0c 80 2f 60 01 8d 00 01 00 42 06
+31 00 80 02 29 0c 00 2f 00 02 8d 00 01 00 84 0c
+31 00 60 02 29 0c 80 2f 40 00 8d 00 01 00 42 04
+31 00 80 02 29 0c 00 2f 40 00 8d 00 01 00 84 08
+31 00 60 02 29 0c 80 2f e0 00 8d 00 01 40 4a 14
+31 00 60 02 29 0c 80 2f 00 01 8d 00 01 40 4a 08
+31 01 60 02 21 0c cf 24 e0 0a 60 00 00 70 10 02
+31 00 60 02 29 0c 40 20 e0 00 8d 00 01 60 4a 0a
+31 00 60 02 29 0c c0 20 80 01 8d 00 02 61 4a 0a
+31 00 80 02 29 0c 40 20 60 01 8d 00 01 60 8c 12
+31 00 80 02 29 0c 40 21 80 02 8d 00 02 61 8c 12
+31 01 60 02 a5 0f 4f 21 44 0e 6e 00 00 e0 11 04
+31 01 60 06 bc 0f 0f 20 24 0e 6e 00 00 40 09 0a
+31 01 60 06 bc 0f 0f 20 24 0e 6e 00 00 40 08 82
+31 01 60 06 3c 0c 0f 20 24 01 6e 00 21 40 09 04
+31 01 60 06 3c 0c 0f 20 24 01 6e 00 03 80 08 02
+31 01 60 06 bc 0f 0f 20 24 0e 6e 00 00 40 09 06
+31 01 60 06 bc 0f 0f 20 24 0e 6e 00 00 40 08 1a
+31 01 60 06 bc 0f 0f 20 24 0e 6e 00 30 c0 08 8a
+31 00 60 02 29 0c a0 20 a0 02 8d 00 01 00 42 02
+31 00 80 02 29 0c e0 20 a0 02 8d 00 01 00 84 04
+31 01 60 02 a5 0f 8f 21 44 0e 6e 00 00 a0 10 02
+31 01 60 06 3c 0c 0f 20 24 01 6e 00 29 40 09 04
+31 00 60 02 29 0c 40 20 40 01 8d 00 01 70 42 06
+31 00 80 02 29 0c 40 20 40 02 8d 00 01 70 84 0c
+31 00 60 02 29 0c 80 2f c0 00 8d 00 01 40 42 0c
+31 01 60 02 a5 0f 6f 20 44 0e 6e 00 01 a1 10 02
+31 01 60 02 a5 0f af 20 44 0e 6e 00 02 a2 10 02
+31 01 60 02 a5 0f ef 20 44 0e 6e 00 03 a3 10 02
+31 01 60 02 a5 0f 2f 21 44 0e 6e 00 04 a4 10 02
+31 01 60 02 a5 0f 6f 21 44 0e 6e 00 05 a5 10 02
+31 01 60 02 a5 0f af 21 44 0e 6e 00 06 a6 10 02
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diff --git a/src/intel/tools/tests/gen7/sendc.asm b/src/intel/tools/tests/gen7/sendc.asm
new file mode 100644 (file)
index 0000000..07c3660
--- /dev/null
+++ b/src/intel/tools/tests/gen7/sendc.asm
@@ -0,0 +1,98 @@
+sendc(8)        null<1>UW       g124<8,8,1>F    0x88031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g120<8,8,1>F    0x90031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       g114<8,8,1>F    0x82031100
+                            render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1401
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g13<8,8,1>F     0x0e0b0401
+                            render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g121<8,8,1>F    0x8e0b1402
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g7<8,8,1>F      0x180b0001
+                            render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g116<8,8,1>F    0x980b1002
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g123<8,8,1>F    0x8a031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x94031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g5<8,8,1>F      0x0c0b0400
+                            render MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g5<8,8,1>F      0x0c0b0401
+                            render MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g5<8,8,1>F      0x0c0b0402
+                            render MsgDesc: RT write SIMD8 Surface = 2 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g5<8,8,1>F      0x0c0b0403
+                            render MsgDesc: RT write SIMD8 Surface = 3 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g5<8,8,1>F      0x0c0b0404
+                            render MsgDesc: RT write SIMD8 Surface = 4 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1405
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 5 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g5<8,8,1>F      0x140b0000
+                            render MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g5<8,8,1>F      0x140b0001
+                            render MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g5<8,8,1>F      0x140b0002
+                            render MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g5<8,8,1>F      0x140b0003
+                            render MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g5<8,8,1>F      0x140b0004
+                            render MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1005
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g121<8,8,1>F    0x8e0b1400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g116<8,8,1>F    0x980b1000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 12 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g118<8,8,1>F    0x940b1200
+                            render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g3<8,8,1>F      0x140b1200
+                            render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g118<8,8,1>F    0x940b1300
+                            render MsgDesc: RT write SIMD8/DualSrcHigh LastRT Surface = 0 mlen 10 rlen 0 { align1 2Q EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1402
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1002
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g23<8,8,1>F     0x0c0b0405
+                            render MsgDesc: RT write SIMD8 Surface = 5 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g29<8,8,1>F     0x0c0b0406
+                            render MsgDesc: RT write SIMD8 Surface = 6 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1407
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 7 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g57<8,8,1>F     0x140b0005
+                            render MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g17<8,8,1>F     0x140b0006
+                            render MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1007
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1403
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1003
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1404
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 4 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1004
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1406
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 6 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1006
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g121<8,8,1>F    0x8e0b1401
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g116<8,8,1>F    0x980b1001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 12 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x88031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g7<8,8,1>F      0x0e0b0400
+                            render MsgDesc: RT write SIMD8 Surface = 0 mlen 7 rlen 0 { align1 1Q };
+sendc(16)       null<1>UW       g11<8,8,1>F     0x180b0000
+                            render MsgDesc: RT write SIMD16 Surface = 0 mlen 12 rlen 0 { align1 1H };

diff --git a/src/intel/tools/tests/gen7/sendc.expected b/src/intel/tools/tests/gen7/sendc.expected
new file mode 100644 (file)
index 0000000..3bd787a
--- /dev/null
+++ b/src/intel/tools/tests/gen7/sendc.expected
@@ -0,0 +1,49 @@
+32 00 60 05 a8 0f 00 20 80 0f 8d 00 00 14 03 88
+32 00 80 05 a8 0f 00 20 00 0f 8d 00 00 10 03 90
+32 00 80 05 a8 0f 00 20 40 0e 8d 00 00 11 03 82
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 01 14 0b 8c
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 01 10 0b 94
+32 00 60 05 a8 0f 00 20 a0 01 8d 00 01 04 0b 0e
+32 00 60 05 a8 0f 00 20 20 0f 8d 00 02 14 0b 8e
+32 00 80 05 a8 0f 00 20 e0 00 8d 00 01 00 0b 18
+32 00 80 05 a8 0f 00 20 80 0e 8d 00 02 10 0b 98
+32 00 60 05 a8 0f 00 20 60 0f 8d 00 00 14 03 8a
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 00 10 03 94
+32 00 60 05 a8 0f 00 20 a0 00 8d 00 00 04 0b 0c
+32 00 60 05 a8 0f 00 20 a0 00 8d 00 01 04 0b 0c
+32 00 60 05 a8 0f 00 20 a0 00 8d 00 02 04 0b 0c
+32 00 60 05 a8 0f 00 20 a0 00 8d 00 03 04 0b 0c
+32 00 60 05 a8 0f 00 20 a0 00 8d 00 04 04 0b 0c
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 05 14 0b 8c
+32 00 80 05 a8 0f 00 20 a0 00 8d 00 00 00 0b 14
+32 00 80 05 a8 0f 00 20 a0 00 8d 00 01 00 0b 14
+32 00 80 05 a8 0f 00 20 a0 00 8d 00 02 00 0b 14
+32 00 80 05 a8 0f 00 20 a0 00 8d 00 03 00 0b 14
+32 00 80 05 a8 0f 00 20 a0 00 8d 00 04 00 0b 14
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 05 10 0b 94
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 00 14 0b 8c
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 00 10 0b 94
+32 00 60 05 a8 0f 00 20 20 0f 8d 00 00 14 0b 8e
+32 00 80 05 a8 0f 00 20 80 0e 8d 00 00 10 0b 98
+32 00 60 05 a8 0f 00 20 c0 0e 8d 00 00 12 0b 94
+32 00 60 05 a8 0f 00 20 60 00 8d 00 00 12 0b 14
+32 10 60 05 a8 0f 00 20 c0 0e 8d 00 00 13 0b 94
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 02 14 0b 8c
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 02 10 0b 94
+32 00 60 05 a8 0f 00 20 e0 02 8d 00 05 04 0b 0c
+32 00 60 05 a8 0f 00 20 a0 03 8d 00 06 04 0b 0c
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 07 14 0b 8c
+32 00 80 05 a8 0f 00 20 20 07 8d 00 05 00 0b 14
+32 00 80 05 a8 0f 00 20 20 02 8d 00 06 00 0b 14
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 07 10 0b 94
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 03 14 0b 8c
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 03 10 0b 94
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 04 14 0b 8c
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 04 10 0b 94
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 06 14 0b 8c
+32 00 80 05 a8 0f 00 20 c0 0e 8d 00 06 10 0b 94
+32 00 60 05 a8 0f 00 20 20 0f 8d 00 01 14 0b 8e
+32 00 80 05 a8 0f 00 20 80 0e 8d 00 01 10 0b 98
+32 00 60 05 a8 0f 00 20 40 0f 8d 00 00 14 03 88
+32 00 60 05 a8 0f 00 20 e0 00 8d 00 00 04 0b 0e
+32 00 80 05 a8 0f 00 20 60 01 8d 00 00 00 0b 18

diff --git a/src/intel/tools/tests/gen7/shl.asm b/src/intel/tools/tests/gen7/shl.asm
new file mode 100644 (file)
index 0000000..9d24156
--- /dev/null
+++ b/src/intel/tools/tests/gen7/shl.asm
@@ -0,0 +1,13 @@
+shl(1)          a0<1>UW         a0<0,1,0>UW     0x0002UW        { align1 WE_all 1N };
+shl(1)          g12.2<1>UD      g12.2<0,1,0>UD  0x0000000cUD    { align1 WE_all 1N };
+shl(8)          g87<1>.xD       g4<0>.zD        0x00000004UD    { align16 1Q };
+shl(8)          g13<1>.xyD      g5.4<0>.zwwwD   g6<0>.xyyyUD    { align16 1Q };
+shl(8)          g114<1>UD       g26<4>.xUD      g27<4>.xUD      { align16 1Q };
+shl(8)          g3<1>D          g2<0,1,0>D      0x00000003UD    { align1 1Q };
+shl(16)         g3<1>D          g2<0,1,0>D      0x00000003UD    { align1 1H };
+shl(8)          g37<1>D         g35<8,8,1>D     g5.6<0,1,0>UD   { align1 1Q };
+shl(16)         g68<1>D         g23<8,8,1>D     g7.6<0,1,0>UD   { align1 1H };
+shl(1)          a0<1>UD         g20<0,1,0>UD    0x00000008UD    { align1 WE_all 1N };
+shl(8)          g59<1>.xUD      g58<4>.xUD      g57<4>.xUD      { align16 WE_all 1Q };
+shl(8)          g38<1>UD        g38<8,8,1>UD    0x00000010UD    { align1 1Q };
+shl(16)         g76<1>UD        g76<8,8,1>UD    0x00000010UD    { align1 1H };

diff --git a/src/intel/tools/tests/gen7/shl.expected b/src/intel/tools/tests/gen7/shl.expected
new file mode 100644 (file)
index 0000000..56f943d
--- /dev/null
+++ b/src/intel/tools/tests/gen7/shl.expected
@@ -0,0 +1,13 @@
+09 02 00 00 08 2d 00 22 00 02 00 00 02 00 02 00
+09 02 00 00 21 0c 88 21 88 01 00 00 0c 00 00 00
+09 01 60 00 a5 0c e1 2a 8a 00 0a 00 04 00 00 00
+09 01 60 00 a5 04 a3 21 be 00 0f 00 c4 00 05 00
+09 01 60 00 21 04 4f 2e 40 03 60 00 60 03 60 00
+09 00 60 00 a5 0c 60 20 40 00 00 00 03 00 00 00
+09 00 80 00 a5 0c 60 20 40 00 00 00 03 00 00 00
+09 00 60 00 a5 04 a0 24 60 04 8d 00 b8 00 00 00
+09 00 80 00 a5 04 80 28 e0 02 8d 00 f8 00 00 00
+09 02 00 00 20 0c 00 22 80 02 00 00 08 00 00 00
+09 03 60 00 21 04 61 27 40 07 60 00 20 07 60 00
+09 00 60 00 21 0c c0 24 c0 04 8d 00 10 00 00 00
+09 00 80 00 21 0c 80 29 80 09 8d 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen7/shr.asm b/src/intel/tools/tests/gen7/shr.asm
new file mode 100644 (file)
index 0000000..3c6e23d
--- /dev/null
+++ b/src/intel/tools/tests/gen7/shr.asm
@@ -0,0 +1,8 @@
+shr(1)          g11<1>UD        g11<0,1,0>UD    0x0000000fUD    { align1 1N };
+shr(8)          g13<1>.xUD      g5.4<0>.zUD     g5.4<0>.wUD     { align16 1Q };
+shr(8)          g13<1>UD        g12<8,8,1>UD    0x00000001UD    { align1 1Q };
+shr(16)         g27<1>UD        g25<8,8,1>UD    0x00000001UD    { align1 1H };
+shr(8)          g35<1>UD        g31<8,8,1>UD    g5.5<0,1,0>UD   { align1 1Q };
+shr(16)         g23<1>UD        g56<8,8,1>UD    g7.5<0,1,0>UD   { align1 1H };
+shr(1)          g9<1>UD         g9<0,1,0>UD     5D              { align1 WE_all 1N };
+shr(8)          g54<1>.xUD      g55<4>.xUD      0x00000005UD    { align16 1Q };

diff --git a/src/intel/tools/tests/gen7/shr.expected b/src/intel/tools/tests/gen7/shr.expected
new file mode 100644 (file)
index 0000000..e6db058
--- /dev/null
+++ b/src/intel/tools/tests/gen7/shr.expected
@@ -0,0 +1,8 @@
+08 00 00 00 21 0c 60 21 60 01 00 00 0f 00 00 00
+08 01 60 00 21 04 a1 21 ba 00 0a 00 bf 00 0f 00
+08 00 60 00 21 0c a0 21 80 01 8d 00 01 00 00 00
+08 00 80 00 21 0c 60 23 20 03 8d 00 01 00 00 00
+08 00 60 00 21 04 60 24 e0 03 8d 00 b4 00 00 00
+08 00 80 00 21 04 e0 22 00 07 8d 00 f4 00 00 00
+08 02 00 00 21 1c 20 21 20 01 00 00 05 00 00 00
+08 01 60 00 21 0c c1 26 e0 06 60 00 05 00 00 00

diff --git a/src/intel/tools/tests/gen7/wait.asm b/src/intel/tools/tests/gen7/wait.asm
new file mode 100644 (file)
index 0000000..ea69c7e
--- /dev/null
+++ b/src/intel/tools/tests/gen7/wait.asm
@@ -0,0 +1 @@
+wait(1)                         n0<0>.xUD                       { align16 WE_all 1N };

diff --git a/src/intel/tools/tests/gen7/wait.expected b/src/intel/tools/tests/gen7/wait.expected
new file mode 100644 (file)
index 0000000..c227101
--- /dev/null
+++ b/src/intel/tools/tests/gen7/wait.expected
@@ -0,0 +1 @@
+30 03 00 00 00 70 01 32 00 12 00 00 04 00 6e 00

diff --git a/src/intel/tools/tests/gen7/while.asm b/src/intel/tools/tests/gen7/while.asm
new file mode 100644 (file)
index 0000000..be4e182
--- /dev/null
+++ b/src/intel/tools/tests/gen7/while.asm
@@ -0,0 +1,5 @@
+while(8)        JIP: -50                                        { align1 1Q };
+while(16)       JIP: -58                                        { align1 1H };
+while(8)        JIP: -8                                         { align16 1Q };
+(-f0.0) while(8) JIP: -10                                       { align1 1Q };
+(-f0.0) while(16) JIP: -10                                      { align1 1H };

diff --git a/src/intel/tools/tests/gen7/while.expected b/src/intel/tools/tests/gen7/while.expected
new file mode 100644 (file)
index 0000000..70dd598
--- /dev/null
+++ b/src/intel/tools/tests/gen7/while.expected
@@ -0,0 +1,5 @@
+27 00 60 00 84 3c 00 20 00 00 8d 00 ce ff 00 00
+27 00 80 00 84 3c 00 20 00 00 8d 00 c6 ff 00 00
+27 01 60 00 84 3c 0f 20 04 00 6e 00 f8 ff 00 00
+27 00 71 00 84 3c 00 20 00 00 8d 00 f6 ff 00 00
+27 00 91 00 84 3c 00 20 00 00 8d 00 f6 ff 00 00

diff --git a/src/intel/tools/tests/gen7/xor.asm b/src/intel/tools/tests/gen7/xor.asm
new file mode 100644 (file)
index 0000000..a631d4e
--- /dev/null
+++ b/src/intel/tools/tests/gen7/xor.asm
@@ -0,0 +1,5 @@
+xor(8)          g14<1>.xUD      g5.4<0>.zUD     g13<4>.xUD      { align16 1Q };
+xor(8)          g47<1>UD        g45<8,8,1>UD    g46<8,8,1>UD    { align1 1Q };
+xor(16)         g87<1>UD        g83<8,8,1>UD    g85<8,8,1>UD    { align1 1H };
+xor(8)          g124<1>UD       g5<8,8,1>UD     0x000003ffUD    { align1 1Q };
+xor(16)         g120<1>UD       g13<8,8,1>UD    0x000003ffUD    { align1 1H };

diff --git a/src/intel/tools/tests/gen7/xor.expected b/src/intel/tools/tests/gen7/xor.expected
new file mode 100644 (file)
index 0000000..4bdf856
--- /dev/null
+++ b/src/intel/tools/tests/gen7/xor.expected
@@ -0,0 +1,5 @@
+07 01 60 00 21 04 c1 21 ba 00 0a 00 a0 01 60 00
+07 00 60 00 21 04 e0 25 a0 05 8d 00 c0 05 8d 00
+07 00 80 00 21 04 e0 2a 60 0a 8d 00 a0 0a 8d 00
+07 00 60 00 21 0c 80 2f a0 00 8d 00 ff 03 00 00
+07 00 80 00 21 0c 00 2f a0 01 8d 00 ff 03 00 00

diff --git a/src/intel/tools/tests/gen8/add.asm b/src/intel/tools/tests/gen8/add.asm
new file mode 100644 (file)
index 0000000..ed48a90
--- /dev/null
+++ b/src/intel/tools/tests/gen8/add.asm
@@ -0,0 +1,40 @@
+add(8)          g124<1>F        g7<8,8,1>D      1D              { align1 1Q };
+add(16)         g120<1>F        g11<8,8,1>D     1D              { align1 1H };
+add(16)         g11<1>F         g1<0,1,0>F      -g1.4<0,1,0>F   { align1 1H };
+add(8)          g10.8<1>UW      g10<8,8,1>UW    0x0008UW        { align1 WE_all 1Q };
+add(16)         g14<1>D         g25<8,8,1>D     g19<8,8,1>D     { align1 1H };
+add(16)         g6<1>UW         g1.4<1,4,0>UW   0x11001010V     { align1 WE_all 1H };
+add(32)         g18<1>UW        g1.4<1,4,0>UW   0x11001010V     { align1 WE_all };
+add(8)          g2<1>D          g34<8,8,1>D     -1023D          { align1 1Q };
+add(8)          g4<1>F          g5.6<0,1,0>F    g7.2<0,1,0>F    { align1 1Q };
+add(8)          g53<1>DF        g49<4,4,1>DF    g51<4,4,1>DF    { align1 1Q };
+add.z.f0.0(8)   g3<1>D          g4<8,8,1>D      g2<8,8,1>D      { align1 1Q };
+add.sat(16)     g12<1>UD        g10<8,8,1>UD    0x00000001UD    { align1 1H };
+add(1)          g8.3<1>UD       g0.3<0,1,0>UD   g7<0,1,0>UD     { align1 WE_all 1N };
+add(8)          a0<1>UW         g34<16,8,2>UW   0x0080UW        { align1 1Q };
+add(8)          g8<1>DF         g2<0,1,0>DF     g3.2<0,1,0>DF   { align1 2Q };
+add(16)         a0<1>UW         g3<16,8,2>UW    0x0040UW        { align1 1H };
+add.sat.le.f0.0(8) g125<1>F     -g6<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
+add.z.f0.0(8)   g8<1>F          g2<0,1,0>F      -g2.4<0,1,0>F   { align1 1Q };
+add.z.f0.0(16)  g3<1>F          g2<0,1,0>F      -g2.1<0,1,0>F   { align1 1H };
+add(8)          g3<1>UD         g2<8,8,1>UD     0xffffffffUD    { align1 1Q };
+(+f0.0) add(8)  g15<1>D         -g15<8,8,1>D    31D             { align1 1Q };
+add(1)          a0<1>UD         a0<0,1,0>UD     0x00000200UD    { align1 WE_all 1N };
+add.sat(8)      g124<1>F        g7<8,8,1>F      -g6<8,8,1>F     { align1 1Q };
+add(8)          g8<1>UD         g6<8,8,1>D      0x00000001UD    { align1 1Q };
+add(16)         g11<1>UD        g9<8,8,1>D      0x00000001UD    { align1 1H };
+(+f0.0) add(16) g8<1>D          -g8<8,8,1>D     31D             { align1 1H };
+add.sat(16)     g126<1>F        g2<0,1,0>F      g2.4<0,1,0>F    { align1 1H };
+add.sat(8)      g124<1>F        g17<8,8,1>D     1D              { align1 1Q };
+add(16)         g40<1>D         g38<8,8,1>D     g36<8,8,1>D     { align1 2H };
+add.z.f0.0(16)  null<1>D        g68<8,8,1>D     1D              { align1 1H };
+add.z.f0.0(16)  null<1>D        g8<8,8,1>D      1D              { align1 2H };
+add(16)         g20<1>UD        g17<8,8,1>UD    1D              { align1 1H };
+add(8)          g7<1>F          -g6<4>.xyxyF    g6<4>.zwzwF     { align16 1Q };
+add(16)         g9<1>F          -g7<4>.xyxyF    g7<4>.zwzwF     { align16 1H };
+add(8)          g7<1>UD         g2<8,8,1>UD     -g6<8,8,1>UD    { align1 WE_all 1Q };
+add.le.f0.0(16) g1<1>D          g3.1<0,1,0>D    -g6<8,8,1>D     { align1 1H };
+add.sat(8)      g10<1>UD        g9<8,8,1>UD     0x00000001UD    { align1 1Q };
+add(8)          g22<1>Q         g19<4,4,1>Q     -g21<4,4,1>Q    { align1 1Q };
+add(8)          g8<1>Q          g5<4,4,1>Q      -g7<4,4,1>Q     { align1 2Q };
+add(1)          g4<1>UD         g4<0,1,0>UD     0x00000001UD    { align1 WE_all 3N };

diff --git a/src/intel/tools/tests/gen8/add.expected b/src/intel/tools/tests/gen8/add.expected
new file mode 100644 (file)
index 0000000..bbd9ef5
--- /dev/null
+++ b/src/intel/tools/tests/gen8/add.expected
@@ -0,0 +1,40 @@
+40 00 60 00 e8 0a 80 2f e0 00 8d 0e 01 00 00 00
+40 00 80 00 e8 0a 00 2f 60 01 8d 0e 01 00 00 00
+40 00 80 00 e8 3a 60 21 20 00 00 3a 30 40 00 00
+40 00 60 00 4c 12 50 21 40 01 8d 16 08 00 08 00
+40 00 80 00 28 0a c0 21 20 03 8d 0a 60 02 8d 00
+40 00 80 00 4c 12 c0 20 28 00 28 36 10 10 00 11
+40 00 a0 00 4c 12 40 22 28 00 28 36 10 10 00 11
+40 00 60 00 28 0a 40 20 40 04 8d 0e 01 fc ff ff
+40 00 60 00 e8 3a 80 20 b8 00 00 3a e8 00 00 00
+40 00 60 00 c8 32 a0 26 20 06 69 32 60 06 69 00
+40 00 60 01 28 0a 60 20 80 00 8d 0a 40 00 8d 00
+40 00 80 80 08 02 80 21 40 01 8d 06 01 00 00 00
+40 00 00 00 0c 02 0c 21 0c 00 00 02 e0 00 00 00
+40 00 60 00 40 12 00 22 40 04 ae 16 80 00 80 00
+40 10 60 00 c8 32 00 21 40 00 00 32 70 00 00 00
+40 00 80 00 40 12 00 22 60 00 ae 16 40 00 40 00
+40 00 60 86 e8 3a a0 2f c0 40 8d 3e 00 00 00 3f
+40 00 60 01 e8 3a 00 21 40 00 00 3a 50 40 00 00
+40 00 80 01 e8 3a 60 20 40 00 00 3a 44 40 00 00
+40 00 60 00 08 02 60 20 40 00 8d 06 ff ff ff ff
+40 00 61 00 28 0a e0 21 e0 41 8d 0e 1f 00 00 00
+40 00 00 00 04 00 00 22 00 02 00 06 00 02 00 00
+40 00 60 80 e8 3a 80 2f e0 00 8d 3a c0 40 8d 00
+40 00 60 00 08 0a 00 21 c0 00 8d 06 01 00 00 00
+40 00 80 00 08 0a 60 21 20 01 8d 06 01 00 00 00
+40 00 81 00 28 0a 00 21 00 41 8d 0e 1f 00 00 00
+40 00 80 80 e8 3a c0 2f 40 00 00 3a 50 00 00 00
+40 00 60 80 e8 0a 80 2f 20 02 8d 0e 01 00 00 00
+40 20 80 00 28 0a 00 25 c0 04 8d 0a 80 04 8d 00
+40 00 80 01 20 0a 00 20 80 08 8d 0e 01 00 00 00
+40 20 80 01 20 0a 00 20 00 01 8d 0e 01 00 00 00
+40 00 80 00 08 02 80 22 20 02 8d 0e 01 00 00 00
+40 01 60 00 e8 3a ef 20 c4 40 64 3a ce 00 6e 00
+40 01 80 00 e8 3a 2f 21 e4 40 64 3a ee 00 6e 00
+40 00 60 00 0c 02 e0 20 40 00 8d 02 c0 40 8d 00
+40 00 80 06 28 0a 20 20 64 00 00 0a c0 40 8d 00
+40 00 60 80 08 02 40 21 20 01 8d 06 01 00 00 00
+40 00 60 00 28 4b c0 22 60 02 69 4a a0 42 69 00
+40 10 60 00 28 4b 00 21 a0 00 69 4a e0 40 69 00
+40 10 00 00 0c 02 80 20 80 00 00 06 01 00 00 00

diff --git a/src/intel/tools/tests/gen8/and.asm b/src/intel/tools/tests/gen8/and.asm
new file mode 100644 (file)
index 0000000..49dc122
--- /dev/null
+++ b/src/intel/tools/tests/gen8/and.asm
@@ -0,0 +1,29 @@
+and(8)          g3<1>UD         g2<0,1,0>UD     ~g2.2<0,1,0>D   { align1 1Q };
+and(16)         g3<1>UD         g2<0,1,0>UD     ~g2.2<0,1,0>D   { align1 1H };
+and(8)          g8<1>UD         g0.1<0,1,0>UW   0x07ffUW        { align1 1Q };
+and(16)         g20<1>UD        g0.1<0,1,0>UW   0x07ffUW        { align1 1H };
+and.z.f0.0(8)   g9<1>UD         g8<8,8,1>UD     0x00000003UD    { align1 1Q };
+and(16)         g120<1>D        g7<8,8,1>D      g2<8,8,1>D      { align1 1H };
+and.z.f0.0(8)   null<1>UD       g13<8,8,1>UD    g12<8,8,1>UD    { align1 1Q };
+and.nz.f0.0(8)  null<1>UD       g4.1<0,1,0>UD   g19<8,8,1>UD    { align1 1Q };
+and.z.f0.0(16)  null<1>UD       g27<8,8,1>UD    g18<8,8,1>UD    { align1 1H };
+and.nz.f0.0(16) null<1>UD       g6.1<0,1,0>UD   g22<8,8,1>UD    { align1 1H };
+and(1)          g7<1>UD         g5<0,1,0>UD     0x000000f0UD    { align1 WE_all 1N };
+and.z.f0.0(16)  g21<1>UD        g19<8,8,1>UD    g17<8,8,1>UD    { align1 1H };
+and(8)          g61<1>UD        g79<8,8,1>UD    g32.1<8,4,2>UD  { align1 2Q };
+and(8)          g96<1>D         ~g94<8,8,1>D    ~g95<8,8,1>D    { align1 1Q };
+and(1)          a0<1>UD         g4<0,1,0>UD     0x000000ffUD    { align1 WE_all 1N };
+and(16)         g66<1>UD        g40<8,8,1>UD    0x0000003fUD    { align1 2H };
+and(1)          g2<1>UD         g20<0,1,0>UD    0x000000ffUD    { align1 WE_all 3N };
+and.z.f0.0(8)   null<1>D        g13<8,8,1>UD    0x0000001fUD    { align1 1Q };
+and(8)          g21<1>UD        g15<8,8,1>UD    0x00000003UD    { align1 WE_all 1Q };
+and(8)          g4<1>UW         g3<8,8,1>UW     0xfffcUW        { align1 1Q };
+and(16)         g13<1>UW        g19<16,8,2>UW   0xfffcUW        { align1 1H };
+and.nz.f0.0(8)  null<1>UD       ~g2.2<0,1,0>D   g9<8,8,1>UD     { align1 1Q };
+and(8)          g18<1>UD        ~g2.2<0,1,0>D   g7<8,8,1>UD     { align1 1Q };
+and.nz.f0.0(16) null<1>UD       ~g2.2<0,1,0>D   g14<8,8,1>UD    { align1 1H };
+and(16)         g30<1>UD        ~g2.2<0,1,0>D   g10<8,8,1>UD    { align1 1H };
+and.nz.f0.0(8)  g10<1>UD        g9<8,8,1>UD     0x00000001UD    { align1 1Q };
+and.nz.f0.0(16) g16<1>UD        g14<8,8,1>UD    0x00000001UD    { align1 1H };
+and(8)          g12<1>UQ        g9<4,4,1>UQ     g11<4,4,1>UQ    { align1 1Q };
+and(8)          g26<1>UQ        g18<4,4,1>UQ    g22<4,4,1>UQ    { align1 2Q };

diff --git a/src/intel/tools/tests/gen8/and.expected b/src/intel/tools/tests/gen8/and.expected
new file mode 100644 (file)
index 0000000..6ab0b80
--- /dev/null
+++ b/src/intel/tools/tests/gen8/and.expected
@@ -0,0 +1,29 @@
+05 00 60 00 08 02 60 20 40 00 00 0a 48 40 00 00
+05 00 80 00 08 02 60 20 40 00 00 0a 48 40 00 00
+05 00 60 00 08 12 00 21 02 00 00 16 ff 07 ff 07
+05 00 80 00 08 12 80 22 02 00 00 16 ff 07 ff 07
+05 00 60 01 08 02 20 21 00 01 8d 06 03 00 00 00
+05 00 80 00 28 0a 00 2f e0 00 8d 0a 40 00 8d 00
+05 00 60 01 00 02 00 20 a0 01 8d 02 80 01 8d 00
+05 00 60 02 00 02 00 20 84 00 00 02 60 02 8d 00
+05 00 80 01 00 02 00 20 60 03 8d 02 40 02 8d 00
+05 00 80 02 00 02 00 20 c4 00 00 02 c0 02 8d 00
+05 00 00 00 0c 02 e0 20 a0 00 00 06 f0 00 00 00
+05 00 80 01 08 02 a0 22 60 02 8d 02 20 02 8d 00
+05 10 60 00 08 02 a0 27 e0 09 8d 02 04 04 8a 00
+05 00 60 00 28 0a 00 2c c0 4b 8d 0a e0 4b 8d 00
+05 00 00 00 04 02 00 22 80 00 00 06 ff 00 00 00
+05 20 80 00 08 02 40 28 00 05 8d 06 3f 00 00 00
+05 10 00 00 0c 02 40 20 80 02 00 06 ff 00 00 00
+05 00 60 01 20 02 00 20 a0 01 8d 06 1f 00 00 00
+05 00 60 00 0c 02 a0 22 e0 01 8d 06 03 00 00 00
+05 00 60 00 48 12 80 20 60 00 8d 16 fc ff fc ff
+05 00 80 00 48 12 a0 21 60 02 ae 16 fc ff fc ff
+05 00 60 02 00 0a 00 20 48 40 00 02 20 01 8d 00
+05 00 60 00 08 0a 40 22 48 40 00 02 e0 00 8d 00
+05 00 80 02 00 0a 00 20 48 40 00 02 c0 01 8d 00
+05 00 80 00 08 0a c0 23 48 40 00 02 40 01 8d 00
+05 00 60 02 08 02 40 21 20 01 8d 06 01 00 00 00
+05 00 80 02 08 02 00 22 c0 01 8d 06 01 00 00 00
+05 00 60 00 08 43 80 21 20 01 69 42 60 01 69 00
+05 10 60 00 08 43 40 23 40 02 69 42 c0 02 69 00

diff --git a/src/intel/tools/tests/gen8/asr.asm b/src/intel/tools/tests/gen8/asr.asm
new file mode 100644 (file)
index 0000000..9beabc9
--- /dev/null
+++ b/src/intel/tools/tests/gen8/asr.asm
@@ -0,0 +1,6 @@
+asr(8)          g19<1>D         g7<8,8,1>D      0x00000001UD    { align1 1Q };
+asr(16)         g20<1>D         g2.7<0,1,0>D    0x0000001fUD    { align1 1H };
+asr.nz.f0.0(8)  null<1>D        -g0<0,1,0>W     15D             { align1 1Q };
+asr.nz.f0.0(16) null<1>D        -g0<0,1,0>W     15D             { align1 1H };
+asr(8)          g2<1>D          -g0<0,1,0>W     15D             { align1 1Q };
+asr(16)         g2<1>D          -g0<0,1,0>W     15D             { align1 1H };

diff --git a/src/intel/tools/tests/gen8/asr.expected b/src/intel/tools/tests/gen8/asr.expected
new file mode 100644 (file)
index 0000000..f1832cd
--- /dev/null
+++ b/src/intel/tools/tests/gen8/asr.expected
@@ -0,0 +1,6 @@
+0c 00 60 00 28 0a 60 22 e0 00 8d 06 01 00 00 00
+0c 00 80 00 28 0a 80 22 5c 00 00 06 1f 00 00 00
+0c 00 60 02 20 1a 00 20 00 40 00 0e 0f 00 00 00
+0c 00 80 02 20 1a 00 20 00 40 00 0e 0f 00 00 00
+0c 00 60 00 28 1a 40 20 00 40 00 0e 0f 00 00 00
+0c 00 80 00 28 1a 40 20 00 40 00 0e 0f 00 00 00

diff --git a/src/intel/tools/tests/gen8/bfe.asm b/src/intel/tools/tests/gen8/bfe.asm
new file mode 100644 (file)
index 0000000..e1113c4
--- /dev/null
+++ b/src/intel/tools/tests/gen8/bfe.asm
@@ -0,0 +1,4 @@
+bfe(8)          g34<1>UD        g89<4,4,1>UD    g30<4,4,1>UD    g91<4,4,1>UD { align16 1Q };
+bfe(16)         g13<1>UD        g44<4,4,1>UD    g115<4,4,1>UD   g126<4,4,1>UD { align16 1H };
+bfe(8)          g18<1>D         g17<4,4,1>D     g16<4,4,1>D     g49<4,4,1>D { align16 1Q };
+bfe(16)         g13<1>D         g11<4,4,1>D     g42<4,4,1>D     g5<4,4,1>D { align16 1H };

diff --git a/src/intel/tools/tests/gen8/bfe.expected b/src/intel/tools/tests/gen8/bfe.expected
new file mode 100644 (file)
index 0000000..bc933f0
--- /dev/null
+++ b/src/intel/tools/tests/gen8/bfe.expected
@@ -0,0 +1,4 @@
+18 01 60 00 00 90 1e 22 c8 91 05 39 3c 20 c7 16
+18 01 80 00 00 90 1e 0d c8 c1 02 39 e6 20 87 1f
+18 01 60 00 00 48 1e 12 c8 11 01 39 20 20 47 0c
+18 01 80 00 00 48 1e 0d c8 b1 00 39 54 20 47 01

diff --git a/src/intel/tools/tests/gen8/bfi1.asm b/src/intel/tools/tests/gen8/bfi1.asm
new file mode 100644 (file)
index 0000000..d2bfa85
--- /dev/null
+++ b/src/intel/tools/tests/gen8/bfi1.asm
@@ -0,0 +1,2 @@
+bfi1(8)         g20<1>UD        g19<8,8,1>D     g18<8,8,1>D     { align1 1Q };
+bfi1(16)        g16<1>UD        g14<8,8,1>D     g12<8,8,1>D     { align1 1H };

diff --git a/src/intel/tools/tests/gen8/bfi1.expected b/src/intel/tools/tests/gen8/bfi1.expected
new file mode 100644 (file)
index 0000000..d8b4474
--- /dev/null
+++ b/src/intel/tools/tests/gen8/bfi1.expected
@@ -0,0 +1,2 @@
+19 00 60 00 08 0a 80 22 60 02 8d 0a 40 02 8d 00
+19 00 80 00 08 0a 00 22 c0 01 8d 0a 80 01 8d 00

diff --git a/src/intel/tools/tests/gen8/bfi2.asm b/src/intel/tools/tests/gen8/bfi2.asm
new file mode 100644 (file)
index 0000000..1dadebe
--- /dev/null
+++ b/src/intel/tools/tests/gen8/bfi2.asm
@@ -0,0 +1,2 @@
+bfi2(8)         g31<1>UD        g88<4,4,1>UD    g90<4,4,1>UD    g91<4,4,1>UD { align16 1Q };
+bfi2(16)        g5<1>UD         g42<4,4,1>UD    g40<4,4,1>UD    g126<4,4,1>UD { align16 1H };

diff --git a/src/intel/tools/tests/gen8/bfi2.expected b/src/intel/tools/tests/gen8/bfi2.expected
new file mode 100644 (file)
index 0000000..61eda29
--- /dev/null
+++ b/src/intel/tools/tests/gen8/bfi2.expected
@@ -0,0 +1,2 @@
+1a 01 60 00 00 90 1e 1f c8 81 05 39 b4 20 c7 16
+1a 01 80 00 00 90 1e 05 c8 a1 02 39 50 20 87 1f

diff --git a/src/intel/tools/tests/gen8/bfrev.asm b/src/intel/tools/tests/gen8/bfrev.asm
new file mode 100644 (file)
index 0000000..44b45c5
--- /dev/null
+++ b/src/intel/tools/tests/gen8/bfrev.asm
@@ -0,0 +1,2 @@
+bfrev(8)        g5<1>UD         g5<8,8,1>UD                     { align1 1Q };
+bfrev(16)       g6<1>UD         g8<8,8,1>UD                     { align1 1H };

diff --git a/src/intel/tools/tests/gen8/bfrev.expected b/src/intel/tools/tests/gen8/bfrev.expected
new file mode 100644 (file)
index 0000000..b4d7fb0
--- /dev/null
+++ b/src/intel/tools/tests/gen8/bfrev.expected
@@ -0,0 +1,2 @@
+17 00 60 00 08 02 a0 20 a0 00 8d 00 00 00 00 00
+17 00 80 00 08 02 c0 20 00 01 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen8/break.asm b/src/intel/tools/tests/gen8/break.asm
new file mode 100644 (file)
index 0000000..093ae61
--- /dev/null
+++ b/src/intel/tools/tests/gen8/break.asm
@@ -0,0 +1,4 @@
+break(8)        JIP: 16         UIP: 64                         { align1 1Q };
+break(16)       JIP: 16         UIP: 64                         { align1 1H };
+(+f0.0) break(8) JIP: 32        UIP: 80                         { align1 1Q };
+(+f0.0) break(16) JIP: 32       UIP: 80                         { align1 1H };

diff --git a/src/intel/tools/tests/gen8/break.expected b/src/intel/tools/tests/gen8/break.expected
new file mode 100644 (file)
index 0000000..305af58
--- /dev/null
+++ b/src/intel/tools/tests/gen8/break.expected
@@ -0,0 +1,4 @@
+28 00 60 00 20 0e 00 20 40 00 00 00 10 00 00 00
+28 00 80 00 20 0e 00 20 40 00 00 00 10 00 00 00
+28 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
+28 00 81 00 20 0e 00 20 50 00 00 00 20 00 00 00

diff --git a/src/intel/tools/tests/gen8/cbit.asm b/src/intel/tools/tests/gen8/cbit.asm
new file mode 100644 (file)
index 0000000..a48d5e2
--- /dev/null
+++ b/src/intel/tools/tests/gen8/cbit.asm
@@ -0,0 +1,2 @@
+cbit(8)         g9<1>UD         g31<8,8,1>UD                    { align1 1Q };
+cbit(16)        g6<1>UD         g8<8,8,1>UD                     { align1 1H };

diff --git a/src/intel/tools/tests/gen8/cbit.expected b/src/intel/tools/tests/gen8/cbit.expected
new file mode 100644 (file)
index 0000000..8cb5ca1
--- /dev/null
+++ b/src/intel/tools/tests/gen8/cbit.expected
@@ -0,0 +1,2 @@
+4d 00 60 00 08 02 20 21 e0 03 8d 00 00 00 00 00
+4d 00 80 00 08 02 c0 20 00 01 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen8/cmp.asm b/src/intel/tools/tests/gen8/cmp.asm
new file mode 100644 (file)
index 0000000..3ed7154
--- /dev/null
+++ b/src/intel/tools/tests/gen8/cmp.asm
@@ -0,0 +1,104 @@
+cmp.z.f0.0(8)   null<1>F        g20<8,8,1>F     0xbf800000F  /* -1F */ { align1 1Q };
+cmp.nz.f0.0(8)  g59<1>DF        g2.1<0,1,0>DF   g59<4,4,1>DF    { align1 1Q };
+cmp.nz.f0.0(8)  g49<1>F         g47<8,8,1>F     g14.1<0,1,0>F   { align1 1Q };
+cmp.nz.f0.0(8)  null<1>D        g7<8,8,1>D      0D              { align1 1Q };
+cmp.z.f0.0(8)   g5<1>D          g4<8,8,1>D      g2.5<0,1,0>D    { align1 1Q };
+cmp.z.f0.0(16)  g7<1>D          g5<8,8,1>D      g2.5<0,1,0>D    { align1 1H };
+cmp.l.f0.0(16)  g35<1>F         g33<8,8,1>F     g31<8,8,1>F     { align1 1H };
+cmp.ge.f0.0(16) g37<1>F         g33<8,8,1>F     g31<8,8,1>F     { align1 1H };
+cmp.nz.f0.0(8)  g43<1>D         g42<8,8,1>D     g2.1<0,1,0>D    { align1 1Q };
+cmp.z.f0.0(8)   g32<1>DF        (abs)g6.2<0,1,0>DF g68<4,4,1>DF { align1 1Q };
+cmp.le.f0.0(8)  g108<1>D        g106<8,8,1>D    0D              { align1 1Q };
+cmp.nz.f0.0(8)  null<1>DF       g6.2<0,1,0>DF   g66<4,4,1>DF    { align1 1Q };
+cmp.l.f0.0(8)   g5<1>DF         g36<4,4,1>DF    g53<4,4,1>DF    { align1 1Q };
+cmp.ge.f0.0(8)  g18<1>DF        g36<4,4,1>DF    g53<4,4,1>DF    { align1 1Q };
+cmp.z.f0.0(8)   g34<1>DF        (abs)g106<4,4,1>DF g52<4,4,1>DF { align1 2Q };
+cmp.le.f0.0(16) g35<1>D         g21<8,8,1>D     0D              { align1 1H };
+cmp.nz.f0.0(8)  null<1>DF       g106<4,4,1>DF   g50<4,4,1>DF    { align1 2Q };
+cmp.nz.f0.0(8)  g113<1>DF       g3.1<0,1,0>DF   g59<4,4,1>DF    { align1 2Q };
+cmp.l.f0.0(8)   null<1>UD       g12<8,8,1>UD    0x00000004UD    { align1 1Q };
+cmp.l.f0.0(8)   g53<1>F         g52<8,8,1>F     g51<8,8,1>F     { align1 1Q };
+cmp.ge.f0.0(8)  g55<1>F         g52<8,8,1>F     g51<8,8,1>F     { align1 1Q };
+cmp.g.f0.0(8)   null<1>F        g14<8,8,1>F     0x3f800000F  /* 1F */ { align1 1Q };
+cmp.le.f0.0(8)  null<1>F        g4<8,8,1>F      0x3f800000F  /* 1F */ { align1 1Q };
+cmp.ge.f0.0(8)  g15<1>D         (abs)g12<8,8,1>D 1D             { align1 1Q };
+cmp.l.f0.0(8)   null<1>D        g6<0,1,0>D      2D              { align1 1Q };
+(+f0.1) cmp.z.f0.1(8) null<1>D  g3<8,8,1>D      0D              { align1 1Q };
+cmp.nz.f0.0(16) g4<1>D          g2<8,8,1>D      3D              { align1 1H };
+(+f0.1) cmp.z.f0.1(16) null<1>D g4<8,8,1>D      0D              { align1 1H };
+cmp.z.f0.0(8)   null<1>D        g22<8,8,1>D     1D              { align1 1Q };
+cmp.z.f0.0(16)  null<1>D        g55<8,8,1>D     1D              { align1 1H };
+cmp.ge.f0.0(8)  g30<1>UD        g29<8,8,1>UD    g5.7<0,1,0>UD   { align1 1Q };
+cmp.l.f0.0(8)   g31<1>UD        g29<8,8,1>UD    g5.3<0,1,0>UD   { align1 1Q };
+cmp.ge.f0.0(16) g50<1>UD        g48<8,8,1>UD    g7.7<0,1,0>UD   { align1 1H };
+cmp.l.f0.0(16)  g52<1>UD        g48<8,8,1>UD    g7.3<0,1,0>UD   { align1 1H };
+cmp.nz.f0.0(16) g12<1>F         g2.5<0,1,0>F    g1.1<0,1,0>F    { align1 1H };
+cmp.ge.f0.0(8)  null<1>D        g38<8,8,1>D     32D             { align1 1Q };
+cmp.ge.f0.0(8)  null<1>DF       g21<4,4,1>DF    g13<4,4,1>DF    { align1 1Q };
+cmp.ge.f0.0(16) g3<1>D          g1.1<0,1,0>D    g1<0,1,0>D      { align1 1H };
+cmp.l.f0.0(16)  g5<1>D          g1.1<0,1,0>D    g1<0,1,0>D      { align1 1H };
+cmp.ge.f0.0(16) null<1>D        g7<8,8,1>D      g6<0,1,0>D      { align1 1H };
+cmp.nz.f0.0(16) null<1>D        g31<8,8,1>D     0D              { align1 1H };
+cmp.z.f0.0(8)   g25<1>F         g4.3<0,1,0>F    g4.1<0,1,0>F    { align1 1Q };
+cmp.l.f0.0(8)   g33<1>D         g5<0,1,0>D      1D              { align1 1Q };
+cmp.l.f0.0(8)   g43<1>DF        g39<4,4,1>DF    g37<4,4,1>DF    { align1 2Q };
+cmp.ge.f0.0(8)  g46<1>DF        g39<4,4,1>DF    g37<4,4,1>DF    { align1 2Q };
+cmp.l.f0.0(16)  null<1>D        g6<0,1,0>D      1D              { align1 1H };
+cmp.z.f0.0(16)  g62<1>F         g12<8,8,1>F     g6.3<0,1,0>F    { align1 1H };
+cmp.nz.f0.0(8)  null<1>F        g2<0,1,0>F      0x0F  /* 0F */  { align1 1Q };
+cmp.nz.f0.0(16) null<1>F        g2<0,1,0>F      0x0F  /* 0F */  { align1 1H };
+cmp.ge.f0.0(16) null<1>UD       g5<8,8,1>UD     0x00000040UD    { align1 1H };
+cmp.z.f0.0(16)  null<1>F        g14<8,8,1>F     g6.1<0,1,0>F    { align1 1H };
+cmp.l.f0.0(16)  null<1>UD       g39<8,8,1>UD    0x00000004UD    { align1 1H };
+cmp.le.f0.0(8)  g20<1>F         g5.3<0,1,0>F    0x0F  /* 0F */  { align1 1Q };
+cmp.ge.f0.0(8)  null<1>F        (abs)g26<8,8,1>F 0x5d5e0b6bF  /* 1e+18F */ { align1 1Q };
+cmp.g.f0.0(8)   g80<1>F         (abs)g44<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
+cmp.z.f0.0(8)   g4<1>F          g13<8,4,2>F     g2.5<0,1,0>F    { align1 2Q };
+cmp.g.f0.0(16)  null<1>F        g120<8,8,1>F    0x0F  /* 0F */  { align1 1H };
+cmp.l.f0.0(8)   null<1>DF       (abs)g5<0,1,0>DF g20<4,4,1>DF   { align1 1Q };
+cmp.nz.f0.0(8)  g29<1>D         g22.1<8,4,2>D   g3.2<0,1,0>D    { align1 2Q };
+cmp.l.f0.0(8)   null<1>DF       g11<4,4,1>DF    g8<4,4,1>DF     { align1 2Q };
+cmp.nz.f0.0(8)  g73<1>F         g6.1<0,1,0>F    g14<8,4,2>F     { align1 2Q };
+cmp.g.f0.0(8)   g7<1>D          g2<0,1,0>D      0D              { align1 1Q };
+cmp.l.f0.0(8)   null<1>F        g4.4<0,1,0>F    0x0F  /* 0F */  { align1 1Q };
+cmp.l.f0.0(16)  null<1>F        g6.4<0,1,0>F    0x0F  /* 0F */  { align1 1H };
+cmp.le.f0.0(8)  g4<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1Q };
+cmp.g.f0.0(8)   g5<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1Q };
+cmp.le.f0.0(16) g5<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1H };
+cmp.g.f0.0(16)  g7<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1H };
+cmp.le.f0.0(16) null<1>F        g115<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1H };
+cmp.le.f0.0(16) g121<1>F        g27<8,8,1>F     0x461c3f9aF  /* 9999.9F */ { align1 1H };
+cmp.le.f0.0(8)  null<1>D        g8<8,8,1>D      50D             { align1 1Q };
+cmp.le.f0.0(16) null<1>D        g21<8,8,1>D     50D             { align1 1H };
+cmp.ge.f0.0(16) null<1>F        g42<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1H };
+cmp.g.f0.0(16)  g13<1>F         g11<8,8,1>F     0x3727c5acF  /* 1e-05F */ { align1 1H };
+cmp.z.f0.0(8)   g5<1>D          g14<8,4,2>D     g3.1<0,1,0>D    { align1 2Q };
+cmp.g.f0.0(8)   null<1>D        g5.2<0,1,0>D    31D             { align1 1Q };
+cmp.g.f0.0(8)   null<1>UD       g4.2<0,1,0>UD   0x0000001fUD    { align1 1Q };
+cmp.z.f0.0(16)  null<1>D        g1<8,8,1>D      1024D           { align1 2H };
+cmp.l.f0.0(16)  null<1>D        g66<8,8,1>D     32D             { align1 2H };
+cmp.nz.f0.0(8)  null<1>UD       g3<8,8,1>UD     0x00000000UD    { align1 1Q };
+cmp.nz.f0.0(16) null<1>UD       g3<8,8,1>UD     0x00000000UD    { align1 1H };
+cmp.g.f0.0(16)  null<1>D        g2.1<0,1,0>D    0D              { align1 1H };
+cmp.nz.f0.0(8)  null<1>Q        g6<4,4,1>Q      g3<4,4,1>Q      { align1 1Q };
+cmp.z.f0.0(8)   g8<1>Q          g5<4,4,1>Q      g3<4,4,1>Q      { align1 1Q };
+cmp.nz.f0.0(8)  g2<1>Q          g5<4,4,1>Q      g3<4,4,1>Q      { align1 1Q };
+cmp.nz.f0.0(8)  null<1>Q        g9<4,4,1>Q      g4<4,4,1>Q      { align1 2Q };
+cmp.z.f0.0(8)   g17<1>Q         g11<4,4,1>Q     g4<4,4,1>Q      { align1 2Q };
+cmp.nz.f0.0(8)  g20<1>Q         g11<4,4,1>Q     g4<4,4,1>Q      { align1 2Q };
+cmp.z.f0.0(8)   null<1>UD       g5<8,8,1>UD     0x00000000UD    { align1 1Q };
+cmp.z.f0.0(16)  null<1>UD       g15<8,8,1>UD    0x00000000UD    { align1 1H };
+cmp.g.f0.0(16)  g1<1>D          g8<8,8,1>D      0D              { align1 1H };
+cmp.ge.f0.0(8)  null<1>UD       g10<8,8,1>UD    g8<8,8,1>UD     { align1 1Q };
+(+f0.1) cmp.nz.f0.1(8) null<1>UW g0<8,8,1>UW    g0<8,8,1>UW     { align1 1Q };
+(+f0.1) cmp.nz.f0.1(16) null<1>UW g0<8,8,1>UW   g0<8,8,1>UW     { align1 1H };
+cmp.ge.f0.0(8)  null<1>DF       g37<4,4,1>DF    g26<4,4,1>DF    { align1 2Q };
+cmp.l.f0.0(8)   null<1>Q        g17<4,4,1>Q     g22<4,4,1>Q     { align1 1Q };
+cmp.l.f0.0(8)   null<1>Q        g2<4,4,1>Q      g8<4,4,1>Q      { align1 2Q };
+cmp.ge.f0.0(8)  null<1>Q        g17<4,4,1>Q     g24<4,4,1>Q     { align1 1Q };
+cmp.ge.f0.0(8)  null<1>Q        g2<4,4,1>Q      g8<4,4,1>Q      { align1 2Q };
+cmp.le.f0.0(8)  null<1>UD       g19<8,8,1>UD    0x000000ffUD    { align1 1Q };
+cmp.le.f0.0(16) null<1>UD       g33<8,8,1>UD    0x000000ffUD    { align1 1H };
+cmp.z.f0.0(8)   null<1>Q        g12<4,4,1>Q     g7<4,4,1>Q      { align1 1Q };
+cmp.z.f0.0(8)   null<1>Q        g26<4,4,1>Q     g12<4,4,1>Q     { align1 2Q };
+cmp.g.f0.0(16)  null<1>UD       g4.2<0,1,0>UD   0x0000001fUD    { align1 1H };

diff --git a/src/intel/tools/tests/gen8/cmp.expected b/src/intel/tools/tests/gen8/cmp.expected
new file mode 100644 (file)
index 0000000..e1d5598
--- /dev/null
+++ b/src/intel/tools/tests/gen8/cmp.expected
@@ -0,0 +1,104 @@
+10 00 60 01 e0 3a 00 20 80 02 8d 3e 00 00 80 bf
+10 00 60 02 c8 32 60 27 48 00 00 32 60 07 69 00
+10 00 60 02 e8 3a 20 26 e0 05 8d 3a c4 01 00 00
+10 00 60 02 20 0a 00 20 e0 00 8d 0e 00 00 00 00
+10 00 60 01 28 0a a0 20 80 00 8d 0a 54 00 00 00
+10 00 80 01 28 0a e0 20 a0 00 8d 0a 54 00 00 00
+10 00 80 05 e8 3a 60 24 20 04 8d 3a e0 03 8d 00
+10 00 80 04 e8 3a a0 24 20 04 8d 3a e0 03 8d 00
+10 00 60 02 28 0a 60 25 40 05 8d 0a 44 00 00 00
+10 00 60 01 c8 32 00 24 d0 20 00 32 80 08 69 00
+10 00 60 06 28 0a 80 2d 40 0d 8d 0e 00 00 00 00
+10 00 60 02 c0 32 00 20 d0 00 00 32 40 08 69 00
+10 00 60 05 c8 32 a0 20 80 04 69 32 a0 06 69 00
+10 00 60 04 c8 32 40 22 80 04 69 32 a0 06 69 00
+10 10 60 01 c8 32 40 24 40 2d 69 32 80 06 69 00
+10 00 80 06 28 0a 60 24 a0 02 8d 0e 00 00 00 00
+10 10 60 02 c0 32 00 20 40 0d 69 32 40 06 69 00
+10 10 60 02 c8 32 20 2e 68 00 00 32 60 07 69 00
+10 00 60 05 00 02 00 20 80 01 8d 06 04 00 00 00
+10 00 60 05 e8 3a a0 26 80 06 8d 3a 60 06 8d 00
+10 00 60 04 e8 3a e0 26 80 06 8d 3a 60 06 8d 00
+10 00 60 03 e0 3a 00 20 c0 01 8d 3e 00 00 80 3f
+10 00 60 06 e0 3a 00 20 80 00 8d 3e 00 00 80 3f
+10 00 60 04 28 0a e0 21 80 21 8d 0e 01 00 00 00
+10 00 60 05 20 0a 00 20 c0 00 00 0e 02 00 00 00
+10 00 61 01 21 0a 00 20 60 00 8d 0e 00 00 00 00
+10 00 80 02 28 0a 80 20 40 00 8d 0e 03 00 00 00
+10 00 81 01 21 0a 00 20 80 00 8d 0e 00 00 00 00
+10 00 60 01 20 0a 00 20 c0 02 8d 0e 01 00 00 00
+10 00 80 01 20 0a 00 20 e0 06 8d 0e 01 00 00 00
+10 00 60 04 08 02 c0 23 a0 03 8d 02 bc 00 00 00
+10 00 60 05 08 02 e0 23 a0 03 8d 02 ac 00 00 00
+10 00 80 04 08 02 40 26 00 06 8d 02 fc 00 00 00
+10 00 80 05 08 02 80 26 00 06 8d 02 ec 00 00 00
+10 00 80 02 e8 3a 80 21 54 00 00 3a 24 00 00 00
+10 00 60 04 20 0a 00 20 c0 04 8d 0e 20 00 00 00
+10 00 60 04 c0 32 00 20 a0 02 69 32 a0 01 69 00
+10 00 80 04 28 0a 60 20 24 00 00 0a 20 00 00 00
+10 00 80 05 28 0a a0 20 24 00 00 0a 20 00 00 00
+10 00 80 04 20 0a 00 20 e0 00 8d 0a c0 00 00 00
+10 00 80 02 20 0a 00 20 e0 03 8d 0e 00 00 00 00
+10 00 60 01 e8 3a 20 23 8c 00 00 3a 84 00 00 00
+10 00 60 05 28 0a 20 24 a0 00 00 0e 01 00 00 00
+10 10 60 05 c8 32 60 25 e0 04 69 32 a0 04 69 00
+10 10 60 04 c8 32 c0 25 e0 04 69 32 a0 04 69 00
+10 00 80 05 20 0a 00 20 c0 00 00 0e 01 00 00 00
+10 00 80 01 e8 3a c0 27 80 01 8d 3a cc 00 00 00
+10 00 60 02 e0 3a 00 20 40 00 00 3e 00 00 00 00
+10 00 80 02 e0 3a 00 20 40 00 00 3e 00 00 00 00
+10 00 80 04 00 02 00 20 a0 00 8d 06 40 00 00 00
+10 00 80 01 e0 3a 00 20 c0 01 8d 3a c4 00 00 00
+10 00 80 05 00 02 00 20 e0 04 8d 06 04 00 00 00
+10 00 60 06 e8 3a 80 22 ac 00 00 3e 00 00 00 00
+10 00 60 04 e0 3a 00 20 40 23 8d 3e 6b 0b 5e 5d
+10 00 60 03 e8 3a 00 2a 80 25 8d 3e 00 00 80 3f
+10 10 60 01 e8 3a 80 20 a0 01 8a 3a 54 00 00 00
+10 00 80 03 e0 3a 00 20 00 0f 8d 3e 00 00 00 00
+10 00 60 05 c0 32 00 20 a0 20 00 32 80 02 69 00
+10 10 60 02 28 0a a0 23 c4 02 8a 0a 68 00 00 00
+10 10 60 05 c0 32 00 20 60 01 69 32 00 01 69 00
+10 10 60 02 e8 3a 20 29 c4 00 00 3a c0 01 8a 00
+10 00 60 03 28 0a e0 20 40 00 00 0e 00 00 00 00
+10 00 60 05 e0 3a 00 20 90 00 00 3e 00 00 00 00
+10 00 80 05 e0 3a 00 20 d0 00 00 3e 00 00 00 00
+10 00 60 06 08 02 80 20 40 00 00 06 01 00 00 00
+10 00 60 03 08 02 a0 20 40 00 00 06 01 00 00 00
+10 00 80 06 08 02 a0 20 40 00 00 06 01 00 00 00
+10 00 80 03 08 02 e0 20 40 00 00 06 01 00 00 00
+10 00 80 06 e0 3a 00 20 60 0e 8d 3e 00 00 00 3f
+10 00 80 06 e8 3a 20 2f 60 03 8d 3e 9a 3f 1c 46
+10 00 60 06 20 0a 00 20 00 01 8d 0e 32 00 00 00
+10 00 80 06 20 0a 00 20 a0 02 8d 0e 32 00 00 00
+10 00 80 04 e0 3a 00 20 40 05 8d 3e 00 00 00 3f
+10 00 80 03 e8 3a a0 21 60 01 8d 3e ac c5 27 37
+10 10 60 01 28 0a a0 20 c0 01 8a 0a 64 00 00 00
+10 00 60 03 20 0a 00 20 a8 00 00 0e 1f 00 00 00
+10 00 60 03 00 02 00 20 88 00 00 06 1f 00 00 00
+10 20 80 01 20 0a 00 20 20 00 8d 0e 00 04 00 00
+10 20 80 05 20 0a 00 20 40 08 8d 0e 20 00 00 00
+10 00 60 02 00 02 00 20 60 00 8d 06 00 00 00 00
+10 00 80 02 00 02 00 20 60 00 8d 06 00 00 00 00
+10 00 80 03 20 0a 00 20 44 00 00 0e 00 00 00 00
+10 00 60 02 20 4b 00 20 c0 00 69 4a 60 00 69 00
+10 00 60 01 28 4b 00 21 a0 00 69 4a 60 00 69 00
+10 00 60 02 28 4b 40 20 a0 00 69 4a 60 00 69 00
+10 10 60 02 20 4b 00 20 20 01 69 4a 80 00 69 00
+10 10 60 01 28 4b 20 22 60 01 69 4a 80 00 69 00
+10 10 60 02 28 4b 80 22 60 01 69 4a 80 00 69 00
+10 00 60 01 00 02 00 20 a0 00 8d 06 00 00 00 00
+10 00 80 01 00 02 00 20 e0 01 8d 06 00 00 00 00
+10 00 80 03 28 0a 20 20 00 01 8d 0e 00 00 00 00
+10 00 60 04 00 02 00 20 40 01 8d 02 00 01 8d 00
+10 00 61 02 41 12 00 20 00 00 8d 12 00 00 8d 00
+10 00 81 02 41 12 00 20 00 00 8d 12 00 00 8d 00
+10 10 60 04 c0 32 00 20 a0 04 69 32 40 03 69 00
+10 00 60 05 20 4b 00 20 20 02 69 4a c0 02 69 00
+10 10 60 05 20 4b 00 20 40 00 69 4a 00 01 69 00
+10 00 60 04 20 4b 00 20 20 02 69 4a 00 03 69 00
+10 10 60 04 20 4b 00 20 40 00 69 4a 00 01 69 00
+10 00 60 06 00 02 00 20 60 02 8d 06 ff 00 00 00
+10 00 80 06 00 02 00 20 20 04 8d 06 ff 00 00 00
+10 00 60 01 20 4b 00 20 80 01 69 4a e0 00 69 00
+10 10 60 01 20 4b 00 20 40 03 69 4a 80 01 69 00
+10 00 80 03 00 02 00 20 88 00 00 06 1f 00 00 00

diff --git a/src/intel/tools/tests/gen8/cont.asm b/src/intel/tools/tests/gen8/cont.asm
new file mode 100644 (file)
index 0000000..c5a194b
--- /dev/null
+++ b/src/intel/tools/tests/gen8/cont.asm
@@ -0,0 +1,2 @@
+cont(8)         JIP: 16         UIP: 64                         { align1 1Q };
+cont(16)        JIP: 16         UIP: 64                         { align1 1H };

diff --git a/src/intel/tools/tests/gen8/cont.expected b/src/intel/tools/tests/gen8/cont.expected
new file mode 100644 (file)
index 0000000..83aa4f5
--- /dev/null
+++ b/src/intel/tools/tests/gen8/cont.expected
@@ -0,0 +1,2 @@
+29 00 60 00 00 0e 00 34 40 00 00 00 10 00 00 00
+29 00 80 00 00 0e 00 34 40 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen8/csel.asm b/src/intel/tools/tests/gen8/csel.asm
new file mode 100644 (file)
index 0000000..b5ec2cc
--- /dev/null
+++ b/src/intel/tools/tests/gen8/csel.asm
@@ -0,0 +1,13 @@
+csel.nz(8)      g15<1>F         g11<4,4,1>F     (abs)g11<4,4,1>F g11<4,4,1>F { align16 1Q };
+csel.nz(16)     g14<1>F         g8<4,4,1>F      (abs)g8<4,4,1>F g8<4,4,1>F { align16 1H };
+csel.le(8)      g21<1>F         (abs)g5.3<0,1,0>F g5.0<0,1,0>F  g5.3<0,1,0>F { align16 1Q };
+csel.l(8)       g107<1>F        -g101<4,4,1>F   g101<4,4,1>F    g104<4,4,1>F { align16 1Q };
+csel.le(8)      g21<1>F         g5.0<0,1,0>F    (abs)g5.1<0,1,0>F g5.1<0,1,0>F { align16 1Q };
+csel.l(8)       g127<1>F        g2<4,4,1>F      g8<4,4,1>F      g4.0<0,1,0>F { align16 1Q };
+csel.l(16)      g126<1>F        g2<4,4,1>F      g13<4,4,1>F     g6.0<0,1,0>F { align16 1H };
+csel.le(16)     g13<1>F         (abs)g73<4,4,1>F g58<4,4,1>F    g73<4,4,1>F { align16 1H };
+csel.le(16)     g15<1>F         g58<4,4,1>F     (abs)g73<4,4,1>F g73<4,4,1>F { align16 1H };
+csel.l(16)      g69<1>F         -g11<4,4,1>F    g11<4,4,1>F     g67<4,4,1>F { align16 1H };
+csel.sat.g(8)   g125<1>F        g2.3<0,1,0>F    g2.2<0,1,0>F    g2.0<0,1,0>F { align16 1Q };
+csel.g(8)       g125<1>F        g2.3<0,1,0>F    g2.2<0,1,0>F    g2.0<0,1,0>F { align16 1Q };
+csel.g(16)      g122<1>F        g2.3<0,1,0>F    g2.2<0,1,0>F    g2.0<0,1,0>F { align16 1H };

diff --git a/src/intel/tools/tests/gen8/csel.expected b/src/intel/tools/tests/gen8/csel.expected
new file mode 100644 (file)
index 0000000..6cefe9a
--- /dev/null
+++ b/src/intel/tools/tests/gen8/csel.expected
@@ -0,0 +1,13 @@
+12 01 60 02 80 00 1e 0f c8 b1 00 39 16 20 c7 02
+12 01 80 02 80 00 1e 0e c8 81 00 39 10 20 07 02
+12 01 60 06 20 00 1e 15 01 56 20 00 0a 04 58 01
+12 01 60 05 40 00 1e 6b c8 51 06 39 ca 20 07 1a
+12 01 60 06 80 00 1e 15 01 50 20 40 0a 04 48 01
+12 01 60 05 00 00 1e 7f c8 21 00 39 10 04 00 01
+12 01 80 05 00 00 1e 7e c8 21 00 39 1a 04 80 01
+12 01 80 06 20 00 1e 0d c8 91 04 39 74 20 47 12
+12 01 80 06 80 00 1e 0f c8 a1 03 39 92 20 47 12
+12 01 80 05 40 00 1e 45 c8 b1 00 39 16 20 c7 10
+12 01 60 83 00 00 1e 7d 01 26 20 80 04 04 80 00
+12 01 60 03 00 00 1e 7d 01 26 20 80 04 04 80 00
+12 01 80 03 00 00 1e 7a 01 26 20 80 04 04 80 00

diff --git a/src/intel/tools/tests/gen8/else.asm b/src/intel/tools/tests/gen8/else.asm
new file mode 100644 (file)
index 0000000..837df09
--- /dev/null
+++ b/src/intel/tools/tests/gen8/else.asm
@@ -0,0 +1,3 @@
+else(8)         JIP: 288        UIP: 288                        { align1 1Q };
+else(16)        JIP: 240        UIP: 240                        { align1 1H };
+else(32)        JIP: 144        UIP: 144                        { align1 };

diff --git a/src/intel/tools/tests/gen8/else.expected b/src/intel/tools/tests/gen8/else.expected
new file mode 100644 (file)
index 0000000..1394b46
--- /dev/null
+++ b/src/intel/tools/tests/gen8/else.expected
@@ -0,0 +1,3 @@
+24 00 60 00 20 0e 00 20 20 01 00 00 20 01 00 00
+24 00 80 00 20 0e 00 20 f0 00 00 00 f0 00 00 00
+24 00 a0 00 20 0e 00 20 90 00 00 00 90 00 00 00

diff --git a/src/intel/tools/tests/gen8/endif.asm b/src/intel/tools/tests/gen8/endif.asm
new file mode 100644 (file)
index 0000000..bfd04ea
--- /dev/null
+++ b/src/intel/tools/tests/gen8/endif.asm
@@ -0,0 +1,3 @@
+endif(8)        JIP: 80                                         { align1 1Q };
+endif(16)       JIP: 48                                         { align1 1H };
+endif(32)       JIP: 16                                         { align1 };

diff --git a/src/intel/tools/tests/gen8/endif.expected b/src/intel/tools/tests/gen8/endif.expected
new file mode 100644 (file)
index 0000000..898a148
--- /dev/null
+++ b/src/intel/tools/tests/gen8/endif.expected
@@ -0,0 +1,3 @@
+25 00 60 00 00 0e 00 00 00 00 00 08 50 00 00 00
+25 00 80 00 00 0e 00 00 00 00 00 08 30 00 00 00
+25 00 a0 00 00 0e 00 00 00 00 00 08 10 00 00 00

diff --git a/src/intel/tools/tests/gen8/fbh.asm b/src/intel/tools/tests/gen8/fbh.asm
new file mode 100644 (file)
index 0000000..fb62e76
--- /dev/null
+++ b/src/intel/tools/tests/gen8/fbh.asm
@@ -0,0 +1,2 @@
+fbh(8)          g15<1>D         g35<8,8,1>D                     { align1 1Q };
+fbh(16)         g8<1>D          g4<8,8,1>D                      { align1 1H };

diff --git a/src/intel/tools/tests/gen8/fbh.expected b/src/intel/tools/tests/gen8/fbh.expected
new file mode 100644 (file)
index 0000000..a3a1fce
--- /dev/null
+++ b/src/intel/tools/tests/gen8/fbh.expected
@@ -0,0 +1,2 @@
+4b 00 60 00 28 0a e0 21 60 04 8d 00 00 00 00 00
+4b 00 80 00 28 0a 00 21 80 00 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen8/fbl.asm b/src/intel/tools/tests/gen8/fbl.asm
new file mode 100644 (file)
index 0000000..948f70a
--- /dev/null
+++ b/src/intel/tools/tests/gen8/fbl.asm
@@ -0,0 +1,3 @@
+fbl(8)          g5<1>UD         g5<8,8,1>UD                     { align1 1Q };
+fbl(16)         g6<1>UD         g8<8,8,1>UD                     { align1 1H };
+fbl(1)          g27<1>UD        mask0<0,1,0>UD                  { align1 WE_all 1N };

diff --git a/src/intel/tools/tests/gen8/fbl.expected b/src/intel/tools/tests/gen8/fbl.expected
new file mode 100644 (file)
index 0000000..10a8948
--- /dev/null
+++ b/src/intel/tools/tests/gen8/fbl.expected
@@ -0,0 +1,3 @@
+4c 00 60 00 08 02 a0 20 a0 00 8d 00 00 00 00 00
+4c 00 80 00 08 02 c0 20 00 01 8d 00 00 00 00 00
+4c 00 00 00 0c 00 60 23 00 08 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen8/frc.asm b/src/intel/tools/tests/gen8/frc.asm
new file mode 100644 (file)
index 0000000..4ef83b8
--- /dev/null
+++ b/src/intel/tools/tests/gen8/frc.asm
@@ -0,0 +1,2 @@
+frc(8)          g28<1>F         g4<8,8,1>F                      { align1 1Q };
+frc(16)         g10<1>F         g1<0,1,0>F                      { align1 1H };

diff --git a/src/intel/tools/tests/gen8/frc.expected b/src/intel/tools/tests/gen8/frc.expected
new file mode 100644 (file)
index 0000000..302884c
--- /dev/null
+++ b/src/intel/tools/tests/gen8/frc.expected
@@ -0,0 +1,2 @@
+43 00 60 00 e8 3a 80 23 80 00 8d 00 00 00 00 00
+43 00 80 00 e8 3a 40 21 20 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen8/halt.asm b/src/intel/tools/tests/gen8/halt.asm
new file mode 100644 (file)
index 0000000..d844326
--- /dev/null
+++ b/src/intel/tools/tests/gen8/halt.asm
@@ -0,0 +1,4 @@
+(-f0.1.any4h) halt(8) JIP: 176  UIP: 192                        { align1 1Q };
+halt(8)         JIP: 16         UIP: 16                         { align1 1Q };
+(-f0.1.any4h) halt(16) JIP: 176 UIP: 192                        { align1 1H };
+halt(16)        JIP: 16         UIP: 16                         { align1 1H };

diff --git a/src/intel/tools/tests/gen8/halt.expected b/src/intel/tools/tests/gen8/halt.expected
new file mode 100644 (file)
index 0000000..4e4573d
--- /dev/null
+++ b/src/intel/tools/tests/gen8/halt.expected
@@ -0,0 +1,4 @@
+2a 00 76 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
+2a 00 60 00 20 0e 00 20 10 00 00 00 10 00 00 00
+2a 00 96 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
+2a 00 80 00 20 0e 00 20 10 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen8/if.asm b/src/intel/tools/tests/gen8/if.asm
new file mode 100644 (file)
index 0000000..5eb7b53
--- /dev/null
+++ b/src/intel/tools/tests/gen8/if.asm
@@ -0,0 +1,5 @@
+(+f0.0) if(8)   JIP: 1376       UIP: 1392                       { align1 1Q };
+(-f0.0) if(8)   JIP: 4704       UIP: 4704                       { align1 1Q };
+(-f0.0) if(16)  JIP: 64         UIP: 64                         { align1 1H };
+(+f0.0) if(16)  JIP: 96         UIP: 320                        { align1 1H };
+(+f0.0) if(32)  JIP: 80         UIP: 80                         { align1 };

diff --git a/src/intel/tools/tests/gen8/if.expected b/src/intel/tools/tests/gen8/if.expected
new file mode 100644 (file)
index 0000000..b2fc285
--- /dev/null
+++ b/src/intel/tools/tests/gen8/if.expected
@@ -0,0 +1,5 @@
+22 00 61 00 20 0e 00 20 70 05 00 00 60 05 00 00
+22 00 71 00 20 0e 00 20 60 12 00 00 60 12 00 00
+22 00 91 00 20 0e 00 20 40 00 00 00 40 00 00 00
+22 00 81 00 20 0e 00 20 40 01 00 00 60 00 00 00
+22 00 a1 00 20 0e 00 20 50 00 00 00 50 00 00 00

diff --git a/src/intel/tools/tests/gen8/lrp.asm b/src/intel/tools/tests/gen8/lrp.asm
new file mode 100644 (file)
index 0000000..d2445c6
--- /dev/null
+++ b/src/intel/tools/tests/gen8/lrp.asm
@@ -0,0 +1,5 @@
+lrp(8)          g4<1>F          g16<4,4,1>F     g7.2<0,1,0>F    g6.6<0,1,0>F { align16 1Q };
+lrp(16)         g4<1>F          g2.4<0,1,0>F    g2.2<0,1,0>F    g2.0<0,1,0>F { align16 1H };
+lrp.z.f0.0(8)   g8<1>F          g3.2<0,1,0>F    g3.1<0,1,0>F    g3.0<0,1,0>F { align16 1Q };
+lrp.sat(8)      g7<1>F          g10<4,4,1>F     g13<4,4,1>F     g16<4,4,1>F { align16 1Q };
+lrp.sat(16)     g18<1>F         g20<4,4,1>F     g26<4,4,1>F     g32<4,4,1>F { align16 1H };

diff --git a/src/intel/tools/tests/gen8/lrp.expected b/src/intel/tools/tests/gen8/lrp.expected
new file mode 100644 (file)
index 0000000..b109e92
--- /dev/null
+++ b/src/intel/tools/tests/gen8/lrp.expected
@@ -0,0 +1,5 @@
+5c 01 60 00 00 00 1e 04 c8 01 21 80 0e 04 b0 01
+5c 01 80 00 00 00 1e 04 01 28 20 80 04 04 80 00
+5c 01 60 01 00 00 1e 08 01 34 20 40 06 04 c0 00
+5c 01 60 80 00 00 1e 07 c8 a1 00 39 1a 20 07 04
+5c 01 80 80 00 00 1e 12 c8 41 01 39 34 20 07 08

diff --git a/src/intel/tools/tests/gen8/lzd.asm b/src/intel/tools/tests/gen8/lzd.asm
new file mode 100644 (file)
index 0000000..2dba1a1
--- /dev/null
+++ b/src/intel/tools/tests/gen8/lzd.asm
@@ -0,0 +1,2 @@
+lzd(8)          g25<1>UD        g3.1<0,1,0>UD                   { align1 1Q };
+lzd(16)         g27<1>UD        g3.1<0,1,0>UD                   { align1 1H };

diff --git a/src/intel/tools/tests/gen8/lzd.expected b/src/intel/tools/tests/gen8/lzd.expected
new file mode 100644 (file)
index 0000000..74afe29
--- /dev/null
+++ b/src/intel/tools/tests/gen8/lzd.expected
@@ -0,0 +1,2 @@
+4a 00 60 00 08 02 20 23 64 00 00 00 00 00 00 00
+4a 00 80 00 08 02 60 23 64 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen8/mach.asm b/src/intel/tools/tests/gen8/mach.asm
new file mode 100644 (file)
index 0000000..9ddbe0b
--- /dev/null
+++ b/src/intel/tools/tests/gen8/mach.asm
@@ -0,0 +1,4 @@
+mach(8)         g19<1>UD        g17<8,8,1>UD    0xaaaaaaabUD    { align1 1Q AccWrEnable };
+mach(8)         g23<1>D         g17<8,8,1>D     1431655766D     { align1 1Q AccWrEnable };
+mach(8)         g50<1>UD        g47<8,8,1>UD    0xaaaaaaabUD    { align1 2Q AccWrEnable };
+mach(8)         g58<1>D         g47<8,8,1>D     1431655766D     { align1 2Q AccWrEnable };

diff --git a/src/intel/tools/tests/gen8/mach.expected b/src/intel/tools/tests/gen8/mach.expected
new file mode 100644 (file)
index 0000000..a14964a
--- /dev/null
+++ b/src/intel/tools/tests/gen8/mach.expected
@@ -0,0 +1,4 @@
+49 00 60 10 08 02 60 22 20 02 8d 06 ab aa aa aa
+49 00 60 10 28 0a e0 22 20 02 8d 0e 56 55 55 55
+49 10 60 10 08 02 40 26 e0 05 8d 06 ab aa aa aa
+49 10 60 10 28 0a 40 27 e0 05 8d 0e 56 55 55 55

diff --git a/src/intel/tools/tests/gen8/mad.asm b/src/intel/tools/tests/gen8/mad.asm
new file mode 100644 (file)
index 0000000..d399595
--- /dev/null
+++ b/src/intel/tools/tests/gen8/mad.asm
@@ -0,0 +1,43 @@
+mad(8)          g26<1>F         g22<4,4,1>F     g2.4<0,1,0>F    g5<4,4,1>F { align16 1Q };
+mad(16)         g21<1>F         g19<4,4,1>F     g11<4,4,1>F     g11<4,4,1>F { align16 1H };
+mad(8)          g64<1>DF        g62<4,4,1>DF    g40<4,4,1>DF    g92<4,4,1>DF { align16 1Q };
+mad(8)          g74<1>DF        -g50<4,4,1>DF   g24<4,4,1>DF    g74<4,4,1>DF { align16 1Q };
+mad(8)          g27<1>DF        g48<4,4,1>DF    g106<4,4,1>DF   g25<4,4,1>DF { align16 2Q };
+mad(8)          g29<1>DF        g23<4,4,1>DF    g27<4,4,1>DF    -g25<4,4,1>DF { align16 1Q };
+mad(16)         g15<1>F         -g2.6<0,1,0>F   g13<4,4,1>F     g1.0<0,1,0>F { align16 1H };
+mad(8)          g124<1>F        -g15.0<0,1,0>F  g14<4,4,1>F     g15.1<0,1,0>F { align16 1Q };
+mad(8)          g124<1>F        g15.0<0,1,0>F   g14<4,4,1>F     -g15.1<0,1,0>F { align16 1Q };
+mad.le.f0.0(8)  g9<1>F          g3<4,4,1>F      g4.2<0,1,0>F    g15<4,4,1>F { align16 1Q };
+mad.le.f0.0(16) g15<1>F         g4<4,4,1>F      g6.2<0,1,0>F    g24<4,4,1>F { align16 1H };
+mad(16)         g56<1>F         g54<4,4,1>F     g2.3<0,1,0>F    -g5<4,4,1>F { align16 1H };
+mad.sat(8)      g12<1>F         g4.1<0,1,0>F    g4.0<0,1,0>F    g13<4,4,1>F { align16 1Q };
+mad.sat(16)     g18<1>F         g6.1<0,1,0>F    g6.0<0,1,0>F    g10<4,4,1>F { align16 1H };
+mad(8)          g86<1>F         g88.6<0,1,0>F   -g88.7<0,1,0>F  g77<4,4,1>F { align16 1Q };
+mad(8)          g85<1>DF        g28<4,4,1>DF    g26<4,4,1>DF    -g81<4,4,1>DF { align16 2Q };
+mad(8)          g11<1>F         -g2.0<0,1,0>F   g10<4,4,1>F     (abs)g5.6<0,1,0>F { align16 1Q };
+mad(8)          g15<1>F         g2.1<0,1,0>F    g11<4,4,1>F     (abs)g5.6<0,1,0>F { align16 1Q };
+mad.l.f0.0(8)   g2<1>F          g22<4,4,1>F     g5.7<0,1,0>F    g6.3<0,1,0>F { align16 1Q };
+mad(8)          g79<1>DF        -g39<4,4,1>DF   g21<4,4,1>DF    g79<4,4,1>DF { align16 2Q };
+mad(8)          g117<1>F        -g116<4,4,1>F   g9.0<0,1,0>F    -g113<4,4,1>F { align16 1Q };
+mad.ge.f0.0(8)  g13<1>F         g28.0<0,1,0>F   g9<4,4,1>F      -g2.4<0,1,0>F { align16 1Q };
+mad.ge.f0.0(16) g23<1>F         g17.0<0,1,0>F   g6<4,4,1>F      -g3.0<0,1,0>F { align16 1H };
+mad(8)          g26<1>F         g2.0<0,1,0>F    -g2.1<0,1,0>F   (abs)g5.6<0,1,0>F { align16 1Q };
+mad(8)          g70<1>F         -g13<4,4,1>F    -g2.1<0,1,0>F   -g47<4,4,1>F { align16 1Q };
+mad(16)         g95<1>F         -g93<4,4,1>F    g85<4,4,1>F     -g85<4,4,1>F { align16 1H };
+mad(16)         g5<1>F          -g21<4,4,1>F    -g2.1<0,1,0>F   -g85<4,4,1>F { align16 1H };
+mad(16)         g56<1>F         g6.4<0,1,0>F    -g6.5<0,1,0>F   g51<4,4,1>F { align16 1H };
+mad.sat(8)      g124<1>F        -g7<4,4,1>F     g2.6<0,1,0>F    g2.1<0,1,0>F { align16 1Q };
+mad(16)         g28<1>F         g58.0<0,1,0>F   -g58.1<0,1,0>F  (abs)g1.0<0,1,0>F { align16 1H };
+mad(16)         g34<1>F         -g58.2<0,1,0>F  g28<4,4,1>F     (abs)g1.0<0,1,0>F { align16 1H };
+mad(16)         g40<1>F         g58.3<0,1,0>F   g34<4,4,1>F     (abs)g1.0<0,1,0>F { align16 1H };
+mad(8)          g43<1>DF        g42<4,4,1>DF    -g34<4,4,1>DF   g7<4,4,1>DF { align16 1Q };
+mad(8)          g3<1>DF         g2<4,4,1>DF     -g111<4,4,1>DF  g39<4,4,1>DF { align16 2Q };
+mad(8)          g2<1>F          -g2<4,4,1>F     (abs)g7<4,4,1>F g8.0<0,1,0>F { align16 1Q };
+mad(16)         g2<1>F          -g10<4,4,1>F    (abs)g19<4,4,1>F g28.0<0,1,0>F { align16 1H };
+mad.sat(8)      g125<1>F        g9<4,4,1>F      g6<4,4,1>F      -g64.0<0,1,0>F { align16 1Q };
+mad.l.f0.0(16)  g5<1>F          g9<4,4,1>F      g2.7<0,1,0>F    g3.3<0,1,0>F { align16 1H };
+mad(8)          g6<1>DF         -g55<4,4,1>DF   g2<4,4,1>DF     -g47<4,4,1>DF { align16 1Q };
+mad.z.f0.0(8)   g8<1>F          g3.2<0,1,0>F    g3.1<0,1,0>F    g3.0<0,1,0>F { align16 1Q };
+mad(8)          g63<1>DF        -g48<4,4,1>DF   g56<4,4,1>DF    -g44<4,4,1>DF { align16 2Q };
+mad.nz.f0.0(8)  g10<1>F         -g12.0<0,1,0>F  g7<4,4,1>F      g10<4,4,1>F { align16 1Q };
+mad.nz.f0.0(16) g15<1>F         -g33.0<0,1,0>F  g9<4,4,1>F      g17<4,4,1>F { align16 1H };

diff --git a/src/intel/tools/tests/gen8/mad.expected b/src/intel/tools/tests/gen8/mad.expected
new file mode 100644 (file)
index 0000000..9f9cd7e
--- /dev/null
+++ b/src/intel/tools/tests/gen8/mad.expected
@@ -0,0 +1,43 @@
+5b 01 60 00 00 00 1e 1a c8 61 21 00 05 20 47 01
+5b 01 80 00 00 00 1e 15 c8 31 01 39 16 20 c7 02
+5b 01 60 00 00 d8 1e 40 c8 e1 03 39 50 20 07 17
+5b 01 60 00 40 d8 1e 4a c8 21 03 39 30 20 87 12
+5b 11 60 00 00 d8 1e 1b c8 01 03 39 d4 20 47 06
+5b 01 60 00 00 dc 1e 1d c8 71 01 39 36 20 47 06
+5b 01 80 00 40 00 1e 0f 01 2c 00 39 1a 04 40 00
+5b 01 60 00 40 00 1e 7c 01 f0 00 39 1c 04 c8 03
+5b 01 60 00 00 04 1e 7c 01 f0 00 39 1c 04 c8 03
+5b 01 60 06 00 00 1e 09 c8 31 20 80 08 20 c7 03
+5b 01 80 06 00 00 1e 0f c8 41 20 80 0c 20 07 06
+5b 01 80 00 00 04 1e 38 c8 61 23 c0 04 20 47 01
+5b 01 60 80 00 00 1e 0c 01 42 20 00 08 20 47 03
+5b 01 80 80 00 00 1e 12 01 62 20 00 0c 20 87 02
+5b 01 60 00 00 01 1e 56 01 8c 25 c0 b1 20 47 13
+5b 11 60 00 00 dc 1e 55 c8 c1 01 39 34 20 47 14
+5b 01 60 00 40 02 1e 0b 01 20 00 39 14 04 70 01
+5b 01 60 00 00 02 1e 0f 01 22 00 39 16 04 70 01
+5b 01 60 05 00 00 1e 02 c8 61 21 c0 0b 04 98 01
+5b 11 60 00 40 d8 1e 4f c8 71 02 39 2a 20 c7 13
+5b 01 60 00 40 04 1e 75 c8 41 27 00 12 20 47 1c
+5b 01 60 04 00 04 1e 0d 01 c0 01 39 12 04 a0 00
+5b 01 80 04 00 04 1e 17 01 10 01 39 0c 04 c0 00
+5b 01 60 00 00 03 1e 1a 01 20 20 40 04 04 70 01
+5b 01 60 00 40 05 1e 46 c8 d1 20 40 04 20 c7 0b
+5b 01 80 00 40 04 1e 5f c8 d1 05 39 aa 20 47 15
+5b 01 80 00 40 05 1e 05 c8 51 21 40 04 20 47 15
+5b 01 80 00 00 01 1e 38 01 68 20 40 0d 20 c7 0c
+5b 01 60 80 40 00 1e 7c c8 71 20 80 05 04 88 00
+5b 01 80 00 00 03 1e 1c 01 a0 23 40 74 04 40 00
+5b 01 80 00 40 02 1e 22 01 a4 03 39 38 04 40 00
+5b 01 80 00 00 02 1e 28 01 a6 03 39 44 04 40 00
+5b 01 60 00 00 d9 1e 2b c8 a1 02 39 44 20 c7 01
+5b 11 60 00 00 d9 1e 03 c8 21 00 39 de 20 c7 09
+5b 01 60 00 c0 00 1e 02 c8 21 00 39 0e 04 00 02
+5b 01 80 00 c0 00 1e 02 c8 a1 00 39 26 04 00 07
+5b 01 60 80 00 04 1e 7d c8 91 00 39 0c 04 00 10
+5b 01 80 05 00 00 1e 05 c8 91 20 c0 05 04 d8 00
+5b 01 60 00 40 dc 1e 06 c8 71 03 39 04 20 c7 0b
+5b 01 60 01 00 00 1e 08 01 34 20 40 06 04 c0 00
+5b 11 60 00 40 dc 1e 3f c8 01 03 39 70 20 07 0b
+5b 01 60 02 40 00 1e 0a 01 c0 00 39 0e 20 87 02
+5b 01 80 02 40 00 1e 0f 01 10 02 39 12 20 47 04

diff --git a/src/intel/tools/tests/gen8/math.asm b/src/intel/tools/tests/gen8/math.asm
new file mode 100644 (file)
index 0000000..f0e74df
--- /dev/null
+++ b/src/intel/tools/tests/gen8/math.asm
@@ -0,0 +1,31 @@
+math sqrt(16)   g27<1>F         g25<8,8,1>F     null<8,8,1>F    { align1 1H };
+math inv(8)     g95<1>F         g94<8,8,1>F     null<8,8,1>F    { align1 1Q };
+math inv(16)    g10<1>F         g8<8,8,1>F      null<8,8,1>F    { align1 1H };
+math intmod(8)  g3<1>UD         g1<0,1,0>UD     g1.2<0,1,0>UD   { align1 1Q };
+math intmod(8)  g4<1>UD         g1<0,1,0>UD     g1.2<0,1,0>UD   { align1 2Q };
+math sqrt(8)    g24<1>F         g23<8,8,1>F     null<8,8,1>F    { align1 1Q };
+math rsq(8)     g5<1>F          g2<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math pow(8)     g20<1>F         g14<8,8,1>F     0x42fc6666F  /* 126.2F */ { align1 1Q };
+math pow(16)    g26<1>F         g24<8,8,1>F     0x42fc6666F  /* 126.2F */ { align1 1H };
+math log(8)     g7<1>F          g6<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math log(16)    g11<1>F         g9<8,8,1>F      null<8,8,1>F    { align1 1H };
+math cos(8)     g3<1>F          g2<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math cos(16)    g4<1>F          g2<8,8,1>F      null<8,8,1>F    { align1 1H };
+math intdiv(8)  g11<1>UD        g1<0,1,0>UD     g1.4<0,1,0>UD   { align1 1Q };
+math intdiv(8)  g12<1>UD        g1<0,1,0>UD     g1.4<0,1,0>UD   { align1 2Q };
+math intdiv(8)  g24<1>D         g4<0,1,0>D      g2.2<0,1,0>D    { align1 1Q };
+math sin(8)     g10<1>F         g9<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math rsq(16)    g68<1>F         g66<8,8,1>F     null<8,8,1>F    { align1 1H };
+math exp(8)     g124<1>F        g10<8,8,1>F     null<8,8,1>F    { align1 1Q };
+math exp(16)    g120<1>F        g7<8,8,1>F      null<8,8,1>F    { align1 1H };
+math intdiv(8)  g5<1>D          g2<0,1,0>D      g2.4<0,1,0>D    { align1 2Q };
+math sin(16)    g3<1>F          g2<0,1,0>F      null<8,8,1>F    { align1 1H };
+math.sat pow(8) g3<1>F          g2<0,1,0>F      g2.4<0,1,0>F    { align1 1Q };
+math.sat pow(16) g3<1>F         g2<0,1,0>F      g2.4<0,1,0>F    { align1 1H };
+math.sat sqrt(8) g3<1>F         g2<0,1,0>F      null<8,8,1>F    { align1 1Q };
+math.sat sqrt(16) g3<1>F        g2<0,1,0>F      null<8,8,1>F    { align1 1H };
+math.sat exp(8) g3<1>F          g2<0,1,0>F      null<8,8,1>F    { align1 1Q };
+math.sat exp(16) g3<1>F         g2<0,1,0>F      null<8,8,1>F    { align1 1H };
+math.sat rsq(8) g127<1>F        (abs)g7<8,8,1>F null<8,8,1>F    { align1 1Q };
+math.sat inv(8) g124<1>F        g2<0,1,0>F      null<8,8,1>F    { align1 1Q };
+math.sat log(8) g127<1>F        g7<8,8,1>F      null<8,8,1>F    { align1 1Q };

diff --git a/src/intel/tools/tests/gen8/math.expected b/src/intel/tools/tests/gen8/math.expected
new file mode 100644 (file)
index 0000000..27f38c3
--- /dev/null
+++ b/src/intel/tools/tests/gen8/math.expected
@@ -0,0 +1,31 @@
+38 00 80 04 e8 3a 60 23 20 03 8d 38 00 00 8d 00
+38 00 60 01 e8 3a e0 2b c0 0b 8d 38 00 00 8d 00
+38 00 80 01 e8 3a 40 21 00 01 8d 38 00 00 8d 00
+38 00 60 0d 08 02 60 20 20 00 00 02 28 00 00 00
+38 10 60 0d 08 02 80 20 20 00 00 02 28 00 00 00
+38 00 60 04 e8 3a 00 23 e0 02 8d 38 00 00 8d 00
+38 00 60 05 e8 3a a0 20 40 00 8d 38 00 00 8d 00
+38 00 60 0a e8 3a 80 22 c0 01 8d 3e 66 66 fc 42
+38 00 80 0a e8 3a 40 23 00 03 8d 3e 66 66 fc 42
+38 00 60 02 e8 3a e0 20 c0 00 8d 38 00 00 8d 00
+38 00 80 02 e8 3a 60 21 20 01 8d 38 00 00 8d 00
+38 00 60 07 e8 3a 60 20 40 00 8d 38 00 00 8d 00
+38 00 80 07 e8 3a 80 20 40 00 8d 38 00 00 8d 00
+38 00 60 0c 08 02 60 21 20 00 00 02 30 00 00 00
+38 10 60 0c 08 02 80 21 20 00 00 02 30 00 00 00
+38 00 60 0c 28 0a 00 23 80 00 00 0a 48 00 00 00
+38 00 60 06 e8 3a 40 21 20 01 8d 38 00 00 8d 00
+38 00 80 05 e8 3a 80 28 40 08 8d 38 00 00 8d 00
+38 00 60 03 e8 3a 80 2f 40 01 8d 38 00 00 8d 00
+38 00 80 03 e8 3a 00 2f e0 00 8d 38 00 00 8d 00
+38 10 60 0c 28 0a a0 20 40 00 00 0a 50 00 00 00
+38 00 80 06 e8 3a 60 20 40 00 00 38 00 00 8d 00
+38 00 60 8a e8 3a 60 20 40 00 00 3a 50 00 00 00
+38 00 80 8a e8 3a 60 20 40 00 00 3a 50 00 00 00
+38 00 60 84 e8 3a 60 20 40 00 00 38 00 00 8d 00
+38 00 80 84 e8 3a 60 20 40 00 00 38 00 00 8d 00
+38 00 60 83 e8 3a 60 20 40 00 00 38 00 00 8d 00
+38 00 80 83 e8 3a 60 20 40 00 00 38 00 00 8d 00
+38 00 60 85 e8 3a e0 2f e0 20 8d 38 00 00 8d 00
+38 00 60 81 e8 3a 80 2f 40 00 00 38 00 00 8d 00
+38 00 60 82 e8 3a e0 2f e0 00 8d 38 00 00 8d 00

diff --git a/src/intel/tools/tests/gen8/mov.asm b/src/intel/tools/tests/gen8/mov.asm
new file mode 100644 (file)
index 0000000..6d1485b
--- /dev/null
+++ b/src/intel/tools/tests/gen8/mov.asm
@@ -0,0 +1,145 @@
+mov(8)          g123<1>UD       g1<8,8,1>UD                     { align1 WE_all 1Q };
+mov(8)          g124<1>F        0x40c00000F      /* 6F */       { align1 1Q };
+mov(8)          g14<1>UD        0x00000000UD                    { align1 1Q };
+mov(8)          g17<1>F         g12<8,8,1>F                     { align1 1Q };
+mov.sat(8)      g124<1>F        g8<8,8,1>F                      { align1 1Q };
+mov(8)          g61<2>D         g22<8,8,1>D                     { align1 1Q };
+mov(8)          g21<1>D         g59<8,4,2>UD                    { align1 1Q };
+mov(8)          g4<1>D          -1D                             { align1 1Q };
+mov.nz.f0.0(8)  null<1>D        g4<8,8,1>D                      { align1 1Q };
+mov(1)          g2.2<1>UD       0x00000000UD                    { align1 WE_all 1N };
+mov(4)          g114<1>F        g2.3<8,2,4>F                    { align1 WE_all 1N };
+mov(8)          g125<1>F        -g7<8,8,1>D                     { align1 1Q };
+mov(16)         g124<1>F        0x0F             /* 0F */       { align1 1H };
+mov(16)         g122<1>F        -g11<8,8,1>D                    { align1 1H };
+mov(16)         g124<1>D        1065353216D                     { align1 1H };
+mov.nz.f0.0(16) null<1>D        g2<0,1,0>D                      { align1 1H };
+mov(8)          g10<1>UW        0x76543210V                     { align1 WE_all 1Q };
+mov(16)         g27<1>UD        g0.1<0,1,0>UD                   { align1 1H };
+mov(8)          g3<1>UD         0D                              { align1 WE_all 1Q };
+mov(1)          g3.7<1>UD       -1D                             { align1 WE_all 1N };
+mov(16)         g13<1>D         g10<8,8,1>UW                    { align1 1H };
+mov(8)          g1<1>UD         0D                              { align1 WE_all 2Q };
+mov(8)          g2<1>D          g15<8,8,1>D                     { align1 2Q };
+mov(8)          g6<1>D          0D                              { align1 2Q };
+mov(1)          g1.7<1>UD       -1D                             { align1 WE_all 3N };
+mov(8)          g2<1>F          g6<8,4,1>UW                     { align1 1Q };
+mov(8)          g7<1>D          g2<8,8,1>F                      { align1 1Q };
+mov(16)         g16<1>F         g9.3<0,1,0>F                    { align1 1H };
+mov(16)         g25<1>F         g18<8,4,1>UW                    { align1 1H };
+mov(16)         g19<1>D         g25<8,8,1>F                     { align1 1H };
+mov(8)          g74<1>DF        g5<0,1,0>DF                     { align1 1Q };
+mov(8)          g92<2>UD        g6.4<0,1,0>UD                   { align1 1Q };
+mov(8)          g62<1>Q         0xbff0000000000000Q             { align1 1Q };
+mov(8)          g92<2>F         g92<4,4,1>DF                    { align1 1Q };
+mov(8)          g92<1>DF        g95<4,4,1>F                     { align1 1Q };
+mov(8)          g106<1>DF       g2<0,1,0>F                      { align1 2Q };
+mov(8)          g48<1>Q         0xbff0000000000000Q             { align1 2Q };
+mov(8)          g127<1>UD       g106.1<8,4,2>UD                 { align1 2Q };
+mov(8)          g11<2>F         g7<4,4,1>DF                     { align1 2Q };
+mov(8)          g33<1>D         g34<8,4,2>UD                    { align1 2Q };
+mov(8)          g6<2>UD         0x00000000UD                    { align1 2Q };
+mov(8)          g2<1>UW         0x76543210UV                    { align1 1Q };
+mov(8)          g12<1>UD        g2<8,8,1>UW                     { align1 1Q };
+mov(8)          g7<1>UD         0x00080000UD                    { align1 WE_all 1Q };
+mov(1)          g2<1>F          0x3e800000F      /* 0.25F */    { align1 WE_all 1N };
+mov(8)          g15<1>F         g26<8,8,1>UD                    { align1 1Q };
+mov(1)          f0.1<1>UW       g1.14<0,1,0>UW                  { align1 WE_all 1N };
+mov(8)          g18<1>UD        g2<8,8,1>D                      { align1 1Q };
+mov(16)         g18<1>UD        g26<8,8,1>D                     { align1 1H };
+mov(16)         g120<1>D        g34<8,8,1>D                     { align1 1H };
+mov(8)          g8<1>Q          g13<4,4,1>Q                     { align1 1Q };
+mov(8)          g21<1>UD        g0<8,8,1>UD                     { align1 WE_all 2Q };
+mov(8)          g23<1>F         g6<0,1,0>F                      { align1 2Q };
+mov(1)          g21.2<1>UD      0x000003f2UD                    { align1 WE_all 3N };
+mov.nz.f0.0(8)  g19<1>D         g3<8,4,2>UD                     { align1 1Q };
+mov(8)          g3<1>UD         0D                              { align1 1Q };
+mov(16)         g4<1>UD         0D                              { align1 1H };
+mov(1)          f1<1>UD         g1.7<0,1,0>UD                   { align1 WE_all 1N };
+mov.sat(8)      g126<1>F        0x0F             /* 0F */       { align1 1Q };
+mov.sat(8)      g124<1>F        -g36<8,8,1>D                    { align1 1Q };
+mov(16)         g86<1>UD        g88<8,8,1>UD                    { align1 WE_all 1H };
+mov.sat(16)     g120<1>F        g2<0,1,0>F                      { align1 1H };
+mov(16)         g2<1>F          g18<8,8,1>UD                    { align1 1H };
+mov(8)          g4<1>UD         0x0F             /* 0F */       { align1 1Q };
+mov(8)          g8<1>DF         g2<0,1,0>D                      { align1 1Q };
+mov(16)         g5<1>UD         0x00000000UD                    { align1 1H };
+mov.nz.f0.0(8)  g4<1>F          -(abs)g2<0,1,0>F                { align1 1Q };
+(+f0.0) mov(8)  g4<1>F          0xbf800000F      /* -1F */      { align1 1Q };
+mov.nz.f0.0(16) g4<1>F          -(abs)g2<0,1,0>F                { align1 1H };
+(+f0.0) mov(16) g4<1>F          0xbf800000F      /* -1F */      { align1 1H };
+mov(1)          g14.7<1>UD      g1.7<0,1,0>UD                   { align1 WE_all 1N };
+mov(1)          g7.7<1>UD       g1.7<0,1,0>UD                   { align1 WE_all 3N };
+mov(8)          g32<1>DF        g2<0,1,0>DF                     { align1 2Q };
+mov(8)          g5<1>F          g2<0,1,0>HF                     { align1 1Q };
+mov(16)         g6<1>F          g2<0,1,0>HF                     { align1 1H };
+mov(8)          g7<1>UD         g2<0,1,0>F                      { align1 1Q };
+mov(8)          g123<1>UW       g2<16,8,2>UW                    { align1 WE_all 1Q };
+mov(16)         g119<1>UW       g2<16,8,2>UW                    { align1 WE_all 1H };
+mov(16)         g15<1>UD        g11<8,8,1>F                     { align1 1H };
+mov(16)         g19<1>UD        g15<16,8,2>UW                   { align1 1H };
+mov(8)          g7<1>D          0x00000000UD                    { align1 1Q };
+mov(16)         g75<1>D         0x00000000UD                    { align1 1H };
+mov(16)         g79<1>D         g18<8,8,1>UD                    { align1 1H };
+mov(16)         g29<1>UD        g27<32,8,4>UB                   { align1 1H };
+mov(8)          g7<1>DF         0x0000000000000000DF /* 0DF */  { align1 1Q };
+mov(8)          g14<1>F         0x3f000000F      /* 0.5F */     { align1 2Q };
+mov(8)          g5<1>F          0x0F             /* 0F */       { align1 WE_all 1Q };
+mov(16)         g4<1>UD         0x00000000UD                    { align1 WE_all 1H };
+mov(8)          g5<2>UD         g2<0,1,0>DF                     { align1 1Q };
+mov(8)          g10<2>UD        g2<0,1,0>DF                     { align1 2Q };
+mov(8)          g3<1>DF         g2<0,1,0>UD                     { align1 1Q };
+mov(8)          g3<1>DF         g2<0,1,0>UD                     { align1 2Q };
+mov(1)          f0<1>UW         0x0000UW                        { align1 WE_all 1N };
+mov(1)          g1<1>D          0D                              { align1 WE_all 1N };
+(+f0.0.any16h) mov(1) g1<1>D    -1D                             { align1 WE_all 1N };
+mov(8)          g9<1>F          g2<0,1,0>W                      { align1 1Q };
+mov(8)          g7<1>UQ         g4<4,4,1>UQ                     { align1 1Q };
+mov(16)         g11<1>UD        0x0F             /* 0F */       { align1 1H };
+mov(8)          g5<2>D          g2<0,1,0>DF                     { align1 1Q };
+mov(8)          g10<2>D         g2<0,1,0>DF                     { align1 2Q };
+mov(1)          g24.7<1>UD      f0.1<0,1,0>UW                   { align1 WE_all 1N };
+mov(1)          g2.7<1>UD       f0.1<0,1,0>UW                   { align1 WE_all 3N };
+mov(16)         g6<1>D          0D                              { align1 2H };
+mov(8)          g14<1>UD        g13<32,8,4>UB                   { align1 1Q };
+mov(16)         g38<1>D         g2<8,8,1>UW                     { align1 2H };
+mov(16)         g124<1>UD       g44<8,8,1>UD                    { align1 2H };
+mov(16)         g4<1>UD         0x00000001UD                    { align1 2H };
+mov(1)          g4<2>UW         0x00000000UD                    { align1 WE_all 1N };
+mov(8)          g4<1>UD         f0<0,1,0>UW                     { align1 1Q };
+mov(8)          g8<1>D          g2<8,8,1>UW                     { align1 1Q };
+mov(16)         g4<1>UD         f0<0,1,0>UW                     { align1 1H };
+mov(8)          g3<1>DF         -g2<0,1,0>D                     { align1 2Q };
+mov(8)          g5<1>F          g2<0,1,0>B                      { align1 1Q };
+mov(16)         g6<1>F          g2<0,1,0>B                      { align1 1H };
+mov(8)          g4<1>DF         0x0000000000000000DF /* 0DF */  { align1 2Q };
+mov.nz.f0.0(8)  g16<1>D         g17<8,4,2>UD                    { align1 2Q };
+mov(8)          g34<1>UW        0x76543210V                     { align1 1Q };
+mov(8)          g7<2>HF         g2.1<0,1,0>F                    { align1 1Q };
+mov(1)          g5<1>D          g[a0 96]<0,1,0>D                { align1 WE_all 1N };
+mov(1)          f1<1>UW         f0.1<0,1,0>UW                   { align1 WE_all 1N };
+(+f0.0.any8h) mov(1) g2<1>D     -1D                             { align1 WE_all 1N };
+mov(8)          g2<2>UW         g9<8,8,1>F                      { align1 1Q };
+mov(8)          g3<1>UW         g2<16,8,2>UW                    { align1 1Q };
+mov.sat(16)     g13<1>F         0x3f800000F      /* 1F */       { align1 1H };
+mov(16)         g19<2>UW        g17<8,8,1>F                     { align1 1H };
+mov.nz.f0.0(8)  null<1>D        0x00000000UD                    { align1 1Q };
+mov.nz.f0.0(16) null<1>D        0x00000000UD                    { align1 1H };
+mov(4)          g3<1>UD         tm0<4,4,1>UD                    { align1 WE_all 1N };
+(+f0.0.all16h) mov(1) g1<1>D    -1D                             { align1 WE_all 1N };
+mov(8)          g9<1>F          g2<0,1,0>UB                     { align1 1Q };
+mov(16)         g6<1>F          g2<0,1,0>UB                     { align1 1H };
+mov(16)         g10<2>HF        g4<8,8,1>F                      { align1 1H };
+mov.z.f0.0(8)   null<1>UD       g2<8,8,1>UD                     { align1 1Q };
+mov.sat(8)      g125<1>F        g9<8,8,1>UD                     { align1 1Q };
+mov.z.f0.0(16)  g1<1>UD         g0.7<0,1,0>UD                   { align1 1H };
+mov.z.f0.0(8)   g18<1>D         g17<8,8,1>F                     { align1 1Q };
+mov(8)          g2<1>D          g12<16,8,2>W                    { align1 1Q };
+mov(16)         g40<1>D         g18<16,8,2>W                    { align1 1H };
+mov(8)          g2<1>D          g12<32,8,4>B                    { align1 1Q };
+mov(16)         g40<1>D         g18<32,8,4>B                    { align1 1H };
+mov(16)         g42<1>F         g4<16,8,2>W                     { align1 1H };
+mov(8)          g23<1>Q         g26<4,4,1>Q                     { align1 2Q };
+(+f0.0.all8h) mov(1) g7<1>D     -1D                             { align1 WE_all 1N };
+mov.z.f0.0(8)   null<1>D        g21<8,8,1>F                     { align1 1Q };
+mov.z.f0.0(16)  null<1>D        g65<8,8,1>F                     { align1 1H };

diff --git a/src/intel/tools/tests/gen8/mov.expected b/src/intel/tools/tests/gen8/mov.expected
new file mode 100644 (file)
index 0000000..c14c348
--- /dev/null
+++ b/src/intel/tools/tests/gen8/mov.expected
@@ -0,0 +1,145 @@
+01 00 60 00 0c 02 60 2f 20 00 8d 00 00 00 00 00
+01 00 60 00 e8 3e 80 2f 00 00 00 38 00 00 c0 40
+01 00 60 00 08 06 c0 21 00 00 00 00 00 00 00 00
+01 00 60 00 e8 3a 20 22 80 01 8d 00 00 00 00 00
+01 00 60 80 e8 3a 80 2f 00 01 8d 00 00 00 00 00
+01 00 60 00 28 0a a0 47 c0 02 8d 00 00 00 00 00
+01 00 60 00 28 02 a0 22 60 07 8a 00 00 00 00 00
+01 00 60 00 28 0e 80 20 00 00 00 08 ff ff ff ff
+01 00 60 02 20 0a 00 20 80 00 8d 00 00 00 00 00
+01 00 00 00 0c 06 48 20 00 00 00 00 00 00 00 00
+01 00 40 00 ec 3a 40 2e 4c 00 87 00 00 00 00 00
+01 00 60 00 e8 0a a0 2f e0 40 8d 00 00 00 00 00
+01 00 80 00 e8 3e 80 2f 00 00 00 38 00 00 00 00
+01 00 80 00 e8 0a 40 2f 60 41 8d 00 00 00 00 00
+01 00 80 00 28 0e 80 2f 00 00 00 08 00 00 80 3f
+01 00 80 02 20 0a 00 20 40 00 00 00 00 00 00 00
+01 00 60 00 4c 36 40 21 00 00 00 30 10 32 54 76
+01 00 80 00 08 02 60 23 04 00 00 00 00 00 00 00
+01 00 60 00 0c 0e 60 20 00 00 00 08 00 00 00 00
+01 00 00 00 0c 0e 7c 20 00 00 00 08 ff ff ff ff
+01 00 80 00 28 12 a0 21 40 01 8d 00 00 00 00 00
+01 10 60 00 0c 0e 20 20 00 00 00 08 00 00 00 00
+01 10 60 00 28 0a 40 20 e0 01 8d 00 00 00 00 00
+01 10 60 00 28 0e c0 20 00 00 00 08 00 00 00 00
+01 10 00 00 0c 0e 3c 20 00 00 00 08 ff ff ff ff
+01 00 60 00 e8 12 40 20 c0 00 89 00 00 00 00 00
+01 00 60 00 28 3a e0 20 40 00 8d 00 00 00 00 00
+01 00 80 00 e8 3a 00 22 2c 01 00 00 00 00 00 00
+01 00 80 00 e8 12 20 23 40 02 89 00 00 00 00 00
+01 00 80 00 28 3a 60 22 20 03 8d 00 00 00 00 00
+01 00 60 00 c8 32 40 29 a0 00 00 00 00 00 00 00
+01 00 60 00 08 02 80 4b d0 00 00 00 00 00 00 00
+01 00 60 00 28 4f c0 27 00 00 00 00 00 00 f0 bf
+01 00 60 00 e8 32 80 4b 80 0b 69 00 00 00 00 00
+01 00 60 00 c8 3a 80 2b e0 0b 69 00 00 00 00 00
+01 10 60 00 c8 3a 40 2d 40 00 00 00 00 00 00 00
+01 10 60 00 28 4f 00 26 00 00 00 00 00 00 f0 bf
+01 10 60 00 08 02 e0 2f 44 0d 8a 00 00 00 00 00
+01 10 60 00 e8 32 60 41 e0 00 69 00 00 00 00 00
+01 10 60 00 28 02 20 24 40 04 8a 00 00 00 00 00
+01 10 60 00 08 06 c0 40 00 00 00 00 00 00 00 00
+01 00 60 00 48 26 40 20 00 00 00 20 10 32 54 76
+01 00 60 00 08 12 80 21 40 00 8d 00 00 00 00 00
+01 00 60 00 0c 06 e0 20 00 00 00 00 00 00 08 00
+01 00 00 00 ec 3e 40 20 00 00 00 38 00 00 80 3e
+01 00 60 00 e8 02 e0 21 40 03 8d 00 00 00 00 00
+01 00 00 00 44 12 02 26 3c 00 00 00 00 00 00 00
+01 00 60 00 08 0a 40 22 40 00 8d 00 00 00 00 00
+01 00 80 00 08 0a 40 22 40 03 8d 00 00 00 00 00
+01 00 80 00 28 0a 00 2f 40 04 8d 00 00 00 00 00
+01 00 60 00 28 4b 00 21 a0 01 69 00 00 00 00 00
+01 10 60 00 0c 02 a0 22 00 00 8d 00 00 00 00 00
+01 10 60 00 e8 3a e0 22 c0 00 00 00 00 00 00 00
+01 10 00 00 0c 06 a8 22 00 00 00 00 f2 03 00 00
+01 00 60 02 28 02 60 22 60 00 8a 00 00 00 00 00
+01 00 60 00 08 0e 60 20 00 00 00 08 00 00 00 00
+01 00 80 00 08 0e 80 20 00 00 00 08 00 00 00 00
+01 00 00 00 04 02 20 26 3c 00 00 00 00 00 00 00
+01 00 60 80 e8 3e c0 2f 00 00 00 38 00 00 00 00
+01 00 60 80 e8 0a 80 2f 80 44 8d 00 00 00 00 00
+01 00 80 00 0c 02 c0 2a 00 0b 8d 00 00 00 00 00
+01 00 80 80 e8 3a 00 2f 40 00 00 00 00 00 00 00
+01 00 80 00 e8 02 40 20 40 02 8d 00 00 00 00 00
+01 00 60 00 08 3e 80 20 00 00 00 38 00 00 00 00
+01 00 60 00 c8 0a 00 21 40 00 00 00 00 00 00 00
+01 00 80 00 08 06 a0 20 00 00 00 00 00 00 00 00
+01 00 60 02 e8 3a 80 20 40 60 00 00 00 00 00 00
+01 00 61 00 e8 3e 80 20 00 00 00 38 00 00 80 bf
+01 00 80 02 e8 3a 80 20 40 60 00 00 00 00 00 00
+01 00 81 00 e8 3e 80 20 00 00 00 38 00 00 80 bf
+01 00 00 00 0c 02 dc 21 3c 00 00 00 00 00 00 00
+01 10 00 00 0c 02 fc 20 3c 00 00 00 00 00 00 00
+01 10 60 00 c8 32 00 24 40 00 00 00 00 00 00 00
+01 00 60 00 e8 52 a0 20 40 00 00 00 00 00 00 00
+01 00 80 00 e8 52 c0 20 40 00 00 00 00 00 00 00
+01 00 60 00 08 3a e0 20 40 00 00 00 00 00 00 00
+01 00 60 00 4c 12 60 2f 40 00 ae 00 00 00 00 00
+01 00 80 00 4c 12 e0 2e 40 00 ae 00 00 00 00 00
+01 00 80 00 08 3a e0 21 60 01 8d 00 00 00 00 00
+01 00 80 00 08 12 60 22 e0 01 ae 00 00 00 00 00
+01 00 60 00 28 06 e0 20 00 00 00 00 00 00 00 00
+01 00 80 00 28 06 60 29 00 00 00 00 00 00 00 00
+01 00 80 00 28 02 e0 29 40 02 8d 00 00 00 00 00
+01 00 80 00 08 22 a0 23 60 03 cf 00 00 00 00 00
+01 00 60 00 c8 56 e0 20 00 00 00 00 00 00 00 00
+01 10 60 00 e8 3e c0 21 00 00 00 38 00 00 00 3f
+01 00 60 00 ec 3e a0 20 00 00 00 38 00 00 00 00
+01 00 80 00 0c 06 80 20 00 00 00 00 00 00 00 00
+01 00 60 00 08 32 a0 40 40 00 00 00 00 00 00 00
+01 10 60 00 08 32 40 41 40 00 00 00 00 00 00 00
+01 00 60 00 c8 02 60 20 40 00 00 00 00 00 00 00
+01 10 60 00 c8 02 60 20 40 00 00 00 00 00 00 00
+01 00 00 00 44 16 00 26 00 00 00 10 00 00 00 00
+01 00 00 00 2c 0e 20 20 00 00 00 08 00 00 00 00
+01 00 0a 00 2c 0e 20 20 00 00 00 08 ff ff ff ff
+01 00 60 00 e8 1a 20 21 40 00 00 00 00 00 00 00
+01 00 60 00 08 43 e0 20 80 00 69 00 00 00 00 00
+01 00 80 00 08 3e 60 21 00 00 00 38 00 00 00 00
+01 00 60 00 28 32 a0 40 40 00 00 00 00 00 00 00
+01 10 60 00 28 32 40 41 40 00 00 00 00 00 00 00
+01 00 00 00 0c 10 1c 23 02 06 00 00 00 00 00 00
+01 10 00 00 0c 10 5c 20 02 06 00 00 00 00 00 00
+01 20 80 00 28 0e c0 20 00 00 00 08 00 00 00 00
+01 00 60 00 08 22 c0 21 a0 01 cf 00 00 00 00 00
+01 20 80 00 28 12 c0 24 40 00 8d 00 00 00 00 00
+01 20 80 00 08 02 80 2f 80 05 8d 00 00 00 00 00
+01 20 80 00 08 06 80 20 00 00 00 00 01 00 00 00
+01 00 00 00 4c 06 80 40 00 00 00 00 00 00 00 00
+01 00 60 00 08 10 80 20 00 06 00 00 00 00 00 00
+01 00 60 00 28 12 00 21 40 00 8d 00 00 00 00 00
+01 00 80 00 08 10 80 20 00 06 00 00 00 00 00 00
+01 10 60 00 c8 0a 60 20 40 40 00 00 00 00 00 00
+01 00 60 00 e8 2a a0 20 40 00 00 00 00 00 00 00
+01 00 80 00 e8 2a c0 20 40 00 00 00 00 00 00 00
+01 10 60 00 c8 56 80 20 00 00 00 00 00 00 00 00
+01 10 60 02 28 02 00 22 20 02 8a 00 00 00 00 00
+01 00 60 00 48 36 40 24 00 00 00 30 10 32 54 76
+01 00 60 00 48 3b e0 40 44 00 00 00 00 00 00 00
+01 00 00 00 2c 0a a0 20 60 80 00 00 00 00 00 00
+01 00 00 00 44 10 20 26 02 06 00 00 00 00 00 00
+01 00 08 00 2c 0e 40 20 00 00 00 08 ff ff ff ff
+01 00 60 00 48 3a 40 40 20 01 8d 00 00 00 00 00
+01 00 60 00 48 12 60 20 40 00 ae 00 00 00 00 00
+01 00 80 80 e8 3e a0 21 00 00 00 38 00 00 80 3f
+01 00 80 00 48 3a 60 42 20 02 8d 00 00 00 00 00
+01 00 60 02 20 06 00 20 00 00 00 00 00 00 00 00
+01 00 80 02 20 06 00 20 00 00 00 00 00 00 00 00
+01 00 40 00 0c 00 60 20 00 18 69 00 00 00 00 00
+01 00 0b 00 2c 0e 20 20 00 00 00 08 ff ff ff ff
+01 00 60 00 e8 22 20 21 40 00 00 00 00 00 00 00
+01 00 80 00 e8 22 c0 20 40 00 00 00 00 00 00 00
+01 00 80 00 48 3b 40 41 80 00 8d 00 00 00 00 00
+01 00 60 01 00 02 00 20 40 00 8d 00 00 00 00 00
+01 00 60 80 e8 02 a0 2f 20 01 8d 00 00 00 00 00
+01 00 80 01 08 02 20 20 1c 00 00 00 00 00 00 00
+01 00 60 01 28 3a 40 22 20 02 8d 00 00 00 00 00
+01 00 60 00 28 1a 40 20 80 01 ae 00 00 00 00 00
+01 00 80 00 28 1a 00 25 40 02 ae 00 00 00 00 00
+01 00 60 00 28 2a 40 20 80 01 cf 00 00 00 00 00
+01 00 80 00 28 2a 00 25 40 02 cf 00 00 00 00 00
+01 00 80 00 e8 1a 40 25 80 00 ae 00 00 00 00 00
+01 10 60 00 28 4b e0 22 40 03 69 00 00 00 00 00
+01 00 09 00 2c 0e e0 20 00 00 00 08 ff ff ff ff
+01 00 60 01 20 3a 00 20 a0 02 8d 00 00 00 00 00
+01 00 80 01 20 3a 00 20 20 08 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen8/mul.asm b/src/intel/tools/tests/gen8/mul.asm
new file mode 100644 (file)
index 0000000..a9c7ed2
--- /dev/null
+++ b/src/intel/tools/tests/gen8/mul.asm
@@ -0,0 +1,31 @@
+mul(8)          g22<1>F         g4<8,8,1>F      g2<0,1,0>F      { align1 1Q };
+mul(16)         g33<1>F         g2<0,1,0>F      g2<0,1,0>F      { align1 1H };
+mul(8)          g36<1>DF        g8<0,1,0>DF     g8<0,1,0>DF     { align1 1Q };
+mul(8)          g9<1>UD         g32<8,8,1>UD    0x00000004UD    { align1 1Q };
+mul(8)          acc0<1>UD       g17<8,8,1>UD    0xaaabUW        { align1 1Q };
+mul(8)          acc0<1>D        g17<8,8,1>D     0x5556UW        { align1 1Q };
+mul(8)          g21<1>D         g20<8,8,1>D     3D              { align1 1Q };
+mul(8)          acc0<1>UD       g47<8,8,1>UD    0xaaabUW        { align1 2Q };
+mul(16)         g53<1>D         g51<8,8,1>D     3D              { align1 1H };
+mul(8)          acc0<1>D        g47<8,8,1>D     0x5556UW        { align1 2Q };
+mul.z.f0.0(8)   g10<1>F         g5<0,1,0>F      g9<8,8,1>F      { align1 1Q };
+mul(8)          g39<1>DF        g3.3<0,1,0>DF   g3.3<0,1,0>DF   { align1 2Q };
+mul.z.f0.0(16)  g6<1>F          g2<0,1,0>F      g4<8,8,1>F      { align1 1H };
+mul.sat(8)      g17<1>F         g4<8,8,1>F      g16<8,8,1>F     { align1 1Q };
+mul.sat(16)     g16<1>F         g10<8,8,1>F     g14<8,8,1>F     { align1 1H };
+mul.l.f0.0(8)   null<1>F        g6<0,1,0>F      g5.7<0,1,0>F    { align1 1Q };
+mul.sat(8)      g8<1>DF         g34<4,4,1>DF    g5<4,4,1>DF     { align1 1Q };
+mul(8)          g4<1>UQ         g8<4,4,1>UD     g12<4,4,1>UD    { align1 1Q };
+mul(8)          g20<1>UQ        g5<4,4,1>UD     g13<4,4,1>UD    { align1 2Q };
+mul(8)          g5<1>Q          g9<4,4,1>D      g13<4,4,1>D     { align1 1Q };
+mul.sat(8)      g10<1>DF        g10<4,4,1>DF    g16<4,4,1>DF    { align1 2Q };
+mul.l.f0.0(8)   g20<1>F         g2<8,8,1>F      0x42700000F  /* 60F */ { align1 1Q };
+mul.l.f0.0(16)  g32<1>F         g2<8,8,1>F      0x42700000F  /* 60F */ { align1 1H };
+mul(1)          g6<1>UD         g12<0,1,0>UD    0x00000101UD    { align1 WE_all 1N };
+mul(8)          g21<1>Q         g6<4,4,1>D      g14<4,4,1>D     { align1 2Q };
+mul.l.f0.0(16)  null<1>F        g2.2<0,1,0>F    g2.1<0,1,0>F    { align1 1H };
+mul(8)          g6<1>UW         g6<8,8,1>UW     0x0808UW        { align1 1Q };
+mul(16)         g15<1>UW        g14<16,16,1>UW  0x0808UW        { align1 1H };
+mul.nz.f0.0(8)  g6<1>F          g12<8,8,1>F     0x3f808000F  /* 1.00391F */ { align1 1Q };
+mul.nz.f0.0(16) g9<1>F          g7<8,8,1>F      0x3f808000F  /* 1.00391F */ { align1 1H };
+mul(1)          g4<1>UD         g4<0,1,0>UD     0x00000101UD    { align1 WE_all 3N };

diff --git a/src/intel/tools/tests/gen8/mul.expected b/src/intel/tools/tests/gen8/mul.expected
new file mode 100644 (file)
index 0000000..0563fd1
--- /dev/null
+++ b/src/intel/tools/tests/gen8/mul.expected
@@ -0,0 +1,31 @@
+41 00 60 00 e8 3a c0 22 80 00 8d 3a 40 00 00 00
+41 00 80 00 e8 3a 20 24 40 00 00 3a 40 00 00 00
+41 00 60 00 c8 32 80 24 00 01 00 32 00 01 00 00
+41 00 60 00 08 02 20 21 00 04 8d 06 04 00 00 00
+41 00 60 00 00 02 00 24 20 02 8d 16 ab aa ab aa
+41 00 60 00 20 0a 00 24 20 02 8d 16 56 55 56 55
+41 00 60 00 28 0a a0 22 80 02 8d 0e 03 00 00 00
+41 10 60 00 00 02 00 24 e0 05 8d 16 ab aa ab aa
+41 00 80 00 28 0a a0 26 60 06 8d 0e 03 00 00 00
+41 10 60 00 20 0a 00 24 e0 05 8d 16 56 55 56 55
+41 00 60 01 e8 3a 40 21 a0 00 00 3a 20 01 8d 00
+41 10 60 00 c8 32 e0 24 78 00 00 32 78 00 00 00
+41 00 80 01 e8 3a c0 20 40 00 00 3a 80 00 8d 00
+41 00 60 80 e8 3a 20 22 80 00 8d 3a 00 02 8d 00
+41 00 80 80 e8 3a 00 22 40 01 8d 3a c0 01 8d 00
+41 00 60 05 e0 3a 00 20 c0 00 00 3a bc 00 00 00
+41 00 60 80 c8 32 00 21 40 04 69 32 a0 00 69 00
+41 00 60 00 08 03 80 20 00 01 69 02 80 01 69 00
+41 10 60 00 08 03 80 22 a0 00 69 02 a0 01 69 00
+41 00 60 00 28 0b a0 20 20 01 69 0a a0 01 69 00
+41 10 60 80 c8 32 40 21 40 01 69 32 00 02 69 00
+41 00 60 05 e8 3a 80 22 40 00 8d 3e 00 00 70 42
+41 00 80 05 e8 3a 00 24 40 00 8d 3e 00 00 70 42
+41 00 00 00 0c 02 c0 20 80 01 00 06 01 01 00 00
+41 10 60 00 28 0b a0 22 c0 00 69 0a c0 01 69 00
+41 00 80 05 e0 3a 00 20 48 00 00 3a 44 00 00 00
+41 00 60 00 48 12 c0 20 c0 00 8d 16 08 08 08 08
+41 00 80 00 48 12 e0 21 c0 01 b1 16 08 08 08 08
+41 00 60 02 e8 3a c0 20 80 01 8d 3e 00 80 80 3f
+41 00 80 02 e8 3a 20 21 e0 00 8d 3e 00 80 80 3f
+41 10 00 00 0c 02 80 20 80 00 00 06 01 01 00 00

diff --git a/src/intel/tools/tests/gen8/nop.asm b/src/intel/tools/tests/gen8/nop.asm
new file mode 100644 (file)
index 0000000..0b66395
--- /dev/null
+++ b/src/intel/tools/tests/gen8/nop.asm
@@ -0,0 +1 @@
+nop                                                             ;

diff --git a/src/intel/tools/tests/gen8/nop.expected b/src/intel/tools/tests/gen8/nop.expected
new file mode 100644 (file)
index 0000000..9a3dcf2
--- /dev/null
+++ b/src/intel/tools/tests/gen8/nop.expected
@@ -0,0 +1 @@
+7e 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen8/not.asm b/src/intel/tools/tests/gen8/not.asm
new file mode 100644 (file)
index 0000000..4ec8010
--- /dev/null
+++ b/src/intel/tools/tests/gen8/not.asm
@@ -0,0 +1,2 @@
+not(16)         g10<1>D         g1.2<0,1,0>D                    { align1 1H };
+not(8)          g4<1>D          g8<8,8,1>D                      { align1 1Q };

diff --git a/src/intel/tools/tests/gen8/not.expected b/src/intel/tools/tests/gen8/not.expected
new file mode 100644 (file)
index 0000000..6ee27a2
--- /dev/null
+++ b/src/intel/tools/tests/gen8/not.expected
@@ -0,0 +1,2 @@
+04 00 80 00 28 0a 40 21 28 00 00 00 00 00 00 00
+04 00 60 00 28 0a 80 20 00 01 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen8/or.asm b/src/intel/tools/tests/gen8/or.asm
new file mode 100644 (file)
index 0000000..88f4d9b
--- /dev/null
+++ b/src/intel/tools/tests/gen8/or.asm
@@ -0,0 +1,18 @@
+or(8)           g53<1>UD        g49<8,8,1>UD    g21<8,8,1>UD    { align1 1Q };
+or.nz.f0.0(8)   null<1>UD       g21<8,8,1>UD    g2<8,8,1>UD     { align1 1Q };
+or.nz.f0.0(8)   g5<1>UD         g62<8,8,1>UD    g67<8,8,1>UD    { align1 1Q };
+or(8)           g5<1>UD         g106.1<8,4,2>UD 0x7ff00000UD    { align1 2Q };
+or.nz.f0.0(16)  null<1>UD       g35<8,8,1>UD    g32<8,8,1>UD    { align1 1H };
+or(16)          g36<1>UD        g34<8,8,1>UD    g20<8,8,1>UD    { align1 1H };
+or.nz.f0.0(16)  g56<1>UD        g54<8,8,1>UD    g52<8,8,1>UD    { align1 1H };
+or(1)           g2<1>UD         g2<0,1,0>UD     g4<0,1,0>UD     { align1 WE_all 1N };
+or(1)           a0<1>UD         g2<0,1,0>UD     0x064a7000UD    { align1 WE_all 1N };
+(+f0.0) or(8)   g3<1>UD         g3<8,8,1>UD     0x3f800000UD    { align1 1Q };
+(+f0.0) or(16)  g3<1>UD         g3<8,8,1>UD     0x3f800000UD    { align1 1H };
+or(1)           a0<1>UD         a0<0,1,0>UD     0x02280300UD    { align1 WE_all 1N };
+or(1)           a0<1>UD         g2<0,1,0>UD     0x0e0b6000UD    { align1 WE_all 3N };
+(+f0.0) or(8)   g17.1<2>UD      g17.1<8,4,2>UD  0x3ff00000UD    { align1 2Q };
+or(8)           g4<1>UW         g4<8,8,1>UW     g6<8,8,1>UW     { align1 1Q };
+or(16)          g16<1>UW        g14<16,16,1>UW  g15<16,16,1>UW  { align1 1H };
+or(8)           g22<1>UD        ~g2.2<0,1,0>D   g21<8,8,1>UD    { align1 1Q };
+or(16)          g37<1>UD        ~g2.2<0,1,0>D   g35<8,8,1>UD    { align1 1H };

diff --git a/src/intel/tools/tests/gen8/or.expected b/src/intel/tools/tests/gen8/or.expected
new file mode 100644 (file)
index 0000000..182b23d
--- /dev/null
+++ b/src/intel/tools/tests/gen8/or.expected
@@ -0,0 +1,18 @@
+06 00 60 00 08 02 a0 26 20 06 8d 02 a0 02 8d 00
+06 00 60 02 00 02 00 20 a0 02 8d 02 40 00 8d 00
+06 00 60 02 08 02 a0 20 c0 07 8d 02 60 08 8d 00
+06 10 60 00 08 02 a0 20 44 0d 8a 06 00 00 f0 7f
+06 00 80 02 00 02 00 20 60 04 8d 02 00 04 8d 00
+06 00 80 00 08 02 80 24 40 04 8d 02 80 02 8d 00
+06 00 80 02 08 02 00 27 c0 06 8d 02 80 06 8d 00
+06 00 00 00 0c 02 40 20 40 00 00 02 80 00 00 00
+06 00 00 00 04 02 00 22 40 00 00 06 00 70 4a 06
+06 00 61 00 08 02 60 20 60 00 8d 06 00 00 80 3f
+06 00 81 00 08 02 60 20 60 00 8d 06 00 00 80 3f
+06 00 00 00 04 00 00 22 00 02 00 06 00 03 28 02
+06 10 00 00 04 02 00 22 40 00 00 06 00 60 0b 0e
+06 10 61 00 08 02 24 42 24 02 8a 06 00 00 f0 3f
+06 00 60 00 48 12 80 20 80 00 8d 12 c0 00 8d 00
+06 00 80 00 48 12 00 22 c0 01 b1 12 e0 01 b1 00
+06 00 60 00 08 0a c0 22 48 40 00 02 a0 02 8d 00
+06 00 80 00 08 0a a0 24 48 40 00 02 60 04 8d 00

diff --git a/src/intel/tools/tests/gen8/pln.asm b/src/intel/tools/tests/gen8/pln.asm
new file mode 100644 (file)
index 0000000..5b0adcf
--- /dev/null
+++ b/src/intel/tools/tests/gen8/pln.asm
@@ -0,0 +1,10 @@
+pln(8)          g124<1>F        g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln(16)         g120<1>F        g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.sat(8)      g9<1>F          g5<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.sat(16)     g12<1>F         g7<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.g.f0.0(8)   g7<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.g.f0.0(16)  g11<1>F         g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.l.f0.0(8)   g8<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.l.f0.0(16)  g11<1>F         g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.nz.f0.0(8)  g18<1>F         g5<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.nz.f0.0(16) g14<1>F         g7<0,1,0>F      g2<8,8,1>F      { align1 1H };

diff --git a/src/intel/tools/tests/gen8/pln.expected b/src/intel/tools/tests/gen8/pln.expected
new file mode 100644 (file)
index 0000000..eb77b2a
--- /dev/null
+++ b/src/intel/tools/tests/gen8/pln.expected
@@ -0,0 +1,10 @@
+5a 00 60 00 e8 3a 80 2f 80 00 00 3a 40 00 8d 00
+5a 00 80 00 e8 3a 00 2f c0 00 00 3a 40 00 8d 00
+5a 00 60 80 e8 3a 20 21 a0 00 00 3a 40 00 8d 00
+5a 00 80 80 e8 3a 80 21 e0 00 00 3a 40 00 8d 00
+5a 00 60 03 e8 3a e0 20 80 00 00 3a 40 00 8d 00
+5a 00 80 03 e8 3a 60 21 c0 00 00 3a 40 00 8d 00
+5a 00 60 05 e8 3a 00 21 80 00 00 3a 40 00 8d 00
+5a 00 80 05 e8 3a 60 21 c0 00 00 3a 40 00 8d 00
+5a 00 60 02 e8 3a 40 22 a0 00 00 3a 40 00 8d 00
+5a 00 80 02 e8 3a c0 21 e0 00 00 3a 40 00 8d 00

diff --git a/src/intel/tools/tests/gen8/rndd.asm b/src/intel/tools/tests/gen8/rndd.asm
new file mode 100644 (file)
index 0000000..463ef80
--- /dev/null
+++ b/src/intel/tools/tests/gen8/rndd.asm
@@ -0,0 +1,5 @@
+rndd(8)         g22<1>F         g17<0,1,0>F                     { align1 1Q };
+rndd(16)        g7<1>F          g5<8,8,1>F                      { align1 1H };
+rndd.z.f0.0(8)  null<1>F        g17<8,8,1>F                     { align1 1Q };
+rndd.z.f0.0(16) null<1>F        g39<8,8,1>F                     { align1 1H };
+rndd.sat(8)     g124<1>F        g10<8,8,1>F                     { align1 1Q };

diff --git a/src/intel/tools/tests/gen8/rndd.expected b/src/intel/tools/tests/gen8/rndd.expected
new file mode 100644 (file)
index 0000000..ff7ca82
--- /dev/null
+++ b/src/intel/tools/tests/gen8/rndd.expected
@@ -0,0 +1,5 @@
+45 00 60 00 e8 3a c0 22 20 02 00 00 00 00 00 00
+45 00 80 00 e8 3a e0 20 a0 00 8d 00 00 00 00 00
+45 00 60 01 e0 3a 00 20 20 02 8d 00 00 00 00 00
+45 00 80 01 e0 3a 00 20 e0 04 8d 00 00 00 00 00
+45 00 60 80 e8 3a 80 2f 40 01 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen8/rnde.asm b/src/intel/tools/tests/gen8/rnde.asm
new file mode 100644 (file)
index 0000000..bc65bbc
--- /dev/null
+++ b/src/intel/tools/tests/gen8/rnde.asm
@@ -0,0 +1,2 @@
+rnde(8)         g7<1>F          g5<8,8,1>F                      { align1 1Q };
+rnde(16)        g11<1>F         g7<8,8,1>F                      { align1 1H };

diff --git a/src/intel/tools/tests/gen8/rnde.expected b/src/intel/tools/tests/gen8/rnde.expected
new file mode 100644 (file)
index 0000000..edac496
--- /dev/null
+++ b/src/intel/tools/tests/gen8/rnde.expected
@@ -0,0 +1,2 @@
+46 00 60 00 e8 3a e0 20 a0 00 8d 00 00 00 00 00
+46 00 80 00 e8 3a 60 21 e0 00 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen8/rndz.asm b/src/intel/tools/tests/gen8/rndz.asm
new file mode 100644 (file)
index 0000000..4b082d0
--- /dev/null
+++ b/src/intel/tools/tests/gen8/rndz.asm
@@ -0,0 +1,2 @@
+rndz(8)         g7<1>F          g2<0,1,0>F                      { align1 1Q };
+rndz(16)        g102<1>F        g99<8,8,1>F                     { align1 1H };

diff --git a/src/intel/tools/tests/gen8/rndz.expected b/src/intel/tools/tests/gen8/rndz.expected
new file mode 100644 (file)
index 0000000..2a79a23
--- /dev/null
+++ b/src/intel/tools/tests/gen8/rndz.expected
@@ -0,0 +1,2 @@
+47 00 60 00 e8 3a e0 20 40 00 00 00 00 00 00 00
+47 00 80 00 e8 3a c0 2c 60 0c 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen8/sel.asm b/src/intel/tools/tests/gen8/sel.asm
new file mode 100644 (file)
index 0000000..c41fd39
--- /dev/null
+++ b/src/intel/tools/tests/gen8/sel.asm
@@ -0,0 +1,33 @@
+(-f0.0) sel(8)  g124<1>UD       g124<8,8,1>UD   0x3f800000UD    { align1 1Q };
+(+f0.0) sel(8)  g124<1>UD       g124<8,8,1>UD   0x00000000UD    { align1 1Q };
+(+f0.0) sel(8)  g24<1>UQ        g66<4,4,1>UQ    g40<4,4,1>UQ    { align1 1Q };
+(+f0.0) sel(8)  g36<1>UQ        g50<4,4,1>UQ    g31<4,4,1>UQ    { align1 2Q };
+sel.ge(8)       g10<1>F         g4<8,8,1>F      g5<8,8,1>F      { align1 1Q };
+(+f0.0) sel(16) g23<1>UD        g39<8,8,1>UD    g41<8,8,1>UD    { align1 1H };
+(-f0.0) sel(16) g11<1>UD        g58<8,8,1>UD    0x00000000UD    { align1 1H };
+sel.l(8)        g3<1>UD         g2.1<0,1,0>UD   0x00000001UD    { align1 1Q };
+sel.l(16)       g3<1>UD         g2.1<0,1,0>UD   0x00000001UD    { align1 1H };
+sel.ge(8)       g3<1>D          g2<0,1,0>D      -1D             { align1 1Q };
+sel.l(8)        g4<1>D          g3<8,8,1>D      1D              { align1 1Q };
+sel.ge(16)      g3<1>D          g2<0,1,0>D      -1D             { align1 1H };
+sel.l(16)       g5<1>D          g3<8,8,1>D      1D              { align1 1H };
+sel.ge(16)      g24<1>F         g20<8,8,1>F     0x0F  /* 0F */  { align1 1H };
+sel.l(8)        g8<1>F          g7<8,8,1>F      0x43000000F  /* 128F */ { align1 1Q };
+(-f0.0) sel.sat(8) g126<1>F     g11<8,8,1>F     0x0F  /* 0F */  { align1 1Q };
+sel.l(8)        g18<1>DF        g5<0,1,0>DF     g5.1<0,1,0>DF   { align1 1Q };
+sel.ge(16)      g37<1>UD        g9<8,8,1>UD     g13<8,8,1>UD    { align1 1H };
+sel.ge(8)       g19<1>UD        g5<0,1,0>UD     g5.4<0,1,0>UD   { align1 1Q };
+sel.sat.l(8)    g124<1>F        g6<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 1Q };
+(+f0.0) sel(8)  g26<1>F         g5<0,1,0>F      (abs)g5.3<0,1,0>F { align1 1Q };
+(-f0.0) sel(8)  g44<1>F         (abs)g41<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
+sel.l(16)       g120<1>F        g2.3<0,1,0>F    g2.2<0,1,0>F    { align1 1H };
+(+f0.0) sel(8)  g9<1>DF         g2<0,1,0>DF     -g2<0,1,0>DF    { align1 1Q };
+(+f0.0) sel(8)  g12<1>DF        g2<0,1,0>DF     -g2<0,1,0>DF    { align1 2Q };
+sel.ge(8)       g5<1>DF         g2<0,1,0>DF     g2.2<0,1,0>DF   { align1 1Q };
+sel.ge(8)       g35<1>DF        g2<0,1,0>DF     g2.2<0,1,0>DF   { align1 2Q };
+sel.l(8)        g11<1>DF        g35<4,4,1>DF    g3<0,1,0>DF     { align1 2Q };
+(+f0.0) sel.sat(8) g126<1>F     g11<8,8,1>F     0x0F  /* 0F */  { align1 1Q };
+(-f0.0) sel(16) g27<1>F         (abs)g25<8,8,1>F 0x3f800000F  /* 1F */ { align1 1H };
+(+f0.0) sel(16) g36<1>F         g2<0,1,0>F      (abs)g2.4<0,1,0>F { align1 1H };
+(+f0.0) sel(16) g8<1>UD         g4<8,8,1>UD     g6<8,8,1>UD     { align1 2H };
+sel.sat.l(16)   g8<1>F          g83<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1H };

diff --git a/src/intel/tools/tests/gen8/sel.expected b/src/intel/tools/tests/gen8/sel.expected
new file mode 100644 (file)
index 0000000..01f3e5a
--- /dev/null
+++ b/src/intel/tools/tests/gen8/sel.expected
@@ -0,0 +1,33 @@
+02 00 71 00 08 02 80 2f 80 0f 8d 06 00 00 80 3f
+02 00 61 00 08 02 80 2f 80 0f 8d 06 00 00 00 00
+02 00 61 00 08 43 00 23 40 08 69 42 00 05 69 00
+02 10 61 00 08 43 80 24 40 06 69 42 e0 03 69 00
+02 00 60 04 e8 3a 40 21 80 00 8d 3a a0 00 8d 00
+02 00 81 00 08 02 e0 22 e0 04 8d 02 20 05 8d 00
+02 00 91 00 08 02 60 21 40 07 8d 06 00 00 00 00
+02 00 60 05 08 02 60 20 44 00 00 06 01 00 00 00
+02 00 80 05 08 02 60 20 44 00 00 06 01 00 00 00
+02 00 60 04 28 0a 60 20 40 00 00 0e ff ff ff ff
+02 00 60 05 28 0a 80 20 60 00 8d 0e 01 00 00 00
+02 00 80 04 28 0a 60 20 40 00 00 0e ff ff ff ff
+02 00 80 05 28 0a a0 20 60 00 8d 0e 01 00 00 00
+02 00 80 04 e8 3a 00 23 80 02 8d 3e 00 00 00 00
+02 00 60 05 e8 3a 00 21 e0 00 8d 3e 00 00 00 43
+02 00 71 80 e8 3a c0 2f 60 01 8d 3e 00 00 00 00
+02 00 60 05 c8 32 40 22 a0 00 00 32 a8 00 00 00
+02 00 80 04 08 02 a0 24 20 01 8d 02 a0 01 8d 00
+02 00 60 04 08 02 60 22 a0 00 00 02 b0 00 00 00
+02 00 60 85 e8 3a 80 2f c0 00 8d 3e 00 00 00 3f
+02 00 61 00 e8 3a 40 23 a0 00 00 3a ac 20 00 00
+02 00 71 00 e8 3a 80 25 20 25 8d 3e 00 00 80 3f
+02 00 80 05 e8 3a 00 2f 4c 00 00 3a 48 00 00 00
+02 00 61 00 c8 32 20 21 40 00 00 32 40 40 00 00
+02 10 61 00 c8 32 80 21 40 00 00 32 40 40 00 00
+02 00 60 04 c8 32 a0 20 40 00 00 32 50 00 00 00
+02 10 60 04 c8 32 60 24 40 00 00 32 50 00 00 00
+02 10 60 05 c8 32 60 21 60 04 69 32 60 00 00 00
+02 00 61 80 e8 3a c0 2f 60 01 8d 3e 00 00 00 00
+02 00 91 00 e8 3a 60 23 20 23 8d 3e 00 00 80 3f
+02 00 81 00 e8 3a 80 24 40 00 00 3a 50 20 00 00
+02 20 81 00 08 02 00 21 80 00 8d 02 c0 00 8d 00
+02 00 80 85 e8 3a 00 21 60 0a 8d 3e 00 00 00 3f

diff --git a/src/intel/tools/tests/gen8/send.asm b/src/intel/tools/tests/gen8/send.asm
new file mode 100644 (file)
index 0000000..ae1ee83
--- /dev/null
+++ b/src/intel/tools/tests/gen8/send.asm
@@ -0,0 +1,4380 @@
+send(8)         null<1>F        g123<8,8,1>F    0x8a080017
+                            urb MsgDesc: 1 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         null<1>F        g13<8,8,1>F     0x12080007
+                            urb MsgDesc: 0 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080027
+                            urb MsgDesc: 2 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(16)        g9<1>UD         g2<8,8,1>UD     0x02280300
+                            const MsgDesc: (0, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         null<1>F        g119<8,8,1>F    0x92080017
+                            urb MsgDesc: 1 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         null<1>UW       g3<8,8,1>UD     0x0e0b5001
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 7 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g1<8,8,1>UD     0x0e0b6001
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 7 rlen 0 { align1 2Q };
+send(16)        null<1>UW       g127<8,8,1>UW   0x82000010
+                            thread_spawner MsgDesc: mlen 1 rlen 0           { align1 WE_all 1H EOT };
+send(8)         g124<1>UW       g13<8,8,1>UD    0x08427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g10<8,8,1>UD    0x10847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g10<1>UD        g2<8,8,1>UD     0x02480028
+                            urb MsgDesc: 2 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         null<1>F        g8<8,8,1>F      0x140a0017
+                            urb MsgDesc: 1 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g118<8,8,1>F    0x940a0017
+                            urb MsgDesc: 1 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT };
+send(8)         null<1>F        g11<8,8,1>UD    0x0c0a0037
+                            urb MsgDesc: 3 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a080027
+                            urb MsgDesc: 2 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0c088017
+                            urb MsgDesc: 1 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a088017
+                            urb MsgDesc: 1 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x08088017
+                            urb MsgDesc: 1 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g2<8,8,1>UD     0x06088017
+                            urb MsgDesc: 1 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0c088007
+                            urb MsgDesc: 0 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a088007
+                            urb MsgDesc: 0 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x02480008
+                            urb MsgDesc: 0 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         g6<1>UD         g6<8,8,1>UD     0x02480018
+                            urb MsgDesc: 1 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         null<1>F        g125<8,8,1>UD   0x86088007
+                            urb MsgDesc: 0 SIMD8 write masked mlen 3 rlen 0 { align1 1Q EOT };
+send(8)         g7<1>UW         g7<8,8,1>UD     0x04427000
+                            sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>F     0x12080017
+                            urb MsgDesc: 1 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>F     0x12080037
+                            urb MsgDesc: 3 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080057
+                            urb MsgDesc: 5 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x08840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x0643d001
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g8<1>UW         g16<8,8,1>UD    0x0c85d001
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g8<1>UW         g17<8,8,1>UD    0x0a43e001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g34<1>UW        g16<8,8,1>UD    0x1485e001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g5<1>UW         g7<8,8,1>UD     0x0242a000
+                            sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g15<8,8,1>UD    0x064a8000
+                            sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g11<8,8,1>UD    0x06420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g19<8,8,1>UD    0x0c840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g12<1>UW        g5<8,8,1>UD     0x02427000
+                            sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080037
+                            urb MsgDesc: 3 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x144a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 1Q };
+(+f1.0) send(16) g122<1>UW      g9<8,8,1>UD     0x0420a501
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 2 { align1 1H };
+send(8)         g12<1>UW        g7<8,8,1>UD     0x0443d001
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g13<1>UW        g5<8,8,1>UD     0x0843e001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g15<1>UW        g11<8,8,1>UD    0x0885d001
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g27<1>UW        g7<8,8,1>UD     0x1085e001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+(+f1.0) send(8) g125<1>UW       g3<8,8,1>UD     0x0210b501
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g8<8,8,1>UD     a0<0,1,0>UD     0x00000200
+                            sampler MsgDesc: indirect                       { align1 1Q };
+send(8)         g124<1>UW       g8<8,8,1>UD     0x084a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g8<8,8,1>UD     0x064a8001
+                            sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g12<8,8,1>UD    0x0a8c8001
+                            sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x0a4a6001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g12<8,8,1>UD    0x0a4a6102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x128c6001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g20<8,8,1>UD    0x128c6102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x0a43e000
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080027
+                            urb MsgDesc: 2 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         g2<1>UW         g3<8,8,1>UD     0x0643d000
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         null<1>F        g7<8,8,1>UD     0x0a080037
+                            urb MsgDesc: 3 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g8<8,8,1>UD     0x0a080047
+                            urb MsgDesc: 4 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>F     0x0c0a0017
+                            urb MsgDesc: 1 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g122<8,8,1>F    0x8c0a0017
+                            urb MsgDesc: 1 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g5<1>UW         g21<8,8,1>UD    0x02420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g26<8,8,1>UD    0x04840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g8<1>UW         g10<8,8,1>UD    0x0242a001
+                            sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x0c4b1001
+                            sampler MsgDesc: gather4_po SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(16)        g23<1>UW        g20<8,8,1>UD    0x0484a001
+                            sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(16)        g18<1>UW        g7<8,8,1>UD     0x168d1001
+                            sampler MsgDesc: gather4_po SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a088027
+                            urb MsgDesc: 2 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g7<8,8,1>UD     0x0a088037
+                            urb MsgDesc: 3 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g8<8,8,1>UD     0x0a088047
+                            urb MsgDesc: 4 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g9<8,8,1>UD     0x0a088057
+                            urb MsgDesc: 5 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x084a8001
+                            sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g14<1>UW        g7<8,8,1>UD     0x0e8c8001
+                            sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x0c424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x0c4b1000
+                            sampler MsgDesc: gather4_po SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x0242a101
+                            sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g10<8,8,1>UD    0x0242a202
+                            sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 2 mlen 1 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g14<8,8,1>UD    0x0242a303
+                            sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 3 mlen 1 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x0242a404
+                            sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 4 mlen 1 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g22<8,8,1>UD    0x0242a505
+                            sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 5 mlen 1 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g26<8,8,1>UD    0x0242a606
+                            sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 6 mlen 1 rlen 4 { align1 1Q };
+send(8)         g6<1>UD         g15<8,8,1>UD    0x042a0318
+                            urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g8<1>UD         g15<8,8,1>UD    0x042a0518
+                            urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g10<1>UD        g15<8,8,1>UD    0x042a0718
+                            urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g12<1>UD        g15<8,8,1>UD    0x042a0918
+                            urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g14<1>UD        g15<8,8,1>UD    0x042a0128
+                            urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g16<1>UD        g14<8,8,1>UD    0x042a0218
+                            urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g18<1>UD        g14<8,8,1>UD    0x042a0418
+                            urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g20<1>UD        g14<8,8,1>UD    0x042a0618
+                            urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g22<1>UD        g14<8,8,1>UD    0x042a0818
+                            urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g13<1>UD        g14<8,8,1>UD    0x042a0028
+                            urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g30<8,8,1>UD    0x02480208
+                            urb MsgDesc: 32 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g14<1>UD        g30<8,8,1>UD    0x02480408
+                            urb MsgDesc: 64 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g18<1>UD        g30<8,8,1>UD    0x02480608
+                            urb MsgDesc: 96 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g30<8,8,1>UD    0x02480808
+                            urb MsgDesc: 128 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a0a8217
+                            urb MsgDesc: 33 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x0a0a8227
+                            urb MsgDesc: 34 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0a0a8237
+                            urb MsgDesc: 35 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x0a0a8247
+                            urb MsgDesc: 36 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x0a0a8257
+                            urb MsgDesc: 37 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x0a0a8267
+                            urb MsgDesc: 38 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0a0a8277
+                            urb MsgDesc: 39 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0a0a8287
+                            urb MsgDesc: 40 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0a0a8297
+                            urb MsgDesc: 41 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0a0a82a7
+                            urb MsgDesc: 42 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0a0a82b7
+                            urb MsgDesc: 43 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0a0a82c7
+                            urb MsgDesc: 44 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0a0a82d7
+                            urb MsgDesc: 45 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0a0a82e7
+                            urb MsgDesc: 46 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0a0a82f7
+                            urb MsgDesc: 47 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0a0a8307
+                            urb MsgDesc: 48 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0a0a8317
+                            urb MsgDesc: 49 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0a0a8327
+                            urb MsgDesc: 50 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0a0a8337
+                            urb MsgDesc: 51 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0a0a8347
+                            urb MsgDesc: 52 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0a0a8357
+                            urb MsgDesc: 53 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0a0a8367
+                            urb MsgDesc: 54 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0a0a8377
+                            urb MsgDesc: 55 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0a0a8387
+                            urb MsgDesc: 56 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0a0a8397
+                            urb MsgDesc: 57 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0a0a83a7
+                            urb MsgDesc: 58 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0a0a83b7
+                            urb MsgDesc: 59 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0a0a83c7
+                            urb MsgDesc: 60 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0a0a83d7
+                            urb MsgDesc: 61 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0a0a83e7
+                            urb MsgDesc: 62 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x0a0a83f7
+                            urb MsgDesc: 63 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x08088027
+                            urb MsgDesc: 2 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x08088037
+                            urb MsgDesc: 3 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x08088047
+                            urb MsgDesc: 4 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x08088057
+                            urb MsgDesc: 5 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x08088067
+                            urb MsgDesc: 6 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x08088077
+                            urb MsgDesc: 7 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x08088087
+                            urb MsgDesc: 8 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x08088097
+                            urb MsgDesc: 9 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x080880a7
+                            urb MsgDesc: 10 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x080880b7
+                            urb MsgDesc: 11 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x080880c7
+                            urb MsgDesc: 12 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x080880d7
+                            urb MsgDesc: 13 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x080880e7
+                            urb MsgDesc: 14 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x080880f7
+                            urb MsgDesc: 15 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x08088107
+                            urb MsgDesc: 16 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x08088117
+                            urb MsgDesc: 17 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x08088127
+                            urb MsgDesc: 18 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x08088137
+                            urb MsgDesc: 19 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x08088147
+                            urb MsgDesc: 20 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x08088157
+                            urb MsgDesc: 21 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x08088167
+                            urb MsgDesc: 22 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x08088177
+                            urb MsgDesc: 23 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x08088187
+                            urb MsgDesc: 24 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x08088197
+                            urb MsgDesc: 25 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x080881a7
+                            urb MsgDesc: 26 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x080881b7
+                            urb MsgDesc: 27 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x080881c7
+                            urb MsgDesc: 28 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x080881d7
+                            urb MsgDesc: 29 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x080881e7
+                            urb MsgDesc: 30 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x080881f7
+                            urb MsgDesc: 31 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x0c0a0207
+                            urb MsgDesc: 32 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080057
+                            urb MsgDesc: 5 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         g10<1>UW        g18<8,8,1>UD    0x084a8000
+                            sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g1<8,8,1>UD     0x0c847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        null<1>UW       g57<8,8,1>UD    0x04008502
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x08842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x06427000
+                            sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g5<1>UW         g3<8,8,1>UD     0x02427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g8<1>UW         g5<8,8,1>UD     0x04847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         null<1>F        g119<8,8,1>F    0x92080007
+                            urb MsgDesc: 0 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         null<1>F        g126<8,8,1>UD   0x84080017
+                            urb MsgDesc: 1 SIMD8 write mlen 2 rlen 0        { align1 1Q EOT };
+send(8)         g124<1>UW       g9<8,8,1>UD     0x08421001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g14<8,8,1>UD    0x10841001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g38<1>UD        g1<8,8,1>UD     0x02180028
+                            urb MsgDesc: 2 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g40<1>UD        g1<8,8,1>UD     0x02180038
+                            urb MsgDesc: 3 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g42<1>UD        g1<8,8,1>UD     0x02180048
+                            urb MsgDesc: 4 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g44<1>UD        g1<8,8,1>UD     0x02180058
+                            urb MsgDesc: 5 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g46<1>UD        g1<8,8,1>UD     0x02180068
+                            urb MsgDesc: 6 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g48<1>UD        g1<8,8,1>UD     0x02180078
+                            urb MsgDesc: 7 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g50<1>UD        g1<8,8,1>UD     0x02180088
+                            urb MsgDesc: 8 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g52<1>UD        g1<8,8,1>UD     0x02180098
+                            urb MsgDesc: 9 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g54<1>UD        g1<8,8,1>UD     0x021800a8
+                            urb MsgDesc: 10 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g56<1>UD        g1<8,8,1>UD     0x021800b8
+                            urb MsgDesc: 11 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g58<1>UD        g1<8,8,1>UD     0x021800c8
+                            urb MsgDesc: 12 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g60<1>UD        g1<8,8,1>UD     0x021800d8
+                            urb MsgDesc: 13 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g62<1>UD        g1<8,8,1>UD     0x021800e8
+                            urb MsgDesc: 14 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g64<1>UD        g1<8,8,1>UD     0x021800f8
+                            urb MsgDesc: 15 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g66<1>UD        g1<8,8,1>UD     0x02180108
+                            urb MsgDesc: 16 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g68<1>UD        g1<8,8,1>UD     0x02180118
+                            urb MsgDesc: 17 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g70<1>UD        g1<8,8,1>UD     0x02180128
+                            urb MsgDesc: 18 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g72<1>UD        g1<8,8,1>UD     0x02180138
+                            urb MsgDesc: 19 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g74<1>UD        g1<8,8,1>UD     0x02180148
+                            urb MsgDesc: 20 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g76<1>UD        g1<8,8,1>UD     0x02180158
+                            urb MsgDesc: 21 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g78<1>UD        g1<8,8,1>UD     0x02180168
+                            urb MsgDesc: 22 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g80<1>UD        g1<8,8,1>UD     0x02180178
+                            urb MsgDesc: 23 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g82<1>UD        g1<8,8,1>UD     0x02180188
+                            urb MsgDesc: 24 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g84<1>UD        g1<8,8,1>UD     0x02180198
+                            urb MsgDesc: 25 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g86<1>UD        g1<8,8,1>UD     0x021801a8
+                            urb MsgDesc: 26 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g88<1>UD        g1<8,8,1>UD     0x021801b8
+                            urb MsgDesc: 27 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g90<1>UD        g1<8,8,1>UD     0x021801c8
+                            urb MsgDesc: 28 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g92<1>UD        g1<8,8,1>UD     0x021801d8
+                            urb MsgDesc: 29 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g94<1>UD        g1<8,8,1>UD     0x021801e8
+                            urb MsgDesc: 30 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g96<1>UD        g1<8,8,1>UD     0x021801f8
+                            urb MsgDesc: 31 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g98<1>UD        g1<8,8,1>UD     0x02180208
+                            urb MsgDesc: 32 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0c0a0027
+                            urb MsgDesc: 2 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g126<8,8,1>UD   0x040a02fd
+                            data MsgDesc: ( DC OWORD block write, 253, 2) mlen 2 rlen 0 { align1 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c001b
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 27, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c001c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 28, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c001d
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 29, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c001e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 30, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c001f
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 31, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0020
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 32, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0021
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 33, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         null<1>F        g25<8,8,1>F     0x12080057
+                            urb MsgDesc: 5 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>F     0x12080077
+                            urb MsgDesc: 7 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g43<8,8,1>F     0x12080097
+                            urb MsgDesc: 9 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g52<8,8,1>F     0x120800b7
+                            urb MsgDesc: 11 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g61<8,8,1>F     0x120800d7
+                            urb MsgDesc: 13 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g70<8,8,1>F     0x120800f7
+                            urb MsgDesc: 15 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         g2<1>UW         g0<8,8,1>F      0x021c0000
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 0, 0) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         g3<1>UW         g0<8,8,1>F      0x021c0001
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 1, 0) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         g4<1>UW         g0<8,8,1>F      0x021c0002
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 2, 0) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         g5<1>UW         g0<8,8,1>F      0x021c0003
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 3, 0) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         g6<1>UW         g0<8,8,1>F      0x021c0004
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 4, 0) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         g7<1>UW         g0<8,8,1>F      0x021c0005
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 5, 0) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         g8<1>UW         g0<8,8,1>F      0x021c0006
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 6, 0) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         g9<1>UW         g0<8,8,1>F      0x021c0007
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 7, 0) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         g10<1>UW        g0<8,8,1>F      0x021c0008
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 8, 0) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         null<1>F        g2<8,8,1>F      0x12080117
+                            urb MsgDesc: 17 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         g2<1>UW         g0<8,8,1>F      0x021c0009
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 9, 0) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         g3<1>UW         g0<8,8,1>F      0x021c000a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 10, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g4<1>UW         g0<8,8,1>F      0x021c000b
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 11, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g5<1>UW         g0<8,8,1>F      0x021c000c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 12, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g6<1>UW         g0<8,8,1>F      0x021c000d
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 13, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g7<1>UW         g0<8,8,1>F      0x021c000e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 14, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g8<1>UW         g0<8,8,1>F      0x021c000f
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 15, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g9<1>UW         g0<8,8,1>F      0x021c0010
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 16, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g10<1>UW        g0<8,8,1>F      0x021c0011
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 17, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         null<1>F        g2<8,8,1>F      0x12080137
+                            urb MsgDesc: 19 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         g2<1>UW         g0<8,8,1>F      0x021c0012
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 18, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g3<1>UW         g0<8,8,1>F      0x021c0013
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 19, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g4<1>UW         g0<8,8,1>F      0x021c0014
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 20, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g5<1>UW         g0<8,8,1>F      0x021c0015
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 21, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g6<1>UW         g0<8,8,1>F      0x021c0016
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 22, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g7<1>UW         g0<8,8,1>F      0x021c0017
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 23, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g8<1>UW         g0<8,8,1>F      0x021c0018
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 24, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g9<1>UW         g0<8,8,1>F      0x021c0019
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 25, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g10<1>UW        g0<8,8,1>F      0x021c001a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 26, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         null<1>F        g2<8,8,1>F      0x12080157
+                            urb MsgDesc: 21 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g79<8,8,1>F     0x12080177
+                            urb MsgDesc: 23 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g88<8,8,1>F     0x12080197
+                            urb MsgDesc: 25 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g97<8,8,1>F     0x120801b7
+                            urb MsgDesc: 27 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g106<8,8,1>F    0x120801d7
+                            urb MsgDesc: 29 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g117<8,8,1>F    0x920801f7
+                            urb MsgDesc: 31 SIMD8 write mlen 9 rlen 0       { align1 1Q EOT };
+send(8)         g124<1>UW       g12<8,8,1>UD    0x0a4b1001
+                            sampler MsgDesc: gather4_po SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x128d1001
+                            sampler MsgDesc: gather4_po SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x02429001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x04849001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x08427000
+                            sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        null<1>UW       g40<8,8,1>UD    0x04008501
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(8)         null<1>F        g127<8,8,1>UD   0x82080007
+                            urb MsgDesc: 0 SIMD8 write mlen 1 rlen 0        { align1 1Q EOT };
+send(8)         g124<1>UW       g9<8,8,1>UD     0x0a4a8000
+                            sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x0e434001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+(+f1.0) send(8) g12<1>UW        g2<8,8,1>UD     0x0410b201
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g2<8,8,1>UD     0x02009501
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 0 { align1 1Q };
+(+f1.0) send(16) g14<1>UW       g16<8,8,1>UD    0x0820a201
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 4 rlen 2 { align1 1H };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x08434001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g119<1>UW       g0<8,8,1>F      0x021c0022
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 34, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g120<1>UW       g0<8,8,1>F      0x021c0023
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 35, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         null<1>F        g102<8,8,1>F    0x120801f7
+                            urb MsgDesc: 31 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g121<8,8,1>F    0x8a080217
+                            urb MsgDesc: 33 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(16)        null<1>UW       g3<8,8,1>UD     0x08025efe
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 254, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
+send(16)        null<1>UW       g3<8,8,1>UD     0x02008004
+                            gateway MsgDesc: (barrier msg) mlen 1 rlen 0    { align1 WE_all 1H };
+send(16)        null<1>UW       g7<8,8,1>UD     0x080087fe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, add) mlen 4 rlen 0 { align1 1H };
+send(16)        g3<1>UW         g5<8,8,1>UD     0x04205efe
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 254, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x06423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g10<8,8,1>UD    0x0c843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        g30<8,8,1>F     0x140a0027
+                            urb MsgDesc: 2 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>F     0x0c0a0047
+                            urb MsgDesc: 4 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g126<8,8,1>UD   0x84080007
+                            urb MsgDesc: 0 SIMD8 write mlen 2 rlen 0        { align1 1Q EOT };
+send(8)         g5<1>UW         g11<8,8,1>UD    0x06495001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 3 rlen 4 { align1 1Q };
+send(8)         null<1>UW       g14<8,8,1>UD    0x0e0b5002
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0x0) mlen 7 rlen 0 { align1 1Q };
+send(8)         g2<1>UW         g11<8,8,1>UD    0x06496001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 3 rlen 4 { align1 2Q };
+send(8)         null<1>UW       g7<8,8,1>UD     0x0e0b6002
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0x0) mlen 7 rlen 0 { align1 2Q };
+send(8)         g13<1>UD        g3<8,8,1>UD     0x02480038
+                            urb MsgDesc: 3 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         null<1>F        g7<8,8,1>F      0x140a0037
+                            urb MsgDesc: 3 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         g15<1>UD        g2<8,8,1>UD     0x02280038
+                            urb MsgDesc: 3 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080037
+                            urb MsgDesc: 3 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         null<1>F        g8<8,8,1>F      0x140a0007
+                            urb MsgDesc: 0 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g118<8,8,1>F    0x940a0007
+                            urb MsgDesc: 0 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT };
+send(8)         g116<1>UW       g0<8,8,1>F      0x021c0024
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 36, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g117<1>UW       g0<8,8,1>F      0x021c0025
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 37, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g118<1>UW       g0<8,8,1>F      0x021c0026
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 38, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g119<1>UW       g0<8,8,1>F      0x021c0027
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 39, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g120<1>UW       g0<8,8,1>F      0x021c0028
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 40, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g10<1>UD        g2<8,8,1>UD     0x02480048
+                            urb MsgDesc: 4 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         g6<1>UD         g2<8,8,1>UD     0x02480088
+                            urb MsgDesc: 8 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         g14<1>UD        g2<8,8,1>UD     0x02480058
+                            urb MsgDesc: 5 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         g11<1>UD        g2<8,8,1>UD     0x024800a8
+                            urb MsgDesc: 10 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g18<1>UD        g2<8,8,1>UD     0x02480068
+                            urb MsgDesc: 6 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         g16<1>UD        g2<8,8,1>UD     0x023800c8
+                            urb MsgDesc: 12 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g2<8,8,1>UD     0x02480078
+                            urb MsgDesc: 7 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x024800b8
+                            urb MsgDesc: 11 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g7<1>UD         g2<8,8,1>UD     0x02480098
+                            urb MsgDesc: 9 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x920800b7
+                            urb MsgDesc: 11 SIMD8 write mlen 9 rlen 0       { align1 1Q EOT };
+send(8)         g4<1>UW         g10<8,8,1>UD    0x084b0000
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g7<1>UW         g0<8,8,1>UD     0x02200008
+                            pixel interp MsgDesc: (persp, per_message_offset, 0x08) mlen 1 rlen 2 { align1 1Q };
+send(16)        g9<1>UW         g0<8,8,1>UD     0x02410008
+                            pixel interp MsgDesc: (persp, per_message_offset, 0x08) mlen 1 rlen 4 { align1 1H };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x0a4b1000
+                            sampler MsgDesc: gather4_po SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g74<1>UD        g2<8,8,1>UD     0x02280028
+                            urb MsgDesc: 2 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         g7<1>UD         g2<8,8,1>UD     0x02380028
+                            urb MsgDesc: 2 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         g15<1>UD        g2<8,8,1>UD     0x02380038
+                            urb MsgDesc: 3 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x0843e000
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g3<8,8,1>UD     0x0443d000
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g11<8,8,1>UD    0x0a4a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g19<8,8,1>UD    0x128c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         null<1>F        g2<8,8,1>F      0x0c0a0057
+                            urb MsgDesc: 5 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g9<8,8,1>UD     0x04080027
+                            urb MsgDesc: 2 SIMD8 write mlen 2 rlen 0        { align1 1Q };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x04429001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08849001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x08434102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(8)         g7<1>UW         g7<8,8,1>UD     0x024ab000
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         null<1>F        g50<8,8,1>F     0x140a0057
+                            urb MsgDesc: 5 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g60<8,8,1>F     0x140a0077
+                            urb MsgDesc: 7 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g70<8,8,1>F     0x0c0a0097
+                            urb MsgDesc: 9 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g122<8,8,1>F    0x8c0a0097
+                            urb MsgDesc: 9 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x08427005
+                            sampler MsgDesc: ld SIMD8 Surface = 5 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g10<8,8,1>UD    0x08427006
+                            sampler MsgDesc: ld SIMD8 Surface = 6 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g14<8,8,1>UD    0x08427007
+                            sampler MsgDesc: ld SIMD8 Surface = 7 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g18<8,8,1>UD    0x08427008
+                            sampler MsgDesc: ld SIMD8 Surface = 8 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g65<1>UW        g73<8,8,1>UD    0x10847005
+                            sampler MsgDesc: ld SIMD16 Surface = 5 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(16)        g32<1>UW        g81<8,8,1>UD    0x10847006
+                            sampler MsgDesc: ld SIMD16 Surface = 6 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(16)        g40<1>UW        g49<8,8,1>UD    0x10847007
+                            sampler MsgDesc: ld SIMD16 Surface = 7 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(16)        g48<1>UW        g57<8,8,1>UD    0x10847008
+                            sampler MsgDesc: ld SIMD16 Surface = 8 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x0a4b0000
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x064a3001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g9<8,8,1>UD     0x064a3102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0a8c3001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0a8c3102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 5 rlen 8 { align1 1H };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080077
+                            urb MsgDesc: 7 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         null<1>F        g30<8,8,1>UD    0x0c0a0067
+                            urb MsgDesc: 6 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0c0a0077
+                            urb MsgDesc: 7 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g42<8,8,1>UD    0x0c0a0087
+                            urb MsgDesc: 8 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x0a4a8001
+                            sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g16<1>UW        g7<8,8,1>UD     0x128c8001
+                            sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06420102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0c840102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x04420102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06420304
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08840102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0c840304
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 6 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x04420304
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06420708
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08840304
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0c840708
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x06421001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x0c841001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        g4<1>UD         g13<8,8,1>UD    0x02280301
+                            const MsgDesc: (1, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x06427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g11<8,8,1>UD    0x06425001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g14<8,8,1>UD    0x06425102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g21<8,8,1>UD    0x0c845001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g27<8,8,1>UD    0x0c845102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x06422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g17<8,8,1>UD    0x0c842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g38<1>UD        g2<8,8,1>UD     0x024800c8
+                            urb MsgDesc: 12 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g39<1>UD        g2<8,8,1>UD     0x024800d8
+                            urb MsgDesc: 13 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g40<1>UD        g2<8,8,1>UD     0x024800e8
+                            urb MsgDesc: 14 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g41<1>UD        g2<8,8,1>UD     0x024800f8
+                            urb MsgDesc: 15 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g42<1>UD        g2<8,8,1>UD     0x02480108
+                            urb MsgDesc: 16 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g43<1>UD        g2<8,8,1>UD     0x02480118
+                            urb MsgDesc: 17 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g44<1>UD        g2<8,8,1>UD     0x02480128
+                            urb MsgDesc: 18 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g45<1>UD        g2<8,8,1>UD     0x02480138
+                            urb MsgDesc: 19 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g46<1>UD        g2<8,8,1>UD     0x02480148
+                            urb MsgDesc: 20 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g47<1>UD        g2<8,8,1>UD     0x02480158
+                            urb MsgDesc: 21 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g48<1>UD        g2<8,8,1>UD     0x02480168
+                            urb MsgDesc: 22 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g49<1>UD        g2<8,8,1>UD     0x02480178
+                            urb MsgDesc: 23 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g50<1>UD        g2<8,8,1>UD     0x02480188
+                            urb MsgDesc: 24 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g51<1>UD        g2<8,8,1>UD     0x02480198
+                            urb MsgDesc: 25 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g52<1>UD        g2<8,8,1>UD     0x024801a8
+                            urb MsgDesc: 26 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g53<1>UD        g2<8,8,1>UD     0x024801b8
+                            urb MsgDesc: 27 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g54<1>UD        g2<8,8,1>UD     0x024801c8
+                            urb MsgDesc: 28 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g55<1>UD        g2<8,8,1>UD     0x024801d8
+                            urb MsgDesc: 29 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g56<1>UD        g2<8,8,1>UD     0x024801e8
+                            urb MsgDesc: 30 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g57<1>UD        g2<8,8,1>UD     0x024801f8
+                            urb MsgDesc: 31 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c003e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 62, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c003d
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 61, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0029
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 41, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c002a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 42, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c002b
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 43, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c002c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 44, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c002d
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 45, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c002e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 46, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c002f
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 47, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0030
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 48, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0031
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 49, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0032
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 50, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0033
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 51, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0034
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 52, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0035
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 53, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0036
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 54, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0037
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 55, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0038
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 56, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c0039
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 57, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g2<1>UW         g0<8,8,1>F      0x021c003a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 58, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c003b
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 59, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g2<1>UW         g0<8,8,1>F      0x021c003c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 60, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x080a8027
+                            urb MsgDesc: 2 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g8<8,8,1>UD     0x0a0a8027
+                            urb MsgDesc: 2 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x0e424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g8<1>UD         g14<8,8,1>UD    0x044a0128
+                            urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g22<1>UD        g16<8,8,1>UD    0x044a0028
+                            urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x0a080017
+                            urb MsgDesc: 1 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g7<8,8,1>F      0x0a080057
+                            urb MsgDesc: 5 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         g4<1>UW         g2<8,8,1>UD     0x02406001
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x0a026001
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 5 rlen 0 { align1 1Q };
+send(16)        g6<1>UW         g2<8,8,1>UD     0x04805001
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 2 rlen 8 { align1 1H };
+(+f1.0) send(16) null<1>UW      g4<8,8,1>UD     0x14025001
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 10 rlen 0 { align1 1H };
+send(8)         g3<1>UW         g7<8,8,1>UD     0x08427002
+                            sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g3<1>UW         g11<8,8,1>UD    0x10847002
+                            sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g12<8,8,1>UD    0x084b0001
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x0e8d0001
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g17<8,8,1>UD    0x0e434102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 7 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g10<8,8,1>UD    0x064a8202
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x084a8101
+                            sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x08422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g15<8,8,1>UD    0x10842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         null<1>F        g122<8,8,1>F    0x8c0a0037
+                            urb MsgDesc: 3 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         null<1>F        g10<8,8,1>F     0x12080027
+                            urb MsgDesc: 2 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080047
+                            urb MsgDesc: 4 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         g14<1>UW        g2<8,8,1>UD     0x06422000
+                            sampler MsgDesc: sample_l SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g61<1>UD        g107<8,8,1>UD   0x02380048
+                            urb MsgDesc: 4 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         g64<1>UD        g113<8,8,1>UD   0x02380058
+                            urb MsgDesc: 5 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080047
+                            urb MsgDesc: 4 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         null<1>UW       g2<8,8,1>UD     0x04009b00
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, imin) mlen 2 rlen 0 { align1 1Q };
+send(8)         g5<1>UW         g4<8,8,1>UD     0x08495001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 4 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x08496001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 4 rlen 4 { align1 2Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080077
+                            urb MsgDesc: 7 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         g12<1>UD        g8<4,4,1>UD     0x044a0038
+                            urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g21<1>UD        g8<4,4,1>UD     0x044a0048
+                            urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0c0a00a7
+                            urb MsgDesc: 10 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g56<8,8,1>F     0x140a0097
+                            urb MsgDesc: 9 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g76<8,8,1>F     0x0c0a00b7
+                            urb MsgDesc: 11 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g122<8,8,1>F    0x8c0a00b7
+                            urb MsgDesc: 11 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a080007
+                            urb MsgDesc: 0 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         g2<1>UW         g9<8,8,1>UD     0x08423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g16<1>UW        g8<8,8,1>UD     0x10843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g11<8,8,1>UD    0x06426001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g14<8,8,1>UD    0x06426102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g21<8,8,1>UD    0x0c846001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g27<8,8,1>UD    0x0c846102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x0a421001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g9<8,8,1>UD     0x14841001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x08843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g4<1>UW         g0<8,8,1>UD     0x02201000
+                            pixel interp MsgDesc: (persp, sample_position, 0x00) mlen 1 rlen 2 { align1 1Q };
+send(16)        g6<1>UW         g0<8,8,1>UD     0x02411000
+                            pixel interp MsgDesc: (persp, sample_position, 0x00) mlen 1 rlen 4 { align1 1H };
+send(8)         g124<1>UW       g14<8,8,1>UD    0x0a4b0001
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x128d0001
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         null<1>F        g118<8,8,1>F    0x940a0037
+                            urb MsgDesc: 3 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT };
+send(8)         g8<1>UD         g15<8,8,1>UD    0x042a0138
+                            urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g10<1>UD        g15<8,8,1>UD    0x042a0338
+                            urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g12<1>UD        g15<8,8,1>UD    0x042a0538
+                            urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g14<1>UD        g15<8,8,1>UD    0x042a0738
+                            urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g8<1>UD         g15<8,8,1>UD    0x042a0038
+                            urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g10<1>UD        g15<8,8,1>UD    0x042a0238
+                            urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g12<1>UD        g15<8,8,1>UD    0x042a0438
+                            urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g14<1>UD        g15<8,8,1>UD    0x042a0638
+                            urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g35<8,8,1>UD    0x02480228
+                            urb MsgDesc: 34 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g8<1>UD         g35<8,8,1>UD    0x02480428
+                            urb MsgDesc: 66 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g35<8,8,1>UD    0x02480628
+                            urb MsgDesc: 98 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a0a8037
+                            urb MsgDesc: 3 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x0a0a8047
+                            urb MsgDesc: 4 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0a0a8057
+                            urb MsgDesc: 5 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x0a0a8067
+                            urb MsgDesc: 6 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x0a0a8077
+                            urb MsgDesc: 7 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x0a0a8087
+                            urb MsgDesc: 8 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0a0a8097
+                            urb MsgDesc: 9 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0a0a80a7
+                            urb MsgDesc: 10 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0a0a80b7
+                            urb MsgDesc: 11 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0a0a80c7
+                            urb MsgDesc: 12 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0a0a80d7
+                            urb MsgDesc: 13 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0a0a80e7
+                            urb MsgDesc: 14 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0a0a80f7
+                            urb MsgDesc: 15 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0a0a8107
+                            urb MsgDesc: 16 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0a0a8117
+                            urb MsgDesc: 17 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0a0a8127
+                            urb MsgDesc: 18 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0a0a8137
+                            urb MsgDesc: 19 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0a0a8147
+                            urb MsgDesc: 20 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0a0a8157
+                            urb MsgDesc: 21 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0a0a8167
+                            urb MsgDesc: 22 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0a0a8177
+                            urb MsgDesc: 23 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0a0a8187
+                            urb MsgDesc: 24 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0a0a8197
+                            urb MsgDesc: 25 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0a0a81a7
+                            urb MsgDesc: 26 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0a0a81b7
+                            urb MsgDesc: 27 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0a0a81c7
+                            urb MsgDesc: 28 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0a0a81d7
+                            urb MsgDesc: 29 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0a0a81e7
+                            urb MsgDesc: 30 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0a0a81f7
+                            urb MsgDesc: 31 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0a0a8207
+                            urb MsgDesc: 32 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g122<8,8,1>F    0x8c0a0027
+                            urb MsgDesc: 2 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x06429001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g12<8,8,1>UD    0x0c849001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g5<1>UW         g17<8,8,1>UD    0x06427102
+                            sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g21<1>UW        g7<8,8,1>UD     0x0c847102
+                            sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        g118<8,8,1>F    0x940a0027
+                            urb MsgDesc: 2 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT };
+send(8)         null<1>F        g2<8,8,1>F      0x12080067
+                            urb MsgDesc: 6 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080087
+                            urb MsgDesc: 8 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         g21<1>UD        g2<8,8,1>UD     0x02380068
+                            urb MsgDesc: 6 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         g35<1>UD        g2<8,8,1>UD     0x02380088
+                            urb MsgDesc: 8 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         null<1>F        g5<8,8,1>F      0x140a0067
+                            urb MsgDesc: 6 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g118<8,8,1>F    0x940a0067
+                            urb MsgDesc: 6 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x08847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g5<8,8,1>UD     0x08425001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x10845001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         null<1>F        g123<8,8,1>F    0x8a0800d7
+                            urb MsgDesc: 13 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(8)         g22<1>UW        g14<8,8,1>UD    0x064a8405
+                            sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x084a8102
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g10<8,8,1>UD    0x084a8203
+                            sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g26<8,8,1>UD    0x0a4a8304
+                            sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 3 mlen 5 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g43<8,8,1>UD    0x0a8c8405
+                            sampler MsgDesc: gather4 SIMD16 Surface = 5 Sampler = 4 mlen 5 rlen 8 { align1 1H };
+send(16)        g43<1>UW        g7<8,8,1>UD     0x0e8c8102
+                            sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g51<8,8,1>UD    0x0e8c8203
+                            sampler MsgDesc: gather4 SIMD16 Surface = 3 Sampler = 2 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g26<8,8,1>UD    0x128c8304
+                            sampler MsgDesc: gather4 SIMD16 Surface = 4 Sampler = 3 mlen 9 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x0e4a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g10<8,8,1>UD    0x084a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g17<8,8,1>UD    0x0e8c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g9<8,8,1>UD     0x0a422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x14842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(16)        null<1>UW       g2<8,8,1>UD     0x04008601
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, dec) mlen 2 rlen 0 { align1 1H };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x08426001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x08426102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x10846001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g19<8,8,1>UD    0x10846102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+send(8)         null<1>F        g18<8,8,1>UD    0x0e0a8047
+                            urb MsgDesc: 4 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q };
+send(8)         g9<1>UD         g34<8,8,1>UD    0x02480218
+                            urb MsgDesc: 33 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g17<1>UD        g34<8,8,1>UD    0x02480238
+                            urb MsgDesc: 35 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g2<1>UD         g6<8,8,1>UD     0x041a0128
+                            urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g22<1>UD        g8<8,8,1>UD     0x041a0028
+                            urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         null<1>F        g2<8,8,1>UD     0x06088027
+                            urb MsgDesc: 2 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x06088037
+                            urb MsgDesc: 3 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x06088047
+                            urb MsgDesc: 4 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x06088057
+                            urb MsgDesc: 5 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x06088067
+                            urb MsgDesc: 6 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x06088077
+                            urb MsgDesc: 7 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x06088087
+                            urb MsgDesc: 8 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x06088097
+                            urb MsgDesc: 9 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x060880a7
+                            urb MsgDesc: 10 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x060880b7
+                            urb MsgDesc: 11 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x060880c7
+                            urb MsgDesc: 12 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x060880d7
+                            urb MsgDesc: 13 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x060880e7
+                            urb MsgDesc: 14 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x060880f7
+                            urb MsgDesc: 15 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x06088107
+                            urb MsgDesc: 16 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x06088117
+                            urb MsgDesc: 17 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x06088127
+                            urb MsgDesc: 18 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x06088137
+                            urb MsgDesc: 19 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x06088147
+                            urb MsgDesc: 20 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x06088157
+                            urb MsgDesc: 21 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x06088167
+                            urb MsgDesc: 22 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x06088177
+                            urb MsgDesc: 23 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x06088187
+                            urb MsgDesc: 24 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x06088197
+                            urb MsgDesc: 25 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x060881a7
+                            urb MsgDesc: 26 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x060881b7
+                            urb MsgDesc: 27 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x060881c7
+                            urb MsgDesc: 28 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x060881d7
+                            urb MsgDesc: 29 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x060881e7
+                            urb MsgDesc: 30 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x060881f7
+                            urb MsgDesc: 31 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x02406000
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 1Q };
+send(8)         g23<1>UW        g11<8,8,1>UD    0x06195e01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 3 rlen 1 { align1 1Q };
+send(8)         null<1>UW       g24<8,8,1>UD    0x080b5e01
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1Q };
+send(8)         g39<1>UW        g17<8,8,1>UD    0x06196e01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 3 rlen 1 { align1 2Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x080b6e01
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g11<8,8,1>UD    0x06098501
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, inc) mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06099501
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, inc) mlen 3 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g24<8,8,1>UD    0x08098c01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, umax) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099c01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, umax) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g24<8,8,1>UD    0x08098401
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, mov) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099401
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, mov) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g26<8,8,1>UD    0x0a098e01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, cmpwr) mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g14<8,8,1>UD    0x0a099e01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, cmpwr) mlen 5 rlen 0 { align1 2Q };
+send(8)         g6<1>UW         g8<8,8,1>UD     0x04423102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x08843102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(8)         g6<1>UD         g22<8,8,1>UD    0x044a0318
+                            urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g10<1>UD        g22<8,8,1>UD    0x044a0518
+                            urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g14<1>UD        g22<8,8,1>UD    0x044a0718
+                            urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g18<1>UD        g22<8,8,1>UD    0x044a0918
+                            urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g13<1>UD        g29<8,8,1>UD    0x044a0218
+                            urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g17<1>UD        g29<8,8,1>UD    0x044a0418
+                            urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g21<1>UD        g29<8,8,1>UD    0x044a0618
+                            urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g25<1>UD        g29<8,8,1>UD    0x044a0818
+                            urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0c0a0217
+                            urb MsgDesc: 33 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0c0a0227
+                            urb MsgDesc: 34 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x0c0a0237
+                            urb MsgDesc: 35 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x0c0a0247
+                            urb MsgDesc: 36 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x0c0a0257
+                            urb MsgDesc: 37 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0c0a0267
+                            urb MsgDesc: 38 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0c0a0277
+                            urb MsgDesc: 39 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0c0a0287
+                            urb MsgDesc: 40 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0c0a0297
+                            urb MsgDesc: 41 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0c0a02a7
+                            urb MsgDesc: 42 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0c0a02b7
+                            urb MsgDesc: 43 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0c0a02c7
+                            urb MsgDesc: 44 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0c0a02d7
+                            urb MsgDesc: 45 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0c0a02e7
+                            urb MsgDesc: 46 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0c0a02f7
+                            urb MsgDesc: 47 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0c0a0307
+                            urb MsgDesc: 48 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0c0a0317
+                            urb MsgDesc: 49 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0c0a0327
+                            urb MsgDesc: 50 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0c0a0337
+                            urb MsgDesc: 51 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0c0a0347
+                            urb MsgDesc: 52 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0c0a0357
+                            urb MsgDesc: 53 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0c0a0367
+                            urb MsgDesc: 54 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0c0a0377
+                            urb MsgDesc: 55 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0c0a0387
+                            urb MsgDesc: 56 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0c0a0397
+                            urb MsgDesc: 57 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0c0a03a7
+                            urb MsgDesc: 58 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0c0a03b7
+                            urb MsgDesc: 59 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0c0a03c7
+                            urb MsgDesc: 60 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0c0a03d7
+                            urb MsgDesc: 61 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x0c0a03e7
+                            urb MsgDesc: 62 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g41<8,8,1>UD    0x0c0a03f7
+                            urb MsgDesc: 63 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0a080067
+                            urb MsgDesc: 6 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0a080077
+                            urb MsgDesc: 7 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0a080087
+                            urb MsgDesc: 8 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0a080097
+                            urb MsgDesc: 9 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0a0800a7
+                            urb MsgDesc: 10 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0a0800b7
+                            urb MsgDesc: 11 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0a0800c7
+                            urb MsgDesc: 12 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0a0800d7
+                            urb MsgDesc: 13 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0a0800e7
+                            urb MsgDesc: 14 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0a0800f7
+                            urb MsgDesc: 15 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0a080107
+                            urb MsgDesc: 16 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0a080117
+                            urb MsgDesc: 17 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0a080127
+                            urb MsgDesc: 18 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0a080137
+                            urb MsgDesc: 19 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0a080147
+                            urb MsgDesc: 20 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0a080157
+                            urb MsgDesc: 21 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0a080167
+                            urb MsgDesc: 22 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0a080177
+                            urb MsgDesc: 23 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0a080187
+                            urb MsgDesc: 24 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0a080197
+                            urb MsgDesc: 25 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0a0801a7
+                            urb MsgDesc: 26 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0a0801b7
+                            urb MsgDesc: 27 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0a0801c7
+                            urb MsgDesc: 28 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0a0801d7
+                            urb MsgDesc: 29 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x0a0801e7
+                            urb MsgDesc: 30 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g41<8,8,1>UD    0x0a0801f7
+                            urb MsgDesc: 31 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         g124<1>UW       g5<8,8,1>UD     0x064a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x0a8c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06423102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g26<8,8,1>UD    0x0c843102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g9<8,8,1>UD     0x08420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x10840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g5<1>UW         g15<8,8,1>UD    0x04420203
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g27<8,8,1>UD    0x08840203
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 8 { align1 1H };
+send(16)        g4<1>UW         g17<8,8,1>UD    0x0420a503
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 3, SIMD16, inc) mlen 2 rlen 2 { align1 1H };
+send(16)        null<1>UW       g18<8,8,1>UD    0x04008504
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 4, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(16)        g11<1>UW        g19<8,8,1>UD    0x0420a602
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, dec) mlen 2 rlen 2 { align1 1H };
+send(16)        null<1>UW       g20<8,8,1>UD    0x04008505
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 5, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(16)        g16<1>UW        g21<8,8,1>UD    0x04205e01
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+send(16)        null<1>UW       g22<8,8,1>UD    0x04008506
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 6, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(8)         g26<1>UW        g26<8,8,1>UD    0x0242a203
+                            sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 1Q };
+send(8)         g30<1>UW        g30<8,8,1>UD    0x0242a304
+                            sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 4 { align1 1Q };
+send(8)         g34<1>UW        g34<8,8,1>UD    0x0242a405
+                            sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 4 { align1 1Q };
+send(8)         g38<1>UW        g38<8,8,1>UD    0x0242a506
+                            sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g25<8,8,1>UD    0x0242a102
+                            sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(8)         g42<1>UW        g42<8,8,1>UD    0x0242a607
+                            sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 6 mlen 1 rlen 4 { align1 1Q };
+send(8)         g46<1>UW        g46<8,8,1>UD    0x0242a708
+                            sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 7 mlen 1 rlen 4 { align1 1Q };
+send(8)         g50<1>UW        g50<8,8,1>UD    0x0242a809
+                            sampler MsgDesc: resinfo SIMD8 Surface = 9 Sampler = 8 mlen 1 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g54<8,8,1>UD    0x0242a90a
+                            sampler MsgDesc: resinfo SIMD8 Surface = 10 Sampler = 9 mlen 1 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g55<8,8,1>UD    0x0242aa0b
+                            sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 10 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g56<8,8,1>UD    0x0242ab0c
+                            sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 11 mlen 1 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g57<8,8,1>UD    0x0242ac0d
+                            sampler MsgDesc: resinfo SIMD8 Surface = 13 Sampler = 12 mlen 1 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0484a102
+                            sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H };
+send(16)        g82<1>UW        g110<8,8,1>UD   0x0484aa0b
+                            sampler MsgDesc: resinfo SIMD16 Surface = 11 Sampler = 10 mlen 2 rlen 8 { align1 1H };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x0484a203
+                            sampler MsgDesc: resinfo SIMD16 Surface = 3 Sampler = 2 mlen 2 rlen 8 { align1 1H };
+send(16)        g90<1>UW        g112<8,8,1>UD   0x0484ab0c
+                            sampler MsgDesc: resinfo SIMD16 Surface = 12 Sampler = 11 mlen 2 rlen 8 { align1 1H };
+send(16)        g98<1>UW        g106<8,8,1>UD   0x0484ac0d
+                            sampler MsgDesc: resinfo SIMD16 Surface = 13 Sampler = 12 mlen 2 rlen 8 { align1 1H };
+send(16)        g26<1>UW        g34<8,8,1>UD    0x0484a304
+                            sampler MsgDesc: resinfo SIMD16 Surface = 4 Sampler = 3 mlen 2 rlen 8 { align1 1H };
+send(16)        g34<1>UW        g42<8,8,1>UD    0x0484a405
+                            sampler MsgDesc: resinfo SIMD16 Surface = 5 Sampler = 4 mlen 2 rlen 8 { align1 1H };
+send(16)        g42<1>UW        g50<8,8,1>UD    0x0484a506
+                            sampler MsgDesc: resinfo SIMD16 Surface = 6 Sampler = 5 mlen 2 rlen 8 { align1 1H };
+send(16)        g50<1>UW        g58<8,8,1>UD    0x0484a607
+                            sampler MsgDesc: resinfo SIMD16 Surface = 7 Sampler = 6 mlen 2 rlen 8 { align1 1H };
+send(16)        g58<1>UW        g66<8,8,1>UD    0x0484a708
+                            sampler MsgDesc: resinfo SIMD16 Surface = 8 Sampler = 7 mlen 2 rlen 8 { align1 1H };
+send(16)        g66<1>UW        g74<8,8,1>UD    0x0484a809
+                            sampler MsgDesc: resinfo SIMD16 Surface = 9 Sampler = 8 mlen 2 rlen 8 { align1 1H };
+send(16)        g74<1>UW        g108<8,8,1>UD   0x0484a90a
+                            sampler MsgDesc: resinfo SIMD16 Surface = 10 Sampler = 9 mlen 2 rlen 8 { align1 1H };
+send(16)        null<1>UW       g1<8,8,1>UD     0x040085fe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(16)        null<1>UW       g1<8,8,1>UD     0x08008dfe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, umin) mlen 4 rlen 0 { align1 1H };
+send(16)        null<1>UW       g5<8,8,1>UD     0x08008bfe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, imin) mlen 4 rlen 0 { align1 1H };
+send(16)        null<1>UW       g1<8,8,1>UD     0x08008cfe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, umax) mlen 4 rlen 0 { align1 1H };
+send(16)        null<1>UW       g5<8,8,1>UD     0x08008afe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, imax) mlen 4 rlen 0 { align1 1H };
+send(16)        null<1>UW       g1<8,8,1>UD     0x080081fe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, and) mlen 4 rlen 0 { align1 1H };
+send(16)        null<1>UW       g1<8,8,1>UD     0x080082fe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, or) mlen 4 rlen 0 { align1 1H };
+send(16)        null<1>UW       g1<8,8,1>UD     0x080083fe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, xor) mlen 4 rlen 0 { align1 1H };
+send(16)        null<1>UW       g1<8,8,1>UD     0x080084fe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, mov) mlen 4 rlen 0 { align1 1H };
+send(16)        null<1>UW       g1<8,8,1>UD     0x0c008efe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, cmpwr) mlen 6 rlen 0 { align1 1H };
+send(8)         null<1>F        g119<8,8,1>F    0x92080067
+                            urb MsgDesc: 6 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         g124<1>UW       g11<8,8,1>UD    0x12424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 4 { align1 1Q };
+send(16)        g1<1>UW         g14<8,8,1>UD    0x0820a4fe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, mov) mlen 4 rlen 2 { align1 1H };
+send(16)        g13<1>UW        g17<8,8,1>UD    0x0820a2fe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, or) mlen 4 rlen 2 { align1 1H };
+send(16)        null<1>UW       g123<8,8,1>UD   0x060a03fd
+                            data MsgDesc: ( DC OWORD block write, 253, 3) mlen 3 rlen 0 { align1 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1000
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 0, 16) mlen 1 rlen 2           { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1002
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 2, 16) mlen 1 rlen 2           { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1012
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 18, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1014
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 20, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1004
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 4, 16) mlen 1 rlen 2           { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1006
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 6, 16) mlen 1 rlen 2           { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1016
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 22, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1018
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 24, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1008
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 8, 16) mlen 1 rlen 2           { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c100a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 10, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c101a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 26, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c101c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 28, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c100c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 12, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c100e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 14, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c101e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 30, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1022
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 34, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1010
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 16, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1020
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 32, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1024
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 36, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c102a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 42, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1026
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 38, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1028
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 40, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c102c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 44, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1032
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 50, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c102e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 46, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1030
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 48, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1034
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 52, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c103a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 58, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1036
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 54, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1038
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 56, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c103c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 60, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1042
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 66, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c103e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 62, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1040
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 64, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1044
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 68, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c104a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 74, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1046
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 70, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1048
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 72, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c104c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 76, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1052
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 82, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c104e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 78, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1050
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 80, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1054
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 84, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c105a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 90, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1056
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 86, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1058
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 88, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c105c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 92, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1062
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 98, 16) mlen 1 rlen 2          { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c105e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 94, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1060
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 96, 16) mlen 1 rlen 2          { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1064
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 100, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c106a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 106, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1066
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 102, 16) mlen 1 rlen 2         { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1068
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 104, 16) mlen 1 rlen 2         { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c106c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 108, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1072
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 114, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c106e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 110, 16) mlen 1 rlen 2         { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1070
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 112, 16) mlen 1 rlen 2         { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1074
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 116, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c107a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 122, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1076
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 118, 16) mlen 1 rlen 2         { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1078
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 120, 16) mlen 1 rlen 2         { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c107c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 124, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1082
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 130, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c107e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 126, 16) mlen 1 rlen 2         { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1080
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 128, 16) mlen 1 rlen 2         { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1084
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 132, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c108a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 138, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c1086
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 134, 16) mlen 1 rlen 2         { align1 WE_all 2H };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c1088
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 136, 16) mlen 1 rlen 2         { align1 WE_all 2H };
+send(16)        g4<1>UW         g0<8,8,1>F      0x022c108c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 140, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(8)         null<1>F        g12<8,8,1>UD    0x0c0a0127
+                            urb MsgDesc: 18 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         g2<1>UW         g11<8,8,1>UD    0x04420405
+                            sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x04420506
+                            sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x04420607
+                            sampler MsgDesc: sample SIMD8 Surface = 7 Sampler = 6 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g14<8,8,1>UD    0x04420708
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g15<8,8,1>UD    0x04420809
+                            sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 8 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g16<8,8,1>UD    0x0442090a
+                            sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 9 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g17<8,8,1>UD    0x04420a0b
+                            sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 10 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g18<8,8,1>UD    0x04420b0c
+                            sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 11 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g19<8,8,1>UD    0x04420c0d
+                            sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 12 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g20<8,8,1>UD    0x04420d0e
+                            sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 13 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g21<8,8,1>UD    0x04420e0f
+                            sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 14 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g22<8,8,1>UD    0x04420f10
+                            sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0011
+                            sampler MsgDesc: sample SIMD8 Surface = 17 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0112
+                            sampler MsgDesc: sample SIMD8 Surface = 18 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0213
+                            sampler MsgDesc: sample SIMD8 Surface = 19 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0314
+                            sampler MsgDesc: sample SIMD8 Surface = 20 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0415
+                            sampler MsgDesc: sample SIMD8 Surface = 21 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0516
+                            sampler MsgDesc: sample SIMD8 Surface = 22 Sampler = 5 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0617
+                            sampler MsgDesc: sample SIMD8 Surface = 23 Sampler = 6 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0718
+                            sampler MsgDesc: sample SIMD8 Surface = 24 Sampler = 7 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0819
+                            sampler MsgDesc: sample SIMD8 Surface = 25 Sampler = 8 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a091a
+                            sampler MsgDesc: sample SIMD8 Surface = 26 Sampler = 9 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0a1b
+                            sampler MsgDesc: sample SIMD8 Surface = 27 Sampler = 10 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0b1c
+                            sampler MsgDesc: sample SIMD8 Surface = 28 Sampler = 11 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0c1d
+                            sampler MsgDesc: sample SIMD8 Surface = 29 Sampler = 12 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0d1e
+                            sampler MsgDesc: sample SIMD8 Surface = 30 Sampler = 13 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0e1f
+                            sampler MsgDesc: sample SIMD8 Surface = 31 Sampler = 14 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0f20
+                            sampler MsgDesc: sample SIMD8 Surface = 32 Sampler = 15 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g28<8,8,1>UD    0x08840405
+                            sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g29<8,8,1>UD    0x08840506
+                            sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g30<8,8,1>UD    0x08840607
+                            sampler MsgDesc: sample SIMD16 Surface = 7 Sampler = 6 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g31<8,8,1>UD    0x08840708
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g32<8,8,1>UD    0x08840809
+                            sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 8 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g33<8,8,1>UD    0x0884090a
+                            sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 9 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g34<8,8,1>UD    0x08840a0b
+                            sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 10 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g35<8,8,1>UD    0x08840b0c
+                            sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 11 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g36<8,8,1>UD    0x08840c0d
+                            sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 12 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g37<8,8,1>UD    0x08840d0e
+                            sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 13 mlen 4 rlen 8 { align1 1H };
+send(16)        g7<1>UW         g38<8,8,1>UD    0x08840e0f
+                            sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 14 mlen 4 rlen 8 { align1 1H };
+send(16)        g23<1>UW        g39<8,8,1>UD    0x08840f10
+                            sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 4 rlen 8 { align1 1H };
+send(16)        g17<1>UW        g2<8,8,1>UD     0x0a8c0011
+                            sampler MsgDesc: sample SIMD16 Surface = 17 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(16)        g29<1>UW        g7<8,8,1>UD     0x0a8c0112
+                            sampler MsgDesc: sample SIMD16 Surface = 18 Sampler = 1 mlen 5 rlen 8 { align1 1H };
+send(16)        g27<1>UW        g12<8,8,1>UD    0x0a8c0213
+                            sampler MsgDesc: sample SIMD16 Surface = 19 Sampler = 2 mlen 5 rlen 8 { align1 1H };
+send(16)        g32<1>UW        g17<8,8,1>UD    0x0a8c0314
+                            sampler MsgDesc: sample SIMD16 Surface = 20 Sampler = 3 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g22<8,8,1>UD    0x0a8c0415
+                            sampler MsgDesc: sample SIMD16 Surface = 21 Sampler = 4 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g27<8,8,1>UD    0x0a8c0516
+                            sampler MsgDesc: sample SIMD16 Surface = 22 Sampler = 5 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g32<8,8,1>UD    0x0a8c0617
+                            sampler MsgDesc: sample SIMD16 Surface = 23 Sampler = 6 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g37<8,8,1>UD    0x0a8c0718
+                            sampler MsgDesc: sample SIMD16 Surface = 24 Sampler = 7 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g42<8,8,1>UD    0x0a8c0819
+                            sampler MsgDesc: sample SIMD16 Surface = 25 Sampler = 8 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g47<8,8,1>UD    0x0a8c091a
+                            sampler MsgDesc: sample SIMD16 Surface = 26 Sampler = 9 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g52<8,8,1>UD    0x0a8c0a1b
+                            sampler MsgDesc: sample SIMD16 Surface = 27 Sampler = 10 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g57<8,8,1>UD    0x0a8c0b1c
+                            sampler MsgDesc: sample SIMD16 Surface = 28 Sampler = 11 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g62<8,8,1>UD    0x0a8c0c1d
+                            sampler MsgDesc: sample SIMD16 Surface = 29 Sampler = 12 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g67<8,8,1>UD    0x0a8c0d1e
+                            sampler MsgDesc: sample SIMD16 Surface = 30 Sampler = 13 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g72<8,8,1>UD    0x0a8c0e1f
+                            sampler MsgDesc: sample SIMD16 Surface = 31 Sampler = 14 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g77<8,8,1>UD    0x0a8c0f20
+                            sampler MsgDesc: sample SIMD16 Surface = 32 Sampler = 15 mlen 5 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g2<8,8,1>UD     0x02420102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g2<8,8,1>UD     0x04840102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H };
+send(8)         null<1>UW       g10<8,8,1>UD    0x0a026000
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 0, SIMD8, Mask = 0x0) mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g8<8,8,1>UD     0x0c0a8027
+                            urb MsgDesc: 2 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>F     0x12080047
+                            urb MsgDesc: 4 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080087
+                            urb MsgDesc: 8 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         g2<1>UW         g74<8,8,1>UD    0x02106e02
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(8)         null<1>UW       g1<8,8,1>UD     0x04026efe
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 254, SIMD8, Mask = 0xe) mlen 2 rlen 0 { align1 1Q };
+send(8)         g67<1>UW        g2<8,8,1>UD     0x0410bdfe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD8, umin) mlen 2 rlen 1 { align1 1Q };
+send(8)         g68<1>UW        g2<8,8,1>UD     0x02106efe
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 254, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(8)         g73<1>UW        g4<8,8,1>UD     0x0410b4fe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD8, mov) mlen 2 rlen 1 { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080097
+                            urb MsgDesc: 9 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         g29<1>UW        g5<8,8,1>UD     0x0e4b2001
+                            sampler MsgDesc: gather4_po_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x084a2001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x0e8c2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g5<8,8,1>UD     0x0a426001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g10<8,8,1>UD    0x0a426102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g15<8,8,1>UD    0x14846001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g25<8,8,1>UD    0x14846102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H };
+send(8)         null<1>F        g14<8,8,1>UD    0x0c0a8037
+                            urb MsgDesc: 3 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x0c0a8047
+                            urb MsgDesc: 4 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0c0a8057
+                            urb MsgDesc: 5 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x084a5001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x084a5102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x0e8c5001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0e8c5102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(16)        g1<1>UW         g7<8,8,1>UD     0x0820a7fe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, add) mlen 4 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x084a3001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g10<8,8,1>UD    0x084a3102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0e8c3001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0e8c3102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x044a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g4<8,8,1>UD     0x068c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 8 { align1 1H };
+send(8)         g17<1>UW        g12<8,8,1>UD    0x04420003
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g39<8,8,1>UD    0x08840003
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g11<1>UW        g39<8,8,1>UD    0x06427008
+                            sampler MsgDesc: ld SIMD8 Surface = 8 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g15<1>UW        g39<8,8,1>UD    0x06427109
+                            sampler MsgDesc: ld SIMD8 Surface = 9 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(8)         g19<1>UW        g39<8,8,1>UD    0x0642720a
+                            sampler MsgDesc: ld SIMD8 Surface = 10 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(8)         g23<1>UW        g39<8,8,1>UD    0x0642730b
+                            sampler MsgDesc: ld SIMD8 Surface = 11 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(8)         g27<1>UW        g39<8,8,1>UD    0x0642740c
+                            sampler MsgDesc: ld SIMD8 Surface = 12 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
+send(8)         g31<1>UW        g39<8,8,1>UD    0x0642750d
+                            sampler MsgDesc: ld SIMD8 Surface = 13 Sampler = 5 mlen 3 rlen 4 { align1 1Q };
+send(8)         g35<1>UW        g39<8,8,1>UD    0x0642760e
+                            sampler MsgDesc: ld SIMD8 Surface = 14 Sampler = 6 mlen 3 rlen 4 { align1 1Q };
+send(8)         g39<1>UW        g39<8,8,1>UD    0x0642770f
+                            sampler MsgDesc: ld SIMD8 Surface = 15 Sampler = 7 mlen 3 rlen 4 { align1 1Q };
+send(16)        g67<1>UW        g93<8,8,1>UD    0x0c847008
+                            sampler MsgDesc: ld SIMD16 Surface = 8 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        g27<1>UW        g93<8,8,1>UD    0x0c847109
+                            sampler MsgDesc: ld SIMD16 Surface = 9 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(16)        g37<1>UW        g93<8,8,1>UD    0x0c84720a
+                            sampler MsgDesc: ld SIMD16 Surface = 10 Sampler = 2 mlen 6 rlen 8 { align1 1H };
+send(16)        g47<1>UW        g93<8,8,1>UD    0x0c84730b
+                            sampler MsgDesc: ld SIMD16 Surface = 11 Sampler = 3 mlen 6 rlen 8 { align1 1H };
+send(16)        g57<1>UW        g93<8,8,1>UD    0x0c84740c
+                            sampler MsgDesc: ld SIMD16 Surface = 12 Sampler = 4 mlen 6 rlen 8 { align1 1H };
+send(16)        g17<1>UW        g93<8,8,1>UD    0x0c84750d
+                            sampler MsgDesc: ld SIMD16 Surface = 13 Sampler = 5 mlen 6 rlen 8 { align1 1H };
+send(16)        g85<1>UW        g93<8,8,1>UD    0x0c84760e
+                            sampler MsgDesc: ld SIMD16 Surface = 14 Sampler = 6 mlen 6 rlen 8 { align1 1H };
+send(16)        g77<1>UW        g93<8,8,1>UD    0x0c84770f
+                            sampler MsgDesc: ld SIMD16 Surface = 15 Sampler = 7 mlen 6 rlen 8 { align1 1H };
+send(16)        g81<1>UW        g84<8,8,1>UD    0x04205e00
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+send(8)         null<1>F        g122<8,8,1>F    0x8c0a0047
+                            urb MsgDesc: 4 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g124<1>UW       g8<8,8,1>UD     0x064a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g15<8,8,1>UD    0x0a8c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         g14<1>UW        g11<8,8,1>UD    0x084b0202
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x0a4b0101
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(8)         null<1>F        g3<8,8,1>F      0x12080087
+                            urb MsgDesc: 8 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a0800a7
+                            urb MsgDesc: 10 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x084a6001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x084a6102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x0e8c6001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0e8c6102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(8)         g31<1>UD        g28<8,8,1>UD    0x02380238
+                            urb MsgDesc: 35 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g34<1>UD        g28<8,8,1>UD    0x02380438
+                            urb MsgDesc: 67 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g37<1>UD        g28<8,8,1>UD    0x02380638
+                            urb MsgDesc: 99 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g28<8,8,1>UD    0x02380248
+                            urb MsgDesc: 36 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g28<8,8,1>UD    0x02380448
+                            urb MsgDesc: 68 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g28<1>UD        g28<8,8,1>UD    0x02380648
+                            urb MsgDesc: 100 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g22<1>UD        g29<8,8,1>UD    0x02380258
+                            urb MsgDesc: 37 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g29<8,8,1>UD    0x02380458
+                            urb MsgDesc: 69 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g28<1>UD        g29<8,8,1>UD    0x02380658
+                            urb MsgDesc: 101 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g22<1>UD        g30<8,8,1>UD    0x02380268
+                            urb MsgDesc: 38 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g30<8,8,1>UD    0x02380468
+                            urb MsgDesc: 70 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g28<1>UD        g30<8,8,1>UD    0x02380668
+                            urb MsgDesc: 102 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g22<1>UD        g31<8,8,1>UD    0x02380278
+                            urb MsgDesc: 39 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g31<8,8,1>UD    0x02380478
+                            urb MsgDesc: 71 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g28<1>UD        g31<8,8,1>UD    0x02380678
+                            urb MsgDesc: 103 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g25<1>UD        g32<8,8,1>UD    0x02380488
+                            urb MsgDesc: 72 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g32<8,8,1>UD    0x02380288
+                            urb MsgDesc: 40 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g28<1>UD        g32<8,8,1>UD    0x02380688
+                            urb MsgDesc: 104 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g25<1>UD        g33<8,8,1>UD    0x02380498
+                            urb MsgDesc: 73 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g33<8,8,1>UD    0x02380298
+                            urb MsgDesc: 41 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g28<1>UD        g33<8,8,1>UD    0x02380698
+                            urb MsgDesc: 105 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g25<1>UD        g34<8,8,1>UD    0x023806a8
+                            urb MsgDesc: 106 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g34<8,8,1>UD    0x023802a8
+                            urb MsgDesc: 42 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g34<8,8,1>UD    0x023804a8
+                            urb MsgDesc: 74 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g8<1>UD         g35<8,8,1>UD    0x023802b8
+                            urb MsgDesc: 43 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g35<8,8,1>UD    0x023804b8
+                            urb MsgDesc: 75 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g35<8,8,1>UD    0x023806b8
+                            urb MsgDesc: 107 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g36<8,8,1>UD    0x023802c8
+                            urb MsgDesc: 44 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g36<8,8,1>UD    0x023804c8
+                            urb MsgDesc: 76 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g36<8,8,1>UD    0x023806c8
+                            urb MsgDesc: 108 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g37<8,8,1>UD    0x023802d8
+                            urb MsgDesc: 45 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g37<8,8,1>UD    0x023804d8
+                            urb MsgDesc: 77 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g37<8,8,1>UD    0x023806d8
+                            urb MsgDesc: 109 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g38<8,8,1>UD    0x023802e8
+                            urb MsgDesc: 46 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g38<8,8,1>UD    0x023804e8
+                            urb MsgDesc: 78 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g38<8,8,1>UD    0x023806e8
+                            urb MsgDesc: 110 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g39<8,8,1>UD    0x023802f8
+                            urb MsgDesc: 47 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g39<8,8,1>UD    0x023804f8
+                            urb MsgDesc: 79 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g39<8,8,1>UD    0x023806f8
+                            urb MsgDesc: 111 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g40<8,8,1>UD    0x02380308
+                            urb MsgDesc: 48 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g40<8,8,1>UD    0x02380508
+                            urb MsgDesc: 80 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g40<8,8,1>UD    0x02380708
+                            urb MsgDesc: 112 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g41<8,8,1>UD    0x02380318
+                            urb MsgDesc: 49 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g41<8,8,1>UD    0x02380518
+                            urb MsgDesc: 81 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g41<8,8,1>UD    0x02380718
+                            urb MsgDesc: 113 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g3<8,8,1>UD     0x02380328
+                            urb MsgDesc: 50 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g3<8,8,1>UD     0x02380528
+                            urb MsgDesc: 82 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g3<8,8,1>UD     0x02380728
+                            urb MsgDesc: 114 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g43<8,8,1>UD    0x02380338
+                            urb MsgDesc: 51 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g43<8,8,1>UD    0x02380538
+                            urb MsgDesc: 83 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g43<8,8,1>UD    0x02380738
+                            urb MsgDesc: 115 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g44<8,8,1>UD    0x02380348
+                            urb MsgDesc: 52 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g44<8,8,1>UD    0x02380548
+                            urb MsgDesc: 84 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g44<8,8,1>UD    0x02380748
+                            urb MsgDesc: 116 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g45<8,8,1>UD    0x02380358
+                            urb MsgDesc: 53 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g45<8,8,1>UD    0x02380558
+                            urb MsgDesc: 85 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g45<8,8,1>UD    0x02380758
+                            urb MsgDesc: 117 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g46<8,8,1>UD    0x02380368
+                            urb MsgDesc: 54 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g46<8,8,1>UD    0x02380568
+                            urb MsgDesc: 86 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g46<8,8,1>UD    0x02380768
+                            urb MsgDesc: 118 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g47<8,8,1>UD    0x02380378
+                            urb MsgDesc: 55 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g47<8,8,1>UD    0x02380578
+                            urb MsgDesc: 87 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g47<8,8,1>UD    0x02380778
+                            urb MsgDesc: 119 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g48<8,8,1>UD    0x02380388
+                            urb MsgDesc: 56 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g48<8,8,1>UD    0x02380588
+                            urb MsgDesc: 88 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g48<8,8,1>UD    0x02380788
+                            urb MsgDesc: 120 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g49<8,8,1>UD    0x02380398
+                            urb MsgDesc: 57 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g49<8,8,1>UD    0x02380598
+                            urb MsgDesc: 89 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g49<8,8,1>UD    0x02380798
+                            urb MsgDesc: 121 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g50<8,8,1>UD    0x023803a8
+                            urb MsgDesc: 58 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g50<8,8,1>UD    0x023805a8
+                            urb MsgDesc: 90 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g50<8,8,1>UD    0x023807a8
+                            urb MsgDesc: 122 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g54<8,8,1>UD    0x023803b8
+                            urb MsgDesc: 59 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g54<8,8,1>UD    0x023805b8
+                            urb MsgDesc: 91 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g54<8,8,1>UD    0x023807b8
+                            urb MsgDesc: 123 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g55<8,8,1>UD    0x023803c8
+                            urb MsgDesc: 60 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g55<8,8,1>UD    0x023805c8
+                            urb MsgDesc: 92 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g55<8,8,1>UD    0x023807c8
+                            urb MsgDesc: 124 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g56<8,8,1>UD    0x023803d8
+                            urb MsgDesc: 61 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g56<8,8,1>UD    0x023805d8
+                            urb MsgDesc: 93 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g56<8,8,1>UD    0x023807d8
+                            urb MsgDesc: 125 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g57<8,8,1>UD    0x023803e8
+                            urb MsgDesc: 62 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g57<8,8,1>UD    0x023805e8
+                            urb MsgDesc: 94 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g57<8,8,1>UD    0x023807e8
+                            urb MsgDesc: 126 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g58<8,8,1>UD    0x023803f8
+                            urb MsgDesc: 63 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g58<8,8,1>UD    0x023805f8
+                            urb MsgDesc: 95 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g58<8,8,1>UD    0x023807f8
+                            urb MsgDesc: 127 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g59<8,8,1>UD    0x02380208
+                            urb MsgDesc: 32 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g59<8,8,1>UD    0x02380408
+                            urb MsgDesc: 64 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g59<8,8,1>UD    0x02380608
+                            urb MsgDesc: 96 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g17<1>UD        g59<8,8,1>UD    0x02380808
+                            urb MsgDesc: 128 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g60<8,8,1>UD    0x02380218
+                            urb MsgDesc: 33 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g60<8,8,1>UD    0x02380418
+                            urb MsgDesc: 65 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g60<8,8,1>UD    0x02380618
+                            urb MsgDesc: 97 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g17<1>UD        g60<8,8,1>UD    0x02380818
+                            urb MsgDesc: 129 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x0c0a8067
+                            urb MsgDesc: 6 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x0c0a8077
+                            urb MsgDesc: 7 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0c0a8087
+                            urb MsgDesc: 8 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0c0a8097
+                            urb MsgDesc: 9 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0c0a80a7
+                            urb MsgDesc: 10 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0c0a80b7
+                            urb MsgDesc: 11 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0c0a80c7
+                            urb MsgDesc: 12 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0c0a80d7
+                            urb MsgDesc: 13 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0c0a80e7
+                            urb MsgDesc: 14 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0c0a80f7
+                            urb MsgDesc: 15 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0c0a8107
+                            urb MsgDesc: 16 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0c0a8117
+                            urb MsgDesc: 17 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0c0a8127
+                            urb MsgDesc: 18 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0c0a8137
+                            urb MsgDesc: 19 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0c0a8147
+                            urb MsgDesc: 20 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0c0a8157
+                            urb MsgDesc: 21 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0c0a8167
+                            urb MsgDesc: 22 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0c0a8177
+                            urb MsgDesc: 23 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0c0a8187
+                            urb MsgDesc: 24 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0c0a8197
+                            urb MsgDesc: 25 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0c0a81a7
+                            urb MsgDesc: 26 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0c0a81b7
+                            urb MsgDesc: 27 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0c0a81c7
+                            urb MsgDesc: 28 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0c0a81d7
+                            urb MsgDesc: 29 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0c0a81e7
+                            urb MsgDesc: 30 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0c0a81f7
+                            urb MsgDesc: 31 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x0c0a8207
+                            urb MsgDesc: 32 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g41<8,8,1>UD    0x0c0a8217
+                            urb MsgDesc: 33 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(1)         g1<1>UW         g1<0,1,0>UW     0x0209c000
+                            data MsgDesc: ( DC mfence, 0, 0) mlen 1 rlen 0  { align1 WE_all 1N };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x02106e01
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(16)        g11<1>UW        g19<8,8,1>UD    0x0420a601
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, dec) mlen 2 rlen 2 { align1 1H };
+send(16)        null<1>UW       g20<8,8,1>UD    0x04008503
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 3, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(8)         null<1>F        g122<8,8,1>UD   0x8c088007
+                            urb MsgDesc: 0 SIMD8 write masked mlen 6 rlen 0 { align1 1Q EOT };
+(+f1.0) send(8) null<1>UW       g6<8,8,1>UD     0x04026e01
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g6<8,8,1>UD     0x04026e02
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g8<8,8,1>UD     0x08025e01
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g8<8,8,1>UD     0x08025e02
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1H };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x0a4a5001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g17<8,8,1>UD    0x0a4a5102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g25<1>UW        g7<8,8,1>UD     0x128c5001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(16)        g33<1>UW        g16<8,8,1>UD    0x128c5102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x0c4b2001
+                            sampler MsgDesc: gather4_po_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g15<8,8,1>UD    0x168d2001
+                            sampler MsgDesc: gather4_po_c SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(8)         g54<1>UD        g7<8,8,1>UD     0x02280048
+                            urb MsgDesc: 4 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         g7<1>UW         g53<8,8,1>UD    0x02106e00
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(8)         null<1>UW       g53<8,8,1>UD    0x02009500
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, inc) mlen 1 rlen 0 { align1 1Q };
+send(8)         g7<1>UD         g37<8,8,1>UD    0x02480438
+                            urb MsgDesc: 67 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g11<1>UD        g37<8,8,1>UD    0x02480638
+                            urb MsgDesc: 99 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g13<1>UD        g14<8,8,1>UD    0x042a0148
+                            urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g14<8,8,1>UD    0x042a0048
+                            urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x124b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g16<8,8,1>UD    0x124b4102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 9 rlen 4 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x02380078
+                            urb MsgDesc: 7 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x0a4a2001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g9<8,8,1>UD     0x128c2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         g50<1>UD        g51<8,8,1>UD    0x02180018
+                            urb MsgDesc: 1 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g59<1>UW        g64<8,8,1>UD    0x02427002
+                            sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g64<8,8,1>UD    0x02427003
+                            sampler MsgDesc: ld SIMD8 Surface = 3 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g64<8,8,1>UD    0x02427004
+                            sampler MsgDesc: ld SIMD8 Surface = 4 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g64<8,8,1>UD    0x02427005
+                            sampler MsgDesc: ld SIMD8 Surface = 5 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g64<8,8,1>UD    0x02427006
+                            sampler MsgDesc: ld SIMD8 Surface = 6 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g64<8,8,1>UD    0x02427007
+                            sampler MsgDesc: ld SIMD8 Surface = 7 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g64<8,8,1>UD    0x02427008
+                            sampler MsgDesc: ld SIMD8 Surface = 8 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g64<8,8,1>UD    0x02427009
+                            sampler MsgDesc: ld SIMD8 Surface = 9 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g30<1>UW        g64<8,8,1>UD    0x0242700a
+                            sampler MsgDesc: ld SIMD8 Surface = 10 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g34<1>UW        g64<8,8,1>UD    0x0242700b
+                            sampler MsgDesc: ld SIMD8 Surface = 11 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g38<1>UW        g64<8,8,1>UD    0x0242700c
+                            sampler MsgDesc: ld SIMD8 Surface = 12 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g42<1>UW        g64<8,8,1>UD    0x0242700d
+                            sampler MsgDesc: ld SIMD8 Surface = 13 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x06422505
+                            sampler MsgDesc: sample_l SIMD8 Surface = 5 Sampler = 5 mlen 3 rlen 4 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0a088067
+                            urb MsgDesc: 6 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0a088077
+                            urb MsgDesc: 7 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0a088087
+                            urb MsgDesc: 8 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0a088097
+                            urb MsgDesc: 9 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0a0880a7
+                            urb MsgDesc: 10 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0a0880b7
+                            urb MsgDesc: 11 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0a0880c7
+                            urb MsgDesc: 12 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0a0880d7
+                            urb MsgDesc: 13 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0a0880e7
+                            urb MsgDesc: 14 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0a0880f7
+                            urb MsgDesc: 15 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0a088107
+                            urb MsgDesc: 16 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0a088117
+                            urb MsgDesc: 17 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0a088127
+                            urb MsgDesc: 18 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0a088137
+                            urb MsgDesc: 19 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0a088147
+                            urb MsgDesc: 20 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0a088157
+                            urb MsgDesc: 21 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0a088167
+                            urb MsgDesc: 22 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0a088177
+                            urb MsgDesc: 23 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0a088187
+                            urb MsgDesc: 24 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0a088197
+                            urb MsgDesc: 25 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0a0881a7
+                            urb MsgDesc: 26 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0a0881b7
+                            urb MsgDesc: 27 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0a0881c7
+                            urb MsgDesc: 28 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0a0881d7
+                            urb MsgDesc: 29 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x0a0881e7
+                            urb MsgDesc: 30 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g41<8,8,1>UD    0x0a0881f7
+                            urb MsgDesc: 31 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g4<8,8,1>UD     0x0e0a8027
+                            urb MsgDesc: 2 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q };
+(+f1.0) send(8) g3<1>UW         g3<8,8,1>UD     0x0410b702
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, add) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(16) g4<1>UW        g6<8,8,1>UD     0x0820a702
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, add) mlen 4 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x0a423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g15<8,8,1>UD    0x0a423102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g29<1>UW        g9<8,8,1>UD     0x14843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(16)        g37<1>UW        g19<8,8,1>UD    0x14843102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x06424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+(+f1.0) send(8) g4<1>UW         g12<8,8,1>UD    0x0210b502
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, inc) mlen 1 rlen 1 { align1 1Q };
+(+f1.0) send(16) g5<1>UW        g17<8,8,1>UD    0x0420a502
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, inc) mlen 2 rlen 2 { align1 1H };
+send(8)         g12<1>UD        g1<8,8,1>UD     0x02280058
+                            urb MsgDesc: 5 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0e0a8067
+                            urb MsgDesc: 6 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q };
+send(8)         g12<1>UD        g1<8,8,1>UD     0x02280078
+                            urb MsgDesc: 7 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0e0a8087
+                            urb MsgDesc: 8 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q };
+send(8)         g12<1>UD        g1<8,8,1>UD     0x02280098
+                            urb MsgDesc: 9 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0e0a80a7
+                            urb MsgDesc: 10 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q };
+send(8)         g2<1>UW         g9<8,8,1>UD     0x024ab001
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x028cb001
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 1 Sampler = 0 mlen 1 rlen 8 { align1 1H };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x06026c01
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0xc) mlen 3 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g4<8,8,1>UD     0x0c025c01
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0xc) mlen 6 rlen 0 { align1 1H };
+send(8)         null<1>UW       g9<8,8,1>UD     0x04026e00
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 0, SIMD8, Mask = 0xe) mlen 2 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g9<8,8,1>UD     0x06026c00
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 0, SIMD8, Mask = 0xc) mlen 3 rlen 0 { align1 1Q };
+send(16)        g9<1>UW         g17<8,8,1>UD    0x04847002
+                            sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+(+f1.0) send(8) g14<1>UW        g13<8,8,1>UD    0x0410bb02
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, imin) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g18<1>UW        g4<8,8,1>UD     0x0410b402
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, mov) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(16) g22<1>UW       g24<8,8,1>UD    0x0820ab02
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, imin) mlen 4 rlen 2 { align1 1H };
+send(16)        g23<1>UW        g3<8,8,1>UD     0x04205e02
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+(+f1.0) send(16) g26<1>UW       g6<8,8,1>UD     0x0820a402
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, mov) mlen 4 rlen 2 { align1 1H };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280068
+                            urb MsgDesc: 6 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280088
+                            urb MsgDesc: 8 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022800a8
+                            urb MsgDesc: 10 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022800b8
+                            urb MsgDesc: 11 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022800c8
+                            urb MsgDesc: 12 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022800d8
+                            urb MsgDesc: 13 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022800e8
+                            urb MsgDesc: 14 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022800f8
+                            urb MsgDesc: 15 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280108
+                            urb MsgDesc: 16 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280118
+                            urb MsgDesc: 17 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280128
+                            urb MsgDesc: 18 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280138
+                            urb MsgDesc: 19 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280148
+                            urb MsgDesc: 20 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280158
+                            urb MsgDesc: 21 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280168
+                            urb MsgDesc: 22 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280178
+                            urb MsgDesc: 23 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280188
+                            urb MsgDesc: 24 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280198
+                            urb MsgDesc: 25 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022801a8
+                            urb MsgDesc: 26 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022801b8
+                            urb MsgDesc: 27 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022801c8
+                            urb MsgDesc: 28 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022801d8
+                            urb MsgDesc: 29 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022801e8
+                            urb MsgDesc: 30 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022801f8
+                            urb MsgDesc: 31 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280208
+                            urb MsgDesc: 32 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g2<1>UW         g3<8,8,1>UD     0x04203000
+                            pixel interp MsgDesc: (persp, per_slot_offset, 0x00) mlen 2 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x08413000
+                            pixel interp MsgDesc: (persp, per_slot_offset, 0x00) mlen 4 rlen 4 { align1 1H };
+send(8)         g2<1>UW         g0<8,8,1>UD     0x02201010
+                            pixel interp MsgDesc: (persp, sample_position, 0x10) mlen 1 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g0<8,8,1>UD     0x02411010
+                            pixel interp MsgDesc: (persp, sample_position, 0x10) mlen 1 rlen 4 { align1 1H };
+send(8)         g2<1>UW         g0<8,8,1>UD     0x02201020
+                            pixel interp MsgDesc: (persp, sample_position, 0x20) mlen 1 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g0<8,8,1>UD     0x02411020
+                            pixel interp MsgDesc: (persp, sample_position, 0x20) mlen 1 rlen 4 { align1 1H };
+send(8)         g2<1>UW         g0<8,8,1>UD     0x02201030
+                            pixel interp MsgDesc: (persp, sample_position, 0x30) mlen 1 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g0<8,8,1>UD     0x02411030
+                            pixel interp MsgDesc: (persp, sample_position, 0x30) mlen 1 rlen 4 { align1 1H };
+(+f1.0) send(8) null<1>UW       g118<8,8,1>UD   0x02009601
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, dec) mlen 1 rlen 0 { align1 1Q };
+(+f1.0) send(8) g47<1>UW        g118<8,8,1>UD   0x0210b601
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, dec) mlen 1 rlen 1 { align1 1Q };
+send(16)        null<1>UW       g8<8,8,1>UD     0x0c025c02
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xc) mlen 6 rlen 0 { align1 1H };
+send(16)        g4<1>UW         g1<8,8,1>UD     0x04405c02
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD16, Mask = 0xc) mlen 2 rlen 4 { align1 1H };
+send(8)         null<1>UW       g124<8,8,1>UD   0x02009600
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, dec) mlen 1 rlen 0 { align1 1Q };
+send(8)         g51<1>UW        g124<8,8,1>UD   0x0210b600
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, dec) mlen 1 rlen 1 { align1 1Q };
+send(8)         g127<1>UW       g9<8,8,1>UD     0x0819a401
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, mov) mlen 4 rlen 1 { align1 1Q };
+send(8)         g127<1>UW       g2<8,8,1>UD     0x0819b401
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, mov) mlen 4 rlen 1 { align1 2Q };
+send(16)        g13<1>UW        g21<8,8,1>UD    0x0c85d002
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 2 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g13<1>UW        g31<8,8,1>UD    0x0a43e002
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 2 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x04421001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x08841001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g36<1>UW        g0<8,8,1>F      0x021c003f
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 63, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g37<1>UW        g0<8,8,1>F      0x021c0040
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 64, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g38<1>UW        g0<8,8,1>F      0x021c0041
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 65, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g39<1>UW        g0<8,8,1>F      0x021c0042
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 66, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g41<1>UW        g0<8,8,1>F      0x021c0044
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 68, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g40<1>UW        g0<8,8,1>F      0x021c0043
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 67, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g42<1>UW        g0<8,8,1>F      0x021c0045
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 69, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g43<1>UW        g0<8,8,1>F      0x021c0046
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 70, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g45<1>UW        g0<8,8,1>F      0x021c0048
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 72, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g44<1>UW        g0<8,8,1>F      0x021c0047
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 71, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g46<1>UW        g0<8,8,1>F      0x021c0049
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 73, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g47<1>UW        g0<8,8,1>F      0x021c004a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 74, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g61<1>UW        g0<8,8,1>F      0x021c0057
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 87, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g48<1>UW        g0<8,8,1>F      0x021c004b
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 75, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g62<1>UW        g0<8,8,1>F      0x021c0058
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 88, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g57<1>UW        g0<8,8,1>F      0x021c0053
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 83, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g63<1>UW        g0<8,8,1>F      0x021c0059
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 89, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g58<1>UW        g0<8,8,1>F      0x021c0054
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 84, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g64<1>UW        g0<8,8,1>F      0x021c005a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 90, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g53<1>UW        g0<8,8,1>F      0x021c004f
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 79, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g59<1>UW        g0<8,8,1>F      0x021c0055
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 85, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g54<1>UW        g0<8,8,1>F      0x021c0050
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 80, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g60<1>UW        g0<8,8,1>F      0x021c0056
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 86, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g51<1>UW        g0<8,8,1>F      0x021c004d
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 77, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g55<1>UW        g0<8,8,1>F      0x021c0051
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 81, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g52<1>UW        g0<8,8,1>F      0x021c004e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 78, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g56<1>UW        g0<8,8,1>F      0x021c0052
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 82, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g50<1>UW        g0<8,8,1>F      0x021c004c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 76, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080117
+                            urb MsgDesc: 17 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(8)         g6<1>UW         g9<8,8,1>UD     0x02406002
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 1Q };
+send(16)        g16<1>UW        g14<8,8,1>UD    0x04805002
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD16, Mask = 0x0) mlen 2 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g17<8,8,1>UD    0x0210b500
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, inc) mlen 1 rlen 1 { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080097
+                            urb MsgDesc: 9 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         null<1>F        g4<8,8,1>F      0x120800c7
+                            urb MsgDesc: 12 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g5<8,8,1>F      0x120800e7
+                            urb MsgDesc: 14 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080107
+                            urb MsgDesc: 16 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x024ab101
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 1 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g10<8,8,1>UD    0x024ab202
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 2 Sampler = 2 mlen 1 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g14<8,8,1>UD    0x024ab303
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 3 Sampler = 3 mlen 1 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x024ab404
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 4 Sampler = 4 mlen 1 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g22<8,8,1>UD    0x024ab505
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 5 Sampler = 5 mlen 1 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g8<8,8,1>UD     0x064a2001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g12<8,8,1>UD    0x0a8c2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g15<8,8,1>UD    0x08423102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g2<8,8,1>UD     0x10843102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+send(8)         g2<1>UD         g9<8,8,1>UD     0x043a0028
+                            urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x02380098
+                            urb MsgDesc: 9 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x023800a8
+                            urb MsgDesc: 10 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x023800b8
+                            urb MsgDesc: 11 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x023800d8
+                            urb MsgDesc: 13 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x023800e8
+                            urb MsgDesc: 14 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x023800f8
+                            urb MsgDesc: 15 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x02380108
+                            urb MsgDesc: 16 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x02380118
+                            urb MsgDesc: 17 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         null<1>F        g60<8,8,1>F     0x120800a7
+                            urb MsgDesc: 10 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080107
+                            urb MsgDesc: 16 SIMD8 write mlen 9 rlen 0       { align1 1Q EOT };
+send(8)         g3<1>UW         g3<8,8,1>UD     0x04195e01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 2 rlen 1 { align1 1Q };
+send(8)         null<1>UW       g5<8,8,1>UD     0x060b5e02
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 3 rlen 0 { align1 1Q };
+send(8)         g5<1>UW         g8<8,8,1>UD     0x04196e01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 2 rlen 1 { align1 2Q };
+send(8)         null<1>UW       g10<8,8,1>UD    0x060b6e02
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 3 rlen 0 { align1 2Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080067
+                            urb MsgDesc: 6 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c0077
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 119, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g30<1>UW        g0<8,8,1>F      0x021c0075
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 117, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c0074
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 116, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g14<1>UW        g0<8,8,1>F      0x021c0073
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 115, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g118<1>UW       g0<8,8,1>F      0x021c0070
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 112, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g122<1>UW       g0<8,8,1>F      0x021c0071
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 113, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g6<1>UW         g0<8,8,1>F      0x021c0072
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 114, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g66<1>UW        g0<8,8,1>F      0x021c006a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 106, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g70<1>UW        g0<8,8,1>F      0x021c006b
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 107, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g102<1>UW       g0<8,8,1>F      0x021c006c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 108, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g106<1>UW       g0<8,8,1>F      0x021c006d
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 109, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g110<1>UW       g0<8,8,1>F      0x021c006e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 110, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g114<1>UW       g0<8,8,1>F      0x021c006f
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 111, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g6<1>UW         g0<8,8,1>F      0x021c005e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 94, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g14<1>UW        g0<8,8,1>F      0x021c005f
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 95, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c0060
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 96, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g30<1>UW        g0<8,8,1>F      0x021c0061
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 97, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g34<1>UW        g0<8,8,1>F      0x021c0062
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 98, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g38<1>UW        g0<8,8,1>F      0x021c0063
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 99, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g42<1>UW        g0<8,8,1>F      0x021c0064
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 100, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g46<1>UW        g0<8,8,1>F      0x021c0065
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 101, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g50<1>UW        g0<8,8,1>F      0x021c0066
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 102, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g54<1>UW        g0<8,8,1>F      0x021c0067
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 103, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g58<1>UW        g0<8,8,1>F      0x021c0068
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 104, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g62<1>UW        g0<8,8,1>F      0x021c0069
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 105, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c005b
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 91, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g6<1>UW         g0<8,8,1>F      0x021c005c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 92, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         g6<1>UW         g0<8,8,1>F      0x021c005d
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 93, 0) mlen 1 rlen 1           { align1 WE_all 1Q };
+send(8)         null<1>F        g80<8,8,1>F     0x140a00b7
+                            urb MsgDesc: 11 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a00d7
+                            urb MsgDesc: 13 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a00f7
+                            urb MsgDesc: 15 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a0117
+                            urb MsgDesc: 17 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a0137
+                            urb MsgDesc: 19 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g90<8,8,1>F     0x140a0157
+                            urb MsgDesc: 21 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g100<8,8,1>F    0x140a0177
+                            urb MsgDesc: 23 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g110<8,8,1>F    0x0c0a0197
+                            urb MsgDesc: 25 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         g16<1>UW        g0<8,8,1>F      0x021c0076
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 118, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g4<1>UW         g0<8,8,1>F      0x021c0079
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 121, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g4<1>UW         g0<8,8,1>F      0x021c0078
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 120, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         null<1>F        g120<8,8,1>F    0x8c0a0197
+                            urb MsgDesc: 25 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         null<1>F        g123<8,8,1>F    0x8a0800b7
+                            urb MsgDesc: 11 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(8)         g22<1>UD        g53<8,8,1>UD    0x02180238
+                            urb MsgDesc: 35 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g54<1>UD        g53<8,8,1>UD    0x02180438
+                            urb MsgDesc: 67 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g67<1>UD        g53<8,8,1>UD    0x02180638
+                            urb MsgDesc: 99 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g61<1>UD        g53<8,8,1>UD    0x02180248
+                            urb MsgDesc: 36 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g66<1>UD        g53<8,8,1>UD    0x02180448
+                            urb MsgDesc: 68 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g63<1>UD        g53<8,8,1>UD    0x02180648
+                            urb MsgDesc: 100 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g68<1>UD        g65<8,8,1>UD    0x02180258
+                            urb MsgDesc: 37 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g69<1>UD        g65<8,8,1>UD    0x02180458
+                            urb MsgDesc: 69 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g70<1>UD        g65<8,8,1>UD    0x02180658
+                            urb MsgDesc: 101 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g75<1>UD        g24<8,8,1>UD    0x02180268
+                            urb MsgDesc: 38 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g76<1>UD        g24<8,8,1>UD    0x02180468
+                            urb MsgDesc: 70 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g77<1>UD        g24<8,8,1>UD    0x02180668
+                            urb MsgDesc: 102 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g82<1>UD        g25<8,8,1>UD    0x02180278
+                            urb MsgDesc: 39 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g83<1>UD        g25<8,8,1>UD    0x02180478
+                            urb MsgDesc: 71 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g84<1>UD        g25<8,8,1>UD    0x02180678
+                            urb MsgDesc: 103 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g89<1>UD        g26<8,8,1>UD    0x02180288
+                            urb MsgDesc: 40 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g90<1>UD        g26<8,8,1>UD    0x02180488
+                            urb MsgDesc: 72 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g91<1>UD        g26<8,8,1>UD    0x02180688
+                            urb MsgDesc: 104 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g96<1>UD        g27<8,8,1>UD    0x02180298
+                            urb MsgDesc: 41 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g97<1>UD        g27<8,8,1>UD    0x02180498
+                            urb MsgDesc: 73 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g98<1>UD        g27<8,8,1>UD    0x02180698
+                            urb MsgDesc: 105 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g103<1>UD       g28<8,8,1>UD    0x021802a8
+                            urb MsgDesc: 42 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g104<1>UD       g28<8,8,1>UD    0x021804a8
+                            urb MsgDesc: 74 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g105<1>UD       g28<8,8,1>UD    0x021806a8
+                            urb MsgDesc: 106 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g110<1>UD       g29<8,8,1>UD    0x021802b8
+                            urb MsgDesc: 43 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g111<1>UD       g29<8,8,1>UD    0x021804b8
+                            urb MsgDesc: 75 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g112<1>UD       g29<8,8,1>UD    0x021806b8
+                            urb MsgDesc: 107 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g117<1>UD       g30<8,8,1>UD    0x021802c8
+                            urb MsgDesc: 44 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g118<1>UD       g30<8,8,1>UD    0x021804c8
+                            urb MsgDesc: 76 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g119<1>UD       g30<8,8,1>UD    0x021806c8
+                            urb MsgDesc: 108 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g124<1>UD       g31<8,8,1>UD    0x021802d8
+                            urb MsgDesc: 45 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g125<1>UD       g31<8,8,1>UD    0x021804d8
+                            urb MsgDesc: 77 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g126<1>UD       g31<8,8,1>UD    0x021806d8
+                            urb MsgDesc: 109 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g10<1>UD        g32<8,8,1>UD    0x021802e8
+                            urb MsgDesc: 46 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g11<1>UD        g32<8,8,1>UD    0x021804e8
+                            urb MsgDesc: 78 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g12<1>UD        g32<8,8,1>UD    0x021806e8
+                            urb MsgDesc: 110 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g26<1>UD        g33<8,8,1>UD    0x021802f8
+                            urb MsgDesc: 47 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g27<1>UD        g33<8,8,1>UD    0x021804f8
+                            urb MsgDesc: 79 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g28<1>UD        g33<8,8,1>UD    0x021806f8
+                            urb MsgDesc: 111 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g33<1>UD        g35<8,8,1>UD    0x02180308
+                            urb MsgDesc: 48 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g34<1>UD        g35<8,8,1>UD    0x02180508
+                            urb MsgDesc: 80 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g35<1>UD        g35<8,8,1>UD    0x02180708
+                            urb MsgDesc: 112 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g64<1>UD        g36<8,8,1>UD    0x02180318
+                            urb MsgDesc: 49 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g41<1>UD        g36<8,8,1>UD    0x02180518
+                            urb MsgDesc: 81 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g42<1>UD        g36<8,8,1>UD    0x02180718
+                            urb MsgDesc: 113 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g6<1>UD         g37<8,8,1>UD    0x02180328
+                            urb MsgDesc: 50 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g48<1>UD        g37<8,8,1>UD    0x02180528
+                            urb MsgDesc: 82 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g49<1>UD        g37<8,8,1>UD    0x02180728
+                            urb MsgDesc: 114 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g67<1>UD        g38<8,8,1>UD    0x02180338
+                            urb MsgDesc: 51 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g56<1>UD        g38<8,8,1>UD    0x02180538
+                            urb MsgDesc: 83 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g57<1>UD        g38<8,8,1>UD    0x02180738
+                            urb MsgDesc: 115 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g66<1>UD        g39<8,8,1>UD    0x02180348
+                            urb MsgDesc: 52 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g63<1>UD        g39<8,8,1>UD    0x02180548
+                            urb MsgDesc: 84 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g40<1>UD        g39<8,8,1>UD    0x02180748
+                            urb MsgDesc: 116 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g69<1>UD        g64<8,8,1>UD    0x02180358
+                            urb MsgDesc: 53 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g70<1>UD        g64<8,8,1>UD    0x02180558
+                            urb MsgDesc: 85 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g71<1>UD        g64<8,8,1>UD    0x02180758
+                            urb MsgDesc: 117 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g76<1>UD        g41<8,8,1>UD    0x02180368
+                            urb MsgDesc: 54 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g77<1>UD        g41<8,8,1>UD    0x02180568
+                            urb MsgDesc: 86 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g78<1>UD        g41<8,8,1>UD    0x02180768
+                            urb MsgDesc: 118 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g83<1>UD        g42<8,8,1>UD    0x02180378
+                            urb MsgDesc: 55 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g84<1>UD        g42<8,8,1>UD    0x02180578
+                            urb MsgDesc: 87 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g85<1>UD        g42<8,8,1>UD    0x02180778
+                            urb MsgDesc: 119 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g90<1>UD        g43<8,8,1>UD    0x02180388
+                            urb MsgDesc: 56 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g91<1>UD        g43<8,8,1>UD    0x02180588
+                            urb MsgDesc: 88 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g92<1>UD        g43<8,8,1>UD    0x02180788
+                            urb MsgDesc: 120 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g97<1>UD        g44<8,8,1>UD    0x02180398
+                            urb MsgDesc: 57 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g98<1>UD        g44<8,8,1>UD    0x02180598
+                            urb MsgDesc: 89 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g99<1>UD        g44<8,8,1>UD    0x02180798
+                            urb MsgDesc: 121 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g104<1>UD       g45<8,8,1>UD    0x021803a8
+                            urb MsgDesc: 58 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g105<1>UD       g45<8,8,1>UD    0x021805a8
+                            urb MsgDesc: 90 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g106<1>UD       g45<8,8,1>UD    0x021807a8
+                            urb MsgDesc: 122 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g111<1>UD       g46<8,8,1>UD    0x021803b8
+                            urb MsgDesc: 59 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g112<1>UD       g46<8,8,1>UD    0x021805b8
+                            urb MsgDesc: 91 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g113<1>UD       g46<8,8,1>UD    0x021807b8
+                            urb MsgDesc: 123 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g118<1>UD       g6<8,8,1>UD     0x021803c8
+                            urb MsgDesc: 60 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g119<1>UD       g6<8,8,1>UD     0x021805c8
+                            urb MsgDesc: 92 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g120<1>UD       g6<8,8,1>UD     0x021807c8
+                            urb MsgDesc: 124 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g125<1>UD       g48<8,8,1>UD    0x021803d8
+                            urb MsgDesc: 61 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g126<1>UD       g48<8,8,1>UD    0x021805d8
+                            urb MsgDesc: 93 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g2<1>UD         g48<8,8,1>UD    0x021807d8
+                            urb MsgDesc: 125 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g12<1>UD        g49<8,8,1>UD    0x021803e8
+                            urb MsgDesc: 62 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g13<1>UD        g49<8,8,1>UD    0x021805e8
+                            urb MsgDesc: 94 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g14<1>UD        g49<8,8,1>UD    0x021807e8
+                            urb MsgDesc: 126 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g19<1>UD        g50<8,8,1>UD    0x021803f8
+                            urb MsgDesc: 63 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g20<1>UD        g50<8,8,1>UD    0x021805f8
+                            urb MsgDesc: 95 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g53<1>UD        g50<8,8,1>UD    0x021807f8
+                            urb MsgDesc: 127 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g28<1>UD        g51<8,8,1>UD    0x02180408
+                            urb MsgDesc: 64 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g29<1>UD        g51<8,8,1>UD    0x02180608
+                            urb MsgDesc: 96 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g30<1>UD        g51<8,8,1>UD    0x02180808
+                            urb MsgDesc: 128 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g35<1>UD        g22<8,8,1>UD    0x02180218
+                            urb MsgDesc: 33 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g36<1>UD        g22<8,8,1>UD    0x02180418
+                            urb MsgDesc: 65 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g37<1>UD        g22<8,8,1>UD    0x02180618
+                            urb MsgDesc: 97 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g38<1>UD        g22<8,8,1>UD    0x02180818
+                            urb MsgDesc: 129 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x080a8037
+                            urb MsgDesc: 3 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g10<8,8,1>UD    0x080a8047
+                            urb MsgDesc: 4 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x080a8057
+                            urb MsgDesc: 5 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x080a8067
+                            urb MsgDesc: 6 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x080a8077
+                            urb MsgDesc: 7 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x080a8087
+                            urb MsgDesc: 8 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x080a8097
+                            urb MsgDesc: 9 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x080a80a7
+                            urb MsgDesc: 10 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x080a80b7
+                            urb MsgDesc: 11 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x080a80c7
+                            urb MsgDesc: 12 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x080a80d7
+                            urb MsgDesc: 13 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x080a80e7
+                            urb MsgDesc: 14 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x080a80f7
+                            urb MsgDesc: 15 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x080a8107
+                            urb MsgDesc: 16 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x080a8117
+                            urb MsgDesc: 17 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x080a8127
+                            urb MsgDesc: 18 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x080a8137
+                            urb MsgDesc: 19 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x080a8147
+                            urb MsgDesc: 20 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x080a8157
+                            urb MsgDesc: 21 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x080a8167
+                            urb MsgDesc: 22 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x080a8177
+                            urb MsgDesc: 23 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x080a8187
+                            urb MsgDesc: 24 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x080a8197
+                            urb MsgDesc: 25 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x080a81a7
+                            urb MsgDesc: 26 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x080a81b7
+                            urb MsgDesc: 27 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x080a81c7
+                            urb MsgDesc: 28 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x080a81d7
+                            urb MsgDesc: 29 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x080a81e7
+                            urb MsgDesc: 30 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x080a81f7
+                            urb MsgDesc: 31 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x080a8207
+                            urb MsgDesc: 32 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x080a8217
+                            urb MsgDesc: 33 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         g19<1>UW        g20<8,8,1>UD    0x06195e00
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 3 rlen 1 { align1 1Q };
+send(8)         null<1>UW       g23<8,8,1>UD    0x080b5e00
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 0, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g3<8,8,1>UD     0x080b5e02
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g1<8,8,1>UD     0x080b6e02
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 4 rlen 0 { align1 2Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x0a4b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g12<8,8,1>UD    0x0a4b4102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(8)         g34<1>UD        g42<8,8,1>UD    0x02480248
+                            urb MsgDesc: 36 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g38<1>UD        g42<8,8,1>UD    0x02480448
+                            urb MsgDesc: 68 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g42<1>UD        g42<8,8,1>UD    0x02480648
+                            urb MsgDesc: 100 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g22<1>UD        g43<8,8,1>UD    0x02480258
+                            urb MsgDesc: 37 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g43<8,8,1>UD    0x02480458
+                            urb MsgDesc: 69 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g43<8,8,1>UD    0x02480658
+                            urb MsgDesc: 101 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g22<1>UD        g44<8,8,1>UD    0x02480268
+                            urb MsgDesc: 38 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g44<8,8,1>UD    0x02480468
+                            urb MsgDesc: 70 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g44<8,8,1>UD    0x02480668
+                            urb MsgDesc: 102 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g22<1>UD        g45<8,8,1>UD    0x02480278
+                            urb MsgDesc: 39 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g45<8,8,1>UD    0x02480478
+                            urb MsgDesc: 71 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g45<8,8,1>UD    0x02480678
+                            urb MsgDesc: 103 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g22<1>UD        g55<8,8,1>UD    0x02480288
+                            urb MsgDesc: 40 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g55<8,8,1>UD    0x02480488
+                            urb MsgDesc: 72 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g55<8,8,1>UD    0x02480688
+                            urb MsgDesc: 104 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g26<1>UD        g56<8,8,1>UD    0x02480498
+                            urb MsgDesc: 73 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g56<8,8,1>UD    0x02480298
+                            urb MsgDesc: 41 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g56<8,8,1>UD    0x02480698
+                            urb MsgDesc: 105 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g26<1>UD        g82<8,8,1>UD    0x024804a8
+                            urb MsgDesc: 74 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g82<8,8,1>UD    0x024802a8
+                            urb MsgDesc: 42 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g82<8,8,1>UD    0x024806a8
+                            urb MsgDesc: 106 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g26<1>UD        g83<8,8,1>UD    0x024804b8
+                            urb MsgDesc: 75 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g83<8,8,1>UD    0x024802b8
+                            urb MsgDesc: 43 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g83<8,8,1>UD    0x024806b8
+                            urb MsgDesc: 107 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g26<1>UD        g84<8,8,1>UD    0x024806c8
+                            urb MsgDesc: 108 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g84<8,8,1>UD    0x024802c8
+                            urb MsgDesc: 44 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g84<8,8,1>UD    0x024804c8
+                            urb MsgDesc: 76 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g8<1>UD         g85<8,8,1>UD    0x024802d8
+                            urb MsgDesc: 45 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g85<8,8,1>UD    0x024804d8
+                            urb MsgDesc: 77 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g85<8,8,1>UD    0x024806d8
+                            urb MsgDesc: 109 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g6<8,8,1>UD     0x024802e8
+                            urb MsgDesc: 46 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g6<8,8,1>UD     0x024804e8
+                            urb MsgDesc: 78 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g6<8,8,1>UD     0x024806e8
+                            urb MsgDesc: 110 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g3<8,8,1>UD     0x024802f8
+                            urb MsgDesc: 47 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g3<8,8,1>UD     0x024804f8
+                            urb MsgDesc: 79 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g3<8,8,1>UD     0x024806f8
+                            urb MsgDesc: 111 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g46<8,8,1>UD    0x02480308
+                            urb MsgDesc: 48 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g46<8,8,1>UD    0x02480508
+                            urb MsgDesc: 80 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g46<8,8,1>UD    0x02480708
+                            urb MsgDesc: 112 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g47<8,8,1>UD    0x02480318
+                            urb MsgDesc: 49 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g47<8,8,1>UD    0x02480518
+                            urb MsgDesc: 81 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g47<8,8,1>UD    0x02480718
+                            urb MsgDesc: 113 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g57<8,8,1>UD    0x02480328
+                            urb MsgDesc: 50 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g57<8,8,1>UD    0x02480528
+                            urb MsgDesc: 82 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g57<8,8,1>UD    0x02480728
+                            urb MsgDesc: 114 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g58<8,8,1>UD    0x02480338
+                            urb MsgDesc: 51 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g58<8,8,1>UD    0x02480538
+                            urb MsgDesc: 83 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g58<8,8,1>UD    0x02480738
+                            urb MsgDesc: 115 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g59<8,8,1>UD    0x02480348
+                            urb MsgDesc: 52 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g59<8,8,1>UD    0x02480548
+                            urb MsgDesc: 84 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g59<8,8,1>UD    0x02480748
+                            urb MsgDesc: 116 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g60<8,8,1>UD    0x02480358
+                            urb MsgDesc: 53 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g60<8,8,1>UD    0x02480558
+                            urb MsgDesc: 85 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g60<8,8,1>UD    0x02480758
+                            urb MsgDesc: 117 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g61<8,8,1>UD    0x02480368
+                            urb MsgDesc: 54 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g61<8,8,1>UD    0x02480568
+                            urb MsgDesc: 86 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g61<8,8,1>UD    0x02480768
+                            urb MsgDesc: 118 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g62<8,8,1>UD    0x02480378
+                            urb MsgDesc: 55 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g62<8,8,1>UD    0x02480578
+                            urb MsgDesc: 87 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g62<8,8,1>UD    0x02480778
+                            urb MsgDesc: 119 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g63<8,8,1>UD    0x02480388
+                            urb MsgDesc: 56 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g63<8,8,1>UD    0x02480588
+                            urb MsgDesc: 88 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g63<8,8,1>UD    0x02480788
+                            urb MsgDesc: 120 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g64<8,8,1>UD    0x02480398
+                            urb MsgDesc: 57 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g64<8,8,1>UD    0x02480598
+                            urb MsgDesc: 89 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g64<8,8,1>UD    0x02480798
+                            urb MsgDesc: 121 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g68<8,8,1>UD    0x024803a8
+                            urb MsgDesc: 58 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g68<8,8,1>UD    0x024805a8
+                            urb MsgDesc: 90 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g68<8,8,1>UD    0x024807a8
+                            urb MsgDesc: 122 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g69<8,8,1>UD    0x024803b8
+                            urb MsgDesc: 59 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g69<8,8,1>UD    0x024805b8
+                            urb MsgDesc: 91 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g69<8,8,1>UD    0x024807b8
+                            urb MsgDesc: 123 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g70<8,8,1>UD    0x024803c8
+                            urb MsgDesc: 60 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g70<8,8,1>UD    0x024805c8
+                            urb MsgDesc: 92 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g16<1>UD        g70<8,8,1>UD    0x024807c8
+                            urb MsgDesc: 124 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g71<8,8,1>UD    0x024803d8
+                            urb MsgDesc: 61 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g71<8,8,1>UD    0x024805d8
+                            urb MsgDesc: 93 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g16<1>UD        g71<8,8,1>UD    0x024807d8
+                            urb MsgDesc: 125 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g72<8,8,1>UD    0x024803e8
+                            urb MsgDesc: 62 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g72<8,8,1>UD    0x024805e8
+                            urb MsgDesc: 94 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g16<1>UD        g72<8,8,1>UD    0x024807e8
+                            urb MsgDesc: 126 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g73<8,8,1>UD    0x024803f8
+                            urb MsgDesc: 63 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g73<8,8,1>UD    0x024805f8
+                            urb MsgDesc: 95 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g16<1>UD        g73<8,8,1>UD    0x024807f8
+                            urb MsgDesc: 127 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g12<1>UD        g75<8,8,1>UD    0x02480418
+                            urb MsgDesc: 65 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g16<1>UD        g75<8,8,1>UD    0x02480618
+                            urb MsgDesc: 97 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g20<1>UD        g75<8,8,1>UD    0x02480818
+                            urb MsgDesc: 129 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0c0a00c7
+                            urb MsgDesc: 12 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0c0a00d7
+                            urb MsgDesc: 13 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0c0a00e7
+                            urb MsgDesc: 14 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0c0a00f7
+                            urb MsgDesc: 15 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0c0a0107
+                            urb MsgDesc: 16 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0c0a0117
+                            urb MsgDesc: 17 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0c0a0137
+                            urb MsgDesc: 19 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0c0a0147
+                            urb MsgDesc: 20 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0c0a0157
+                            urb MsgDesc: 21 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0c0a0167
+                            urb MsgDesc: 22 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0c0a0177
+                            urb MsgDesc: 23 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0c0a0187
+                            urb MsgDesc: 24 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0c0a01a7
+                            urb MsgDesc: 26 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0c0a01b7
+                            urb MsgDesc: 27 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0c0a01c7
+                            urb MsgDesc: 28 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0c0a01d7
+                            urb MsgDesc: 29 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0c0a01e7
+                            urb MsgDesc: 30 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0c0a01f7
+                            urb MsgDesc: 31 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(16)        g46<1>UD        g12<8,8,1>UD    0x02280302
+                            const MsgDesc: (2, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g50<1>UD        g15<8,8,1>UD    0x02280304
+                            const MsgDesc: (4, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g34<1>UD        g20<8,8,1>UD    0x02280303
+                            const MsgDesc: (3, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g16<1>UD        g21<8,8,1>UD    0x02280306
+                            const MsgDesc: (6, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(32)        g87<1>UW        g0<8,8,1>F      0x024c200c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 12, 32) mlen 1 rlen 4          { align1 WE_all };
+send(32)        g91<1>UW        g0<8,8,1>F      0x024c2014
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 20, 32) mlen 1 rlen 4          { align1 WE_all };
+send(32)        g95<1>UW        g0<8,8,1>F      0x024c201c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 28, 32) mlen 1 rlen 4          { align1 WE_all };
+send(8)         g8<1>UW         g24<8,8,1>UD    0x02106e04
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(8)         g5<1>UW         g21<8,8,1>UD    0x02106e03
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(16)        g14<1>UW        g40<8,8,1>UD    0x04205e04
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+send(16)        g8<1>UW         g36<8,8,1>UD    0x04205e03
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+(+f1.0) send(8) null<1>UW       g11<8,8,1>UD    0x0a026002
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD8, Mask = 0x0) mlen 5 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g11<8,8,1>UD    0x14025002
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0x0) mlen 10 rlen 0 { align1 1H };
+send(8)         g15<1>UD        g12<8,8,1>UD    0x041a0038
+                            urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g22<1>UW        g14<8,8,1>UD    0x064a8404
+                            sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g10<8,8,1>UD    0x084a8202
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g26<8,8,1>UD    0x0a4a8303
+                            sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 3 mlen 5 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g54<8,8,1>UD    0x0242a707
+                            sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 7 mlen 1 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g55<8,8,1>UD    0x0242a808
+                            sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 8 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g56<8,8,1>UD    0x0242a909
+                            sampler MsgDesc: resinfo SIMD8 Surface = 9 Sampler = 9 mlen 1 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g57<8,8,1>UD    0x0242aa0a
+                            sampler MsgDesc: resinfo SIMD8 Surface = 10 Sampler = 10 mlen 1 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g58<8,8,1>UD    0x0242ab0b
+                            sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 11 mlen 1 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g59<8,8,1>UD    0x0242ac0c
+                            sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 12 mlen 1 rlen 4 { align1 1Q };
+send(8)         null<1>F        g9<8,8,1>UD     0x0c088027
+                            urb MsgDesc: 2 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g10<8,8,1>UD    0x0c088047
+                            urb MsgDesc: 4 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x0c088067
+                            urb MsgDesc: 6 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0c088037
+                            urb MsgDesc: 3 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g7<8,8,1>UD     0x0c088057
+                            urb MsgDesc: 5 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g8<8,8,1>UD     0x0c088077
+                            urb MsgDesc: 7 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c0100
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 0, 1) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00c1
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 193, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g79<1>UW        g0<8,8,1>F      0x021c00fe
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 254, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g75<1>UW        g0<8,8,1>F      0x021c00fd
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 253, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g71<1>UW        g0<8,8,1>F      0x021c00fc
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 252, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g67<1>UW        g0<8,8,1>F      0x021c00fb
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 251, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g63<1>UW        g0<8,8,1>F      0x021c00fa
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 250, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g47<1>UW        g0<8,8,1>F      0x021c00f6
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 246, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g8<1>UW         g0<8,8,1>F      0x021c00ef
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 239, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g15<1>UW        g0<8,8,1>F      0x021c00f0
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 240, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g23<1>UW        g0<8,8,1>F      0x021c00f1
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 241, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g31<1>UW        g0<8,8,1>F      0x021c00f2
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 242, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g35<1>UW        g0<8,8,1>F      0x021c00f3
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 243, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g39<1>UW        g0<8,8,1>F      0x021c00f4
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 244, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g43<1>UW        g0<8,8,1>F      0x021c00f5
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 245, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g51<1>UW        g0<8,8,1>F      0x021c00f7
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 247, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g55<1>UW        g0<8,8,1>F      0x021c00f8
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 248, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g59<1>UW        g0<8,8,1>F      0x021c00f9
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 249, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g89<1>UW        g0<8,8,1>F      0x021c00ee
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 238, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g85<1>UW        g0<8,8,1>F      0x021c00ed
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 237, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g81<1>UW        g0<8,8,1>F      0x021c00ec
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 236, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g77<1>UW        g0<8,8,1>F      0x021c00eb
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 235, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00df
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 223, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g33<1>UW        g0<8,8,1>F      0x021c00e0
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 224, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g69<1>UW        g0<8,8,1>F      0x021c00e9
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 233, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g73<1>UW        g0<8,8,1>F      0x021c00ea
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 234, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g37<1>UW        g0<8,8,1>F      0x021c00e1
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 225, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g41<1>UW        g0<8,8,1>F      0x021c00e2
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 226, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g45<1>UW        g0<8,8,1>F      0x021c00e3
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 227, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g49<1>UW        g0<8,8,1>F      0x021c00e4
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 228, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g53<1>UW        g0<8,8,1>F      0x021c00e5
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 229, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g57<1>UW        g0<8,8,1>F      0x021c00e6
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 230, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g61<1>UW        g0<8,8,1>F      0x021c00e7
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 231, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g65<1>UW        g0<8,8,1>F      0x021c00e8
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 232, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g23<1>UW        g0<8,8,1>F      0x021c00be
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 190, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00c0
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 192, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g116<1>UW       g0<8,8,1>F      0x021c00bf
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 191, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g7<1>UW         g0<8,8,1>F      0x021c00c3
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 195, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00c4
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 196, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00c5
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 197, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00c6
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 198, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00c7
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 199, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00c8
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 200, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00c9
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 201, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00ca
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 202, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00cb
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 203, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00cc
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 204, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00cd
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 205, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00ce
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 206, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00cf
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 207, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00d0
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 208, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00d1
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 209, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00d2
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 210, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00d3
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 211, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00d4
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 212, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00d5
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 213, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00d6
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 214, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g6<1>UW         g0<8,8,1>F      0x021c00db
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 219, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00dc
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 220, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00dd
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 221, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00de
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 222, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00d7
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 215, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g6<1>UW         g0<8,8,1>F      0x021c00d8
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 216, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g6<1>UW         g0<8,8,1>F      0x021c00d9
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 217, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g6<1>UW         g0<8,8,1>F      0x021c00da
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 218, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a0197
+                            urb MsgDesc: 25 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a01b7
+                            urb MsgDesc: 27 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a01d7
+                            urb MsgDesc: 29 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(16)        g6<1>UW         g0<8,8,1>F      0x022c10a0
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 160, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g8<1>UW         g0<8,8,1>F      0x022c10a2
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 162, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g10<1>UW        g0<8,8,1>F      0x022c10a4
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 164, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g12<1>UW        g0<8,8,1>F      0x022c10a6
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 166, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g14<1>UW        g0<8,8,1>F      0x022c10a8
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 168, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(8)         null<1>F        g6<8,8,1>F      0x140a01f7
+                            urb MsgDesc: 31 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         g16<1>UW        g0<8,8,1>F      0x021c00ff
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 255, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(16)        g18<1>UW        g0<8,8,1>F      0x022c108e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 142, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g20<1>UW        g0<8,8,1>F      0x022c1090
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 144, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g22<1>UW        g0<8,8,1>F      0x022c1092
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 146, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g24<1>UW        g0<8,8,1>F      0x022c1094
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 148, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g16<1>UW        g0<8,8,1>F      0x022c10aa
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 170, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g18<1>UW        g0<8,8,1>F      0x022c10ac
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 172, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g20<1>UW        g0<8,8,1>F      0x022c10ae
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 174, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g22<1>UW        g0<8,8,1>F      0x022c10b0
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 176, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g24<1>UW        g0<8,8,1>F      0x022c10b2
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 178, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(8)         g4<1>UW         g0<8,8,1>F      0x021c0102
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 2, 1) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         g4<1>UW         g0<8,8,1>F      0x021c0101
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 1, 1) mlen 1 rlen 1            { align1 WE_all 1Q };
+send(8)         g5<1>UW         g0<8,8,1>F      0x021c00c2
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 194, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(16)        g16<1>UW        g0<8,8,1>F      0x022c1096
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 150, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g18<1>UW        g0<8,8,1>F      0x022c1098
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 152, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g20<1>UW        g0<8,8,1>F      0x022c109a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 154, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g22<1>UW        g0<8,8,1>F      0x022c109c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 156, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g24<1>UW        g0<8,8,1>F      0x022c109e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 158, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g16<1>UW        g0<8,8,1>F      0x022c10b4
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 180, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g18<1>UW        g0<8,8,1>F      0x022c10b6
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 182, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g20<1>UW        g0<8,8,1>F      0x022c10b8
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 184, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g22<1>UW        g0<8,8,1>F      0x022c10ba
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 186, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(16)        g24<1>UW        g0<8,8,1>F      0x022c10bc
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 188, 16) mlen 1 rlen 2         { align1 WE_all 1H };
+send(8)         null<1>F        g120<8,8,1>F    0x8c0a0217
+                            urb MsgDesc: 33 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g8<1>UD         g6<8,8,1>UD     0x041a0318
+                            urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g9<1>UD         g6<8,8,1>UD     0x041a0518
+                            urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g10<1>UD        g6<8,8,1>UD     0x041a0718
+                            urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g11<1>UD        g6<8,8,1>UD     0x041a0918
+                            urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g7<1>UD         g11<8,8,1>UD    0x041a0218
+                            urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g8<1>UD         g11<8,8,1>UD    0x041a0418
+                            urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g9<1>UD         g11<8,8,1>UD    0x041a0618
+                            urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g10<1>UD        g11<8,8,1>UD    0x041a0818
+                            urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         null<1>F        g10<8,8,1>UD    0x080a8227
+                            urb MsgDesc: 34 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x080a8237
+                            urb MsgDesc: 35 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x080a8247
+                            urb MsgDesc: 36 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x080a8257
+                            urb MsgDesc: 37 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x080a8267
+                            urb MsgDesc: 38 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x080a8277
+                            urb MsgDesc: 39 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x080a8287
+                            urb MsgDesc: 40 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x080a8297
+                            urb MsgDesc: 41 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x080a82a7
+                            urb MsgDesc: 42 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x080a82b7
+                            urb MsgDesc: 43 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x080a82c7
+                            urb MsgDesc: 44 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x080a82d7
+                            urb MsgDesc: 45 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x080a82e7
+                            urb MsgDesc: 46 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x080a82f7
+                            urb MsgDesc: 47 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x080a8307
+                            urb MsgDesc: 48 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x080a8317
+                            urb MsgDesc: 49 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x080a8327
+                            urb MsgDesc: 50 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x080a8337
+                            urb MsgDesc: 51 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x080a8347
+                            urb MsgDesc: 52 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x080a8357
+                            urb MsgDesc: 53 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x080a8367
+                            urb MsgDesc: 54 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x080a8377
+                            urb MsgDesc: 55 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x080a8387
+                            urb MsgDesc: 56 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x080a8397
+                            urb MsgDesc: 57 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x080a83a7
+                            urb MsgDesc: 58 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x080a83b7
+                            urb MsgDesc: 59 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x080a83c7
+                            urb MsgDesc: 60 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x080a83d7
+                            urb MsgDesc: 61 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x080a83e7
+                            urb MsgDesc: 62 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x080a83f7
+                            urb MsgDesc: 63 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080007
+                            urb MsgDesc: 0 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+(+f1.0) send(8) g14<1>UW        g13<8,8,1>UD    0x0410bd02
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, umin) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(16) g22<1>UW       g24<8,8,1>UD    0x0820ad02
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, umin) mlen 4 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g19<8,8,1>UD    0x06295c01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xc) mlen 3 rlen 2 { align1 1Q };
+send(8)         null<1>UW       g22<8,8,1>UD    0x0a0b5c02
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xc) mlen 5 rlen 0 { align1 1Q };
+send(8)         g49<1>UW        g43<8,8,1>UD    0x06296c01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xc) mlen 3 rlen 2 { align1 2Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x0a0b6c02
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xc) mlen 5 rlen 0 { align1 2Q };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x104a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x084a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x0e8c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g119<1>UW       g0<8,8,1>F      0x021c00b2
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 178, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g39<1>UW        g0<8,8,1>F      0x021c00ad
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 173, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g40<1>UW        g0<8,8,1>F      0x021c00af
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 175, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g41<1>UW        g0<8,8,1>F      0x021c00ae
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 174, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g42<1>UW        g0<8,8,1>F      0x021c00b0
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 176, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g33<1>UW        g0<8,8,1>F      0x021c00a9
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 169, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g34<1>UW        g0<8,8,1>F      0x021c00a8
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 168, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g35<1>UW        g0<8,8,1>F      0x021c00aa
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 170, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g25<1>UW        g0<8,8,1>F      0x021c00a4
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 164, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g36<1>UW        g0<8,8,1>F      0x021c00ab
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 171, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g30<1>UW        g0<8,8,1>F      0x021c00a5
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 165, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g31<1>UW        g0<8,8,1>F      0x021c00a7
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 167, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g32<1>UW        g0<8,8,1>F      0x021c00a6
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 166, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g17<1>UW        g0<8,8,1>F      0x021c00a0
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 160, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g22<1>UW        g0<8,8,1>F      0x021c00a2
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 162, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g23<1>UW        g0<8,8,1>F      0x021c00a1
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 161, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g24<1>UW        g0<8,8,1>F      0x021c00a3
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 163, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g13<1>UW        g0<8,8,1>F      0x021c009d
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 157, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g14<1>UW        g0<8,8,1>F      0x021c009c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 156, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g15<1>UW        g0<8,8,1>F      0x021c009e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 158, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g9<1>UW         g0<8,8,1>F      0x021c0098
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 152, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g16<1>UW        g0<8,8,1>F      0x021c009f
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 159, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g10<1>UW        g0<8,8,1>F      0x021c0099
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 153, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g11<1>UW        g0<8,8,1>F      0x021c009b
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 155, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g12<1>UW        g0<8,8,1>F      0x021c009a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 154, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g121<1>UW       g0<8,8,1>F      0x021c0094
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 148, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g6<1>UW         g0<8,8,1>F      0x021c0096
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 150, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g7<1>UW         g0<8,8,1>F      0x021c0095
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 149, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g8<1>UW         g0<8,8,1>F      0x021c0097
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 151, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g116<1>UW       g0<8,8,1>F      0x021c0091
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 145, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g117<1>UW       g0<8,8,1>F      0x021c0090
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 144, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g119<1>UW       g0<8,8,1>F      0x021c0092
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 146, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g112<1>UW       g0<8,8,1>F      0x021c008c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 140, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g120<1>UW       g0<8,8,1>F      0x021c0093
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 147, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g113<1>UW       g0<8,8,1>F      0x021c008d
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 141, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g114<1>UW       g0<8,8,1>F      0x021c008f
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 143, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g115<1>UW       g0<8,8,1>F      0x021c008e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 142, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g104<1>UW       g0<8,8,1>F      0x021c0084
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 132, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g105<1>UW       g0<8,8,1>F      0x021c0086
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 134, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g106<1>UW       g0<8,8,1>F      0x021c0085
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 133, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g107<1>UW       g0<8,8,1>F      0x021c0087
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 135, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g108<1>UW       g0<8,8,1>F      0x021c0089
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 137, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g109<1>UW       g0<8,8,1>F      0x021c0088
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 136, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g110<1>UW       g0<8,8,1>F      0x021c008a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 138, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g100<1>UW       g0<8,8,1>F      0x021c0080
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 128, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g111<1>UW       g0<8,8,1>F      0x021c008b
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 139, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g101<1>UW       g0<8,8,1>F      0x021c0081
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 129, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g102<1>UW       g0<8,8,1>F      0x021c0083
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 131, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g103<1>UW       g0<8,8,1>F      0x021c0082
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 130, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g96<1>UW        g0<8,8,1>F      0x021c007c
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 124, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g97<1>UW        g0<8,8,1>F      0x021c007e
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 126, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g98<1>UW        g0<8,8,1>F      0x021c007d
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 125, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g99<1>UW        g0<8,8,1>F      0x021c007f
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 127, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g44<1>UW        g0<8,8,1>F      0x021c00b1
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 177, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g94<1>UW        g0<8,8,1>F      0x021c007a
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 122, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g95<1>UW        g0<8,8,1>F      0x021c007b
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 123, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g38<1>UW        g0<8,8,1>F      0x021c00ac
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 172, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         null<1>F        g121<8,8,1>F    0x8a080197
+                            urb MsgDesc: 25 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(8)         g2<1>UW         g17<8,8,1>UD    0x04495000
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g17<8,8,1>UD    0x04295c00
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xc) mlen 2 rlen 2 { align1 1Q };
+send(8)         g18<1>UW        g17<8,8,1>UD    0x04195e00
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 2 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g19<8,8,1>UD    0x0619a700
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, add) mlen 3 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g19<8,8,1>UD    0x0619ad00
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, umin) mlen 3 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g19<8,8,1>UD    0x0619ac00
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, umax) mlen 3 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g19<8,8,1>UD    0x0619a100
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, and) mlen 3 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g19<8,8,1>UD    0x0619a200
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, or) mlen 3 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g19<8,8,1>UD    0x0619a300
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, xor) mlen 3 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g19<8,8,1>UD    0x0619a400
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, mov) mlen 3 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g19<8,8,1>UD    0x0819ae00
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, cmpwr) mlen 4 rlen 1 { align1 1Q };
+send(8)         g34<1>UW        g0<8,8,1>F      0x021c00b3
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 179, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g35<1>UW        g0<8,8,1>F      0x021c00b4
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 180, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g36<1>UW        g0<8,8,1>F      0x021c00b5
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 181, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g119<1>UW       g0<8,8,1>F      0x021c00b8
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 184, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g117<1>UW       g0<8,8,1>F      0x021c00b7
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 183, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g40<1>UW        g0<8,8,1>F      0x021c00b6
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 182, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g17<1>UW        g0<8,8,1>F      0x021c00b9
+                            data MsgDesc: (*** invalid DP DC0 message type value 16 , 185, 0) mlen 1 rlen 1          { align1 WE_all 1Q };
+send(8)         g9<1>UW         g19<8,8,1>UD    0x0843e102
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g23<1>UW        g7<8,8,1>UD     0x1085e102
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+send(8)         g9<1>UW         g21<8,8,1>UD    0x0443d002
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g23<1>UW        g11<8,8,1>UD    0x0885d002
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g5<8,8,1>UD     0x0c4b0001
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x168d0001
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(8)         null<1>UW       g2<8,8,1>UD     0x060b5e01
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x060b6e01
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 3 rlen 0 { align1 2Q };
+(+f1.0) send(8) null<1>UW       g7<8,8,1>UD     0x0a026003
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 5 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g9<8,8,1>UD     0x14025003
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 10 rlen 0 { align1 1H };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x0a434001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g12<8,8,1>UD    0x0a434102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(8)         g22<1>UD        g10<8,8,1>UD    0x041a0138
+                            urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g21<1>UD        g10<8,8,1>UD    0x041a0338
+                            urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g65<1>UD        g10<8,8,1>UD    0x041a0538
+                            urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g10<1>UD        g10<8,8,1>UD    0x041a0738
+                            urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g65<1>UD        g11<8,8,1>UD    0x041a0238
+                            urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g10<1>UD        g11<8,8,1>UD    0x041a0438
+                            urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g11<1>UD        g11<8,8,1>UD    0x041a0638
+                            urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g8<1>UD         g7<8,8,1>UD     0x041a0048
+                            urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x0a4a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g12<8,8,1>UD    0x04009701
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, add) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g20<8,8,1>UD    0x08008701
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, add) mlen 4 rlen 0 { align1 1H };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x0c4b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g13<8,8,1>UD    0x0c4b4102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g10<8,8,1>UD    0x064a8203
+                            sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(16)        g26<1>UW        g2<8,8,1>UD     0x0a8c8203
+                            sampler MsgDesc: gather4 SIMD16 Surface = 3 Sampler = 2 mlen 5 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x08425102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g19<8,8,1>UD    0x10845102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x02306801
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0x8) mlen 1 rlen 3 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x04605801
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0x8) mlen 2 rlen 6 { align1 1H };
+send(8)         g8<1>UD         g7<8,8,1>UD     0x043a0128
+                            urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x104b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g20<8,8,1>UD    0x104b4102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 8 rlen 4 { align1 1Q };
+send(8)         g8<1>UD         g20<8,8,1>UD    0x044a0138
+                            urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g20<8,8,1>UD    0x044a0338
+                            urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g16<1>UD        g20<8,8,1>UD    0x044a0538
+                            urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g20<1>UD        g20<8,8,1>UD    0x044a0738
+                            urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g14<1>UD        g22<8,8,1>UD    0x044a0238
+                            urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g18<1>UD        g22<8,8,1>UD    0x044a0438
+                            urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g22<1>UD        g22<8,8,1>UD    0x044a0638
+                            urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g10<8,8,1>UD    0x04420004
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x08840004
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         null<1>UW       g1<8,8,1>UD     0x100b5001
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 8 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g1<8,8,1>UD     0x100b6001
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 8 rlen 0 { align1 2Q };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x0c4b2000
+                            sampler MsgDesc: gather4_po_c SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g13<1>UD        g39<8,8,1>UD    0x041a0058
+                            urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g10<8,8,1>UD    0x041a0068
+                            urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g3<8,8,1>UD     0x041a0078
+                            urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g3<8,8,1>UD     0x041a0088
+                            urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g3<8,8,1>UD     0x041a0098
+                            urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g3<8,8,1>UD     0x041a00a8
+                            urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g3<8,8,1>UD     0x041a00b8
+                            urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g3<8,8,1>UD     0x041a00c8
+                            urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a00d8
+                            urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a00e8
+                            urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a00f8
+                            urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0108
+                            urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0118
+                            urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0148
+                            urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0158
+                            urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0168
+                            urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0178
+                            urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0188
+                            urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0198
+                            urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a01a8
+                            urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a01b8
+                            urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a01c8
+                            urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a01d8
+                            urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a01e8
+                            urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a01f8
+                            urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0208
+                            urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g38<1>UW        g38<8,8,1>UD    0x084a8405
+                            sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 4 mlen 4 rlen 4 { align1 1Q };
+send(8)         g46<1>UW        g23<8,8,1>UD    0x064a8304
+                            sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(8)         g28<1>UW        g28<8,8,1>UD    0x064a8506
+                            sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 5 mlen 3 rlen 4 { align1 1Q };
+send(8)         g12<1>UW        g23<8,8,1>UD    0x064a8607
+                            sampler MsgDesc: gather4 SIMD8 Surface = 7 Sampler = 6 mlen 3 rlen 4 { align1 1Q };
+send(8)         g12<1>UW        g32<8,8,1>UD    0x084a8708
+                            sampler MsgDesc: gather4 SIMD8 Surface = 8 Sampler = 7 mlen 4 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g13<8,8,1>UD    0x064a8809
+                            sampler MsgDesc: gather4 SIMD8 Surface = 9 Sampler = 8 mlen 3 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g26<8,8,1>UD    0x084b090a
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 10 Sampler = 9 mlen 4 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x0a4b0a0b
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 11 Sampler = 10 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x084b0b0c
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 12 Sampler = 11 mlen 4 rlen 4 { align1 1Q };
+send(16)        g30<1>UW        g73<8,8,1>UD    0x0a8c8304
+                            sampler MsgDesc: gather4 SIMD16 Surface = 4 Sampler = 3 mlen 5 rlen 8 { align1 1H };
+send(16)        g40<1>UW        g2<8,8,1>UD     0x0e8c8405
+                            sampler MsgDesc: gather4 SIMD16 Surface = 5 Sampler = 4 mlen 7 rlen 8 { align1 1H };
+send(16)        g5<1>UW         g33<8,8,1>UD    0x0a8c8506
+                            sampler MsgDesc: gather4 SIMD16 Surface = 6 Sampler = 5 mlen 5 rlen 8 { align1 1H };
+send(16)        g32<1>UW        g55<8,8,1>UD    0x0a8c8607
+                            sampler MsgDesc: gather4 SIMD16 Surface = 7 Sampler = 6 mlen 5 rlen 8 { align1 1H };
+send(16)        g30<1>UW        g23<8,8,1>UD    0x0e8c8708
+                            sampler MsgDesc: gather4 SIMD16 Surface = 8 Sampler = 7 mlen 7 rlen 8 { align1 1H };
+send(16)        g5<1>UW         g40<8,8,1>UD    0x0a8c8809
+                            sampler MsgDesc: gather4 SIMD16 Surface = 9 Sampler = 8 mlen 5 rlen 8 { align1 1H };
+send(16)        g38<1>UW        g67<8,8,1>UD    0x0e8d090a
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 10 Sampler = 9 mlen 7 rlen 8 { align1 1H };
+send(16)        g38<1>UW        g2<8,8,1>UD     0x128d0a0b
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 11 Sampler = 10 mlen 9 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g39<8,8,1>UD    0x0e8d0b0c
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 12 Sampler = 11 mlen 7 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x0e4b2000
+                            sampler MsgDesc: gather4_po_c SIMD8 Surface = 0 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g67<1>UW        g2<8,8,1>UD     0x0410bbfe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD8, imin) mlen 2 rlen 1 { align1 1Q };
+send(8)         g13<1>UW        g4<8,8,1>UD     0x06495002
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD16, Mask = 0x0) mlen 3 rlen 4 { align1 1Q };
+send(8)         g9<1>UW         g7<8,8,1>UD     0x06496002
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD8, Mask = 0x0) mlen 3 rlen 4 { align1 2Q };
+send(8)         null<1>UW       g4<8,8,1>UD     0x0e0b5003
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 7 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g4<8,8,1>UD     0x0e0b6003
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 7 rlen 0 { align1 2Q };
+(+f1.0) send(8) g3<1>UW         g10<8,8,1>UD    0x0410b701
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, add) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g5<1>UW         g10<8,8,1>UD    0x0410bd01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umin) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g6<1>UW         g10<8,8,1>UD    0x0410bc01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umax) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g7<1>UW         g10<8,8,1>UD    0x0410b101
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, and) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g9<1>UW         g10<8,8,1>UD    0x0410b301
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, xor) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g10<1>UW        g10<8,8,1>UD    0x0410b401
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, mov) mlen 2 rlen 1 { align1 1Q };
+(+f1.0) send(8) g11<1>UW        g11<8,8,1>UD    0x0610be01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, cmpwr) mlen 3 rlen 1 { align1 1Q };
+(+f1.0) send(16) g3<1>UW        g19<8,8,1>UD    0x0820a701
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, add) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g7<1>UW        g19<8,8,1>UD    0x0820ad01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umin) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g9<1>UW        g19<8,8,1>UD    0x0820ac01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umax) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g11<1>UW       g19<8,8,1>UD    0x0820a101
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, and) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g15<1>UW       g19<8,8,1>UD    0x0820a301
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, xor) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g17<1>UW       g19<8,8,1>UD    0x0820a401
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, mov) mlen 4 rlen 2 { align1 1H };
+(+f1.0) send(16) g19<1>UW       g21<8,8,1>UD    0x0c20ae01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, cmpwr) mlen 6 rlen 2 { align1 1H };
+send(8)         null<1>F        g16<8,8,1>UD    0x0e0a8057
+                            urb MsgDesc: 5 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q };
+send(8)         g6<1>UD         g18<8,8,1>UD    0x043a0318
+                            urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g9<1>UD         g18<8,8,1>UD    0x043a0518
+                            urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g12<1>UD        g18<8,8,1>UD    0x043a0718
+                            urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g15<1>UD        g18<8,8,1>UD    0x043a0918
+                            urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g11<1>UD        g23<8,8,1>UD    0x043a0218
+                            urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g14<1>UD        g23<8,8,1>UD    0x043a0418
+                            urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g17<1>UD        g23<8,8,1>UD    0x043a0618
+                            urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g20<1>UD        g23<8,8,1>UD    0x043a0818
+                            urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0c0a8227
+                            urb MsgDesc: 34 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x0c0a8237
+                            urb MsgDesc: 35 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x0c0a8247
+                            urb MsgDesc: 36 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x0c0a8257
+                            urb MsgDesc: 37 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0c0a8267
+                            urb MsgDesc: 38 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0c0a8277
+                            urb MsgDesc: 39 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0c0a8287
+                            urb MsgDesc: 40 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0c0a8297
+                            urb MsgDesc: 41 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0c0a82a7
+                            urb MsgDesc: 42 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0c0a82b7
+                            urb MsgDesc: 43 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0c0a82c7
+                            urb MsgDesc: 44 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0c0a82d7
+                            urb MsgDesc: 45 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0c0a82e7
+                            urb MsgDesc: 46 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0c0a82f7
+                            urb MsgDesc: 47 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0c0a8307
+                            urb MsgDesc: 48 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0c0a8317
+                            urb MsgDesc: 49 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0c0a8327
+                            urb MsgDesc: 50 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0c0a8337
+                            urb MsgDesc: 51 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0c0a8347
+                            urb MsgDesc: 52 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0c0a8357
+                            urb MsgDesc: 53 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0c0a8367
+                            urb MsgDesc: 54 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0c0a8377
+                            urb MsgDesc: 55 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0c0a8387
+                            urb MsgDesc: 56 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0c0a8397
+                            urb MsgDesc: 57 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0c0a83a7
+                            urb MsgDesc: 58 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0c0a83b7
+                            urb MsgDesc: 59 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0c0a83c7
+                            urb MsgDesc: 60 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0c0a83d7
+                            urb MsgDesc: 61 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x0c0a83e7
+                            urb MsgDesc: 62 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g41<8,8,1>UD    0x0c0a83f7
+                            urb MsgDesc: 63 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x10434001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g15<8,8,1>UD    0x10434102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 8 rlen 4 { align1 1Q };
+send(8)         g16<1>UD        g16<8,8,1>UD    0x044a0148
+                            urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g38<1>UW        g38<8,8,1>UD    0x084a8404
+                            sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 4 mlen 4 rlen 4 { align1 1Q };
+send(8)         g46<1>UW        g23<8,8,1>UD    0x064a8303
+                            sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(8)         g28<1>UW        g28<8,8,1>UD    0x064a8505
+                            sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 5 mlen 3 rlen 4 { align1 1Q };
+send(8)         g12<1>UW        g23<8,8,1>UD    0x064a8606
+                            sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 6 mlen 3 rlen 4 { align1 1Q };
+send(8)         g12<1>UW        g32<8,8,1>UD    0x084a8707
+                            sampler MsgDesc: gather4 SIMD8 Surface = 7 Sampler = 7 mlen 4 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g13<8,8,1>UD    0x064a8808
+                            sampler MsgDesc: gather4 SIMD8 Surface = 8 Sampler = 8 mlen 3 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g26<8,8,1>UD    0x084b0909
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 9 Sampler = 9 mlen 4 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x0a4b0a0a
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 10 Sampler = 10 mlen 5 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g10<8,8,1>UD    0x084b0b0b
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 11 Sampler = 11 mlen 4 rlen 4 { align1 1Q };
+send(8)         null<1>UW       g1<8,8,1>UD     0x080b5e09
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 9, SIMD16, Mask = 0xe) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g1<8,8,1>UD     0x080b6e09
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 9, SIMD8, Mask = 0xe) mlen 4 rlen 0 { align1 2Q };
+send(8)         g2<1>UD         g15<8,8,1>UD    0x043a0048
+                            urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g12<1>UD        g15<8,8,1>UD    0x043a0058
+                            urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0068
+                            urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0078
+                            urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0088
+                            urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0098
+                            urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a00a8
+                            urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a00b8
+                            urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a00c8
+                            urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a00d8
+                            urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a00e8
+                            urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a00f8
+                            urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0108
+                            urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0118
+                            urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0138
+                            urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0148
+                            urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0158
+                            urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0168
+                            urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0178
+                            urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0188
+                            urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0198
+                            urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a01a8
+                            urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a01b8
+                            urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a01c8
+                            urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a01d8
+                            urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a01e8
+                            urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a01f8
+                            urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0208
+                            urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>F     0x140a0047
+                            urb MsgDesc: 4 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>F     0x140a0087
+                            urb MsgDesc: 8 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g118<8,8,1>F    0x940a0087
+                            urb MsgDesc: 8 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT };
+send(8)         g14<1>UW        g11<8,8,1>UD    0x0a4b0202
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 2 mlen 5 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x0c4b0303
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 3 Sampler = 3 mlen 6 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g24<8,8,1>UD    0x084b0404
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 4 Sampler = 4 mlen 4 rlen 4 { align1 1Q };
+send(8)         g24<1>UW        g2<8,8,1>UD     0x06423203
+                            sampler MsgDesc: sample_c SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(16)        g19<1>UW        g27<8,8,1>UD    0x0c843203
+                            sampler MsgDesc: sample_c SIMD16 Surface = 3 Sampler = 2 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x06422303
+                            sampler MsgDesc: sample_l SIMD8 Surface = 3 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04009d01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umin) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04009c01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umax) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04009101
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, and) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04009201
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04009301
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, xor) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g3<8,8,1>UD     0x04009401
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, mov) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g9<8,8,1>UD     0x06009e01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, cmpwr) mlen 3 rlen 0 { align1 1Q };
+(+f1.0) send(16) null<1>UW      g4<8,8,1>UD     0x08008d01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umin) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g4<8,8,1>UD     0x08008c01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umax) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g4<8,8,1>UD     0x08008101
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, and) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g4<8,8,1>UD     0x08008201
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g4<8,8,1>UD     0x08008301
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, xor) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g4<8,8,1>UD     0x08008401
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, mov) mlen 4 rlen 0 { align1 1H };
+(+f1.0) send(16) null<1>UW      g14<8,8,1>UD    0x0c008e01
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, cmpwr) mlen 6 rlen 0 { align1 1H };
+send(8)         g11<1>UD        g17<8,8,1>UD    0x043a0338
+                            urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g14<1>UD        g17<8,8,1>UD    0x043a0538
+                            urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g17<1>UD        g17<8,8,1>UD    0x043a0738
+                            urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g9<1>UD         g18<8,8,1>UD    0x043a0038
+                            urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g12<1>UD        g18<8,8,1>UD    0x043a0238
+                            urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g15<1>UD        g18<8,8,1>UD    0x043a0438
+                            urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g18<1>UD        g18<8,8,1>UD    0x043a0638
+                            urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x08424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g9<1>UW         g5<8,8,1>UD     0x04420002
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g13<1>UW        g7<8,8,1>UD     0x08840002
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x0419a501
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, inc) mlen 2 rlen 1 { align1 1Q };
+send(8)         g121<1>UW       g2<8,8,1>UD     0x0419b501
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, inc) mlen 2 rlen 1 { align1 2Q };
+send(8)         null<1>UW       g20<8,8,1>UD    0x06098101
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, and) mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06099101
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, and) mlen 3 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g19<8,8,1>UD    0x06098201
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, or) mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06099201
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, or) mlen 3 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g19<8,8,1>UD    0x06098301
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, xor) mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x06099301
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, xor) mlen 3 rlen 0 { align1 2Q };
+send(8)         g22<1>UD        g32<8,8,1>UD    0x02280238
+                            urb MsgDesc: 35 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g24<1>UD        g32<8,8,1>UD    0x02280438
+                            urb MsgDesc: 67 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g26<1>UD        g32<8,8,1>UD    0x02280638
+                            urb MsgDesc: 99 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g28<1>UD        g32<8,8,1>UD    0x02280248
+                            urb MsgDesc: 36 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g30<1>UD        g32<8,8,1>UD    0x02280448
+                            urb MsgDesc: 68 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g32<1>UD        g32<8,8,1>UD    0x02280648
+                            urb MsgDesc: 100 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g22<1>UD        g33<8,8,1>UD    0x02280258
+                            urb MsgDesc: 37 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g24<1>UD        g33<8,8,1>UD    0x02280458
+                            urb MsgDesc: 69 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g26<1>UD        g33<8,8,1>UD    0x02280658
+                            urb MsgDesc: 101 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g22<1>UD        g34<8,8,1>UD    0x02280268
+                            urb MsgDesc: 38 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g24<1>UD        g34<8,8,1>UD    0x02280468
+                            urb MsgDesc: 70 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g26<1>UD        g34<8,8,1>UD    0x02280668
+                            urb MsgDesc: 102 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g24<1>UD        g35<8,8,1>UD    0x02280478
+                            urb MsgDesc: 71 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g35<8,8,1>UD    0x02280278
+                            urb MsgDesc: 39 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g26<1>UD        g35<8,8,1>UD    0x02280678
+                            urb MsgDesc: 103 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g24<1>UD        g36<8,8,1>UD    0x02280688
+                            urb MsgDesc: 104 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g36<8,8,1>UD    0x02280288
+                            urb MsgDesc: 40 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g36<8,8,1>UD    0x02280488
+                            urb MsgDesc: 72 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g37<8,8,1>UD    0x02280298
+                            urb MsgDesc: 41 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g37<8,8,1>UD    0x02280498
+                            urb MsgDesc: 73 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g24<1>UD        g37<8,8,1>UD    0x02280698
+                            urb MsgDesc: 105 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g38<8,8,1>UD    0x022802a8
+                            urb MsgDesc: 42 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g38<8,8,1>UD    0x022804a8
+                            urb MsgDesc: 74 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g24<1>UD        g38<8,8,1>UD    0x022806a8
+                            urb MsgDesc: 106 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g39<8,8,1>UD    0x022802b8
+                            urb MsgDesc: 43 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g39<8,8,1>UD    0x022804b8
+                            urb MsgDesc: 75 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g24<1>UD        g39<8,8,1>UD    0x022806b8
+                            urb MsgDesc: 107 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g40<8,8,1>UD    0x022802c8
+                            urb MsgDesc: 44 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g40<8,8,1>UD    0x022804c8
+                            urb MsgDesc: 76 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g40<8,8,1>UD    0x022806c8
+                            urb MsgDesc: 108 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g41<8,8,1>UD    0x022802d8
+                            urb MsgDesc: 45 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g41<8,8,1>UD    0x022804d8
+                            urb MsgDesc: 77 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g41<8,8,1>UD    0x022806d8
+                            urb MsgDesc: 109 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g42<8,8,1>UD    0x022802e8
+                            urb MsgDesc: 46 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g42<8,8,1>UD    0x022804e8
+                            urb MsgDesc: 78 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g42<8,8,1>UD    0x022806e8
+                            urb MsgDesc: 110 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g43<8,8,1>UD    0x022802f8
+                            urb MsgDesc: 47 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g43<8,8,1>UD    0x022804f8
+                            urb MsgDesc: 79 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g43<8,8,1>UD    0x022806f8
+                            urb MsgDesc: 111 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g44<8,8,1>UD    0x02280308
+                            urb MsgDesc: 48 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g44<8,8,1>UD    0x02280508
+                            urb MsgDesc: 80 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g44<8,8,1>UD    0x02280708
+                            urb MsgDesc: 112 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g45<8,8,1>UD    0x02280318
+                            urb MsgDesc: 49 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g45<8,8,1>UD    0x02280518
+                            urb MsgDesc: 81 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g45<8,8,1>UD    0x02280718
+                            urb MsgDesc: 113 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g46<8,8,1>UD    0x02280328
+                            urb MsgDesc: 50 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g46<8,8,1>UD    0x02280528
+                            urb MsgDesc: 82 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g46<8,8,1>UD    0x02280728
+                            urb MsgDesc: 114 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g47<8,8,1>UD    0x02280338
+                            urb MsgDesc: 51 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g47<8,8,1>UD    0x02280538
+                            urb MsgDesc: 83 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g47<8,8,1>UD    0x02280738
+                            urb MsgDesc: 115 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g48<8,8,1>UD    0x02280348
+                            urb MsgDesc: 52 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g48<8,8,1>UD    0x02280548
+                            urb MsgDesc: 84 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g48<8,8,1>UD    0x02280748
+                            urb MsgDesc: 116 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g49<8,8,1>UD    0x02280358
+                            urb MsgDesc: 53 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g49<8,8,1>UD    0x02280558
+                            urb MsgDesc: 85 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g49<8,8,1>UD    0x02280758
+                            urb MsgDesc: 117 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g50<8,8,1>UD    0x02280368
+                            urb MsgDesc: 54 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g50<8,8,1>UD    0x02280568
+                            urb MsgDesc: 86 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g50<8,8,1>UD    0x02280768
+                            urb MsgDesc: 118 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g53<8,8,1>UD    0x02280378
+                            urb MsgDesc: 55 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g53<8,8,1>UD    0x02280578
+                            urb MsgDesc: 87 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g53<8,8,1>UD    0x02280778
+                            urb MsgDesc: 119 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g54<8,8,1>UD    0x02280388
+                            urb MsgDesc: 56 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g54<8,8,1>UD    0x02280588
+                            urb MsgDesc: 88 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g54<8,8,1>UD    0x02280788
+                            urb MsgDesc: 120 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g55<8,8,1>UD    0x02280398
+                            urb MsgDesc: 57 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g55<8,8,1>UD    0x02280598
+                            urb MsgDesc: 89 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g55<8,8,1>UD    0x02280798
+                            urb MsgDesc: 121 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g56<8,8,1>UD    0x022803a8
+                            urb MsgDesc: 58 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g56<8,8,1>UD    0x022805a8
+                            urb MsgDesc: 90 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g56<8,8,1>UD    0x022807a8
+                            urb MsgDesc: 122 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g57<8,8,1>UD    0x022803b8
+                            urb MsgDesc: 59 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g57<8,8,1>UD    0x022805b8
+                            urb MsgDesc: 91 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g57<8,8,1>UD    0x022807b8
+                            urb MsgDesc: 123 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g58<8,8,1>UD    0x022803c8
+                            urb MsgDesc: 60 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g58<8,8,1>UD    0x022805c8
+                            urb MsgDesc: 92 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g58<8,8,1>UD    0x022807c8
+                            urb MsgDesc: 124 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g59<8,8,1>UD    0x022803d8
+                            urb MsgDesc: 61 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g59<8,8,1>UD    0x022805d8
+                            urb MsgDesc: 93 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g59<8,8,1>UD    0x022807d8
+                            urb MsgDesc: 125 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g60<8,8,1>UD    0x022803e8
+                            urb MsgDesc: 62 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g60<8,8,1>UD    0x022805e8
+                            urb MsgDesc: 94 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g60<8,8,1>UD    0x022807e8
+                            urb MsgDesc: 126 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g61<8,8,1>UD    0x022803f8
+                            urb MsgDesc: 63 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g61<8,8,1>UD    0x022805f8
+                            urb MsgDesc: 95 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g61<8,8,1>UD    0x022807f8
+                            urb MsgDesc: 127 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g10<1>UD        g62<8,8,1>UD    0x02280408
+                            urb MsgDesc: 64 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g62<8,8,1>UD    0x02280608
+                            urb MsgDesc: 96 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g14<1>UD        g62<8,8,1>UD    0x02280808
+                            urb MsgDesc: 128 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g63<8,8,1>UD    0x02280218
+                            urb MsgDesc: 33 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g63<8,8,1>UD    0x02280418
+                            urb MsgDesc: 65 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g63<8,8,1>UD    0x02280618
+                            urb MsgDesc: 97 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g14<1>UD        g63<8,8,1>UD    0x02280818
+                            urb MsgDesc: 129 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g29<1>UW        g18<8,8,1>UD    0x04420008
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g35<1>UW        g18<8,8,1>UD    0x04420109
+                            sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(8)         g41<1>UW        g18<8,8,1>UD    0x0442020a
+                            sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 2 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g18<8,8,1>UD    0x0442030b
+                            sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 3 mlen 2 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g18<8,8,1>UD    0x0442040c
+                            sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g18<8,8,1>UD    0x0442050d
+                            sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 5 mlen 2 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g18<8,8,1>UD    0x0442060e
+                            sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 6 mlen 2 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x0442070f
+                            sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 7 mlen 2 rlen 4 { align1 1Q };
+send(16)        g32<1>UW        g22<8,8,1>UD    0x08840008
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g42<1>UW        g22<8,8,1>UD    0x08840109
+                            sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(16)        g60<1>UW        g22<8,8,1>UD    0x0884020a
+                            sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 2 mlen 4 rlen 8 { align1 1H };
+send(16)        g70<1>UW        g22<8,8,1>UD    0x0884030b
+                            sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 3 mlen 4 rlen 8 { align1 1H };
+send(16)        g78<1>UW        g22<8,8,1>UD    0x0884040c
+                            sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 4 mlen 4 rlen 8 { align1 1H };
+send(16)        g86<1>UW        g22<8,8,1>UD    0x0884050d
+                            sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 5 mlen 4 rlen 8 { align1 1H };
+send(16)        g94<1>UW        g22<8,8,1>UD    0x0884060e
+                            sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 6 mlen 4 rlen 8 { align1 1H };
+send(16)        g52<1>UW        g22<8,8,1>UD    0x0884070f
+                            sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 7 mlen 4 rlen 8 { align1 1H };
+send(8)         g16<1>UW        g42<8,8,1>UD    0x06422101
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(8)         g20<1>UW        g42<8,8,1>UD    0x06422202
+                            sampler MsgDesc: sample_l SIMD8 Surface = 2 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(8)         g29<1>UW        g42<8,8,1>UD    0x06422404
+                            sampler MsgDesc: sample_l SIMD8 Surface = 4 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
+send(8)         g38<1>UW        g42<8,8,1>UD    0x06422606
+                            sampler MsgDesc: sample_l SIMD8 Surface = 6 Sampler = 6 mlen 3 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g42<8,8,1>UD    0x06422707
+                            sampler MsgDesc: sample_l SIMD8 Surface = 7 Sampler = 7 mlen 3 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g16<8,8,1>UD    0x044a0058
+                            urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0068
+                            urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0078
+                            urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0088
+                            urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0098
+                            urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a00a8
+                            urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a00b8
+                            urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a00c8
+                            urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a00d8
+                            urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a00e8
+                            urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a00f8
+                            urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0108
+                            urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0118
+                            urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0158
+                            urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0168
+                            urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0178
+                            urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0188
+                            urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0198
+                            urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a01a8
+                            urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a01b8
+                            urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a01c8
+                            urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a01d8
+                            urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a01e8
+                            urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a01f8
+                            urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0208
+                            urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x0a425001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g17<8,8,1>UD    0x0a425102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g27<1>UW        g7<8,8,1>UD     0x14845001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(16)        g35<1>UW        g17<8,8,1>UD    0x14845102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H };
+send(8)         null<1>F        g120<8,8,1>F    0x8c0a0117
+                            urb MsgDesc: 17 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380128
+                            urb MsgDesc: 18 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380138
+                            urb MsgDesc: 19 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380148
+                            urb MsgDesc: 20 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380158
+                            urb MsgDesc: 21 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380168
+                            urb MsgDesc: 22 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380178
+                            urb MsgDesc: 23 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380188
+                            urb MsgDesc: 24 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380198
+                            urb MsgDesc: 25 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x023801a8
+                            urb MsgDesc: 26 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x023801b8
+                            urb MsgDesc: 27 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x023801c8
+                            urb MsgDesc: 28 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x023801d8
+                            urb MsgDesc: 29 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x023801e8
+                            urb MsgDesc: 30 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x023801f8
+                            urb MsgDesc: 31 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         null<1>UW       g18<8,8,1>UD    0x08098701
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, add) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099701
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, add) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g18<8,8,1>UD    0x08098d01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, umin) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099d01
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, umin) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g18<8,8,1>UD    0x08098101
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, and) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099101
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, and) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g18<8,8,1>UD    0x08098201
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, or) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099201
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, or) mlen 4 rlen 0 { align1 2Q };
+send(8)         null<1>UW       g18<8,8,1>UD    0x08098301
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, xor) mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g2<8,8,1>UD     0x08099301
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, xor) mlen 4 rlen 0 { align1 2Q };
+send(8)         g11<1>UD        g13<8,8,1>UD    0x042a0058
+                            urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a0068
+                            urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a0078
+                            urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a0088
+                            urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a0098
+                            urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a00a8
+                            urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a00b8
+                            urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a00c8
+                            urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a00d8
+                            urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a00e8
+                            urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a00f8
+                            urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a0108
+                            urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a0118
+                            urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a0158
+                            urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a0168
+                            urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a0178
+                            urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a0188
+                            urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a0198
+                            urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a01a8
+                            urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a01b8
+                            urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a01c8
+                            urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a01d8
+                            urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a01e8
+                            urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a01f8
+                            urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a0208
+                            urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x024ab102
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g10<8,8,1>UD    0x024ab203
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g14<8,8,1>UD    0x024ab304
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x024ab405
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g22<8,8,1>UD    0x024ab506
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x028cb102
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 2 Sampler = 1 mlen 1 rlen 8 { align1 1H };
+send(16)        g28<1>UW        g27<8,8,1>UD    0x028cb203
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 3 Sampler = 2 mlen 1 rlen 8 { align1 1H };
+send(16)        g36<1>UW        g44<8,8,1>UD    0x028cb304
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 4 Sampler = 3 mlen 1 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g53<8,8,1>UD    0x028cb506
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 6 Sampler = 5 mlen 1 rlen 8 { align1 1H };
+send(16)        g44<1>UW        g52<8,8,1>UD    0x028cb405
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 5 Sampler = 4 mlen 1 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x0a4b0102
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g11<8,8,1>UD    0x0a4b0203
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 3 Sampler = 2 mlen 5 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x0c4b0304
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 4 Sampler = 3 mlen 6 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g24<8,8,1>UD    0x084b0405
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 5 Sampler = 4 mlen 4 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x128d0203
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 3 Sampler = 2 mlen 9 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g53<8,8,1>UD    0x128d0102
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 8 { align1 1H };
+send(16)        g26<1>UW        g35<8,8,1>UD    0x168d0304
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 4 Sampler = 3 mlen 11 rlen 8 { align1 1H };
+send(16)        g34<1>UW        g46<8,8,1>UD    0x0e8d0405
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 5 Sampler = 4 mlen 7 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g9<8,8,1>UD     0x0c4b0000
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q };

diff --git a/src/intel/tools/tests/gen8/send.expected b/src/intel/tools/tests/gen8/send.expected
new file mode 100644 (file)
index 0000000..1389058
--- /dev/null
+++ b/src/intel/tools/tests/gen8/send.expected
@@ -0,0 +1,2190 @@
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diff --git a/src/intel/tools/tests/gen8/sendc.asm b/src/intel/tools/tests/gen8/sendc.asm
new file mode 100644 (file)
index 0000000..c5d0d6e
--- /dev/null
+++ b/src/intel/tools/tests/gen8/sendc.asm
@@ -0,0 +1,100 @@
+sendc(8)        null<1>UW       g124<8,8,1>F    0x88031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g120<8,8,1>F    0x90031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       g114<8,8,1>F    0x82031100
+                            render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
+(+f0.1) sendc(8) null<1>UW      g124<8,8,1>F    0x88031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1401
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g13<8,8,1>F     0x0e0b0401
+                            render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g121<8,8,1>F    0x8e0b1402
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g7<8,8,1>F      0x180b0001
+                            render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g116<8,8,1>F    0x980b1002
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g123<8,8,1>F    0x8a031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x94031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       g119<8,8,1>F    0x92031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 9 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g5<8,8,1>F      0x0c0b0400
+                            render MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g5<8,8,1>F      0x0c0b0401
+                            render MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g5<8,8,1>F      0x0c0b0402
+                            render MsgDesc: RT write SIMD8 Surface = 2 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g5<8,8,1>F      0x0c0b0403
+                            render MsgDesc: RT write SIMD8 Surface = 3 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g5<8,8,1>F      0x0c0b0404
+                            render MsgDesc: RT write SIMD8 Surface = 4 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1405
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 5 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g5<8,8,1>F      0x140b0000
+                            render MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g5<8,8,1>F      0x140b0001
+                            render MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g5<8,8,1>F      0x140b0002
+                            render MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g5<8,8,1>F      0x140b0003
+                            render MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g5<8,8,1>F      0x140b0004
+                            render MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1005
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1403
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1003
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1402
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1002
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g118<8,8,1>F    0x940b1200
+                            render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g3<8,8,1>F      0x140b1200
+                            render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g118<8,8,1>F    0x940b1300
+                            render MsgDesc: RT write SIMD8/DualSrcHigh LastRT Surface = 0 mlen 10 rlen 0 { align1 2Q EOT };
+sendc(8)        null<1>UW       g23<8,8,1>F     0x0c0b0405
+                            render MsgDesc: RT write SIMD8 Surface = 5 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g29<8,8,1>F     0x0c0b0406
+                            render MsgDesc: RT write SIMD8 Surface = 6 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1407
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 7 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g57<8,8,1>F     0x140b0005
+                            render MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g17<8,8,1>F     0x140b0006
+                            render MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1007
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g10<8,8,1>F     0x0e0b0400
+                            render MsgDesc: RT write SIMD8 Surface = 0 mlen 7 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g121<8,8,1>F    0x8e0b1401
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g2<8,8,1>F      0x160b0000
+                            render MsgDesc: RT write SIMD16 Surface = 0 mlen 11 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g117<8,8,1>F    0x960b1001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 11 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1404
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 4 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1004
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>F    0x8c0b1406
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 6 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<8,8,1>F    0x940b1006
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       g116<8,8,1>F    0x980b1001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 12 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       g11<8,8,1>F     0x180b0000
+                            render MsgDesc: RT write SIMD16 Surface = 0 mlen 12 rlen 0 { align1 1H };

diff --git a/src/intel/tools/tests/gen8/sendc.expected b/src/intel/tools/tests/gen8/sendc.expected
new file mode 100644 (file)
index 0000000..cf93e44
--- /dev/null
+++ b/src/intel/tools/tests/gen8/sendc.expected
@@ -0,0 +1,50 @@
+32 00 60 05 40 3a 00 20 80 0f 8d 06 00 14 03 88
+32 00 80 05 40 3a 00 20 00 0f 8d 06 00 10 03 90
+32 00 80 05 40 3a 00 20 40 0e 8d 06 00 11 03 82
+32 00 61 05 41 3a 00 20 80 0f 8d 06 00 14 03 88
+32 00 60 05 40 3a 00 20 40 0f 8d 06 01 14 0b 8c
+32 00 80 05 40 3a 00 20 c0 0e 8d 06 01 10 0b 94
+32 00 60 05 40 3a 00 20 a0 01 8d 06 01 04 0b 0e
+32 00 60 05 40 3a 00 20 20 0f 8d 06 02 14 0b 8e
+32 00 80 05 40 3a 00 20 e0 00 8d 06 01 00 0b 18
+32 00 80 05 40 3a 00 20 80 0e 8d 06 02 10 0b 98
+32 00 60 05 40 3a 00 20 60 0f 8d 06 00 14 03 8a
+32 00 80 05 40 3a 00 20 c0 0e 8d 06 00 10 03 94
+32 00 80 05 40 3a 00 20 e0 0e 8d 06 00 10 03 92
+32 00 60 05 40 3a 00 20 a0 00 8d 06 00 04 0b 0c
+32 00 60 05 40 3a 00 20 a0 00 8d 06 01 04 0b 0c
+32 00 60 05 40 3a 00 20 a0 00 8d 06 02 04 0b 0c
+32 00 60 05 40 3a 00 20 a0 00 8d 06 03 04 0b 0c
+32 00 60 05 40 3a 00 20 a0 00 8d 06 04 04 0b 0c
+32 00 60 05 40 3a 00 20 40 0f 8d 06 05 14 0b 8c
+32 00 80 05 40 3a 00 20 a0 00 8d 06 00 00 0b 14
+32 00 80 05 40 3a 00 20 a0 00 8d 06 01 00 0b 14
+32 00 80 05 40 3a 00 20 a0 00 8d 06 02 00 0b 14
+32 00 80 05 40 3a 00 20 a0 00 8d 06 03 00 0b 14
+32 00 80 05 40 3a 00 20 a0 00 8d 06 04 00 0b 14
+32 00 80 05 40 3a 00 20 c0 0e 8d 06 05 10 0b 94
+32 00 60 05 40 3a 00 20 40 0f 8d 06 03 14 0b 8c
+32 00 80 05 40 3a 00 20 c0 0e 8d 06 03 10 0b 94
+32 00 60 05 40 3a 00 20 40 0f 8d 06 02 14 0b 8c
+32 00 80 05 40 3a 00 20 c0 0e 8d 06 02 10 0b 94
+32 00 60 05 40 3a 00 20 40 0f 8d 06 00 14 0b 8c
+32 00 80 05 40 3a 00 20 c0 0e 8d 06 00 10 0b 94
+32 00 60 05 40 3a 00 20 c0 0e 8d 06 00 12 0b 94
+32 00 60 05 40 3a 00 20 60 00 8d 06 00 12 0b 14
+32 10 60 05 40 3a 00 20 c0 0e 8d 06 00 13 0b 94
+32 00 60 05 40 3a 00 20 e0 02 8d 06 05 04 0b 0c
+32 00 60 05 40 3a 00 20 a0 03 8d 06 06 04 0b 0c
+32 00 60 05 40 3a 00 20 40 0f 8d 06 07 14 0b 8c
+32 00 80 05 40 3a 00 20 20 07 8d 06 05 00 0b 14
+32 00 80 05 40 3a 00 20 20 02 8d 06 06 00 0b 14
+32 00 80 05 40 3a 00 20 c0 0e 8d 06 07 10 0b 94
+32 00 60 05 40 3a 00 20 40 01 8d 06 00 04 0b 0e
+32 00 60 05 40 3a 00 20 20 0f 8d 06 01 14 0b 8e
+32 00 80 05 40 3a 00 20 40 00 8d 06 00 00 0b 16
+32 00 80 05 40 3a 00 20 a0 0e 8d 06 01 10 0b 96
+32 00 60 05 40 3a 00 20 40 0f 8d 06 04 14 0b 8c
+32 00 80 05 40 3a 00 20 c0 0e 8d 06 04 10 0b 94
+32 00 60 05 40 3a 00 20 40 0f 8d 06 06 14 0b 8c
+32 00 80 05 40 3a 00 20 c0 0e 8d 06 06 10 0b 94
+32 00 80 05 40 3a 00 20 80 0e 8d 06 01 10 0b 98
+32 00 80 05 40 3a 00 20 60 01 8d 06 00 00 0b 18

diff --git a/src/intel/tools/tests/gen8/shl.asm b/src/intel/tools/tests/gen8/shl.asm
new file mode 100644 (file)
index 0000000..0ef2de7
--- /dev/null
+++ b/src/intel/tools/tests/gen8/shl.asm
@@ -0,0 +1,13 @@
+shl(16)         g25<1>D         g27<8,8,1>D     0x00000002UD    { align1 1H };
+shl(8)          g18<1>D         g17<8,8,1>D     0x00000002UD    { align1 1Q };
+shl(1)          g2<1>UD         g5<0,1,0>UD     0x00000008UD    { align1 WE_all 1N };
+shl(8)          g4<1>UD         g6<8,8,1>UD     g3<8,8,1>UD     { align1 1Q };
+shl(1)          a0<1>UD         g27<0,1,0>UD    0x00000002UD    { align1 WE_all 1N };
+shl(16)         g36<1>D         g1<0,1,0>D      0x00000005UD    { align1 2H };
+shl(8)          g26<1>UD        g34<8,8,1>UW    0x00000002UD    { align1 1Q };
+shl(8)          g3<1>UD         g23<8,8,1>UD    g21<8,8,1>UD    { align1 WE_all 1Q };
+shl(16)         g10<1>UD        g10<8,8,1>UD    0x00000010UD    { align1 1H };
+shl(1)          g22<1>UD        g22<0,1,0>UD    0x00000004UD    { align1 WE_all 3N };
+shl(8)          g11<1>Q         g5<4,4,1>Q      g3<4,4,1>UD     { align1 1Q };
+shl(1)          a0<1>UD         g13<0,1,0>D     0x00000002UD    { align1 WE_all 1N };
+shl(8)          g22<1>Q         g8<4,4,1>Q      g4<4,4,1>UD     { align1 2Q };

diff --git a/src/intel/tools/tests/gen8/shl.expected b/src/intel/tools/tests/gen8/shl.expected
new file mode 100644 (file)
index 0000000..2fc795e
--- /dev/null
+++ b/src/intel/tools/tests/gen8/shl.expected
@@ -0,0 +1,13 @@
+09 00 80 00 28 0a 20 23 60 03 8d 06 02 00 00 00
+09 00 60 00 28 0a 40 22 20 02 8d 06 02 00 00 00
+09 00 00 00 0c 02 40 20 a0 00 00 06 08 00 00 00
+09 00 60 00 08 02 80 20 c0 00 8d 02 60 00 8d 00
+09 00 00 00 04 02 00 22 60 03 00 06 02 00 00 00
+09 20 80 00 28 0a 80 24 20 00 00 06 05 00 00 00
+09 00 60 00 08 12 40 23 40 04 8d 06 02 00 00 00
+09 00 60 00 0c 02 60 20 e0 02 8d 02 a0 02 8d 00
+09 00 80 00 08 02 40 21 40 01 8d 06 10 00 00 00
+09 10 00 00 0c 02 c0 22 c0 02 00 06 04 00 00 00
+09 00 60 00 28 4b 60 21 a0 00 69 02 60 00 69 00
+09 00 00 00 04 0a 00 22 a0 01 00 06 02 00 00 00
+09 10 60 00 28 4b c0 22 00 01 69 02 80 00 69 00

diff --git a/src/intel/tools/tests/gen8/shr.asm b/src/intel/tools/tests/gen8/shr.asm
new file mode 100644 (file)
index 0000000..8d6e055
--- /dev/null
+++ b/src/intel/tools/tests/gen8/shr.asm
@@ -0,0 +1,8 @@
+shr(8)          g20<1>UD        g19<8,8,1>UD    0x00000001UD    { align1 1Q };
+shr(16)         g51<1>UD        g49<8,8,1>UD    0x00000001UD    { align1 1H };
+shr(16)         g4<1>UW         g1<1,8,0>UB     0x44440000V     { align1 1H };
+shr.z.f0.0(8)   g3<1>UD         g1<8,8,1>UD     0x0000001bUD    { align1 1Q };
+shr.z.f0.0(8)   null<1>UD       g1<8,8,1>UD     0x0000001bUD    { align1 1Q };
+shr(8)          g3<1>UW         g1.28<1,8,0>UB  0x76543210V     { align1 1Q };
+shr(8)          g3<2>UW         g5<8,8,1>UD     g4<8,8,1>UW     { align1 1Q };
+shr(16)         g20<2>UW        g15<8,8,1>UD    g13<8,8,1>UW    { align1 1H };

diff --git a/src/intel/tools/tests/gen8/shr.expected b/src/intel/tools/tests/gen8/shr.expected
new file mode 100644 (file)
index 0000000..9ed2027
--- /dev/null
+++ b/src/intel/tools/tests/gen8/shr.expected
@@ -0,0 +1,8 @@
+08 00 60 00 08 02 80 22 60 02 8d 06 01 00 00 00
+08 00 80 00 08 02 60 26 20 06 8d 06 01 00 00 00
+08 00 80 00 48 22 80 20 20 00 2c 36 00 00 44 44
+08 00 60 01 08 02 60 20 20 00 8d 06 1b 00 00 00
+08 00 60 01 00 02 00 20 20 00 8d 06 1b 00 00 00
+08 00 60 00 48 22 60 20 3c 00 2c 36 10 32 54 76
+08 00 60 00 48 02 60 40 a0 00 8d 12 80 00 8d 00
+08 00 80 00 48 02 80 42 e0 01 8d 12 a0 01 8d 00

diff --git a/src/intel/tools/tests/gen8/wait.asm b/src/intel/tools/tests/gen8/wait.asm
new file mode 100644 (file)
index 0000000..8cb494e
--- /dev/null
+++ b/src/intel/tools/tests/gen8/wait.asm
@@ -0,0 +1 @@
+wait(1)                         n0<0,1,0>UD                     { align1 WE_all 1N };

diff --git a/src/intel/tools/tests/gen8/wait.expected b/src/intel/tools/tests/gen8/wait.expected
new file mode 100644 (file)
index 0000000..81603b0
--- /dev/null
+++ b/src/intel/tools/tests/gen8/wait.expected
@@ -0,0 +1 @@
+30 00 00 00 04 00 00 32 00 12 00 38 00 00 8d 00

diff --git a/src/intel/tools/tests/gen8/while.asm b/src/intel/tools/tests/gen8/while.asm
new file mode 100644 (file)
index 0000000..00bd8e1
--- /dev/null
+++ b/src/intel/tools/tests/gen8/while.asm
@@ -0,0 +1,4 @@
+while(8)        JIP: -160                                       { align1 1Q };
+while(16)       JIP: -160                                       { align1 1H };
+(-f0.0) while(8) JIP: -384                                      { align1 1Q };
+(-f0.0) while(16) JIP: -384                                     { align1 1H };

diff --git a/src/intel/tools/tests/gen8/while.expected b/src/intel/tools/tests/gen8/while.expected
new file mode 100644 (file)
index 0000000..5b0fd85
--- /dev/null
+++ b/src/intel/tools/tests/gen8/while.expected
@@ -0,0 +1,4 @@
+27 00 60 00 20 0e 00 20 00 00 00 08 60 ff ff ff
+27 00 80 00 20 0e 00 20 00 00 00 08 60 ff ff ff
+27 00 71 00 20 0e 00 20 00 00 00 08 80 fe ff ff
+27 00 91 00 20 0e 00 20 00 00 00 08 80 fe ff ff

diff --git a/src/intel/tools/tests/gen8/xor.asm b/src/intel/tools/tests/gen8/xor.asm
new file mode 100644 (file)
index 0000000..737a16a
--- /dev/null
+++ b/src/intel/tools/tests/gen8/xor.asm
@@ -0,0 +1,2 @@
+xor(16)         g10<1>UD        g1<0,1,0>UD     g1.1<0,1,0>UD   { align1 1H };
+xor(8)          g4<1>UD         g5.6<0,1,0>UD   ~g5.7<0,1,0>D   { align1 1Q };

diff --git a/src/intel/tools/tests/gen8/xor.expected b/src/intel/tools/tests/gen8/xor.expected
new file mode 100644 (file)
index 0000000..c60a3fb
--- /dev/null
+++ b/src/intel/tools/tests/gen8/xor.expected
@@ -0,0 +1,2 @@
+07 00 80 00 08 02 40 21 20 00 00 02 24 00 00 00
+07 00 60 00 08 02 80 20 b8 00 00 0a bc 40 00 00

diff --git a/src/intel/tools/tests/gen9/add.asm b/src/intel/tools/tests/gen9/add.asm
new file mode 100644 (file)
index 0000000..5d751c2
--- /dev/null
+++ b/src/intel/tools/tests/gen9/add.asm
@@ -0,0 +1,40 @@
+add(8)          g124<1>F        g7<8,8,1>D      1D              { align1 1Q };
+add(16)         g120<1>F        g11<8,8,1>D     1D              { align1 1H };
+add(16)         g4<1>F          g1<0,1,0>F      -g1.4<0,1,0>F   { align1 1H };
+add(8)          g3.8<1>UW       g3<8,8,1>UW     0x0008UW        { align1 WE_all 1Q };
+add(16)         g3<1>D          g18<8,8,1>D     g12<8,8,1>D     { align1 1H };
+add(16)         g6<1>UW         g1.4<1,4,0>UW   0x11001010V     { align1 WE_all 1H };
+add(32)         g10<1>UW        g1.4<1,4,0>UW   0x11001010V     { align1 WE_all };
+add(8)          g2<1>D          g96<8,8,1>D     -1023D          { align1 1Q };
+add(8)          g4<1>F          g5.6<0,1,0>F    g7.2<0,1,0>F    { align1 1Q };
+add(8)          g53<1>DF        g49<4,4,1>DF    g51<4,4,1>DF    { align1 1Q };
+add.sat(16)     g5<1>UD         g3<8,8,1>UD     0x00000001UD    { align1 1H };
+add(1)          g125.3<1>UD     g0.3<0,1,0>UD   g7<0,1,0>UD     { align1 WE_all 1N };
+add(8)          a0<1>UW         g34<16,8,2>UW   0x0080UW        { align1 1Q };
+add(8)          g8<1>DF         g2<0,1,0>DF     g3.2<0,1,0>DF   { align1 2Q };
+add(16)         a0<1>UW         g3<16,8,2>UW    0x0040UW        { align1 1H };
+add.sat.le.f0.0(8) g125<1>F     -g6<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
+add.z.f0.0(8)   g8<1>F          g2<0,1,0>F      -g2.4<0,1,0>F   { align1 1Q };
+add.z.f0.0(16)  g3<1>F          g2<0,1,0>F      -g2.1<0,1,0>F   { align1 1H };
+add(8)          g3<1>UD         g2<8,8,1>UD     0xffffffffUD    { align1 1Q };
+(+f0.0) add(8)  g15<1>D         -g15<8,8,1>D    31D             { align1 1Q };
+add(1)          a0<1>UD         a0<0,1,0>UD     0x00000200UD    { align1 WE_all 1N };
+add.sat(8)      g124<1>F        g7<8,8,1>F      -g6<8,8,1>F     { align1 1Q };
+add(8)          g8<1>UD         g6<8,8,1>D      0x00000001UD    { align1 1Q };
+add(16)         g11<1>UD        g9<8,8,1>D      0x00000001UD    { align1 1H };
+(+f0.0) add(16) g8<1>D          -g8<8,8,1>D     31D             { align1 1H };
+add.sat(16)     g126<1>F        g2<0,1,0>F      g2.4<0,1,0>F    { align1 1H };
+add.sat(8)      g124<1>F        g17<8,8,1>D     1D              { align1 1Q };
+add(16)         g114<1>D        g118<8,8,1>D    g116<8,8,1>D    { align1 2H };
+add.z.f0.0(16)  null<1>D        g120<8,8,1>D    1D              { align1 1H };
+add.z.f0.0(16)  null<1>D        g116<8,8,1>D    1D              { align1 2H };
+add.z.f0.0(8)   g3<1>D          g5<8,8,1>D      g4<8,8,1>D      { align1 1Q };
+add(16)         g20<1>UD        g17<8,8,1>UD    1D              { align1 1H };
+add(8)          g7<1>F          -g6<4>.xyxyF    g6<4>.zwzwF     { align16 1Q };
+add(16)         g9<1>F          -g7<4>.xyxyF    g7<4>.zwzwF     { align16 1H };
+add(8)          g7<1>UD         g2<8,8,1>UD     -g6<8,8,1>UD    { align1 WE_all 1Q };
+add.le.f0.0(16) g1<1>D          g3.1<0,1,0>D    -g6<8,8,1>D     { align1 1H };
+add.sat(8)      g10<1>UD        g9<8,8,1>UD     0x00000001UD    { align1 1Q };
+add(1)          g14<1>UD        g14<0,1,0>UD    0x00000001UD    { align1 WE_all 3N };
+add(8)          g25<1>Q         g22<4,4,1>Q     -g24<4,4,1>Q    { align1 1Q };
+add(8)          g12<1>Q         g5<4,4,1>Q      -g11<4,4,1>Q    { align1 2Q };

diff --git a/src/intel/tools/tests/gen9/add.expected b/src/intel/tools/tests/gen9/add.expected
new file mode 100644 (file)
index 0000000..438b6f1
--- /dev/null
+++ b/src/intel/tools/tests/gen9/add.expected
@@ -0,0 +1,40 @@
+40 00 60 00 e8 0a 80 2f e0 00 8d 0e 01 00 00 00
+40 00 80 00 e8 0a 00 2f 60 01 8d 0e 01 00 00 00
+40 00 80 00 e8 3a 80 20 20 00 00 3a 30 40 00 00
+40 00 60 00 4c 12 70 20 60 00 8d 16 08 00 08 00
+40 00 80 00 28 0a 60 20 40 02 8d 0a 80 01 8d 00
+40 00 80 00 4c 12 c0 20 28 00 28 36 10 10 00 11
+40 00 a0 00 4c 12 40 21 28 00 28 36 10 10 00 11
+40 00 60 00 28 0a 40 20 00 0c 8d 0e 01 fc ff ff
+40 00 60 00 e8 3a 80 20 b8 00 00 3a e8 00 00 00
+40 00 60 00 c8 32 a0 26 20 06 69 32 60 06 69 00
+40 00 80 80 08 02 a0 20 60 00 8d 06 01 00 00 00
+40 00 00 00 0c 02 ac 2f 0c 00 00 02 e0 00 00 00
+40 00 60 00 40 12 00 22 40 04 ae 16 80 00 80 00
+40 10 60 00 c8 32 00 21 40 00 00 32 70 00 00 00
+40 00 80 00 40 12 00 22 60 00 ae 16 40 00 40 00
+40 00 60 86 e8 3a a0 2f c0 40 8d 3e 00 00 00 3f
+40 00 60 01 e8 3a 00 21 40 00 00 3a 50 40 00 00
+40 00 80 01 e8 3a 60 20 40 00 00 3a 44 40 00 00
+40 00 60 00 08 02 60 20 40 00 8d 06 ff ff ff ff
+40 00 61 00 28 0a e0 21 e0 41 8d 0e 1f 00 00 00
+40 00 00 00 04 00 00 22 00 02 00 06 00 02 00 00
+40 00 60 80 e8 3a 80 2f e0 00 8d 3a c0 40 8d 00
+40 00 60 00 08 0a 00 21 c0 00 8d 06 01 00 00 00
+40 00 80 00 08 0a 60 21 20 01 8d 06 01 00 00 00
+40 00 81 00 28 0a 00 21 00 41 8d 0e 1f 00 00 00
+40 00 80 80 e8 3a c0 2f 40 00 00 3a 50 00 00 00
+40 00 60 80 e8 0a 80 2f 20 02 8d 0e 01 00 00 00
+40 20 80 00 28 0a 40 2e c0 0e 8d 0a 80 0e 8d 00
+40 00 80 01 20 0a 00 20 00 0f 8d 0e 01 00 00 00
+40 20 80 01 20 0a 00 20 80 0e 8d 0e 01 00 00 00
+40 00 60 01 28 0a 60 20 a0 00 8d 0a 80 00 8d 00
+40 00 80 00 08 02 80 22 20 02 8d 0e 01 00 00 00
+40 01 60 00 e8 3a ef 20 c4 40 64 3a ce 00 6e 00
+40 01 80 00 e8 3a 2f 21 e4 40 64 3a ee 00 6e 00
+40 00 60 00 0c 02 e0 20 40 00 8d 02 c0 40 8d 00
+40 00 80 06 28 0a 20 20 64 00 00 0a c0 40 8d 00
+40 00 60 80 08 02 40 21 20 01 8d 06 01 00 00 00
+40 10 00 00 0c 02 c0 21 c0 01 00 06 01 00 00 00
+40 00 60 00 28 4b 20 23 c0 02 69 4a 00 43 69 00
+40 10 60 00 28 4b 80 21 a0 00 69 4a 60 41 69 00

diff --git a/src/intel/tools/tests/gen9/and.asm b/src/intel/tools/tests/gen9/and.asm
new file mode 100644 (file)
index 0000000..2f5d123
--- /dev/null
+++ b/src/intel/tools/tests/gen9/and.asm
@@ -0,0 +1,29 @@
+and(8)          g3<1>UD         g2<0,1,0>UD     ~g2.2<0,1,0>D   { align1 1Q };
+and(16)         g3<1>UD         g2<0,1,0>UD     ~g2.2<0,1,0>D   { align1 1H };
+and(8)          g8<1>UD         g0.1<0,1,0>UW   0x07ffUW        { align1 1Q };
+and(16)         g18<1>UD        g0.1<0,1,0>UW   0x07ffUW        { align1 1H };
+and(1)          g7<1>UD         g5<0,1,0>UD     0x000000f0UD    { align1 WE_all 1N };
+and.nz.f0.0(8)  null<1>UD       g36<8,8,1>UD    g37<8,8,1>UD    { align1 1Q };
+and.nz.f0.0(16) null<1>UD       g70<8,8,1>UD    g72<8,8,1>UD    { align1 1H };
+and.z.f0.0(16)  g21<1>UD        g19<8,8,1>UD    g17<8,8,1>UD    { align1 1H };
+and(8)          g61<1>UD        g79<8,8,1>UD    g32.1<8,4,2>UD  { align1 2Q };
+and(8)          g96<1>D         ~g94<8,8,1>D    ~g95<8,8,1>D    { align1 1Q };
+and(16)         g24<1>D         ~g20<8,8,1>D    ~g22<8,8,1>D    { align1 1H };
+and(1)          a0<1>UD         g4<0,1,0>UD     0x000000ffUD    { align1 WE_all 1N };
+and(16)         g118<1>UD       g114<8,8,1>UD   0x0000003fUD    { align1 2H };
+and(1)          g4<1>UD         g20<0,1,0>UD    0x000000ffUD    { align1 WE_all 3N };
+and.z.f0.0(8)   null<1>D        g13<8,8,1>UD    0x0000001fUD    { align1 1Q };
+and(8)          g21<1>UD        g15<8,8,1>UD    0x00000003UD    { align1 WE_all 1Q };
+and.z.f0.0(8)   null<1>UD       g20<8,8,1>UD    0x00000001UD    { align1 1Q };
+and.z.f0.0(16)  null<1>UD       g45<8,8,1>UD    0x00000001UD    { align1 1H };
+and(8)          g4<1>UW         g3<8,8,1>UW     0xfffcUW        { align1 1Q };
+and(16)         g13<1>UW        g19<16,8,2>UW   0xfffcUW        { align1 1H };
+and.nz.f0.0(8)  null<1>UD       ~g2.2<0,1,0>D   g9<8,8,1>UD     { align1 1Q };
+and(8)          g18<1>UD        ~g2.2<0,1,0>D   g7<8,8,1>UD     { align1 1Q };
+and.nz.f0.0(16) null<1>UD       ~g2.2<0,1,0>D   g14<8,8,1>UD    { align1 1H };
+and(16)         g30<1>UD        ~g2.2<0,1,0>D   g10<8,8,1>UD    { align1 1H };
+and.nz.f0.0(8)  g10<1>UD        g9<8,8,1>UD     0x00000001UD    { align1 1Q };
+and.nz.f0.0(16) g16<1>UD        g14<8,8,1>UD    0x00000001UD    { align1 1H };
+and.z.f0.0(8)   g9<1>UD         g8<8,8,1>UD     0x00000003UD    { align1 1Q };
+and(8)          g12<1>UQ        g9<4,4,1>UQ     g11<4,4,1>UQ    { align1 1Q };
+and(8)          g26<1>UQ        g18<4,4,1>UQ    g22<4,4,1>UQ    { align1 2Q };

diff --git a/src/intel/tools/tests/gen9/and.expected b/src/intel/tools/tests/gen9/and.expected
new file mode 100644 (file)
index 0000000..4f2b62e
--- /dev/null
+++ b/src/intel/tools/tests/gen9/and.expected
@@ -0,0 +1,29 @@
+05 00 60 00 08 02 60 20 40 00 00 0a 48 40 00 00
+05 00 80 00 08 02 60 20 40 00 00 0a 48 40 00 00
+05 00 60 00 08 12 00 21 02 00 00 16 ff 07 ff 07
+05 00 80 00 08 12 40 22 02 00 00 16 ff 07 ff 07
+05 00 00 00 0c 02 e0 20 a0 00 00 06 f0 00 00 00
+05 00 60 02 00 02 00 20 80 04 8d 02 a0 04 8d 00
+05 00 80 02 00 02 00 20 c0 08 8d 02 00 09 8d 00
+05 00 80 01 08 02 a0 22 60 02 8d 02 20 02 8d 00
+05 10 60 00 08 02 a0 27 e0 09 8d 02 04 04 8a 00
+05 00 60 00 28 0a 00 2c c0 4b 8d 0a e0 4b 8d 00
+05 00 80 00 28 0a 00 23 80 42 8d 0a c0 42 8d 00
+05 00 00 00 04 02 00 22 80 00 00 06 ff 00 00 00
+05 20 80 00 08 02 c0 2e 40 0e 8d 06 3f 00 00 00
+05 10 00 00 0c 02 80 20 80 02 00 06 ff 00 00 00
+05 00 60 01 20 02 00 20 a0 01 8d 06 1f 00 00 00
+05 00 60 00 0c 02 a0 22 e0 01 8d 06 03 00 00 00
+05 00 60 01 00 02 00 20 80 02 8d 06 01 00 00 00
+05 00 80 01 00 02 00 20 a0 05 8d 06 01 00 00 00
+05 00 60 00 48 12 80 20 60 00 8d 16 fc ff fc ff
+05 00 80 00 48 12 a0 21 60 02 ae 16 fc ff fc ff
+05 00 60 02 00 0a 00 20 48 40 00 02 20 01 8d 00
+05 00 60 00 08 0a 40 22 48 40 00 02 e0 00 8d 00
+05 00 80 02 00 0a 00 20 48 40 00 02 c0 01 8d 00
+05 00 80 00 08 0a c0 23 48 40 00 02 40 01 8d 00
+05 00 60 02 08 02 40 21 20 01 8d 06 01 00 00 00
+05 00 80 02 08 02 00 22 c0 01 8d 06 01 00 00 00
+05 00 60 01 08 02 20 21 00 01 8d 06 03 00 00 00
+05 00 60 00 08 43 80 21 20 01 69 42 60 01 69 00
+05 10 60 00 08 43 40 23 40 02 69 42 c0 02 69 00

diff --git a/src/intel/tools/tests/gen9/asr.asm b/src/intel/tools/tests/gen9/asr.asm
new file mode 100644 (file)
index 0000000..9beabc9
--- /dev/null
+++ b/src/intel/tools/tests/gen9/asr.asm
@@ -0,0 +1,6 @@
+asr(8)          g19<1>D         g7<8,8,1>D      0x00000001UD    { align1 1Q };
+asr(16)         g20<1>D         g2.7<0,1,0>D    0x0000001fUD    { align1 1H };
+asr.nz.f0.0(8)  null<1>D        -g0<0,1,0>W     15D             { align1 1Q };
+asr.nz.f0.0(16) null<1>D        -g0<0,1,0>W     15D             { align1 1H };
+asr(8)          g2<1>D          -g0<0,1,0>W     15D             { align1 1Q };
+asr(16)         g2<1>D          -g0<0,1,0>W     15D             { align1 1H };

diff --git a/src/intel/tools/tests/gen9/asr.expected b/src/intel/tools/tests/gen9/asr.expected
new file mode 100644 (file)
index 0000000..f1832cd
--- /dev/null
+++ b/src/intel/tools/tests/gen9/asr.expected
@@ -0,0 +1,6 @@
+0c 00 60 00 28 0a 60 22 e0 00 8d 06 01 00 00 00
+0c 00 80 00 28 0a 80 22 5c 00 00 06 1f 00 00 00
+0c 00 60 02 20 1a 00 20 00 40 00 0e 0f 00 00 00
+0c 00 80 02 20 1a 00 20 00 40 00 0e 0f 00 00 00
+0c 00 60 00 28 1a 40 20 00 40 00 0e 0f 00 00 00
+0c 00 80 00 28 1a 40 20 00 40 00 0e 0f 00 00 00

diff --git a/src/intel/tools/tests/gen9/bfe.asm b/src/intel/tools/tests/gen9/bfe.asm
new file mode 100644 (file)
index 0000000..93ec4fb
--- /dev/null
+++ b/src/intel/tools/tests/gen9/bfe.asm
@@ -0,0 +1,4 @@
+bfe(8)          g96<1>UD        g89<4,4,1>UD    g30<4,4,1>UD    g91<4,4,1>UD { align16 1Q };
+bfe(16)         g13<1>UD        g44<4,4,1>UD    g115<4,4,1>UD   g126<4,4,1>UD { align16 1H };
+bfe(8)          g18<1>D         g17<4,4,1>D     g16<4,4,1>D     g49<4,4,1>D { align16 1Q };
+bfe(16)         g13<1>D         g11<4,4,1>D     g42<4,4,1>D     g5<4,4,1>D { align16 1H };

diff --git a/src/intel/tools/tests/gen9/bfe.expected b/src/intel/tools/tests/gen9/bfe.expected
new file mode 100644 (file)
index 0000000..d6a91b3
--- /dev/null
+++ b/src/intel/tools/tests/gen9/bfe.expected
@@ -0,0 +1,4 @@
+18 01 60 00 00 90 1e 60 c8 91 05 39 3c 20 c7 16
+18 01 80 00 00 90 1e 0d c8 c1 02 39 e6 20 87 1f
+18 01 60 00 00 48 1e 12 c8 11 01 39 20 20 47 0c
+18 01 80 00 00 48 1e 0d c8 b1 00 39 54 20 47 01

diff --git a/src/intel/tools/tests/gen9/bfi1.asm b/src/intel/tools/tests/gen9/bfi1.asm
new file mode 100644 (file)
index 0000000..d2bfa85
--- /dev/null
+++ b/src/intel/tools/tests/gen9/bfi1.asm
@@ -0,0 +1,2 @@
+bfi1(8)         g20<1>UD        g19<8,8,1>D     g18<8,8,1>D     { align1 1Q };
+bfi1(16)        g16<1>UD        g14<8,8,1>D     g12<8,8,1>D     { align1 1H };

diff --git a/src/intel/tools/tests/gen9/bfi1.expected b/src/intel/tools/tests/gen9/bfi1.expected
new file mode 100644 (file)
index 0000000..d8b4474
--- /dev/null
+++ b/src/intel/tools/tests/gen9/bfi1.expected
@@ -0,0 +1,2 @@
+19 00 60 00 08 0a 80 22 60 02 8d 0a 40 02 8d 00
+19 00 80 00 08 0a 00 22 c0 01 8d 0a 80 01 8d 00

diff --git a/src/intel/tools/tests/gen9/bfi2.asm b/src/intel/tools/tests/gen9/bfi2.asm
new file mode 100644 (file)
index 0000000..1dadebe
--- /dev/null
+++ b/src/intel/tools/tests/gen9/bfi2.asm
@@ -0,0 +1,2 @@
+bfi2(8)         g31<1>UD        g88<4,4,1>UD    g90<4,4,1>UD    g91<4,4,1>UD { align16 1Q };
+bfi2(16)        g5<1>UD         g42<4,4,1>UD    g40<4,4,1>UD    g126<4,4,1>UD { align16 1H };

diff --git a/src/intel/tools/tests/gen9/bfi2.expected b/src/intel/tools/tests/gen9/bfi2.expected
new file mode 100644 (file)
index 0000000..61eda29
--- /dev/null
+++ b/src/intel/tools/tests/gen9/bfi2.expected
@@ -0,0 +1,2 @@
+1a 01 60 00 00 90 1e 1f c8 81 05 39 b4 20 c7 16
+1a 01 80 00 00 90 1e 05 c8 a1 02 39 50 20 87 1f

diff --git a/src/intel/tools/tests/gen9/bfrev.asm b/src/intel/tools/tests/gen9/bfrev.asm
new file mode 100644 (file)
index 0000000..44b45c5
--- /dev/null
+++ b/src/intel/tools/tests/gen9/bfrev.asm
@@ -0,0 +1,2 @@
+bfrev(8)        g5<1>UD         g5<8,8,1>UD                     { align1 1Q };
+bfrev(16)       g6<1>UD         g8<8,8,1>UD                     { align1 1H };

diff --git a/src/intel/tools/tests/gen9/bfrev.expected b/src/intel/tools/tests/gen9/bfrev.expected
new file mode 100644 (file)
index 0000000..b4d7fb0
--- /dev/null
+++ b/src/intel/tools/tests/gen9/bfrev.expected
@@ -0,0 +1,2 @@
+17 00 60 00 08 02 a0 20 a0 00 8d 00 00 00 00 00
+17 00 80 00 08 02 c0 20 00 01 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen9/break.asm b/src/intel/tools/tests/gen9/break.asm
new file mode 100644 (file)
index 0000000..093ae61
--- /dev/null
+++ b/src/intel/tools/tests/gen9/break.asm
@@ -0,0 +1,4 @@
+break(8)        JIP: 16         UIP: 64                         { align1 1Q };
+break(16)       JIP: 16         UIP: 64                         { align1 1H };
+(+f0.0) break(8) JIP: 32        UIP: 80                         { align1 1Q };
+(+f0.0) break(16) JIP: 32       UIP: 80                         { align1 1H };

diff --git a/src/intel/tools/tests/gen9/break.expected b/src/intel/tools/tests/gen9/break.expected
new file mode 100644 (file)
index 0000000..305af58
--- /dev/null
+++ b/src/intel/tools/tests/gen9/break.expected
@@ -0,0 +1,4 @@
+28 00 60 00 20 0e 00 20 40 00 00 00 10 00 00 00
+28 00 80 00 20 0e 00 20 40 00 00 00 10 00 00 00
+28 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00
+28 00 81 00 20 0e 00 20 50 00 00 00 20 00 00 00

diff --git a/src/intel/tools/tests/gen9/cbit.asm b/src/intel/tools/tests/gen9/cbit.asm
new file mode 100644 (file)
index 0000000..a48d5e2
--- /dev/null
+++ b/src/intel/tools/tests/gen9/cbit.asm
@@ -0,0 +1,2 @@
+cbit(8)         g9<1>UD         g31<8,8,1>UD                    { align1 1Q };
+cbit(16)        g6<1>UD         g8<8,8,1>UD                     { align1 1H };

diff --git a/src/intel/tools/tests/gen9/cbit.expected b/src/intel/tools/tests/gen9/cbit.expected
new file mode 100644 (file)
index 0000000..8cb5ca1
--- /dev/null
+++ b/src/intel/tools/tests/gen9/cbit.expected
@@ -0,0 +1,2 @@
+4d 00 60 00 08 02 20 21 e0 03 8d 00 00 00 00 00
+4d 00 80 00 08 02 c0 20 00 01 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen9/cmp.asm b/src/intel/tools/tests/gen9/cmp.asm
new file mode 100644 (file)
index 0000000..669224d
--- /dev/null
+++ b/src/intel/tools/tests/gen9/cmp.asm
@@ -0,0 +1,104 @@
+cmp.z.f0.0(8)   null<1>F        g20<8,8,1>F     0xbf800000F  /* -1F */ { align1 1Q };
+cmp.nz.f0.0(8)  g59<1>DF        g2.1<0,1,0>DF   g59<4,4,1>DF    { align1 1Q };
+cmp.nz.f0.0(8)  g49<1>F         g47<8,8,1>F     g14.1<0,1,0>F   { align1 1Q };
+cmp.nz.f0.0(8)  null<1>D        g7<8,8,1>D      0D              { align1 1Q };
+cmp.z.f0.0(8)   g5<1>D          g4<8,8,1>D      g2.5<0,1,0>D    { align1 1Q };
+cmp.z.f0.0(16)  g7<1>D          g5<8,8,1>D      g2.5<0,1,0>D    { align1 1H };
+cmp.l.f0.0(16)  g28<1>F         g26<8,8,1>F     g24<8,8,1>F     { align1 1H };
+cmp.ge.f0.0(16) g30<1>F         g26<8,8,1>F     g24<8,8,1>F     { align1 1H };
+cmp.nz.f0.0(8)  g43<1>D         g42<8,8,1>D     g2.1<0,1,0>D    { align1 1Q };
+cmp.z.f0.0(8)   g86<1>DF        (abs)g6.2<0,1,0>DF g68<4,4,1>DF { align1 1Q };
+cmp.le.f0.0(8)  g108<1>D        g106<8,8,1>D    0D              { align1 1Q };
+cmp.nz.f0.0(8)  null<1>DF       g6.2<0,1,0>DF   g66<4,4,1>DF    { align1 1Q };
+cmp.l.f0.0(8)   g5<1>DF         g36<4,4,1>DF    g53<4,4,1>DF    { align1 1Q };
+cmp.ge.f0.0(8)  g18<1>DF        g36<4,4,1>DF    g53<4,4,1>DF    { align1 1Q };
+cmp.z.f0.0(8)   g34<1>DF        (abs)g106<4,4,1>DF g52<4,4,1>DF { align1 2Q };
+cmp.le.f0.0(16) g35<1>D         g21<8,8,1>D     0D              { align1 1H };
+cmp.nz.f0.0(8)  null<1>DF       g106<4,4,1>DF   g50<4,4,1>DF    { align1 2Q };
+cmp.nz.f0.0(8)  g113<1>DF       g3.1<0,1,0>DF   g59<4,4,1>DF    { align1 2Q };
+cmp.l.f0.0(8)   null<1>UD       g12<8,8,1>UD    0x00000004UD    { align1 1Q };
+cmp.l.f0.0(8)   g53<1>F         g52<8,8,1>F     g51<8,8,1>F     { align1 1Q };
+cmp.ge.f0.0(8)  g55<1>F         g52<8,8,1>F     g51<8,8,1>F     { align1 1Q };
+cmp.ge.f0.0(8)  g15<1>D         (abs)g12<8,8,1>D 1D             { align1 1Q };
+cmp.l.f0.0(8)   null<1>D        g6<0,1,0>D      2D              { align1 1Q };
+(+f0.1) cmp.z.f0.1(8) null<1>D  g8<8,8,1>D      0D              { align1 1Q };
+cmp.nz.f0.0(16) g11<1>D         g9<8,8,1>D      3D              { align1 1H };
+(+f0.1) cmp.z.f0.1(16) null<1>D g11<8,8,1>D     0D              { align1 1H };
+cmp.z.f0.0(8)   null<1>D        g22<8,8,1>D     1D              { align1 1Q };
+cmp.z.f0.0(16)  null<1>D        g47<8,8,1>D     1D              { align1 1H };
+cmp.ge.f0.0(8)  g30<1>UD        g29<8,8,1>UD    g5.7<0,1,0>UD   { align1 1Q };
+cmp.l.f0.0(8)   g31<1>UD        g29<8,8,1>UD    g5.3<0,1,0>UD   { align1 1Q };
+cmp.ge.f0.0(16) g50<1>UD        g48<8,8,1>UD    g7.7<0,1,0>UD   { align1 1H };
+cmp.l.f0.0(16)  g52<1>UD        g48<8,8,1>UD    g7.3<0,1,0>UD   { align1 1H };
+cmp.nz.f0.0(16) g9<1>F          g2.5<0,1,0>F    g1.1<0,1,0>F    { align1 1H };
+cmp.ge.f0.0(8)  null<1>D        g38<8,8,1>D     32D             { align1 1Q };
+cmp.ge.f0.0(8)  null<1>DF       g21<4,4,1>DF    g13<4,4,1>DF    { align1 1Q };
+cmp.ge.f0.0(16) g3<1>D          g1.1<0,1,0>D    g1<0,1,0>D      { align1 1H };
+cmp.l.f0.0(16)  g5<1>D          g1.1<0,1,0>D    g1<0,1,0>D      { align1 1H };
+cmp.z.f0.0(8)   g25<1>F         g4.3<0,1,0>F    g4.1<0,1,0>F    { align1 1Q };
+cmp.l.f0.0(8)   g33<1>D         g5<0,1,0>D      1D              { align1 1Q };
+cmp.l.f0.0(8)   g43<1>DF        g39<4,4,1>DF    g37<4,4,1>DF    { align1 2Q };
+cmp.ge.f0.0(8)  g46<1>DF        g39<4,4,1>DF    g37<4,4,1>DF    { align1 2Q };
+cmp.l.f0.0(16)  null<1>D        g6<0,1,0>D      1D              { align1 1H };
+cmp.z.f0.0(16)  g62<1>F         g12<8,8,1>F     g6.3<0,1,0>F    { align1 1H };
+cmp.nz.f0.0(8)  null<1>F        g2<0,1,0>F      0x0F  /* 0F */  { align1 1Q };
+cmp.nz.f0.0(16) null<1>F        g2<0,1,0>F      0x0F  /* 0F */  { align1 1H };
+cmp.ge.f0.0(16) null<1>UD       g46<8,8,1>UD    0x00000040UD    { align1 1H };
+cmp.z.f0.0(16)  null<1>F        g14<8,8,1>F     g6.1<0,1,0>F    { align1 1H };
+cmp.nz.f0.0(16) null<1>D        g6<0,1,0>D      0D              { align1 1H };
+cmp.l.f0.0(16)  null<1>UD       g39<8,8,1>UD    0x00000004UD    { align1 1H };
+cmp.le.f0.0(8)  null<1>F        g2<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 1Q };
+cmp.le.f0.0(16) null<1>F        g2<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 1H };
+cmp.le.f0.0(8)  g20<1>F         g5.3<0,1,0>F    0x0F  /* 0F */  { align1 1Q };
+cmp.ge.f0.0(8)  null<1>F        (abs)g26<8,8,1>F 0x5d5e0b6bF  /* 1e+18F */ { align1 1Q };
+cmp.g.f0.0(8)   g80<1>F         (abs)g44<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
+cmp.ge.f0.0(16) null<1>D        g67<8,8,1>D     32D             { align1 1H };
+cmp.g.f0.0(8)   null<1>F        g124<8,8,1>F    0x0F  /* 0F */  { align1 1Q };
+cmp.z.f0.0(8)   g4<1>F          g13<8,4,2>F     g2.5<0,1,0>F    { align1 2Q };
+cmp.g.f0.0(16)  null<1>F        g120<8,8,1>F    0x0F  /* 0F */  { align1 1H };
+cmp.g.f0.0(16)  g2<1>F          (abs)g17<8,8,1>F 0x3f800000F  /* 1F */ { align1 1H };
+cmp.l.f0.0(8)   null<1>DF       (abs)g5<0,1,0>DF g20<4,4,1>DF   { align1 1Q };
+cmp.nz.f0.0(8)  g29<1>D         g22.1<8,4,2>D   g3.2<0,1,0>D    { align1 2Q };
+cmp.l.f0.0(8)   null<1>DF       g11<4,4,1>DF    g8<4,4,1>DF     { align1 2Q };
+cmp.nz.f0.0(8)  g73<1>F         g6.1<0,1,0>F    g14<8,4,2>F     { align1 2Q };
+cmp.g.f0.0(8)   g7<1>D          g2<0,1,0>D      0D              { align1 1Q };
+cmp.l.f0.0(8)   null<1>F        g4.4<0,1,0>F    0x0F  /* 0F */  { align1 1Q };
+cmp.l.f0.0(16)  null<1>F        g6.4<0,1,0>F    0x0F  /* 0F */  { align1 1H };
+cmp.le.f0.0(8)  null<1>D        g2<8,8,1>D      50D             { align1 1Q };
+cmp.le.f0.0(16) null<1>D        g2<8,8,1>D      50D             { align1 1H };
+cmp.ge.f0.0(16) null<1>F        g35<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1H };
+cmp.le.f0.0(8)  g4<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1Q };
+cmp.g.f0.0(8)   g5<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1Q };
+cmp.le.f0.0(16) g5<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1H };
+cmp.g.f0.0(16)  g7<1>UD         g2<0,1,0>UD     0x00000001UD    { align1 1H };
+cmp.le.f0.0(16) g121<1>F        g27<8,8,1>F     0x461c3f9aF  /* 9999.9F */ { align1 1H };
+cmp.z.f0.0(8)   g5<1>D          g14<8,4,2>D     g3.1<0,1,0>D    { align1 2Q };
+cmp.g.f0.0(8)   null<1>D        g5.2<0,1,0>D    31D             { align1 1Q };
+cmp.g.f0.0(8)   null<1>UD       g4.2<0,1,0>UD   0x0000001fUD    { align1 1Q };
+(+f0.1) cmp.nz.f0.1(8) null<1>UW g0<8,8,1>UW    g0<8,8,1>UW     { align1 1Q };
+(+f0.1) cmp.nz.f0.1(16) null<1>UW g0<8,8,1>UW   g0<8,8,1>UW     { align1 1H };
+cmp.z.f0.0(16)  null<1>D        g1<8,8,1>D      1024D           { align1 2H };
+cmp.l.f0.0(16)  null<1>D        g118<8,8,1>D    32D             { align1 2H };
+cmp.nz.f0.0(8)  null<1>UD       g3<8,8,1>UD     0x00000000UD    { align1 1Q };
+cmp.nz.f0.0(16) null<1>UD       g3<8,8,1>UD     0x00000000UD    { align1 1H };
+cmp.g.f0.0(16)  null<1>D        g2.1<0,1,0>D    0D              { align1 1H };
+cmp.nz.f0.0(8)  null<1>Q        g6<4,4,1>Q      g3<4,4,1>Q      { align1 1Q };
+cmp.z.f0.0(8)   g8<1>Q          g5<4,4,1>Q      g3<4,4,1>Q      { align1 1Q };
+cmp.nz.f0.0(8)  g2<1>Q          g5<4,4,1>Q      g3<4,4,1>Q      { align1 1Q };
+cmp.nz.f0.0(8)  null<1>Q        g9<4,4,1>Q      g4<4,4,1>Q      { align1 2Q };
+cmp.z.f0.0(8)   g17<1>Q         g11<4,4,1>Q     g4<4,4,1>Q      { align1 2Q };
+cmp.nz.f0.0(8)  g20<1>Q         g11<4,4,1>Q     g4<4,4,1>Q      { align1 2Q };
+cmp.z.f0.0(8)   null<1>UD       g5<8,8,1>UD     0x00000000UD    { align1 1Q };
+cmp.z.f0.0(16)  null<1>UD       g15<8,8,1>UD    0x00000000UD    { align1 1H };
+cmp.g.f0.0(16)  g1<1>D          g8<8,8,1>D      0D              { align1 1H };
+cmp.ge.f0.0(8)  null<1>UD       g10<8,8,1>UD    g8<8,8,1>UD     { align1 1Q };
+cmp.ge.f0.0(8)  null<1>DF       g37<4,4,1>DF    g26<4,4,1>DF    { align1 2Q };
+cmp.l.f0.0(8)   null<1>Q        g20<4,4,1>Q     g25<4,4,1>Q     { align1 1Q };
+cmp.l.f0.0(8)   null<1>Q        g2<4,4,1>Q      g12<4,4,1>Q     { align1 2Q };
+cmp.ge.f0.0(8)  null<1>Q        g20<4,4,1>Q     g27<4,4,1>Q     { align1 1Q };
+cmp.ge.f0.0(8)  null<1>Q        g2<4,4,1>Q      g8<4,4,1>Q      { align1 2Q };
+cmp.le.f0.0(8)  null<1>UD       g18<8,8,1>UD    0x000000ffUD    { align1 1Q };
+cmp.le.f0.0(16) null<1>UD       g32<8,8,1>UD    0x000000ffUD    { align1 1H };
+cmp.z.f0.0(8)   null<1>Q        g12<4,4,1>Q     g7<4,4,1>Q      { align1 1Q };
+cmp.z.f0.0(8)   null<1>Q        g26<4,4,1>Q     g12<4,4,1>Q     { align1 2Q };
+cmp.g.f0.0(16)  null<1>UD       g4.2<0,1,0>UD   0x0000001fUD    { align1 1H };

diff --git a/src/intel/tools/tests/gen9/cmp.expected b/src/intel/tools/tests/gen9/cmp.expected
new file mode 100644 (file)
index 0000000..9e13e8c
--- /dev/null
+++ b/src/intel/tools/tests/gen9/cmp.expected
@@ -0,0 +1,104 @@
+10 00 60 01 e0 3a 00 20 80 02 8d 3e 00 00 80 bf
+10 00 60 02 c8 32 60 27 48 00 00 32 60 07 69 00
+10 00 60 02 e8 3a 20 26 e0 05 8d 3a c4 01 00 00
+10 00 60 02 20 0a 00 20 e0 00 8d 0e 00 00 00 00
+10 00 60 01 28 0a a0 20 80 00 8d 0a 54 00 00 00
+10 00 80 01 28 0a e0 20 a0 00 8d 0a 54 00 00 00
+10 00 80 05 e8 3a 80 23 40 03 8d 3a 00 03 8d 00
+10 00 80 04 e8 3a c0 23 40 03 8d 3a 00 03 8d 00
+10 00 60 02 28 0a 60 25 40 05 8d 0a 44 00 00 00
+10 00 60 01 c8 32 c0 2a d0 20 00 32 80 08 69 00
+10 00 60 06 28 0a 80 2d 40 0d 8d 0e 00 00 00 00
+10 00 60 02 c0 32 00 20 d0 00 00 32 40 08 69 00
+10 00 60 05 c8 32 a0 20 80 04 69 32 a0 06 69 00
+10 00 60 04 c8 32 40 22 80 04 69 32 a0 06 69 00
+10 10 60 01 c8 32 40 24 40 2d 69 32 80 06 69 00
+10 00 80 06 28 0a 60 24 a0 02 8d 0e 00 00 00 00
+10 10 60 02 c0 32 00 20 40 0d 69 32 40 06 69 00
+10 10 60 02 c8 32 20 2e 68 00 00 32 60 07 69 00
+10 00 60 05 00 02 00 20 80 01 8d 06 04 00 00 00
+10 00 60 05 e8 3a a0 26 80 06 8d 3a 60 06 8d 00
+10 00 60 04 e8 3a e0 26 80 06 8d 3a 60 06 8d 00
+10 00 60 04 28 0a e0 21 80 21 8d 0e 01 00 00 00
+10 00 60 05 20 0a 00 20 c0 00 00 0e 02 00 00 00
+10 00 61 01 21 0a 00 20 00 01 8d 0e 00 00 00 00
+10 00 80 02 28 0a 60 21 20 01 8d 0e 03 00 00 00
+10 00 81 01 21 0a 00 20 60 01 8d 0e 00 00 00 00
+10 00 60 01 20 0a 00 20 c0 02 8d 0e 01 00 00 00
+10 00 80 01 20 0a 00 20 e0 05 8d 0e 01 00 00 00
+10 00 60 04 08 02 c0 23 a0 03 8d 02 bc 00 00 00
+10 00 60 05 08 02 e0 23 a0 03 8d 02 ac 00 00 00
+10 00 80 04 08 02 40 26 00 06 8d 02 fc 00 00 00
+10 00 80 05 08 02 80 26 00 06 8d 02 ec 00 00 00
+10 00 80 02 e8 3a 20 21 54 00 00 3a 24 00 00 00
+10 00 60 04 20 0a 00 20 c0 04 8d 0e 20 00 00 00
+10 00 60 04 c0 32 00 20 a0 02 69 32 a0 01 69 00
+10 00 80 04 28 0a 60 20 24 00 00 0a 20 00 00 00
+10 00 80 05 28 0a a0 20 24 00 00 0a 20 00 00 00
+10 00 60 01 e8 3a 20 23 8c 00 00 3a 84 00 00 00
+10 00 60 05 28 0a 20 24 a0 00 00 0e 01 00 00 00
+10 10 60 05 c8 32 60 25 e0 04 69 32 a0 04 69 00
+10 10 60 04 c8 32 c0 25 e0 04 69 32 a0 04 69 00
+10 00 80 05 20 0a 00 20 c0 00 00 0e 01 00 00 00
+10 00 80 01 e8 3a c0 27 80 01 8d 3a cc 00 00 00
+10 00 60 02 e0 3a 00 20 40 00 00 3e 00 00 00 00
+10 00 80 02 e0 3a 00 20 40 00 00 3e 00 00 00 00
+10 00 80 04 00 02 00 20 c0 05 8d 06 40 00 00 00
+10 00 80 01 e0 3a 00 20 c0 01 8d 3a c4 00 00 00
+10 00 80 02 20 0a 00 20 c0 00 00 0e 00 00 00 00
+10 00 80 05 00 02 00 20 e0 04 8d 06 04 00 00 00
+10 00 60 06 e0 3a 00 20 40 00 8d 3e 00 00 00 3f
+10 00 80 06 e0 3a 00 20 40 00 8d 3e 00 00 00 3f
+10 00 60 06 e8 3a 80 22 ac 00 00 3e 00 00 00 00
+10 00 60 04 e0 3a 00 20 40 23 8d 3e 6b 0b 5e 5d
+10 00 60 03 e8 3a 00 2a 80 25 8d 3e 00 00 80 3f
+10 00 80 04 20 0a 00 20 60 08 8d 0e 20 00 00 00
+10 00 60 03 e0 3a 00 20 80 0f 8d 3e 00 00 00 00
+10 10 60 01 e8 3a 80 20 a0 01 8a 3a 54 00 00 00
+10 00 80 03 e0 3a 00 20 00 0f 8d 3e 00 00 00 00
+10 00 80 03 e8 3a 40 20 20 22 8d 3e 00 00 80 3f
+10 00 60 05 c0 32 00 20 a0 20 00 32 80 02 69 00
+10 10 60 02 28 0a a0 23 c4 02 8a 0a 68 00 00 00
+10 10 60 05 c0 32 00 20 60 01 69 32 00 01 69 00
+10 10 60 02 e8 3a 20 29 c4 00 00 3a c0 01 8a 00
+10 00 60 03 28 0a e0 20 40 00 00 0e 00 00 00 00
+10 00 60 05 e0 3a 00 20 90 00 00 3e 00 00 00 00
+10 00 80 05 e0 3a 00 20 d0 00 00 3e 00 00 00 00
+10 00 60 06 20 0a 00 20 40 00 8d 0e 32 00 00 00
+10 00 80 06 20 0a 00 20 40 00 8d 0e 32 00 00 00
+10 00 80 04 e0 3a 00 20 60 04 8d 3e 00 00 00 3f
+10 00 60 06 08 02 80 20 40 00 00 06 01 00 00 00
+10 00 60 03 08 02 a0 20 40 00 00 06 01 00 00 00
+10 00 80 06 08 02 a0 20 40 00 00 06 01 00 00 00
+10 00 80 03 08 02 e0 20 40 00 00 06 01 00 00 00
+10 00 80 06 e8 3a 20 2f 60 03 8d 3e 9a 3f 1c 46
+10 10 60 01 28 0a a0 20 c0 01 8a 0a 64 00 00 00
+10 00 60 03 20 0a 00 20 a8 00 00 0e 1f 00 00 00
+10 00 60 03 00 02 00 20 88 00 00 06 1f 00 00 00
+10 00 61 02 41 12 00 20 00 00 8d 12 00 00 8d 00
+10 00 81 02 41 12 00 20 00 00 8d 12 00 00 8d 00
+10 20 80 01 20 0a 00 20 20 00 8d 0e 00 04 00 00
+10 20 80 05 20 0a 00 20 c0 0e 8d 0e 20 00 00 00
+10 00 60 02 00 02 00 20 60 00 8d 06 00 00 00 00
+10 00 80 02 00 02 00 20 60 00 8d 06 00 00 00 00
+10 00 80 03 20 0a 00 20 44 00 00 0e 00 00 00 00
+10 00 60 02 20 4b 00 20 c0 00 69 4a 60 00 69 00
+10 00 60 01 28 4b 00 21 a0 00 69 4a 60 00 69 00
+10 00 60 02 28 4b 40 20 a0 00 69 4a 60 00 69 00
+10 10 60 02 20 4b 00 20 20 01 69 4a 80 00 69 00
+10 10 60 01 28 4b 20 22 60 01 69 4a 80 00 69 00
+10 10 60 02 28 4b 80 22 60 01 69 4a 80 00 69 00
+10 00 60 01 00 02 00 20 a0 00 8d 06 00 00 00 00
+10 00 80 01 00 02 00 20 e0 01 8d 06 00 00 00 00
+10 00 80 03 28 0a 20 20 00 01 8d 0e 00 00 00 00
+10 00 60 04 00 02 00 20 40 01 8d 02 00 01 8d 00
+10 10 60 04 c0 32 00 20 a0 04 69 32 40 03 69 00
+10 00 60 05 20 4b 00 20 80 02 69 4a 20 03 69 00
+10 10 60 05 20 4b 00 20 40 00 69 4a 80 01 69 00
+10 00 60 04 20 4b 00 20 80 02 69 4a 60 03 69 00
+10 10 60 04 20 4b 00 20 40 00 69 4a 00 01 69 00
+10 00 60 06 00 02 00 20 40 02 8d 06 ff 00 00 00
+10 00 80 06 00 02 00 20 00 04 8d 06 ff 00 00 00
+10 00 60 01 20 4b 00 20 80 01 69 4a e0 00 69 00
+10 10 60 01 20 4b 00 20 40 03 69 4a 80 01 69 00
+10 00 80 03 00 02 00 20 88 00 00 06 1f 00 00 00

diff --git a/src/intel/tools/tests/gen9/cont.asm b/src/intel/tools/tests/gen9/cont.asm
new file mode 100644 (file)
index 0000000..c5a194b
--- /dev/null
+++ b/src/intel/tools/tests/gen9/cont.asm
@@ -0,0 +1,2 @@
+cont(8)         JIP: 16         UIP: 64                         { align1 1Q };
+cont(16)        JIP: 16         UIP: 64                         { align1 1H };

diff --git a/src/intel/tools/tests/gen9/cont.expected b/src/intel/tools/tests/gen9/cont.expected
new file mode 100644 (file)
index 0000000..83aa4f5
--- /dev/null
+++ b/src/intel/tools/tests/gen9/cont.expected
@@ -0,0 +1,2 @@
+29 00 60 00 00 0e 00 34 40 00 00 00 10 00 00 00
+29 00 80 00 00 0e 00 34 40 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen9/csel.asm b/src/intel/tools/tests/gen9/csel.asm
new file mode 100644 (file)
index 0000000..6030fb3
--- /dev/null
+++ b/src/intel/tools/tests/gen9/csel.asm
@@ -0,0 +1,13 @@
+csel.nz(8)      g15<1>F         g11<4,4,1>F     (abs)g11<4,4,1>F g11<4,4,1>F { align16 1Q };
+csel.nz(16)     g14<1>F         g8<4,4,1>F      (abs)g8<4,4,1>F g8<4,4,1>F { align16 1H };
+csel.le(8)      g21<1>F         (abs)g5.3<0,1,0>F g5.0<0,1,0>F  g5.3<0,1,0>F { align16 1Q };
+csel.l(8)       g107<1>F        -g101<4,4,1>F   g101<4,4,1>F    g104<4,4,1>F { align16 1Q };
+csel.le(8)      g21<1>F         g5.0<0,1,0>F    (abs)g5.1<0,1,0>F g5.1<0,1,0>F { align16 1Q };
+csel.l(8)       g127<1>F        g2<4,4,1>F      g8<4,4,1>F      g4.0<0,1,0>F { align16 1Q };
+csel.l(16)      g126<1>F        g2<4,4,1>F      g13<4,4,1>F     g6.0<0,1,0>F { align16 1H };
+csel.le(16)     g13<1>F         (abs)g73<4,4,1>F g58<4,4,1>F    g73<4,4,1>F { align16 1H };
+csel.le(16)     g15<1>F         g58<4,4,1>F     (abs)g73<4,4,1>F g73<4,4,1>F { align16 1H };
+csel.l(16)      g69<1>F         -g65<4,4,1>F    g65<4,4,1>F     g67<4,4,1>F { align16 1H };
+csel.sat.g(8)   g125<1>F        g2.3<0,1,0>F    g2.2<0,1,0>F    g2.0<0,1,0>F { align16 1Q };
+csel.g(8)       g125<1>F        g2.3<0,1,0>F    g2.2<0,1,0>F    g2.0<0,1,0>F { align16 1Q };
+csel.g(16)      g122<1>F        g2.3<0,1,0>F    g2.2<0,1,0>F    g2.0<0,1,0>F { align16 1H };

diff --git a/src/intel/tools/tests/gen9/csel.expected b/src/intel/tools/tests/gen9/csel.expected
new file mode 100644 (file)
index 0000000..300b915
--- /dev/null
+++ b/src/intel/tools/tests/gen9/csel.expected
@@ -0,0 +1,13 @@
+12 01 60 02 80 00 1e 0f c8 b1 00 39 16 20 c7 02
+12 01 80 02 80 00 1e 0e c8 81 00 39 10 20 07 02
+12 01 60 06 20 00 1e 15 01 56 20 00 0a 04 58 01
+12 01 60 05 40 00 1e 6b c8 51 06 39 ca 20 07 1a
+12 01 60 06 80 00 1e 15 01 50 20 40 0a 04 48 01
+12 01 60 05 00 00 1e 7f c8 21 00 39 10 04 00 01
+12 01 80 05 00 00 1e 7e c8 21 00 39 1a 04 80 01
+12 01 80 06 20 00 1e 0d c8 91 04 39 74 20 47 12
+12 01 80 06 80 00 1e 0f c8 a1 03 39 92 20 47 12
+12 01 80 05 40 00 1e 45 c8 11 04 39 82 20 c7 10
+12 01 60 83 00 00 1e 7d 01 26 20 80 04 04 80 00
+12 01 60 03 00 00 1e 7d 01 26 20 80 04 04 80 00
+12 01 80 03 00 00 1e 7a 01 26 20 80 04 04 80 00

diff --git a/src/intel/tools/tests/gen9/else.asm b/src/intel/tools/tests/gen9/else.asm
new file mode 100644 (file)
index 0000000..8324624
--- /dev/null
+++ b/src/intel/tools/tests/gen9/else.asm
@@ -0,0 +1,3 @@
+else(8)         JIP: 288        UIP: 288                        { align1 1Q };
+else(16)        JIP: 240        UIP: 240                        { align1 1H };
+else(32)        JIP: 272        UIP: 272                        { align1 };

diff --git a/src/intel/tools/tests/gen9/else.expected b/src/intel/tools/tests/gen9/else.expected
new file mode 100644 (file)
index 0000000..44503c7
--- /dev/null
+++ b/src/intel/tools/tests/gen9/else.expected
@@ -0,0 +1,3 @@
+24 00 60 00 20 0e 00 20 20 01 00 00 20 01 00 00
+24 00 80 00 20 0e 00 20 f0 00 00 00 f0 00 00 00
+24 00 a0 00 20 0e 00 20 10 01 00 00 10 01 00 00

diff --git a/src/intel/tools/tests/gen9/endif.asm b/src/intel/tools/tests/gen9/endif.asm
new file mode 100644 (file)
index 0000000..bfd04ea
--- /dev/null
+++ b/src/intel/tools/tests/gen9/endif.asm
@@ -0,0 +1,3 @@
+endif(8)        JIP: 80                                         { align1 1Q };
+endif(16)       JIP: 48                                         { align1 1H };
+endif(32)       JIP: 16                                         { align1 };

diff --git a/src/intel/tools/tests/gen9/endif.expected b/src/intel/tools/tests/gen9/endif.expected
new file mode 100644 (file)
index 0000000..898a148
--- /dev/null
+++ b/src/intel/tools/tests/gen9/endif.expected
@@ -0,0 +1,3 @@
+25 00 60 00 00 0e 00 00 00 00 00 08 50 00 00 00
+25 00 80 00 00 0e 00 00 00 00 00 08 30 00 00 00
+25 00 a0 00 00 0e 00 00 00 00 00 08 10 00 00 00

diff --git a/src/intel/tools/tests/gen9/fbh.asm b/src/intel/tools/tests/gen9/fbh.asm
new file mode 100644 (file)
index 0000000..fb62e76
--- /dev/null
+++ b/src/intel/tools/tests/gen9/fbh.asm
@@ -0,0 +1,2 @@
+fbh(8)          g15<1>D         g35<8,8,1>D                     { align1 1Q };
+fbh(16)         g8<1>D          g4<8,8,1>D                      { align1 1H };

diff --git a/src/intel/tools/tests/gen9/fbh.expected b/src/intel/tools/tests/gen9/fbh.expected
new file mode 100644 (file)
index 0000000..a3a1fce
--- /dev/null
+++ b/src/intel/tools/tests/gen9/fbh.expected
@@ -0,0 +1,2 @@
+4b 00 60 00 28 0a e0 21 60 04 8d 00 00 00 00 00
+4b 00 80 00 28 0a 00 21 80 00 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen9/fbl.asm b/src/intel/tools/tests/gen9/fbl.asm
new file mode 100644 (file)
index 0000000..e7f1c70
--- /dev/null
+++ b/src/intel/tools/tests/gen9/fbl.asm
@@ -0,0 +1,3 @@
+fbl(8)          g5<1>UD         g5<8,8,1>UD                     { align1 1Q };
+fbl(16)         g6<1>UD         g8<8,8,1>UD                     { align1 1H };
+fbl(1)          g43<1>UD        mask0<0,1,0>UD                  { align1 WE_all 1N };

diff --git a/src/intel/tools/tests/gen9/fbl.expected b/src/intel/tools/tests/gen9/fbl.expected
new file mode 100644 (file)
index 0000000..60cb680
--- /dev/null
+++ b/src/intel/tools/tests/gen9/fbl.expected
@@ -0,0 +1,3 @@
+4c 00 60 00 08 02 a0 20 a0 00 8d 00 00 00 00 00
+4c 00 80 00 08 02 c0 20 00 01 8d 00 00 00 00 00
+4c 00 00 00 0c 00 60 25 00 08 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen9/frc.asm b/src/intel/tools/tests/gen9/frc.asm
new file mode 100644 (file)
index 0000000..910fbed
--- /dev/null
+++ b/src/intel/tools/tests/gen9/frc.asm
@@ -0,0 +1,2 @@
+frc(8)          g28<1>F         g4<8,8,1>F                      { align1 1Q };
+frc(16)         g3<1>F          g1<0,1,0>F                      { align1 1H };

diff --git a/src/intel/tools/tests/gen9/frc.expected b/src/intel/tools/tests/gen9/frc.expected
new file mode 100644 (file)
index 0000000..00484ff
--- /dev/null
+++ b/src/intel/tools/tests/gen9/frc.expected
@@ -0,0 +1,2 @@
+43 00 60 00 e8 3a 80 23 80 00 8d 00 00 00 00 00
+43 00 80 00 e8 3a 60 20 20 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen9/halt.asm b/src/intel/tools/tests/gen9/halt.asm
new file mode 100644 (file)
index 0000000..d844326
--- /dev/null
+++ b/src/intel/tools/tests/gen9/halt.asm
@@ -0,0 +1,4 @@
+(-f0.1.any4h) halt(8) JIP: 176  UIP: 192                        { align1 1Q };
+halt(8)         JIP: 16         UIP: 16                         { align1 1Q };
+(-f0.1.any4h) halt(16) JIP: 176 UIP: 192                        { align1 1H };
+halt(16)        JIP: 16         UIP: 16                         { align1 1H };

diff --git a/src/intel/tools/tests/gen9/halt.expected b/src/intel/tools/tests/gen9/halt.expected
new file mode 100644 (file)
index 0000000..4e4573d
--- /dev/null
+++ b/src/intel/tools/tests/gen9/halt.expected
@@ -0,0 +1,4 @@
+2a 00 76 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
+2a 00 60 00 20 0e 00 20 10 00 00 00 10 00 00 00
+2a 00 96 00 21 0e 00 20 c0 00 00 00 b0 00 00 00
+2a 00 80 00 20 0e 00 20 10 00 00 00 10 00 00 00

diff --git a/src/intel/tools/tests/gen9/if.asm b/src/intel/tools/tests/gen9/if.asm
new file mode 100644 (file)
index 0000000..5eb7b53
--- /dev/null
+++ b/src/intel/tools/tests/gen9/if.asm
@@ -0,0 +1,5 @@
+(+f0.0) if(8)   JIP: 1376       UIP: 1392                       { align1 1Q };
+(-f0.0) if(8)   JIP: 4704       UIP: 4704                       { align1 1Q };
+(-f0.0) if(16)  JIP: 64         UIP: 64                         { align1 1H };
+(+f0.0) if(16)  JIP: 96         UIP: 320                        { align1 1H };
+(+f0.0) if(32)  JIP: 80         UIP: 80                         { align1 };

diff --git a/src/intel/tools/tests/gen9/if.expected b/src/intel/tools/tests/gen9/if.expected
new file mode 100644 (file)
index 0000000..b2fc285
--- /dev/null
+++ b/src/intel/tools/tests/gen9/if.expected
@@ -0,0 +1,5 @@
+22 00 61 00 20 0e 00 20 70 05 00 00 60 05 00 00
+22 00 71 00 20 0e 00 20 60 12 00 00 60 12 00 00
+22 00 91 00 20 0e 00 20 40 00 00 00 40 00 00 00
+22 00 81 00 20 0e 00 20 40 01 00 00 60 00 00 00
+22 00 a1 00 20 0e 00 20 50 00 00 00 50 00 00 00

diff --git a/src/intel/tools/tests/gen9/lrp.asm b/src/intel/tools/tests/gen9/lrp.asm
new file mode 100644 (file)
index 0000000..d2445c6
--- /dev/null
+++ b/src/intel/tools/tests/gen9/lrp.asm
@@ -0,0 +1,5 @@
+lrp(8)          g4<1>F          g16<4,4,1>F     g7.2<0,1,0>F    g6.6<0,1,0>F { align16 1Q };
+lrp(16)         g4<1>F          g2.4<0,1,0>F    g2.2<0,1,0>F    g2.0<0,1,0>F { align16 1H };
+lrp.z.f0.0(8)   g8<1>F          g3.2<0,1,0>F    g3.1<0,1,0>F    g3.0<0,1,0>F { align16 1Q };
+lrp.sat(8)      g7<1>F          g10<4,4,1>F     g13<4,4,1>F     g16<4,4,1>F { align16 1Q };
+lrp.sat(16)     g18<1>F         g20<4,4,1>F     g26<4,4,1>F     g32<4,4,1>F { align16 1H };

diff --git a/src/intel/tools/tests/gen9/lrp.expected b/src/intel/tools/tests/gen9/lrp.expected
new file mode 100644 (file)
index 0000000..b109e92
--- /dev/null
+++ b/src/intel/tools/tests/gen9/lrp.expected
@@ -0,0 +1,5 @@
+5c 01 60 00 00 00 1e 04 c8 01 21 80 0e 04 b0 01
+5c 01 80 00 00 00 1e 04 01 28 20 80 04 04 80 00
+5c 01 60 01 00 00 1e 08 01 34 20 40 06 04 c0 00
+5c 01 60 80 00 00 1e 07 c8 a1 00 39 1a 20 07 04
+5c 01 80 80 00 00 1e 12 c8 41 01 39 34 20 07 08

diff --git a/src/intel/tools/tests/gen9/lzd.asm b/src/intel/tools/tests/gen9/lzd.asm
new file mode 100644 (file)
index 0000000..2dba1a1
--- /dev/null
+++ b/src/intel/tools/tests/gen9/lzd.asm
@@ -0,0 +1,2 @@
+lzd(8)          g25<1>UD        g3.1<0,1,0>UD                   { align1 1Q };
+lzd(16)         g27<1>UD        g3.1<0,1,0>UD                   { align1 1H };

diff --git a/src/intel/tools/tests/gen9/lzd.expected b/src/intel/tools/tests/gen9/lzd.expected
new file mode 100644 (file)
index 0000000..74afe29
--- /dev/null
+++ b/src/intel/tools/tests/gen9/lzd.expected
@@ -0,0 +1,2 @@
+4a 00 60 00 08 02 20 23 64 00 00 00 00 00 00 00
+4a 00 80 00 08 02 60 23 64 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen9/mach.asm b/src/intel/tools/tests/gen9/mach.asm
new file mode 100644 (file)
index 0000000..7f632bf
--- /dev/null
+++ b/src/intel/tools/tests/gen9/mach.asm
@@ -0,0 +1,4 @@
+mach(8)         g19<1>UD        g17<8,8,1>UD    0xaaaaaaabUD    { align1 1Q AccWrEnable };
+mach(8)         g23<1>D         g17<8,8,1>D     1431655766D     { align1 1Q AccWrEnable };
+mach(8)         g42<1>UD        g39<8,8,1>UD    0xaaaaaaabUD    { align1 2Q AccWrEnable };
+mach(8)         g50<1>D         g39<8,8,1>D     1431655766D     { align1 2Q AccWrEnable };

diff --git a/src/intel/tools/tests/gen9/mach.expected b/src/intel/tools/tests/gen9/mach.expected
new file mode 100644 (file)
index 0000000..d90d46e
--- /dev/null
+++ b/src/intel/tools/tests/gen9/mach.expected
@@ -0,0 +1,4 @@
+49 00 60 10 08 02 60 22 20 02 8d 06 ab aa aa aa
+49 00 60 10 28 0a e0 22 20 02 8d 0e 56 55 55 55
+49 10 60 10 08 02 40 25 e0 04 8d 06 ab aa aa aa
+49 10 60 10 28 0a 40 26 e0 04 8d 0e 56 55 55 55

diff --git a/src/intel/tools/tests/gen9/mad.asm b/src/intel/tools/tests/gen9/mad.asm
new file mode 100644 (file)
index 0000000..a48131f
--- /dev/null
+++ b/src/intel/tools/tests/gen9/mad.asm
@@ -0,0 +1,43 @@
+mad(8)          g26<1>F         g22<4,4,1>F     g2.4<0,1,0>F    g5<4,4,1>F { align16 1Q };
+mad(16)         g14<1>F         g12<4,4,1>F     g4<4,4,1>F      g4<4,4,1>F { align16 1H };
+mad(8)          g64<1>DF        g62<4,4,1>DF    g40<4,4,1>DF    g92<4,4,1>DF { align16 1Q };
+mad(8)          g80<1>DF        -g50<4,4,1>DF   g24<4,4,1>DF    g80<4,4,1>DF { align16 1Q };
+mad(8)          g27<1>DF        g48<4,4,1>DF    g106<4,4,1>DF   g25<4,4,1>DF { align16 2Q };
+mad(8)          g13<1>F         -g14.0<0,1,0>F  g11<4,4,1>F     g6<4,4,1>F { align16 1Q };
+mad(16)         g29<1>F         -g33.0<0,1,0>F  g25<4,4,1>F     g15<4,4,1>F { align16 1H };
+mad(8)          g29<1>DF        g23<4,4,1>DF    g27<4,4,1>DF    -g25<4,4,1>DF { align16 1Q };
+mad.le.f0.0(8)  g5<1>F          g3<4,4,1>F      g4.2<0,1,0>F    g64<4,4,1>F { align16 1Q };
+mad.le.f0.0(16) g7<1>F          g4<4,4,1>F      g6.2<0,1,0>F    g16<4,4,1>F { align16 1H };
+mad(8)          g32<1>F         g31<4,4,1>F     g2.3<0,1,0>F    -g15<4,4,1>F { align16 1Q };
+mad(16)         g56<1>F         g54<4,4,1>F     g2.3<0,1,0>F    -g5<4,4,1>F { align16 1H };
+mad.sat(8)      g12<1>F         g4.1<0,1,0>F    g4.0<0,1,0>F    g8<4,4,1>F { align16 1Q };
+mad.sat(16)     g18<1>F         g6.1<0,1,0>F    g6.0<0,1,0>F    g10<4,4,1>F { align16 1H };
+mad(8)          g86<1>F         g88.6<0,1,0>F   -g88.7<0,1,0>F  g77<4,4,1>F { align16 1Q };
+mad(8)          g85<1>DF        g28<4,4,1>DF    g83<4,4,1>DF    -g81<4,4,1>DF { align16 2Q };
+mad(8)          g11<1>F         -g2.0<0,1,0>F   g10<4,4,1>F     (abs)g5.6<0,1,0>F { align16 1Q };
+mad(8)          g15<1>F         g2.1<0,1,0>F    g11<4,4,1>F     (abs)g5.6<0,1,0>F { align16 1Q };
+mad.l.f0.0(8)   g2<1>F          g22<4,4,1>F     g5.7<0,1,0>F    g6.3<0,1,0>F { align16 1Q };
+mad(8)          g79<1>DF        -g39<4,4,1>DF   g21<4,4,1>DF    g79<4,4,1>DF { align16 2Q };
+mad(8)          g117<1>F        -g116<4,4,1>F   g9.0<0,1,0>F    -g113<4,4,1>F { align16 1Q };
+mad.ge.f0.0(8)  g13<1>F         g28.0<0,1,0>F   g9<4,4,1>F      -g2.4<0,1,0>F { align16 1Q };
+mad.ge.f0.0(16) g23<1>F         g17.0<0,1,0>F   g6<4,4,1>F      -g3.0<0,1,0>F { align16 1H };
+mad(8)          g26<1>F         g2.0<0,1,0>F    -g2.1<0,1,0>F   (abs)g5.6<0,1,0>F { align16 1Q };
+mad(8)          g70<1>F         -g13<4,4,1>F    -g2.1<0,1,0>F   -g47<4,4,1>F { align16 1Q };
+mad(16)         g95<1>F         -g93<4,4,1>F    g85<4,4,1>F     -g85<4,4,1>F { align16 1H };
+mad(16)         g5<1>F          -g21<4,4,1>F    -g2.1<0,1,0>F   -g85<4,4,1>F { align16 1H };
+mad(16)         g56<1>F         g6.4<0,1,0>F    -g6.5<0,1,0>F   g51<4,4,1>F { align16 1H };
+mad.sat(8)      g124<1>F        -g7<4,4,1>F     g2.6<0,1,0>F    g2.1<0,1,0>F { align16 1Q };
+mad(16)         g71<1>F         g55.0<0,1,0>F   -g55.1<0,1,0>F  (abs)g1.0<0,1,0>F { align16 1H };
+mad(16)         g77<1>F         -g55.2<0,1,0>F  g71<4,4,1>F     (abs)g1.0<0,1,0>F { align16 1H };
+mad(16)         g37<1>F         g55.3<0,1,0>F   g77<4,4,1>F     (abs)g1.0<0,1,0>F { align16 1H };
+mad(8)          g43<1>DF        g42<4,4,1>DF    -g34<4,4,1>DF   g7<4,4,1>DF { align16 1Q };
+mad(8)          g3<1>DF         g2<4,4,1>DF     -g111<4,4,1>DF  g39<4,4,1>DF { align16 2Q };
+mad(8)          g12<1>F         -g17<4,4,1>F    (abs)g7<4,4,1>F g4.0<0,1,0>F { align16 1Q };
+mad(16)         g27<1>F         -g22<4,4,1>F    (abs)g19<4,4,1>F g29.0<0,1,0>F { align16 1H };
+mad.sat(8)      g125<1>F        g9<4,4,1>F      g6<4,4,1>F      -g64.0<0,1,0>F { align16 1Q };
+mad.l.f0.0(16)  g5<1>F          g9<4,4,1>F      g2.7<0,1,0>F    g3.3<0,1,0>F { align16 1H };
+mad(8)          g6<1>DF         -g55<4,4,1>DF   g2<4,4,1>DF     -g47<4,4,1>DF { align16 1Q };
+mad.z.f0.0(8)   g8<1>F          g3.2<0,1,0>F    g3.1<0,1,0>F    g3.0<0,1,0>F { align16 1Q };
+mad(8)          g63<1>DF        -g48<4,4,1>DF   g56<4,4,1>DF    -g44<4,4,1>DF { align16 2Q };
+mad.nz.f0.0(8)  g10<1>F         -g12.0<0,1,0>F  g7<4,4,1>F      g10<4,4,1>F { align16 1Q };
+mad.nz.f0.0(16) g15<1>F         -g33.0<0,1,0>F  g9<4,4,1>F      g17<4,4,1>F { align16 1H };

diff --git a/src/intel/tools/tests/gen9/mad.expected b/src/intel/tools/tests/gen9/mad.expected
new file mode 100644 (file)
index 0000000..76df668
--- /dev/null
+++ b/src/intel/tools/tests/gen9/mad.expected
@@ -0,0 +1,43 @@
+5b 01 60 00 00 00 1e 1a c8 61 21 00 05 20 47 01
+5b 01 80 00 00 00 1e 0e c8 c1 00 39 08 20 07 01
+5b 01 60 00 00 d8 1e 40 c8 e1 03 39 50 20 07 17
+5b 01 60 00 40 d8 1e 50 c8 21 03 39 30 20 07 14
+5b 11 60 00 00 d8 1e 1b c8 01 03 39 d4 20 47 06
+5b 01 60 00 40 00 1e 0d 01 e0 00 39 16 20 87 01
+5b 01 80 00 40 00 1e 1d 01 10 02 39 32 20 c7 03
+5b 01 60 00 00 dc 1e 1d c8 71 01 39 36 20 47 06
+5b 01 60 06 00 00 1e 05 c8 31 20 80 08 20 07 10
+5b 01 80 06 00 00 1e 07 c8 41 20 80 0c 20 07 04
+5b 01 60 00 00 04 1e 20 c8 f1 21 c0 04 20 c7 03
+5b 01 80 00 00 04 1e 38 c8 61 23 c0 04 20 47 01
+5b 01 60 80 00 00 1e 0c 01 42 20 00 08 20 07 02
+5b 01 80 80 00 00 1e 12 01 62 20 00 0c 20 87 02
+5b 01 60 00 00 01 1e 56 01 8c 25 c0 b1 20 47 13
+5b 11 60 00 00 dc 1e 55 c8 c1 01 39 a6 20 47 14
+5b 01 60 00 40 02 1e 0b 01 20 00 39 14 04 70 01
+5b 01 60 00 00 02 1e 0f 01 22 00 39 16 04 70 01
+5b 01 60 05 00 00 1e 02 c8 61 21 c0 0b 04 98 01
+5b 11 60 00 40 d8 1e 4f c8 71 02 39 2a 20 c7 13
+5b 01 60 00 40 04 1e 75 c8 41 27 00 12 20 47 1c
+5b 01 60 04 00 04 1e 0d 01 c0 01 39 12 04 a0 00
+5b 01 80 04 00 04 1e 17 01 10 01 39 0c 04 c0 00
+5b 01 60 00 00 03 1e 1a 01 20 20 40 04 04 70 01
+5b 01 60 00 40 05 1e 46 c8 d1 20 40 04 20 c7 0b
+5b 01 80 00 40 04 1e 5f c8 d1 05 39 aa 20 47 15
+5b 01 80 00 40 05 1e 05 c8 51 21 40 04 20 47 15
+5b 01 80 00 00 01 1e 38 01 68 20 40 0d 20 c7 0c
+5b 01 60 80 40 00 1e 7c c8 71 20 80 05 04 88 00
+5b 01 80 00 00 03 1e 47 01 70 23 40 6e 04 40 00
+5b 01 80 00 40 02 1e 4d 01 74 03 39 8e 04 40 00
+5b 01 80 00 00 02 1e 25 01 76 03 39 9a 04 40 00
+5b 01 60 00 00 d9 1e 2b c8 a1 02 39 44 20 c7 01
+5b 11 60 00 00 d9 1e 03 c8 21 00 39 de 20 c7 09
+5b 01 60 00 c0 00 1e 0c c8 11 01 39 0e 04 00 01
+5b 01 80 00 c0 00 1e 1b c8 61 01 39 26 04 40 07
+5b 01 60 80 00 04 1e 7d c8 91 00 39 0c 04 00 10
+5b 01 80 05 00 00 1e 05 c8 91 20 c0 05 04 d8 00
+5b 01 60 00 40 dc 1e 06 c8 71 03 39 04 20 c7 0b
+5b 01 60 01 00 00 1e 08 01 34 20 40 06 04 c0 00
+5b 11 60 00 40 dc 1e 3f c8 01 03 39 70 20 07 0b
+5b 01 60 02 40 00 1e 0a 01 c0 00 39 0e 20 87 02
+5b 01 80 02 40 00 1e 0f 01 10 02 39 12 20 47 04

diff --git a/src/intel/tools/tests/gen9/math.asm b/src/intel/tools/tests/gen9/math.asm
new file mode 100644 (file)
index 0000000..d6a54d2
--- /dev/null
+++ b/src/intel/tools/tests/gen9/math.asm
@@ -0,0 +1,31 @@
+math sqrt(16)   g20<1>F         g18<8,8,1>F     null<8,8,1>F    { align1 1H };
+math inv(8)     g95<1>F         g94<8,8,1>F     null<8,8,1>F    { align1 1Q };
+math inv(16)    g10<1>F         g8<8,8,1>F      null<8,8,1>F    { align1 1H };
+math intmod(8)  g3<1>UD         g1<0,1,0>UD     g1.2<0,1,0>UD   { align1 1Q };
+math intmod(8)  g4<1>UD         g1<0,1,0>UD     g1.2<0,1,0>UD   { align1 2Q };
+math sqrt(8)    g24<1>F         g23<8,8,1>F     null<8,8,1>F    { align1 1Q };
+math rsq(8)     g5<1>F          g2<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math pow(8)     g11<1>F         g10<8,8,1>F     0x42fc6666F  /* 126.2F */ { align1 1Q };
+math pow(16)    g18<1>F         g16<8,8,1>F     0x42fc6666F  /* 126.2F */ { align1 1H };
+math log(8)     g7<1>F          g6<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math log(16)    g11<1>F         g9<8,8,1>F      null<8,8,1>F    { align1 1H };
+math cos(8)     g3<1>F          g2<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math cos(16)    g4<1>F          g2<8,8,1>F      null<8,8,1>F    { align1 1H };
+math intdiv(8)  g4<1>UD         g1<0,1,0>UD     g1.4<0,1,0>UD   { align1 1Q };
+math intdiv(8)  g5<1>UD         g1<0,1,0>UD     g1.4<0,1,0>UD   { align1 2Q };
+math intdiv(8)  g24<1>D         g4<0,1,0>D      g2.2<0,1,0>D    { align1 1Q };
+math sin(8)     g10<1>F         g9<8,8,1>F      null<8,8,1>F    { align1 1Q };
+math rsq(16)    g68<1>F         g66<8,8,1>F     null<8,8,1>F    { align1 1H };
+math exp(8)     g124<1>F        g10<8,8,1>F     null<8,8,1>F    { align1 1Q };
+math exp(16)    g120<1>F        g7<8,8,1>F      null<8,8,1>F    { align1 1H };
+math intdiv(8)  g5<1>D          g2<0,1,0>D      g2.4<0,1,0>D    { align1 2Q };
+math sin(16)    g3<1>F          g2<0,1,0>F      null<8,8,1>F    { align1 1H };
+math.sat pow(8) g3<1>F          g2<0,1,0>F      g2.4<0,1,0>F    { align1 1Q };
+math.sat pow(16) g3<1>F         g2<0,1,0>F      g2.4<0,1,0>F    { align1 1H };
+math.sat sqrt(8) g3<1>F         g2<0,1,0>F      null<8,8,1>F    { align1 1Q };
+math.sat sqrt(16) g3<1>F        g2<0,1,0>F      null<8,8,1>F    { align1 1H };
+math.sat exp(8) g3<1>F          g2<0,1,0>F      null<8,8,1>F    { align1 1Q };
+math.sat exp(16) g3<1>F         g2<0,1,0>F      null<8,8,1>F    { align1 1H };
+math.sat rsq(8) g127<1>F        (abs)g7<8,8,1>F null<8,8,1>F    { align1 1Q };
+math.sat inv(8) g124<1>F        g2<0,1,0>F      null<8,8,1>F    { align1 1Q };
+math.sat log(8) g127<1>F        g7<8,8,1>F      null<8,8,1>F    { align1 1Q };

diff --git a/src/intel/tools/tests/gen9/math.expected b/src/intel/tools/tests/gen9/math.expected
new file mode 100644 (file)
index 0000000..9837a7c
--- /dev/null
+++ b/src/intel/tools/tests/gen9/math.expected
@@ -0,0 +1,31 @@
+38 00 80 04 e8 3a 80 22 40 02 8d 38 00 00 8d 00
+38 00 60 01 e8 3a e0 2b c0 0b 8d 38 00 00 8d 00
+38 00 80 01 e8 3a 40 21 00 01 8d 38 00 00 8d 00
+38 00 60 0d 08 02 60 20 20 00 00 02 28 00 00 00
+38 10 60 0d 08 02 80 20 20 00 00 02 28 00 00 00
+38 00 60 04 e8 3a 00 23 e0 02 8d 38 00 00 8d 00
+38 00 60 05 e8 3a a0 20 40 00 8d 38 00 00 8d 00
+38 00 60 0a e8 3a 60 21 40 01 8d 3e 66 66 fc 42
+38 00 80 0a e8 3a 40 22 00 02 8d 3e 66 66 fc 42
+38 00 60 02 e8 3a e0 20 c0 00 8d 38 00 00 8d 00
+38 00 80 02 e8 3a 60 21 20 01 8d 38 00 00 8d 00
+38 00 60 07 e8 3a 60 20 40 00 8d 38 00 00 8d 00
+38 00 80 07 e8 3a 80 20 40 00 8d 38 00 00 8d 00
+38 00 60 0c 08 02 80 20 20 00 00 02 30 00 00 00
+38 10 60 0c 08 02 a0 20 20 00 00 02 30 00 00 00
+38 00 60 0c 28 0a 00 23 80 00 00 0a 48 00 00 00
+38 00 60 06 e8 3a 40 21 20 01 8d 38 00 00 8d 00
+38 00 80 05 e8 3a 80 28 40 08 8d 38 00 00 8d 00
+38 00 60 03 e8 3a 80 2f 40 01 8d 38 00 00 8d 00
+38 00 80 03 e8 3a 00 2f e0 00 8d 38 00 00 8d 00
+38 10 60 0c 28 0a a0 20 40 00 00 0a 50 00 00 00
+38 00 80 06 e8 3a 60 20 40 00 00 38 00 00 8d 00
+38 00 60 8a e8 3a 60 20 40 00 00 3a 50 00 00 00
+38 00 80 8a e8 3a 60 20 40 00 00 3a 50 00 00 00
+38 00 60 84 e8 3a 60 20 40 00 00 38 00 00 8d 00
+38 00 80 84 e8 3a 60 20 40 00 00 38 00 00 8d 00
+38 00 60 83 e8 3a 60 20 40 00 00 38 00 00 8d 00
+38 00 80 83 e8 3a 60 20 40 00 00 38 00 00 8d 00
+38 00 60 85 e8 3a e0 2f e0 20 8d 38 00 00 8d 00
+38 00 60 81 e8 3a 80 2f 40 00 00 38 00 00 8d 00
+38 00 60 82 e8 3a e0 2f e0 00 8d 38 00 00 8d 00

diff --git a/src/intel/tools/tests/gen9/mov.asm b/src/intel/tools/tests/gen9/mov.asm
new file mode 100644 (file)
index 0000000..833631b
--- /dev/null
+++ b/src/intel/tools/tests/gen9/mov.asm
@@ -0,0 +1,139 @@
+mov(8)          g123<1>UD       g1<8,8,1>UD                     { align1 WE_all 1Q };
+mov(8)          g124<1>F        0x40c00000F      /* 6F */       { align1 1Q };
+mov(8)          g14<1>UD        0x00000000UD                    { align1 1Q };
+mov(8)          g17<1>F         g12<8,8,1>F                     { align1 1Q };
+mov.sat(8)      g124<1>F        g8<8,8,1>F                      { align1 1Q };
+mov(8)          g61<2>D         g22<8,8,1>D                     { align1 1Q };
+mov(8)          g21<1>D         g59<8,4,2>UD                    { align1 1Q };
+mov(8)          g4<1>D          -1D                             { align1 1Q };
+mov.nz.f0.0(8)  null<1>D        g4<8,8,1>D                      { align1 1Q };
+mov(1)          g2.2<1>UD       0x00000000UD                    { align1 WE_all 1N };
+mov(4)          g114<1>F        g2.3<8,2,4>F                    { align1 WE_all 1N };
+mov(8)          g126<1>F        g4<8,8,1>D                      { align1 1Q };
+mov(16)         g124<1>F        g4<8,8,1>D                      { align1 1H };
+mov(16)         g120<1>F        g124<8,8,1>F                    { align1 1H };
+mov(16)         g124<1>F        0x0F             /* 0F */       { align1 1H };
+mov(16)         g124<1>D        1065353216D                     { align1 1H };
+mov.nz.f0.0(16) null<1>D        g2<0,1,0>D                      { align1 1H };
+mov(8)          g3<1>UW         0x76543210V                     { align1 WE_all 1Q };
+mov(16)         g20<1>UD        g0.1<0,1,0>UD                   { align1 1H };
+mov(16)         g6<1>D          g3<8,8,1>UW                     { align1 1H };
+mov(8)          g1<1>D          g4<8,8,1>D                      { align1 2Q };
+mov(8)          g5<1>D          0D                              { align1 2Q };
+mov(8)          g2<1>F          g6<8,4,1>UW                     { align1 1Q };
+mov(8)          g7<1>D          g2<8,8,1>F                      { align1 1Q };
+mov(16)         g2<1>F          g10<8,4,1>UW                    { align1 1H };
+mov(16)         g11<1>D         g2<8,8,1>F                      { align1 1H };
+mov(8)          g80<1>DF        g5<0,1,0>DF                     { align1 1Q };
+mov(8)          g92<2>UD        g6.4<0,1,0>UD                   { align1 1Q };
+mov(8)          g62<1>Q         0xbff0000000000000Q             { align1 1Q };
+mov(8)          g92<2>F         g92<4,4,1>DF                    { align1 1Q };
+mov(8)          g92<1>DF        g95<4,4,1>F                     { align1 1Q };
+mov(8)          g106<1>DF       g2<0,1,0>F                      { align1 2Q };
+mov(8)          g48<1>Q         0xbff0000000000000Q             { align1 2Q };
+mov(8)          g127<1>UD       g106.1<8,4,2>UD                 { align1 2Q };
+mov(8)          g11<2>F         g7<4,4,1>DF                     { align1 2Q };
+mov(8)          g33<1>D         g34<8,4,2>UD                    { align1 2Q };
+mov(8)          g6<2>UD         0x00000000UD                    { align1 2Q };
+mov(8)          g2<1>UW         0x76543210UV                    { align1 1Q };
+mov(8)          g12<1>UD        g2<8,8,1>UW                     { align1 1Q };
+mov(8)          g7<1>UD         0x00080000UD                    { align1 WE_all 1Q };
+mov(1)          g2<1>F          0x3e800000F      /* 0.25F */    { align1 WE_all 1N };
+mov(8)          g15<1>F         g11<8,8,1>UD                    { align1 1Q };
+mov(1)          f0.1<1>UW       g1.14<0,1,0>UW                  { align1 WE_all 1N };
+mov(8)          g18<1>UD        g2<8,8,1>D                      { align1 1Q };
+mov(16)         g18<1>UD        g26<8,8,1>D                     { align1 1H };
+mov(16)         g120<1>D        g34<8,8,1>D                     { align1 1H };
+mov(8)          g8<1>Q          g13<4,4,1>Q                     { align1 1Q };
+mov(8)          g21<1>UD        g0<8,8,1>UD                     { align1 WE_all 2Q };
+mov(8)          g23<1>F         g6<0,1,0>F                      { align1 2Q };
+mov(1)          g21.2<1>UD      0x000003f2UD                    { align1 WE_all 3N };
+mov.nz.f0.0(8)  g19<1>D         g3<8,4,2>UD                     { align1 1Q };
+mov(1)          f1<1>UD         g1.7<0,1,0>UD                   { align1 WE_all 1N };
+mov.sat(8)      g126<1>F        0x0F             /* 0F */       { align1 1Q };
+mov.sat(8)      g124<1>F        -g36<8,8,1>D                    { align1 1Q };
+mov(8)          g41<1>F         0x0F             /* 0F */       { align1 2Q };
+mov(8)          g42<1>UD        g11<8,8,1>D                     { align1 2Q };
+mov(16)         g86<1>UD        g88<8,8,1>UD                    { align1 WE_all 1H };
+mov.sat(16)     g120<1>F        g2<0,1,0>F                      { align1 1H };
+mov(16)         g2<1>F          g18<8,8,1>UD                    { align1 1H };
+mov(8)          g4<1>UD         0x0F             /* 0F */       { align1 1Q };
+mov(8)          g8<1>DF         g2<0,1,0>D                      { align1 1Q };
+mov(16)         g8<1>UD         0x00000000UD                    { align1 1H };
+mov.nz.f0.0(8)  g4<1>F          -(abs)g2<0,1,0>F                { align1 1Q };
+(+f0.0) mov(8)  g4<1>F          0xbf800000F      /* -1F */      { align1 1Q };
+mov.nz.f0.0(16) g4<1>F          -(abs)g2<0,1,0>F                { align1 1H };
+(+f0.0) mov(16) g4<1>F          0xbf800000F      /* -1F */      { align1 1H };
+mov(1)          f1<1>UD         g1.7<0,1,0>UD                   { align1 WE_all 3N };
+mov(8)          g32<1>DF        g2<0,1,0>DF                     { align1 2Q };
+mov(8)          g5<1>F          g2<0,1,0>HF                     { align1 1Q };
+mov(16)         g6<1>F          g2<0,1,0>HF                     { align1 1H };
+mov(8)          g7<1>UD         g2<0,1,0>F                      { align1 1Q };
+mov(16)         g15<1>UD        g11<8,8,1>F                     { align1 1H };
+mov(16)         g19<1>UD        g15<16,8,2>UW                   { align1 1H };
+mov(1)          g19<1>UD        g[a0 64]<0,1,0>UD               { align1 WE_all 1N };
+mov(16)         g23<1>UD        g21<32,8,4>UB                   { align1 1H };
+mov(8)          g7<1>DF         0x0000000000000000DF /* 0DF */  { align1 1Q };
+mov(8)          g5<1>F          0x0F             /* 0F */       { align1 WE_all 1Q };
+mov(16)         g4<1>UD         0x00000000UD                    { align1 WE_all 1H };
+mov(8)          g5<2>UD         g2<0,1,0>DF                     { align1 1Q };
+mov(8)          g10<2>UD        g2<0,1,0>DF                     { align1 2Q };
+mov(8)          g3<1>DF         g2<0,1,0>UD                     { align1 1Q };
+mov(8)          g3<1>DF         g2<0,1,0>UD                     { align1 2Q };
+mov(1)          f0<1>UW         0x0000UW                        { align1 WE_all 1N };
+mov(1)          g1<1>D          0D                              { align1 WE_all 1N };
+(+f0.0.any16h) mov(1) g1<1>D    -1D                             { align1 WE_all 1N };
+mov(8)          g9<1>F          g2<0,1,0>W                      { align1 1Q };
+mov(8)          g7<1>UQ         g4<4,4,1>UQ                     { align1 1Q };
+mov(16)         g11<1>UD        0x0F             /* 0F */       { align1 1H };
+mov(8)          g5<2>D          g2<0,1,0>DF                     { align1 1Q };
+mov(8)          g10<2>D         g2<0,1,0>DF                     { align1 2Q };
+mov(1)          f1<1>UW         f0.1<0,1,0>UW                   { align1 WE_all 1N };
+mov(1)          f1<1>UW         f0.1<0,1,0>UW                   { align1 WE_all 3N };
+mov(16)         g4<1>D          0D                              { align1 2H };
+mov(8)          g14<1>UD        g13<32,8,4>UB                   { align1 1Q };
+mov(16)         g124<1>UD       g15<8,8,1>UD                    { align1 2H };
+mov(16)         g118<1>D        g122<8,8,1>UW                   { align1 2H };
+mov(16)         g101<1>UD       0x00000001UD                    { align1 2H };
+mov(1)          g4<2>UW         0x00000000UD                    { align1 WE_all 1N };
+mov(8)          g4<1>UD         f0<0,1,0>UW                     { align1 1Q };
+mov(8)          g8<1>D          g2<8,8,1>UW                     { align1 1Q };
+mov(16)         g4<1>UD         f0<0,1,0>UW                     { align1 1H };
+mov(8)          g3<1>DF         -g2<0,1,0>D                     { align1 2Q };
+mov(8)          g5<1>F          g2<0,1,0>B                      { align1 1Q };
+mov(16)         g6<1>F          g2<0,1,0>B                      { align1 1H };
+mov(8)          g4<1>DF         0x0000000000000000DF /* 0DF */  { align1 2Q };
+mov.nz.f0.0(8)  g16<1>D         g17<8,4,2>UD                    { align1 2Q };
+mov(8)          g34<1>UW        0x76543210V                     { align1 1Q };
+mov(8)          g8<1>UD         48D                             { align1 1Q };
+mov(16)         g8<1>UD         0D                              { align1 1H };
+mov(8)          g7<2>HF         g2.1<0,1,0>F                    { align1 1Q };
+mov(1)          g5<1>D          g[a0 96]<0,1,0>D                { align1 WE_all 1N };
+(+f0.0.any8h) mov(1) g2<1>D     -1D                             { align1 WE_all 1N };
+mov(8)          g9<1>UD         0D                              { align1 WE_all 1Q };
+mov(8)          g2<2>UW         g9<8,8,1>F                      { align1 1Q };
+mov(8)          g3<1>UW         g2<16,8,2>UW                    { align1 1Q };
+mov(8)          g12<1>UW        g8<16,8,2>UW                    { align1 WE_all 1Q };
+mov.sat(16)     g13<1>F         0x3f800000F      /* 1F */       { align1 1H };
+mov(16)         g19<2>UW        g17<8,8,1>F                     { align1 1H };
+mov(16)         g4<1>UW         g13<16,8,2>UW                   { align1 WE_all 1H };
+mov.nz.f0.0(8)  null<1>D        0x00000000UD                    { align1 1Q };
+mov.nz.f0.0(16) null<1>D        0x00000000UD                    { align1 1H };
+mov(4)          g3<1>UD         tm0<4,4,1>UD                    { align1 WE_all 1N };
+(+f0.0.all16h) mov(1) g1<1>D    -1D                             { align1 WE_all 1N };
+mov(8)          g9<1>F          g2<0,1,0>UB                     { align1 1Q };
+mov(16)         g6<1>F          g2<0,1,0>UB                     { align1 1H };
+mov(16)         g10<2>HF        g4<8,8,1>F                      { align1 1H };
+mov.z.f0.0(8)   null<1>UD       g2<8,8,1>UD                     { align1 1Q };
+mov.sat(8)      g125<1>F        g9<8,8,1>UD                     { align1 1Q };
+mov.z.f0.0(16)  g1<1>UD         g0.7<0,1,0>UD                   { align1 1H };
+mov.z.f0.0(8)   g18<1>D         g17<8,8,1>F                     { align1 1Q };
+mov(16)         g35<1>F         g15<16,8,2>W                    { align1 1H };
+mov(8)          g23<1>Q         g26<4,4,1>Q                     { align1 2Q };
+mov(8)          g2<1>D          0x00000000UD                    { align1 1Q };
+mov(16)         g2<1>D          0x00000000UD                    { align1 1H };
+(+f0.0.all8h) mov(1) g7<1>D     -1D                             { align1 WE_all 1N };
+mov(8)          g127<1>UB       g2<0,1,0>UB                     { align1 WE_all 1Q };
+mov.z.f0.0(8)   null<1>D        g24<8,8,1>F                     { align1 1Q };
+mov.z.f0.0(16)  null<1>D        g76<8,8,1>F                     { align1 1H };
+mov(16)         g7<1>D          g2<16,8,2>B                     { align1 1H };

diff --git a/src/intel/tools/tests/gen9/mov.expected b/src/intel/tools/tests/gen9/mov.expected
new file mode 100644 (file)
index 0000000..c1dc96d
--- /dev/null
+++ b/src/intel/tools/tests/gen9/mov.expected
@@ -0,0 +1,139 @@
+01 00 60 00 0c 02 60 2f 20 00 8d 00 00 00 00 00
+01 00 60 00 e8 3e 80 2f 00 00 00 38 00 00 c0 40
+01 00 60 00 08 06 c0 21 00 00 00 00 00 00 00 00
+01 00 60 00 e8 3a 20 22 80 01 8d 00 00 00 00 00
+01 00 60 80 e8 3a 80 2f 00 01 8d 00 00 00 00 00
+01 00 60 00 28 0a a0 47 c0 02 8d 00 00 00 00 00
+01 00 60 00 28 02 a0 22 60 07 8a 00 00 00 00 00
+01 00 60 00 28 0e 80 20 00 00 00 08 ff ff ff ff
+01 00 60 02 20 0a 00 20 80 00 8d 00 00 00 00 00
+01 00 00 00 0c 06 48 20 00 00 00 00 00 00 00 00
+01 00 40 00 ec 3a 40 2e 4c 00 87 00 00 00 00 00
+01 00 60 00 e8 0a c0 2f 80 00 8d 00 00 00 00 00
+01 00 80 00 e8 0a 80 2f 80 00 8d 00 00 00 00 00
+01 00 80 00 e8 3a 00 2f 80 0f 8d 00 00 00 00 00
+01 00 80 00 e8 3e 80 2f 00 00 00 38 00 00 00 00
+01 00 80 00 28 0e 80 2f 00 00 00 08 00 00 80 3f
+01 00 80 02 20 0a 00 20 40 00 00 00 00 00 00 00
+01 00 60 00 4c 36 60 20 00 00 00 30 10 32 54 76
+01 00 80 00 08 02 80 22 04 00 00 00 00 00 00 00
+01 00 80 00 28 12 c0 20 60 00 8d 00 00 00 00 00
+01 10 60 00 28 0a 20 20 80 00 8d 00 00 00 00 00
+01 10 60 00 28 0e a0 20 00 00 00 08 00 00 00 00
+01 00 60 00 e8 12 40 20 c0 00 89 00 00 00 00 00
+01 00 60 00 28 3a e0 20 40 00 8d 00 00 00 00 00
+01 00 80 00 e8 12 40 20 40 01 89 00 00 00 00 00
+01 00 80 00 28 3a 60 21 40 00 8d 00 00 00 00 00
+01 00 60 00 c8 32 00 2a a0 00 00 00 00 00 00 00
+01 00 60 00 08 02 80 4b d0 00 00 00 00 00 00 00
+01 00 60 00 28 4f c0 27 00 00 00 00 00 00 f0 bf
+01 00 60 00 e8 32 80 4b 80 0b 69 00 00 00 00 00
+01 00 60 00 c8 3a 80 2b e0 0b 69 00 00 00 00 00
+01 10 60 00 c8 3a 40 2d 40 00 00 00 00 00 00 00
+01 10 60 00 28 4f 00 26 00 00 00 00 00 00 f0 bf
+01 10 60 00 08 02 e0 2f 44 0d 8a 00 00 00 00 00
+01 10 60 00 e8 32 60 41 e0 00 69 00 00 00 00 00
+01 10 60 00 28 02 20 24 40 04 8a 00 00 00 00 00
+01 10 60 00 08 06 c0 40 00 00 00 00 00 00 00 00
+01 00 60 00 48 26 40 20 00 00 00 20 10 32 54 76
+01 00 60 00 08 12 80 21 40 00 8d 00 00 00 00 00
+01 00 60 00 0c 06 e0 20 00 00 00 00 00 00 08 00
+01 00 00 00 ec 3e 40 20 00 00 00 38 00 00 80 3e
+01 00 60 00 e8 02 e0 21 60 01 8d 00 00 00 00 00
+01 00 00 00 44 12 02 26 3c 00 00 00 00 00 00 00
+01 00 60 00 08 0a 40 22 40 00 8d 00 00 00 00 00
+01 00 80 00 08 0a 40 22 40 03 8d 00 00 00 00 00
+01 00 80 00 28 0a 00 2f 40 04 8d 00 00 00 00 00
+01 00 60 00 28 4b 00 21 a0 01 69 00 00 00 00 00
+01 10 60 00 0c 02 a0 22 00 00 8d 00 00 00 00 00
+01 10 60 00 e8 3a e0 22 c0 00 00 00 00 00 00 00
+01 10 00 00 0c 06 a8 22 00 00 00 00 f2 03 00 00
+01 00 60 02 28 02 60 22 60 00 8a 00 00 00 00 00
+01 00 00 00 04 02 20 26 3c 00 00 00 00 00 00 00
+01 00 60 80 e8 3e c0 2f 00 00 00 38 00 00 00 00
+01 00 60 80 e8 0a 80 2f 80 44 8d 00 00 00 00 00
+01 10 60 00 e8 3e 20 25 00 00 00 38 00 00 00 00
+01 10 60 00 08 0a 40 25 60 01 8d 00 00 00 00 00
+01 00 80 00 0c 02 c0 2a 00 0b 8d 00 00 00 00 00
+01 00 80 80 e8 3a 00 2f 40 00 00 00 00 00 00 00
+01 00 80 00 e8 02 40 20 40 02 8d 00 00 00 00 00
+01 00 60 00 08 3e 80 20 00 00 00 38 00 00 00 00
+01 00 60 00 c8 0a 00 21 40 00 00 00 00 00 00 00
+01 00 80 00 08 06 00 21 00 00 00 00 00 00 00 00
+01 00 60 02 e8 3a 80 20 40 60 00 00 00 00 00 00
+01 00 61 00 e8 3e 80 20 00 00 00 38 00 00 80 bf
+01 00 80 02 e8 3a 80 20 40 60 00 00 00 00 00 00
+01 00 81 00 e8 3e 80 20 00 00 00 38 00 00 80 bf
+01 10 00 00 04 02 20 26 3c 00 00 00 00 00 00 00
+01 10 60 00 c8 32 00 24 40 00 00 00 00 00 00 00
+01 00 60 00 e8 52 a0 20 40 00 00 00 00 00 00 00
+01 00 80 00 e8 52 c0 20 40 00 00 00 00 00 00 00
+01 00 60 00 08 3a e0 20 40 00 00 00 00 00 00 00
+01 00 80 00 08 3a e0 21 60 01 8d 00 00 00 00 00
+01 00 80 00 08 12 60 22 e0 01 ae 00 00 00 00 00
+01 00 00 00 0c 02 60 22 40 80 00 00 00 00 00 00
+01 00 80 00 08 22 e0 22 a0 02 cf 00 00 00 00 00
+01 00 60 00 c8 56 e0 20 00 00 00 00 00 00 00 00
+01 00 60 00 ec 3e a0 20 00 00 00 38 00 00 00 00
+01 00 80 00 0c 06 80 20 00 00 00 00 00 00 00 00
+01 00 60 00 08 32 a0 40 40 00 00 00 00 00 00 00
+01 10 60 00 08 32 40 41 40 00 00 00 00 00 00 00
+01 00 60 00 c8 02 60 20 40 00 00 00 00 00 00 00
+01 10 60 00 c8 02 60 20 40 00 00 00 00 00 00 00
+01 00 00 00 44 16 00 26 00 00 00 10 00 00 00 00
+01 00 00 00 2c 0e 20 20 00 00 00 08 00 00 00 00
+01 00 0a 00 2c 0e 20 20 00 00 00 08 ff ff ff ff
+01 00 60 00 e8 1a 20 21 40 00 00 00 00 00 00 00
+01 00 60 00 08 43 e0 20 80 00 69 00 00 00 00 00
+01 00 80 00 08 3e 60 21 00 00 00 38 00 00 00 00
+01 00 60 00 28 32 a0 40 40 00 00 00 00 00 00 00
+01 10 60 00 28 32 40 41 40 00 00 00 00 00 00 00
+01 00 00 00 44 10 20 26 02 06 00 00 00 00 00 00
+01 10 00 00 44 10 20 26 02 06 00 00 00 00 00 00
+01 20 80 00 28 0e 80 20 00 00 00 08 00 00 00 00
+01 00 60 00 08 22 c0 21 a0 01 cf 00 00 00 00 00
+01 20 80 00 08 02 80 2f e0 01 8d 00 00 00 00 00
+01 20 80 00 28 12 c0 2e 40 0f 8d 00 00 00 00 00
+01 20 80 00 08 06 a0 2c 00 00 00 00 01 00 00 00
+01 00 00 00 4c 06 80 40 00 00 00 00 00 00 00 00
+01 00 60 00 08 10 80 20 00 06 00 00 00 00 00 00
+01 00 60 00 28 12 00 21 40 00 8d 00 00 00 00 00
+01 00 80 00 08 10 80 20 00 06 00 00 00 00 00 00
+01 10 60 00 c8 0a 60 20 40 40 00 00 00 00 00 00
+01 00 60 00 e8 2a a0 20 40 00 00 00 00 00 00 00
+01 00 80 00 e8 2a c0 20 40 00 00 00 00 00 00 00
+01 10 60 00 c8 56 80 20 00 00 00 00 00 00 00 00
+01 10 60 02 28 02 00 22 20 02 8a 00 00 00 00 00
+01 00 60 00 48 36 40 24 00 00 00 30 10 32 54 76
+01 00 60 00 08 0e 00 21 00 00 00 08 30 00 00 00
+01 00 80 00 08 0e 00 21 00 00 00 08 00 00 00 00
+01 00 60 00 48 3b e0 40 44 00 00 00 00 00 00 00
+01 00 00 00 2c 0a a0 20 60 80 00 00 00 00 00 00
+01 00 08 00 2c 0e 40 20 00 00 00 08 ff ff ff ff
+01 00 60 00 0c 0e 20 21 00 00 00 08 00 00 00 00
+01 00 60 00 48 3a 40 40 20 01 8d 00 00 00 00 00
+01 00 60 00 48 12 60 20 40 00 ae 00 00 00 00 00
+01 00 60 00 4c 12 80 21 00 01 ae 00 00 00 00 00
+01 00 80 80 e8 3e a0 21 00 00 00 38 00 00 80 3f
+01 00 80 00 48 3a 60 42 20 02 8d 00 00 00 00 00
+01 00 80 00 4c 12 80 20 a0 01 ae 00 00 00 00 00
+01 00 60 02 20 06 00 20 00 00 00 00 00 00 00 00
+01 00 80 02 20 06 00 20 00 00 00 00 00 00 00 00
+01 00 40 00 0c 00 60 20 00 18 69 00 00 00 00 00
+01 00 0b 00 2c 0e 20 20 00 00 00 08 ff ff ff ff
+01 00 60 00 e8 22 20 21 40 00 00 00 00 00 00 00
+01 00 80 00 e8 22 c0 20 40 00 00 00 00 00 00 00
+01 00 80 00 48 3b 40 41 80 00 8d 00 00 00 00 00
+01 00 60 01 00 02 00 20 40 00 8d 00 00 00 00 00
+01 00 60 80 e8 02 a0 2f 20 01 8d 00 00 00 00 00
+01 00 80 01 08 02 20 20 1c 00 00 00 00 00 00 00
+01 00 60 01 28 3a 40 22 20 02 8d 00 00 00 00 00
+01 00 80 00 e8 1a 60 24 e0 01 ae 00 00 00 00 00
+01 10 60 00 28 4b e0 22 40 03 69 00 00 00 00 00
+01 00 60 00 28 06 40 20 00 00 00 00 00 00 00 00
+01 00 80 00 28 06 40 20 00 00 00 00 00 00 00 00
+01 00 09 00 2c 0e e0 20 00 00 00 08 ff ff ff ff
+01 00 60 00 8c 22 e0 2f 40 00 00 00 00 00 00 00
+01 00 60 01 20 3a 00 20 00 03 8d 00 00 00 00 00
+01 00 80 01 20 3a 00 20 80 09 8d 00 00 00 00 00
+01 00 80 00 28 2a e0 20 40 00 ae 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen9/mul.asm b/src/intel/tools/tests/gen9/mul.asm
new file mode 100644 (file)
index 0000000..36f4a1b
--- /dev/null
+++ b/src/intel/tools/tests/gen9/mul.asm
@@ -0,0 +1,31 @@
+mul(8)          g22<1>F         g4<8,8,1>F      g2<0,1,0>F      { align1 1Q };
+mul(16)         g26<1>F         g2<0,1,0>F      g2<0,1,0>F      { align1 1H };
+mul(8)          g36<1>DF        g8<0,1,0>DF     g8<0,1,0>DF     { align1 1Q };
+mul(8)          g9<1>UD         g86<8,8,1>UD    0x00000004UD    { align1 1Q };
+mul(8)          acc0<1>UD       g17<8,8,1>UD    0xaaabUW        { align1 1Q };
+mul(8)          acc0<1>D        g17<8,8,1>D     0x5556UW        { align1 1Q };
+mul(8)          g21<1>D         g20<8,8,1>D     3D              { align1 1Q };
+mul(8)          acc0<1>UD       g39<8,8,1>UD    0xaaabUW        { align1 2Q };
+mul(16)         g45<1>D         g43<8,8,1>D     3D              { align1 1H };
+mul(8)          acc0<1>D        g39<8,8,1>D     0x5556UW        { align1 2Q };
+mul.z.f0.0(8)   g10<1>F         g5<0,1,0>F      g9<8,8,1>F      { align1 1Q };
+mul(8)          g39<1>DF        g3.3<0,1,0>DF   g3.3<0,1,0>DF   { align1 2Q };
+mul.z.f0.0(16)  g6<1>F          g2<0,1,0>F      g4<8,8,1>F      { align1 1H };
+mul.sat(8)      g17<1>F         g4<8,8,1>F      g16<8,8,1>F     { align1 1Q };
+mul.sat(16)     g9<1>F          g3<8,8,1>F      g7<8,8,1>F      { align1 1H };
+mul.l.f0.0(8)   null<1>F        g6<0,1,0>F      g5.7<0,1,0>F    { align1 1Q };
+mul.sat(8)      g8<1>DF         g34<4,4,1>DF    g5<4,4,1>DF     { align1 1Q };
+mul(8)          g4<1>UQ         g8<4,4,1>UD     g12<4,4,1>UD    { align1 1Q };
+mul(8)          g20<1>UQ        g5<4,4,1>UD     g13<4,4,1>UD    { align1 2Q };
+mul(8)          g5<1>Q          g9<4,4,1>D      g13<4,4,1>D     { align1 1Q };
+mul.sat(8)      g10<1>DF        g10<4,4,1>DF    g16<4,4,1>DF    { align1 2Q };
+mul.l.f0.0(8)   g20<1>F         g2<8,8,1>F      0x42700000F  /* 60F */ { align1 1Q };
+mul.l.f0.0(16)  g32<1>F         g2<8,8,1>F      0x42700000F  /* 60F */ { align1 1H };
+mul(1)          g6<1>UD         g12<0,1,0>UD    0x00000101UD    { align1 WE_all 1N };
+mul(8)          g21<1>Q         g6<4,4,1>D      g14<4,4,1>D     { align1 2Q };
+mul.l.f0.0(16)  null<1>F        g2.2<0,1,0>F    g2.1<0,1,0>F    { align1 1H };
+mul(8)          g6<1>UW         g6<8,8,1>UW     0x0808UW        { align1 1Q };
+mul(16)         g15<1>UW        g14<16,16,1>UW  0x0808UW        { align1 1H };
+mul.nz.f0.0(8)  g6<1>F          g12<8,8,1>F     0x3f808000F  /* 1.00391F */ { align1 1Q };
+mul.nz.f0.0(16) g9<1>F          g7<8,8,1>F      0x3f808000F  /* 1.00391F */ { align1 1H };
+mul(1)          g4<1>UD         g4<0,1,0>UD     0x00000101UD    { align1 WE_all 3N };

diff --git a/src/intel/tools/tests/gen9/mul.expected b/src/intel/tools/tests/gen9/mul.expected
new file mode 100644 (file)
index 0000000..1a1a79c
--- /dev/null
+++ b/src/intel/tools/tests/gen9/mul.expected
@@ -0,0 +1,31 @@
+41 00 60 00 e8 3a c0 22 80 00 8d 3a 40 00 00 00
+41 00 80 00 e8 3a 40 23 40 00 00 3a 40 00 00 00
+41 00 60 00 c8 32 80 24 00 01 00 32 00 01 00 00
+41 00 60 00 08 02 20 21 c0 0a 8d 06 04 00 00 00
+41 00 60 00 00 02 00 24 20 02 8d 16 ab aa ab aa
+41 00 60 00 20 0a 00 24 20 02 8d 16 56 55 56 55
+41 00 60 00 28 0a a0 22 80 02 8d 0e 03 00 00 00
+41 10 60 00 00 02 00 24 e0 04 8d 16 ab aa ab aa
+41 00 80 00 28 0a a0 25 60 05 8d 0e 03 00 00 00
+41 10 60 00 20 0a 00 24 e0 04 8d 16 56 55 56 55
+41 00 60 01 e8 3a 40 21 a0 00 00 3a 20 01 8d 00
+41 10 60 00 c8 32 e0 24 78 00 00 32 78 00 00 00
+41 00 80 01 e8 3a c0 20 40 00 00 3a 80 00 8d 00
+41 00 60 80 e8 3a 20 22 80 00 8d 3a 00 02 8d 00
+41 00 80 80 e8 3a 20 21 60 00 8d 3a e0 00 8d 00
+41 00 60 05 e0 3a 00 20 c0 00 00 3a bc 00 00 00
+41 00 60 80 c8 32 00 21 40 04 69 32 a0 00 69 00
+41 00 60 00 08 03 80 20 00 01 69 02 80 01 69 00
+41 10 60 00 08 03 80 22 a0 00 69 02 a0 01 69 00
+41 00 60 00 28 0b a0 20 20 01 69 0a a0 01 69 00
+41 10 60 80 c8 32 40 21 40 01 69 32 00 02 69 00
+41 00 60 05 e8 3a 80 22 40 00 8d 3e 00 00 70 42
+41 00 80 05 e8 3a 00 24 40 00 8d 3e 00 00 70 42
+41 00 00 00 0c 02 c0 20 80 01 00 06 01 01 00 00
+41 10 60 00 28 0b a0 22 c0 00 69 0a c0 01 69 00
+41 00 80 05 e0 3a 00 20 48 00 00 3a 44 00 00 00
+41 00 60 00 48 12 c0 20 c0 00 8d 16 08 08 08 08
+41 00 80 00 48 12 e0 21 c0 01 b1 16 08 08 08 08
+41 00 60 02 e8 3a c0 20 80 01 8d 3e 00 80 80 3f
+41 00 80 02 e8 3a 20 21 e0 00 8d 3e 00 80 80 3f
+41 10 00 00 0c 02 80 20 80 00 00 06 01 01 00 00

diff --git a/src/intel/tools/tests/gen9/nop.asm b/src/intel/tools/tests/gen9/nop.asm
new file mode 100644 (file)
index 0000000..0b66395
--- /dev/null
+++ b/src/intel/tools/tests/gen9/nop.asm
@@ -0,0 +1 @@
+nop                                                             ;

diff --git a/src/intel/tools/tests/gen9/nop.expected b/src/intel/tools/tests/gen9/nop.expected
new file mode 100644 (file)
index 0000000..9a3dcf2
--- /dev/null
+++ b/src/intel/tools/tests/gen9/nop.expected
@@ -0,0 +1 @@
+7e 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen9/not.asm b/src/intel/tools/tests/gen9/not.asm
new file mode 100644 (file)
index 0000000..ce4592b
--- /dev/null
+++ b/src/intel/tools/tests/gen9/not.asm
@@ -0,0 +1,2 @@
+not(16)         g3<1>D          g1.2<0,1,0>D                    { align1 1H };
+not(8)          g4<1>D          g8<8,8,1>D                      { align1 1Q };

diff --git a/src/intel/tools/tests/gen9/not.expected b/src/intel/tools/tests/gen9/not.expected
new file mode 100644 (file)
index 0000000..3a66a22
--- /dev/null
+++ b/src/intel/tools/tests/gen9/not.expected
@@ -0,0 +1,2 @@
+04 00 80 00 28 0a 60 20 28 00 00 00 00 00 00 00
+04 00 60 00 28 0a 80 20 00 01 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen9/or.asm b/src/intel/tools/tests/gen9/or.asm
new file mode 100644 (file)
index 0000000..3bfcc98
--- /dev/null
+++ b/src/intel/tools/tests/gen9/or.asm
@@ -0,0 +1,23 @@
+or(8)           g53<1>UD        g49<8,8,1>UD    g21<8,8,1>UD    { align1 1Q };
+or.nz.f0.0(8)   null<1>UD       g21<8,8,1>UD    g2<8,8,1>UD     { align1 1Q };
+or.nz.f0.0(8)   g5<1>UD         g62<8,8,1>UD    g67<8,8,1>UD    { align1 1Q };
+or(8)           g5<1>UD         g106.1<8,4,2>UD 0x7ff00000UD    { align1 2Q };
+or.nz.f0.0(16)  null<1>UD       g35<8,8,1>UD    g32<8,8,1>UD    { align1 1H };
+or(16)          g36<1>UD        g34<8,8,1>UD    g20<8,8,1>UD    { align1 1H };
+or.nz.f0.0(16)  g53<1>UD        g51<8,8,1>UD    g49<8,8,1>UD    { align1 1H };
+or(1)           g8<1>UD         g8<0,1,0>UD     g4<0,1,0>UD     { align1 WE_all 1N };
+or(1)           a0<1>UD         g8<0,1,0>UD     0x060ba000UD    { align1 WE_all 1N };
+(+f0.0) or(8)   g3<1>UD         g3<8,8,1>UD     0x3f800000UD    { align1 1Q };
+(+f0.0) or(16)  g3<1>UD         g3<8,8,1>UD     0x3f800000UD    { align1 1H };
+or(1)           a0<1>UD         a0<0,1,0>UD     0x02280300UD    { align1 WE_all 1N };
+or(1)           a0<1>UD         g4<0,1,0>UD     0x04036000UD    { align1 WE_all 3N };
+(+f0.0) or(8)   g17.1<2>UD      g17.1<8,4,2>UD  0x3ff00000UD    { align1 2Q };
+or(8)           g4<1>UW         g4<8,8,1>UW     g6<8,8,1>UW     { align1 1Q };
+or(16)          g16<1>UW        g14<16,16,1>UW  g15<16,16,1>UW  { align1 1H };
+or(8)           g22<1>UD        ~g2.2<0,1,0>D   g21<8,8,1>UD    { align1 1Q };
+or(16)          g37<1>UD        ~g2.2<0,1,0>D   g35<8,8,1>UD    { align1 1H };
+or(8)           g9<1>D          ~g8<8,8,1>D     ~g7<8,8,1>D     { align1 1Q };
+or(16)          g13<1>D         ~g11<8,8,1>D    ~g9<8,8,1>D     { align1 1H };
+or(1)           g14<1>UD        g14<0,1,0>UD    g19<0,1,0>UD    { align1 WE_all 3N };
+or.z.f0.0(8)    null<1>UD       g5<8,8,1>UD     g6<8,8,1>UD     { align1 1Q };
+or.z.f0.0(16)   null<1>UD       g17<8,8,1>UD    g19<8,8,1>UD    { align1 1H };

diff --git a/src/intel/tools/tests/gen9/or.expected b/src/intel/tools/tests/gen9/or.expected
new file mode 100644 (file)
index 0000000..61e2fcc
--- /dev/null
+++ b/src/intel/tools/tests/gen9/or.expected
@@ -0,0 +1,23 @@
+06 00 60 00 08 02 a0 26 20 06 8d 02 a0 02 8d 00
+06 00 60 02 00 02 00 20 a0 02 8d 02 40 00 8d 00
+06 00 60 02 08 02 a0 20 c0 07 8d 02 60 08 8d 00
+06 10 60 00 08 02 a0 20 44 0d 8a 06 00 00 f0 7f
+06 00 80 02 00 02 00 20 60 04 8d 02 00 04 8d 00
+06 00 80 00 08 02 80 24 40 04 8d 02 80 02 8d 00
+06 00 80 02 08 02 a0 26 60 06 8d 02 20 06 8d 00
+06 00 00 00 0c 02 00 21 00 01 00 02 80 00 00 00
+06 00 00 00 04 02 00 22 00 01 00 06 00 a0 0b 06
+06 00 61 00 08 02 60 20 60 00 8d 06 00 00 80 3f
+06 00 81 00 08 02 60 20 60 00 8d 06 00 00 80 3f
+06 00 00 00 04 00 00 22 00 02 00 06 00 03 28 02
+06 10 00 00 04 02 00 22 80 00 00 06 00 60 03 04
+06 10 61 00 08 02 24 42 24 02 8a 06 00 00 f0 3f
+06 00 60 00 48 12 80 20 80 00 8d 12 c0 00 8d 00
+06 00 80 00 48 12 00 22 c0 01 b1 12 e0 01 b1 00
+06 00 60 00 08 0a c0 22 48 40 00 02 a0 02 8d 00
+06 00 80 00 08 0a a0 24 48 40 00 02 60 04 8d 00
+06 00 60 00 28 0a 20 21 00 41 8d 0a e0 40 8d 00
+06 00 80 00 28 0a a0 21 60 41 8d 0a 20 41 8d 00
+06 10 00 00 0c 02 c0 21 c0 01 00 02 60 02 00 00
+06 00 60 01 00 02 00 20 a0 00 8d 02 c0 00 8d 00
+06 00 80 01 00 02 00 20 20 02 8d 02 60 02 8d 00

diff --git a/src/intel/tools/tests/gen9/pln.asm b/src/intel/tools/tests/gen9/pln.asm
new file mode 100644 (file)
index 0000000..5b0adcf
--- /dev/null
+++ b/src/intel/tools/tests/gen9/pln.asm
@@ -0,0 +1,10 @@
+pln(8)          g124<1>F        g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln(16)         g120<1>F        g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.sat(8)      g9<1>F          g5<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.sat(16)     g12<1>F         g7<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.g.f0.0(8)   g7<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.g.f0.0(16)  g11<1>F         g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.l.f0.0(8)   g8<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.l.f0.0(16)  g11<1>F         g6<0,1,0>F      g2<8,8,1>F      { align1 1H };
+pln.nz.f0.0(8)  g18<1>F         g5<0,1,0>F      g2<8,8,1>F      { align1 1Q };
+pln.nz.f0.0(16) g14<1>F         g7<0,1,0>F      g2<8,8,1>F      { align1 1H };

diff --git a/src/intel/tools/tests/gen9/pln.expected b/src/intel/tools/tests/gen9/pln.expected
new file mode 100644 (file)
index 0000000..eb77b2a
--- /dev/null
+++ b/src/intel/tools/tests/gen9/pln.expected
@@ -0,0 +1,10 @@
+5a 00 60 00 e8 3a 80 2f 80 00 00 3a 40 00 8d 00
+5a 00 80 00 e8 3a 00 2f c0 00 00 3a 40 00 8d 00
+5a 00 60 80 e8 3a 20 21 a0 00 00 3a 40 00 8d 00
+5a 00 80 80 e8 3a 80 21 e0 00 00 3a 40 00 8d 00
+5a 00 60 03 e8 3a e0 20 80 00 00 3a 40 00 8d 00
+5a 00 80 03 e8 3a 60 21 c0 00 00 3a 40 00 8d 00
+5a 00 60 05 e8 3a 00 21 80 00 00 3a 40 00 8d 00
+5a 00 80 05 e8 3a 60 21 c0 00 00 3a 40 00 8d 00
+5a 00 60 02 e8 3a 40 22 a0 00 00 3a 40 00 8d 00
+5a 00 80 02 e8 3a c0 21 e0 00 00 3a 40 00 8d 00

diff --git a/src/intel/tools/tests/gen9/rndd.asm b/src/intel/tools/tests/gen9/rndd.asm
new file mode 100644 (file)
index 0000000..463ef80
--- /dev/null
+++ b/src/intel/tools/tests/gen9/rndd.asm
@@ -0,0 +1,5 @@
+rndd(8)         g22<1>F         g17<0,1,0>F                     { align1 1Q };
+rndd(16)        g7<1>F          g5<8,8,1>F                      { align1 1H };
+rndd.z.f0.0(8)  null<1>F        g17<8,8,1>F                     { align1 1Q };
+rndd.z.f0.0(16) null<1>F        g39<8,8,1>F                     { align1 1H };
+rndd.sat(8)     g124<1>F        g10<8,8,1>F                     { align1 1Q };

diff --git a/src/intel/tools/tests/gen9/rndd.expected b/src/intel/tools/tests/gen9/rndd.expected
new file mode 100644 (file)
index 0000000..ff7ca82
--- /dev/null
+++ b/src/intel/tools/tests/gen9/rndd.expected
@@ -0,0 +1,5 @@
+45 00 60 00 e8 3a c0 22 20 02 00 00 00 00 00 00
+45 00 80 00 e8 3a e0 20 a0 00 8d 00 00 00 00 00
+45 00 60 01 e0 3a 00 20 20 02 8d 00 00 00 00 00
+45 00 80 01 e0 3a 00 20 e0 04 8d 00 00 00 00 00
+45 00 60 80 e8 3a 80 2f 40 01 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen9/rnde.asm b/src/intel/tools/tests/gen9/rnde.asm
new file mode 100644 (file)
index 0000000..bc65bbc
--- /dev/null
+++ b/src/intel/tools/tests/gen9/rnde.asm
@@ -0,0 +1,2 @@
+rnde(8)         g7<1>F          g5<8,8,1>F                      { align1 1Q };
+rnde(16)        g11<1>F         g7<8,8,1>F                      { align1 1H };

diff --git a/src/intel/tools/tests/gen9/rnde.expected b/src/intel/tools/tests/gen9/rnde.expected
new file mode 100644 (file)
index 0000000..edac496
--- /dev/null
+++ b/src/intel/tools/tests/gen9/rnde.expected
@@ -0,0 +1,2 @@
+46 00 60 00 e8 3a e0 20 a0 00 8d 00 00 00 00 00
+46 00 80 00 e8 3a 60 21 e0 00 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen9/rndz.asm b/src/intel/tools/tests/gen9/rndz.asm
new file mode 100644 (file)
index 0000000..4b082d0
--- /dev/null
+++ b/src/intel/tools/tests/gen9/rndz.asm
@@ -0,0 +1,2 @@
+rndz(8)         g7<1>F          g2<0,1,0>F                      { align1 1Q };
+rndz(16)        g102<1>F        g99<8,8,1>F                     { align1 1H };

diff --git a/src/intel/tools/tests/gen9/rndz.expected b/src/intel/tools/tests/gen9/rndz.expected
new file mode 100644 (file)
index 0000000..2a79a23
--- /dev/null
+++ b/src/intel/tools/tests/gen9/rndz.expected
@@ -0,0 +1,2 @@
+47 00 60 00 e8 3a e0 20 40 00 00 00 00 00 00 00
+47 00 80 00 e8 3a c0 2c 60 0c 8d 00 00 00 00 00

diff --git a/src/intel/tools/tests/gen9/sel.asm b/src/intel/tools/tests/gen9/sel.asm
new file mode 100644 (file)
index 0000000..6047c31
--- /dev/null
+++ b/src/intel/tools/tests/gen9/sel.asm
@@ -0,0 +1,33 @@
+(-f0.0) sel(8)  g124<1>UD       g124<8,8,1>UD   0x3f800000UD    { align1 1Q };
+(+f0.0) sel(8)  g124<1>UD       g124<8,8,1>UD   0x00000000UD    { align1 1Q };
+(+f0.0) sel(8)  g24<1>UQ        g66<4,4,1>UQ    g40<4,4,1>UQ    { align1 1Q };
+(+f0.0) sel(8)  g36<1>UQ        g50<4,4,1>UQ    g31<4,4,1>UQ    { align1 2Q };
+sel.ge(8)       g17<1>F         (abs)g16<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
+sel.ge(16)      g37<1>F         (abs)g35<8,8,1>F 0x3f800000F  /* 1F */ { align1 1H };
+(+f0.0) sel(16) g26<1>UD        g31<8,8,1>UD    g33<8,8,1>UD    { align1 1H };
+(-f0.0) sel(16) g1<1>UD         g55<8,8,1>UD    0x00000000UD    { align1 1H };
+sel.l(8)        g3<1>UD         g2.1<0,1,0>UD   0x00000001UD    { align1 1Q };
+sel.l(16)       g3<1>UD         g2.1<0,1,0>UD   0x00000001UD    { align1 1H };
+sel.ge(8)       g3<1>D          g2<0,1,0>D      -1D             { align1 1Q };
+sel.l(8)        g4<1>D          g3<8,8,1>D      1D              { align1 1Q };
+sel.ge(16)      g3<1>D          g2<0,1,0>D      -1D             { align1 1H };
+sel.l(16)       g5<1>D          g3<8,8,1>D      1D              { align1 1H };
+sel.l(8)        g8<1>F          g7<8,8,1>F      0x43000000F  /* 128F */ { align1 1Q };
+(-f0.0) sel.sat(8) g126<1>F     g11<8,8,1>F     0x0F  /* 0F */  { align1 1Q };
+sel.l(8)        g18<1>DF        g5<0,1,0>DF     g5.1<0,1,0>DF   { align1 1Q };
+sel.ge(16)      g37<1>UD        g9<8,8,1>UD     g13<8,8,1>UD    { align1 1H };
+sel.ge(8)       g19<1>UD        g5<0,1,0>UD     g5.4<0,1,0>UD   { align1 1Q };
+sel.sat.l(8)    g124<1>F        g6<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 1Q };
+(+f0.0) sel(8)  g26<1>F         g5<0,1,0>F      (abs)g5.3<0,1,0>F { align1 1Q };
+(-f0.0) sel(8)  g44<1>F         (abs)g41<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
+sel.l(16)       g120<1>F        g2.3<0,1,0>F    g2.2<0,1,0>F    { align1 1H };
+(+f0.0) sel(8)  g9<1>DF         g2<0,1,0>DF     -g2<0,1,0>DF    { align1 1Q };
+(+f0.0) sel(8)  g12<1>DF        g2<0,1,0>DF     -g2<0,1,0>DF    { align1 2Q };
+sel.ge(8)       g5<1>DF         g2<0,1,0>DF     g2.2<0,1,0>DF   { align1 1Q };
+sel.ge(8)       g35<1>DF        g2<0,1,0>DF     g2.2<0,1,0>DF   { align1 2Q };
+sel.l(8)        g11<1>DF        g35<4,4,1>DF    g3<0,1,0>DF     { align1 2Q };
+(+f0.0) sel.sat(8) g126<1>F     g11<8,8,1>F     0x0F  /* 0F */  { align1 1Q };
+(-f0.0) sel(16) g27<1>F         (abs)g25<8,8,1>F 0x3f800000F  /* 1F */ { align1 1H };
+(+f0.0) sel(16) g36<1>F         g2<0,1,0>F      (abs)g2.4<0,1,0>F { align1 1H };
+(+f0.0) sel(16) g116<1>UD       g112<8,8,1>UD   g114<8,8,1>UD   { align1 2H };
+sel.sat.l(16)   g8<1>F          g83<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1H };

diff --git a/src/intel/tools/tests/gen9/sel.expected b/src/intel/tools/tests/gen9/sel.expected
new file mode 100644 (file)
index 0000000..aba34ca
--- /dev/null
+++ b/src/intel/tools/tests/gen9/sel.expected
@@ -0,0 +1,33 @@
+02 00 71 00 08 02 80 2f 80 0f 8d 06 00 00 80 3f
+02 00 61 00 08 02 80 2f 80 0f 8d 06 00 00 00 00
+02 00 61 00 08 43 00 23 40 08 69 42 00 05 69 00
+02 10 61 00 08 43 80 24 40 06 69 42 e0 03 69 00
+02 00 60 04 e8 3a 20 22 00 22 8d 3e 00 00 80 3f
+02 00 80 04 e8 3a a0 24 60 24 8d 3e 00 00 80 3f
+02 00 81 00 08 02 40 23 e0 03 8d 02 20 04 8d 00
+02 00 91 00 08 02 20 20 e0 06 8d 06 00 00 00 00
+02 00 60 05 08 02 60 20 44 00 00 06 01 00 00 00
+02 00 80 05 08 02 60 20 44 00 00 06 01 00 00 00
+02 00 60 04 28 0a 60 20 40 00 00 0e ff ff ff ff
+02 00 60 05 28 0a 80 20 60 00 8d 0e 01 00 00 00
+02 00 80 04 28 0a 60 20 40 00 00 0e ff ff ff ff
+02 00 80 05 28 0a a0 20 60 00 8d 0e 01 00 00 00
+02 00 60 05 e8 3a 00 21 e0 00 8d 3e 00 00 00 43
+02 00 71 80 e8 3a c0 2f 60 01 8d 3e 00 00 00 00
+02 00 60 05 c8 32 40 22 a0 00 00 32 a8 00 00 00
+02 00 80 04 08 02 a0 24 20 01 8d 02 a0 01 8d 00
+02 00 60 04 08 02 60 22 a0 00 00 02 b0 00 00 00
+02 00 60 85 e8 3a 80 2f c0 00 8d 3e 00 00 00 3f
+02 00 61 00 e8 3a 40 23 a0 00 00 3a ac 20 00 00
+02 00 71 00 e8 3a 80 25 20 25 8d 3e 00 00 80 3f
+02 00 80 05 e8 3a 00 2f 4c 00 00 3a 48 00 00 00
+02 00 61 00 c8 32 20 21 40 00 00 32 40 40 00 00
+02 10 61 00 c8 32 80 21 40 00 00 32 40 40 00 00
+02 00 60 04 c8 32 a0 20 40 00 00 32 50 00 00 00
+02 10 60 04 c8 32 60 24 40 00 00 32 50 00 00 00
+02 10 60 05 c8 32 60 21 60 04 69 32 60 00 00 00
+02 00 61 80 e8 3a c0 2f 60 01 8d 3e 00 00 00 00
+02 00 91 00 e8 3a 60 23 20 23 8d 3e 00 00 80 3f
+02 00 81 00 e8 3a 80 24 40 00 00 3a 50 20 00 00
+02 20 81 00 08 02 80 2e 00 0e 8d 02 40 0e 8d 00
+02 00 80 85 e8 3a 00 21 60 0a 8d 3e 00 00 00 3f

diff --git a/src/intel/tools/tests/gen9/send.asm b/src/intel/tools/tests/gen9/send.asm
new file mode 100644 (file)
index 0000000..918859e
--- /dev/null
+++ b/src/intel/tools/tests/gen9/send.asm
@@ -0,0 +1,3606 @@
+send(8)         null<1>F        g123<8,8,1>F    0x8a080017
+                            urb MsgDesc: 1 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         null<1>F        g13<8,8,1>F     0x12080007
+                            urb MsgDesc: 0 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080027
+                            urb MsgDesc: 2 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(16)        g9<1>UD         g2<0,1,0>UD     0x02280300
+                            const MsgDesc: (0, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         null<1>F        g119<8,8,1>F    0x92080017
+                            urb MsgDesc: 1 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(16)        null<1>UW       g127<8,8,1>UW   0x82000010
+                            thread_spawner MsgDesc: mlen 1 rlen 0           { align1 WE_all 1H EOT };
+send(8)         g124<1>UW       g13<8,8,1>UD    0x0643a001
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g23<8,8,1>UD    0x0c85a001
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g10<1>UD        g2<8,8,1>UD     0x02480028
+                            urb MsgDesc: 2 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         null<1>F        g8<8,8,1>F      0x140a0017
+                            urb MsgDesc: 1 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g118<8,8,1>F    0x940a0017
+                            urb MsgDesc: 1 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x08427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g18<8,8,1>UD    0x10847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         null<1>F        g11<8,8,1>UD    0x0c0a0037
+                            urb MsgDesc: 3 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a080027
+                            urb MsgDesc: 2 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0c088017
+                            urb MsgDesc: 1 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a088017
+                            urb MsgDesc: 1 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x08088017
+                            urb MsgDesc: 1 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g2<8,8,1>UD     0x06088017
+                            urb MsgDesc: 1 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0c088007
+                            urb MsgDesc: 0 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a088007
+                            urb MsgDesc: 0 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g125<8,8,1>UD   0x86088007
+                            urb MsgDesc: 0 SIMD8 write masked mlen 3 rlen 0 { align1 1Q EOT };
+send(8)         g7<1>UW         g7<8,8,1>UD     0x0443a000
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g6<8,8,1>UD     0x0222a001
+                            sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 2 { align1 1Q };
+send(8)         g2<1>UW         g19<8,8,1>UD    0x084a8001
+                            sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g25<1>UW        g16<8,8,1>UD    0x0444a001
+                            sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1H };
+send(16)        g14<1>UW        g7<8,8,1>UD     0x0e8c8001
+                            sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         null<1>F        g11<8,8,1>F     0x12080017
+                            urb MsgDesc: 1 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>F     0x12080037
+                            urb MsgDesc: 3 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080057
+                            urb MsgDesc: 5 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         g9<1>UW         g6<8,8,1>UD     0x0613d001
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q };
+send(16)        g12<1>UW        g14<8,8,1>UD    0x0c25d001
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g14<8,8,1>UD    0x0643d001
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g8<1>UW         g17<8,8,1>UD    0x0a43e001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g26<1>UW        g10<8,8,1>UD    0x0c85d001
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        g34<1>UW        g16<8,8,1>UD    0x1485e001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(8)         g5<1>UW         g2<8,8,1>UD     0x04320001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 3 { align1 1Q };
+send(16)        g7<1>UW         g2<8,8,1>UD     0x08640001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 6 { align1 1H };
+send(8)         g12<1>UW        g10<8,8,1>UD    0x0a33e001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 3 { align1 1Q };
+send(16)        g2<1>UW         g18<8,8,1>UD    0x1465e001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 6 { align1 1H };
+send(8)         g5<1>UW         g2<8,8,1>UD     0x04420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g2<8,8,1>UD     0x08840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g11<1>UW        g9<8,8,1>UD     0x0222a000
+                            sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 2 { align1 1Q };
+send(8)         g124<1>UW       g13<8,8,1>UD    0x064a8000
+                            sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g12<1>UW        g5<8,8,1>UD     0x02427000
+                            sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080037
+                            urb MsgDesc: 3 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x144a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 1Q };
+(+f1.0) send(8) g125<1>UW       g3<8,8,1>UD     0x0210b501
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 1 { align1 1Q };
+(+f1.0) send(16) g122<1>UW      g4<8,8,1>UD     0x0420a501
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 2 { align1 1H };
+send(8)         g6<1>UW         g12<8,8,1>UD    0x084a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g98<1>UW        g17<8,8,1>UD    0x0c43c001
+                            sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g8<8,8,1>UD     0x064a8001
+                            sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g12<8,8,1>UD    0x0a8c8001
+                            sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g7<8,8,1>UD     0x0a1a6001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q };
+send(8)         g7<1>UW         g12<8,8,1>UD    0x0a1a6102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q };
+send(16)        g10<1>UW        g12<8,8,1>UD    0x122c6001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 2 { align1 1H };
+send(16)        g12<1>UW        g21<8,8,1>UD    0x122c6102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 2 { align1 1H };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x0a43e000
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080027
+                            urb MsgDesc: 2 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         g2<1>UW         g3<8,8,1>UD     0x0643d000
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         null<1>F        g7<8,8,1>UD     0x0a080037
+                            urb MsgDesc: 3 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g8<8,8,1>UD     0x0a080047
+                            urb MsgDesc: 4 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>F     0x0c0a0017
+                            urb MsgDesc: 1 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g122<8,8,1>F    0x8c0a0017
+                            urb MsgDesc: 1 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g13<1>UW        g10<8,8,1>UD    0x02320001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 3 { align1 1Q };
+send(16)        g22<1>UW        g18<8,8,1>UD    0x04640001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 6 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x0232a000
+                            sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 3 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x0c4b1001
+                            sampler MsgDesc: gather4_po SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g7<8,8,1>UD     0x168d1001
+                            sampler MsgDesc: gather4_po SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a088027
+                            urb MsgDesc: 2 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g7<8,8,1>UD     0x0a088037
+                            urb MsgDesc: 3 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g8<8,8,1>UD     0x0a088047
+                            urb MsgDesc: 4 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g9<8,8,1>UD     0x0a088057
+                            urb MsgDesc: 5 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x06427000
+                            sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x06427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g18<8,8,1>UD    0x0c847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g10<8,8,1>UD    0x0c424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x0c4b1000
+                            sampler MsgDesc: gather4_po SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g4<8,8,1>UD     0x0242a000
+                            sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x0242a101
+                            sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g10<8,8,1>UD    0x0242a202
+                            sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 2 mlen 1 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g14<8,8,1>UD    0x0242a303
+                            sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 3 mlen 1 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x0242a404
+                            sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 4 mlen 1 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g22<8,8,1>UD    0x0242a505
+                            sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 5 mlen 1 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g26<8,8,1>UD    0x0242a606
+                            sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 6 mlen 1 rlen 4 { align1 1Q };
+send(8)         g6<1>UD         g15<8,8,1>UD    0x042a0318
+                            urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g8<1>UD         g15<8,8,1>UD    0x042a0518
+                            urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g10<1>UD        g15<8,8,1>UD    0x042a0718
+                            urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g12<1>UD        g15<8,8,1>UD    0x042a0918
+                            urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g14<1>UD        g15<8,8,1>UD    0x042a0128
+                            urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g16<1>UD        g14<8,8,1>UD    0x042a0218
+                            urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g18<1>UD        g14<8,8,1>UD    0x042a0418
+                            urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g20<1>UD        g14<8,8,1>UD    0x042a0618
+                            urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g22<1>UD        g14<8,8,1>UD    0x042a0818
+                            urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g13<1>UD        g14<8,8,1>UD    0x042a0028
+                            urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g30<8,8,1>UD    0x02480208
+                            urb MsgDesc: 32 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g14<1>UD        g30<8,8,1>UD    0x02480408
+                            urb MsgDesc: 64 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g18<1>UD        g30<8,8,1>UD    0x02480608
+                            urb MsgDesc: 96 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g30<8,8,1>UD    0x02480808
+                            urb MsgDesc: 128 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a0a8217
+                            urb MsgDesc: 33 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x0a0a8227
+                            urb MsgDesc: 34 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0a0a8237
+                            urb MsgDesc: 35 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x0a0a8247
+                            urb MsgDesc: 36 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x0a0a8257
+                            urb MsgDesc: 37 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x0a0a8267
+                            urb MsgDesc: 38 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0a0a8277
+                            urb MsgDesc: 39 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0a0a8287
+                            urb MsgDesc: 40 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0a0a8297
+                            urb MsgDesc: 41 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0a0a82a7
+                            urb MsgDesc: 42 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0a0a82b7
+                            urb MsgDesc: 43 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0a0a82c7
+                            urb MsgDesc: 44 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0a0a82d7
+                            urb MsgDesc: 45 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0a0a82e7
+                            urb MsgDesc: 46 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0a0a82f7
+                            urb MsgDesc: 47 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0a0a8307
+                            urb MsgDesc: 48 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0a0a8317
+                            urb MsgDesc: 49 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0a0a8327
+                            urb MsgDesc: 50 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0a0a8337
+                            urb MsgDesc: 51 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0a0a8347
+                            urb MsgDesc: 52 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0a0a8357
+                            urb MsgDesc: 53 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0a0a8367
+                            urb MsgDesc: 54 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0a0a8377
+                            urb MsgDesc: 55 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0a0a8387
+                            urb MsgDesc: 56 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0a0a8397
+                            urb MsgDesc: 57 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0a0a83a7
+                            urb MsgDesc: 58 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0a0a83b7
+                            urb MsgDesc: 59 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0a0a83c7
+                            urb MsgDesc: 60 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0a0a83d7
+                            urb MsgDesc: 61 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0a0a83e7
+                            urb MsgDesc: 62 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x0a0a83f7
+                            urb MsgDesc: 63 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x08088027
+                            urb MsgDesc: 2 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x08088037
+                            urb MsgDesc: 3 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x08088047
+                            urb MsgDesc: 4 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x08088057
+                            urb MsgDesc: 5 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x08088067
+                            urb MsgDesc: 6 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x08088077
+                            urb MsgDesc: 7 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x08088087
+                            urb MsgDesc: 8 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x08088097
+                            urb MsgDesc: 9 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x080880a7
+                            urb MsgDesc: 10 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x080880b7
+                            urb MsgDesc: 11 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x080880c7
+                            urb MsgDesc: 12 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x080880d7
+                            urb MsgDesc: 13 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x080880e7
+                            urb MsgDesc: 14 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x080880f7
+                            urb MsgDesc: 15 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x08088107
+                            urb MsgDesc: 16 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x08088117
+                            urb MsgDesc: 17 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x08088127
+                            urb MsgDesc: 18 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x08088137
+                            urb MsgDesc: 19 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x08088147
+                            urb MsgDesc: 20 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x08088157
+                            urb MsgDesc: 21 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x08088167
+                            urb MsgDesc: 22 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x08088177
+                            urb MsgDesc: 23 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x08088187
+                            urb MsgDesc: 24 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x08088197
+                            urb MsgDesc: 25 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x080881a7
+                            urb MsgDesc: 26 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x080881b7
+                            urb MsgDesc: 27 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x080881c7
+                            urb MsgDesc: 28 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x080881d7
+                            urb MsgDesc: 29 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x080881e7
+                            urb MsgDesc: 30 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x080881f7
+                            urb MsgDesc: 31 SIMD8 write masked mlen 4 rlen 0 { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x02480018
+                            urb MsgDesc: 1 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x0c0a0207
+                            urb MsgDesc: 32 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080057
+                            urb MsgDesc: 5 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         g10<1>UW        g18<8,8,1>UD    0x084a8000
+                            sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04229001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 2 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x08449001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1H };
+send(16)        g32<1>UW        g44<8,8,1>UD    0x0865a001
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 6 { align1 1H };
+send(16)        null<1>UW       g5<8,8,1>UD     0x04008502
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(8)         g5<1>UW         g3<8,8,1>UD     0x02427001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g8<1>UW         g5<8,8,1>UD     0x04847001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         null<1>F        g119<8,8,1>F    0x92080007
+                            urb MsgDesc: 0 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         null<1>F        g126<8,8,1>UD   0x84080017
+                            urb MsgDesc: 1 SIMD8 write mlen 2 rlen 0        { align1 1Q EOT };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x0a4b1001
+                            sampler MsgDesc: gather4_po SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g16<1>UW        g7<8,8,1>UD     0x128d1001
+                            sampler MsgDesc: gather4_po SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         g38<1>UD        g1<8,8,1>UD     0x02180028
+                            urb MsgDesc: 2 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g40<1>UD        g1<8,8,1>UD     0x02180038
+                            urb MsgDesc: 3 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g42<1>UD        g1<8,8,1>UD     0x02180048
+                            urb MsgDesc: 4 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g44<1>UD        g1<8,8,1>UD     0x02180058
+                            urb MsgDesc: 5 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g46<1>UD        g1<8,8,1>UD     0x02180068
+                            urb MsgDesc: 6 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g48<1>UD        g1<8,8,1>UD     0x02180078
+                            urb MsgDesc: 7 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g50<1>UD        g1<8,8,1>UD     0x02180088
+                            urb MsgDesc: 8 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g52<1>UD        g1<8,8,1>UD     0x02180098
+                            urb MsgDesc: 9 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g54<1>UD        g1<8,8,1>UD     0x021800a8
+                            urb MsgDesc: 10 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g56<1>UD        g1<8,8,1>UD     0x021800b8
+                            urb MsgDesc: 11 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g58<1>UD        g1<8,8,1>UD     0x021800c8
+                            urb MsgDesc: 12 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g60<1>UD        g1<8,8,1>UD     0x021800d8
+                            urb MsgDesc: 13 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g62<1>UD        g1<8,8,1>UD     0x021800e8
+                            urb MsgDesc: 14 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g64<1>UD        g1<8,8,1>UD     0x021800f8
+                            urb MsgDesc: 15 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g66<1>UD        g1<8,8,1>UD     0x02180108
+                            urb MsgDesc: 16 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g68<1>UD        g1<8,8,1>UD     0x02180118
+                            urb MsgDesc: 17 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g70<1>UD        g1<8,8,1>UD     0x02180128
+                            urb MsgDesc: 18 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g72<1>UD        g1<8,8,1>UD     0x02180138
+                            urb MsgDesc: 19 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g74<1>UD        g1<8,8,1>UD     0x02180148
+                            urb MsgDesc: 20 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g76<1>UD        g1<8,8,1>UD     0x02180158
+                            urb MsgDesc: 21 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g78<1>UD        g1<8,8,1>UD     0x02180168
+                            urb MsgDesc: 22 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g80<1>UD        g1<8,8,1>UD     0x02180178
+                            urb MsgDesc: 23 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g82<1>UD        g1<8,8,1>UD     0x02180188
+                            urb MsgDesc: 24 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g84<1>UD        g1<8,8,1>UD     0x02180198
+                            urb MsgDesc: 25 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g86<1>UD        g1<8,8,1>UD     0x021801a8
+                            urb MsgDesc: 26 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g88<1>UD        g1<8,8,1>UD     0x021801b8
+                            urb MsgDesc: 27 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g90<1>UD        g1<8,8,1>UD     0x021801c8
+                            urb MsgDesc: 28 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g92<1>UD        g1<8,8,1>UD     0x021801d8
+                            urb MsgDesc: 29 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g94<1>UD        g1<8,8,1>UD     0x021801e8
+                            urb MsgDesc: 30 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g96<1>UD        g1<8,8,1>UD     0x021801f8
+                            urb MsgDesc: 31 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g98<1>UD        g1<8,8,1>UD     0x02180208
+                            urb MsgDesc: 32 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0c0a0027
+                            urb MsgDesc: 2 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>UW       g126<0,1,0>UD   0x040a02fd
+                            data MsgDesc: ( DC OWORD block write, 253, 2) mlen 2 rlen 0 { align1 1Q };
+send(8)         g115<1>UW       g115<0,1,0>UD   0x021802fd
+                            data MsgDesc: ( DC OWORD block read, 253, 2) mlen 1 rlen 1 { align1 WE_all 1Q };
+send(8)         null<1>F        g25<8,8,1>F     0x12080057
+                            urb MsgDesc: 5 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>F     0x12080077
+                            urb MsgDesc: 7 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g43<8,8,1>F     0x12080097
+                            urb MsgDesc: 9 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g52<8,8,1>F     0x120800b7
+                            urb MsgDesc: 11 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g61<8,8,1>F     0x120800d7
+                            urb MsgDesc: 13 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g70<8,8,1>F     0x120800f7
+                            urb MsgDesc: 15 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g2<8,8,1>F      0x12080117
+                            urb MsgDesc: 17 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g2<8,8,1>F      0x12080137
+                            urb MsgDesc: 19 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g2<8,8,1>F      0x12080157
+                            urb MsgDesc: 21 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g79<8,8,1>F     0x12080177
+                            urb MsgDesc: 23 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g88<8,8,1>F     0x12080197
+                            urb MsgDesc: 25 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g97<8,8,1>F     0x120801b7
+                            urb MsgDesc: 27 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g106<8,8,1>F    0x120801d7
+                            urb MsgDesc: 29 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g117<8,8,1>F    0x920801f7
+                            urb MsgDesc: 31 SIMD8 write mlen 9 rlen 0       { align1 1Q EOT };
+send(8)         g124<1>UW       g11<8,8,1>UD    0x02229001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 2 { align1 1Q };
+send(16)        g120<1>UW       g11<8,8,1>UD    0x04449001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1H };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x08427000
+                            sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        null<1>UW       g40<8,8,1>UD    0x04008501
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(8)         null<1>F        g127<8,8,1>UD   0x82080007
+                            urb MsgDesc: 0 SIMD8 write mlen 1 rlen 0        { align1 1Q EOT };
+send(8)         g124<1>UW       g9<8,8,1>UD     0x0a4a8000
+                            sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g23<8,8,1>UD    0x0633a001
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q };
+send(16)        g4<1>UW         g12<8,8,1>UD    0x0c65a001
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H };
+send(8)         g2<1>UW         g16<8,8,1>UD    0x0e434001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 2Q };
+(+f1.0) send(8) null<1>UW       g4<8,8,1>UD     0x02009501
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 0 { align1 1Q };
+send(8)         g6<1>UW         g9<8,8,1>UD     0x08434001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         null<1>F        g102<8,8,1>F    0x120801f7
+                            urb MsgDesc: 31 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g121<8,8,1>F    0x8a080217
+                            urb MsgDesc: 33 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(16)        null<1>UW       g3<0,1,0>UD     0x02008004
+                            gateway MsgDesc: (barrier msg) mlen 1 rlen 0    { align1 WE_all 1H };
+send(16)        g3<1>UW         g14<8,8,1>UD    0x04205efe
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 254, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+send(8)         null<1>F        g30<8,8,1>F     0x140a0027
+                            urb MsgDesc: 2 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>F     0x0c0a0047
+                            urb MsgDesc: 4 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g126<8,8,1>UD   0x84080007
+                            urb MsgDesc: 0 SIMD8 write mlen 2 rlen 0        { align1 1Q EOT };
+send(8)         g5<1>UW         g11<8,8,1>UD    0x04415001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g3<8,8,1>UD     0x04416001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 2 rlen 4 { align1 2Q };
+send(8)         g13<1>UD        g3<8,8,1>UD     0x02480038
+                            urb MsgDesc: 3 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         null<1>F        g7<8,8,1>F      0x140a0037
+                            urb MsgDesc: 3 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         g15<1>UD        g2<8,8,1>UD     0x02280038
+                            urb MsgDesc: 3 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080037
+                            urb MsgDesc: 3 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         null<1>F        g8<8,8,1>F      0x140a0007
+                            urb MsgDesc: 0 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g118<8,8,1>F    0x940a0007
+                            urb MsgDesc: 0 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT };
+send(8)         g124<1>UW       g12<8,8,1>UD    a0<0,1,0>UD     0x00000200
+                            sampler MsgDesc: indirect                       { align1 1Q };
+send(8)         g10<1>UD        g2<8,8,1>UD     0x02480048
+                            urb MsgDesc: 4 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         g6<1>UD         g2<8,8,1>UD     0x02480088
+                            urb MsgDesc: 8 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         g14<1>UD        g2<8,8,1>UD     0x02480058
+                            urb MsgDesc: 5 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         g11<1>UD        g2<8,8,1>UD     0x024800a8
+                            urb MsgDesc: 10 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g18<1>UD        g2<8,8,1>UD     0x02480068
+                            urb MsgDesc: 6 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         g16<1>UD        g2<8,8,1>UD     0x023800c8
+                            urb MsgDesc: 12 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g2<8,8,1>UD     0x02480078
+                            urb MsgDesc: 7 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x024800b8
+                            urb MsgDesc: 11 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g7<1>UD         g2<8,8,1>UD     0x02480098
+                            urb MsgDesc: 9 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x920800b7
+                            urb MsgDesc: 11 SIMD8 write mlen 9 rlen 0       { align1 1Q EOT };
+send(8)         g6<1>UW         g8<8,8,1>UD     0x084b0000
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g7<1>UW         g0<8,8,1>UD     0x02200008
+                            pixel interp MsgDesc: (persp, per_message_offset, 0x08) mlen 1 rlen 2 { align1 1Q };
+send(16)        g9<1>UW         g0<8,8,1>UD     0x02410008
+                            pixel interp MsgDesc: (persp, per_message_offset, 0x08) mlen 1 rlen 4 { align1 1H };
+send(8)         g2<1>UW         g11<8,8,1>UD    0x0443d001
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g9<8,8,1>UD     0x0843e001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g15<8,8,1>UD    0x0885d001
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g43<1>UW        g11<8,8,1>UD    0x1085e001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x0a4b1000
+                            sampler MsgDesc: gather4_po SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g74<1>UD        g2<8,8,1>UD     0x02280028
+                            urb MsgDesc: 2 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         g7<1>UD         g2<8,8,1>UD     0x02380028
+                            urb MsgDesc: 2 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         g15<1>UD        g2<8,8,1>UD     0x02380038
+                            urb MsgDesc: 3 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         g124<1>UW       g3<8,8,1>UD     0x0843e000
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g3<8,8,1>UD     0x0443d000
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g19<8,8,1>UD    0x0a4a8001
+                            sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g16<8,8,1>UD    0x128c8001
+                            sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         null<1>F        g2<8,8,1>F      0x0c0a0057
+                            urb MsgDesc: 5 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g9<8,8,1>UD     0x04080027
+                            urb MsgDesc: 2 SIMD8 write mlen 2 rlen 0        { align1 1Q };
+send(8)         g6<1>UW         g7<8,8,1>UD     0x08134001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q };
+send(8)         g7<1>UW         g11<8,8,1>UD    0x08134102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q };
+send(8)         g13<1>UW        g17<8,8,1>UD    0x021ab000
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align1 1Q };
+send(8)         null<1>F        g50<8,8,1>F     0x140a0057
+                            urb MsgDesc: 5 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g60<8,8,1>F     0x140a0077
+                            urb MsgDesc: 7 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g70<8,8,1>F     0x0c0a0097
+                            urb MsgDesc: 9 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g122<8,8,1>F    0x8c0a0097
+                            urb MsgDesc: 9 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x0a4b0000
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g5<1>UW         g6<8,8,1>UD     0x061a3001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q };
+send(8)         g6<1>UW         g9<8,8,1>UD     0x061a3102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 1 { align1 1Q };
+send(16)        g9<1>UW         g11<8,8,1>UD    0x0a2c3001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 2 { align1 1H };
+send(16)        g11<1>UW        g2<8,8,1>UD     0x0a2c3102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 5 rlen 2 { align1 1H };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080077
+                            urb MsgDesc: 7 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         null<1>F        g30<8,8,1>UD    0x0c0a0067
+                            urb MsgDesc: 6 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0c0a0077
+                            urb MsgDesc: 7 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g42<8,8,1>UD    0x0c0a0087
+                            urb MsgDesc: 8 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06420102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0c840102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x04420102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06420304
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08840102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0c840304
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 6 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x04420304
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06420708
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08840304
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0c840708
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 6 rlen 8 { align1 1H };
+send(8)         g3<1>UW         g11<8,8,1>UD    0x0a43c001
+                            sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g16<1>UW        g5<8,8,1>UD     0x1485c001
+                            sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H };
+send(16)        g4<1>UD         g13<0,1,0>UD    0x02280301
+                            const MsgDesc: (1, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x0443a001
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0885a001
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g12<1>UW        g12<8,8,1>UD    0x06125001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q };
+send(8)         g13<1>UW        g15<8,8,1>UD    0x06125102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 1 { align1 1Q };
+send(16)        g20<1>UW        g22<8,8,1>UD    0x0c245001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H };
+send(16)        g22<1>UW        g28<8,8,1>UD    0x0c245102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 2 { align1 1H };
+send(8)         g38<1>UD        g2<8,8,1>UD     0x024800c8
+                            urb MsgDesc: 12 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g39<1>UD        g2<8,8,1>UD     0x024800d8
+                            urb MsgDesc: 13 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g40<1>UD        g2<8,8,1>UD     0x024800e8
+                            urb MsgDesc: 14 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g41<1>UD        g2<8,8,1>UD     0x024800f8
+                            urb MsgDesc: 15 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g42<1>UD        g2<8,8,1>UD     0x02480108
+                            urb MsgDesc: 16 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g43<1>UD        g2<8,8,1>UD     0x02480118
+                            urb MsgDesc: 17 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g44<1>UD        g2<8,8,1>UD     0x02480128
+                            urb MsgDesc: 18 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g45<1>UD        g2<8,8,1>UD     0x02480138
+                            urb MsgDesc: 19 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g46<1>UD        g2<8,8,1>UD     0x02480148
+                            urb MsgDesc: 20 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g47<1>UD        g2<8,8,1>UD     0x02480158
+                            urb MsgDesc: 21 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g48<1>UD        g2<8,8,1>UD     0x02480168
+                            urb MsgDesc: 22 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g49<1>UD        g2<8,8,1>UD     0x02480178
+                            urb MsgDesc: 23 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g50<1>UD        g2<8,8,1>UD     0x02480188
+                            urb MsgDesc: 24 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g51<1>UD        g2<8,8,1>UD     0x02480198
+                            urb MsgDesc: 25 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g52<1>UD        g2<8,8,1>UD     0x024801a8
+                            urb MsgDesc: 26 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g53<1>UD        g2<8,8,1>UD     0x024801b8
+                            urb MsgDesc: 27 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g54<1>UD        g2<8,8,1>UD     0x024801c8
+                            urb MsgDesc: 28 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g55<1>UD        g2<8,8,1>UD     0x024801d8
+                            urb MsgDesc: 29 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g56<1>UD        g2<8,8,1>UD     0x024801e8
+                            urb MsgDesc: 30 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g57<1>UD        g2<8,8,1>UD     0x024801f8
+                            urb MsgDesc: 31 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x080a8027
+                            urb MsgDesc: 2 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g8<8,8,1>UD     0x0a0a8027
+                            urb MsgDesc: 2 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x0e424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x0212a000
+                            sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align1 1Q };
+send(8)         g8<1>UD         g14<8,8,1>UD    0x044a0128
+                            urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g22<1>UD        g16<8,8,1>UD    0x044a0028
+                            urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x0a080017
+                            urb MsgDesc: 1 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g7<8,8,1>F      0x0a080057
+                            urb MsgDesc: 5 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         g4<1>UW         g2<8,8,1>UD     0x02406001
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 1Q };
+send(16)        g5<1>UW         g2<8,8,1>UD     0x04805001
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 2 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g13<8,8,1>UD    0x084b0001
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x0e8d0001
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H };
+send(8)         g10<1>UW        g10<8,8,1>UD    0x0e134001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 1 { align1 1Q };
+send(8)         g11<1>UW        g17<8,8,1>UD    0x0e134102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 7 rlen 1 { align1 1Q };
+send(8)         g14<1>UW        g10<8,8,1>UD    0x064a8202
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x084a8101
+                            sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(8)         g5<1>UW         g6<8,8,1>UD     0x021ab001
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 1 { align1 1Q };
+send(16)        g6<1>UW         g3<8,8,1>UD     0x022cb001
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 1 Sampler = 0 mlen 1 rlen 2 { align1 1H };
+send(8)         null<1>F        g122<8,8,1>F    0x8c0a0037
+                            urb MsgDesc: 3 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         null<1>F        g10<8,8,1>F     0x12080027
+                            urb MsgDesc: 2 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080047
+                            urb MsgDesc: 4 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         g14<1>UW        g2<8,8,1>UD     0x04438000
+                            sampler MsgDesc: sample_lz SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g61<1>UD        g107<8,8,1>UD   0x02380048
+                            urb MsgDesc: 4 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         g64<1>UD        g113<8,8,1>UD   0x02380058
+                            urb MsgDesc: 5 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080047
+                            urb MsgDesc: 4 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         g5<1>UW         g4<8,8,1>UD     0x06415001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x06416001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 3 rlen 4 { align1 2Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080077
+                            urb MsgDesc: 7 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         g12<1>UD        g8<4,4,1>UD     0x044a0038
+                            urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g21<1>UD        g8<4,4,1>UD     0x044a0048
+                            urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0c0a00a7
+                            urb MsgDesc: 10 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(16)        g1<1>UW         g9<8,8,1>UD     0x08858001
+                            sampler MsgDesc: sample_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         null<1>F        g56<8,8,1>F     0x140a0097
+                            urb MsgDesc: 9 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g76<8,8,1>F     0x0c0a00b7
+                            urb MsgDesc: 11 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g122<8,8,1>F    0x8c0a00b7
+                            urb MsgDesc: 11 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g4<1>UW         g3<8,8,1>UD     0x0232a001
+                            sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 3 { align1 1Q };
+send(16)        g8<1>UW         g3<8,8,1>UD     0x0464a001
+                            sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 6 { align1 1H };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a080007
+                            urb MsgDesc: 0 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         g126<1>UW       g10<8,8,1>UD    0x08123001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q };
+send(16)        g124<1>UW       g8<8,8,1>UD     0x10243001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H };
+send(8)         g12<1>UW        g12<8,8,1>UD    0x06126001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q };
+send(8)         g13<1>UW        g15<8,8,1>UD    0x06126102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 1 { align1 1Q };
+send(16)        g20<1>UW        g22<8,8,1>UD    0x0c246001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H };
+send(16)        g22<1>UW        g28<8,8,1>UD    0x0c246102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 2 { align1 1H };
+send(8)         g4<1>UW         g0<8,8,1>UD     0x02201000
+                            pixel interp MsgDesc: (persp, sample_position, 0x00) mlen 1 rlen 2 { align1 1Q };
+send(16)        g6<1>UW         g0<8,8,1>UD     0x02411000
+                            pixel interp MsgDesc: (persp, sample_position, 0x00) mlen 1 rlen 4 { align1 1H };
+send(8)         g124<1>UW       g19<8,8,1>UD    0x0a4b0001
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x128d0001
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g15<8,8,1>UD    0x06422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g14<1>UW        g8<8,8,1>UD     0x0c842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        g118<8,8,1>F    0x940a0037
+                            urb MsgDesc: 3 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT };
+send(8)         g4<1>UW         g5<8,8,1>UD     0x0212a001
+                            sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 1 { align1 1Q };
+send(16)        g4<1>UW         g6<8,8,1>UD     0x0424a001
+                            sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 2 { align1 1H };
+send(8)         g8<1>UD         g15<8,8,1>UD    0x042a0138
+                            urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g10<1>UD        g15<8,8,1>UD    0x042a0338
+                            urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g12<1>UD        g15<8,8,1>UD    0x042a0538
+                            urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g14<1>UD        g15<8,8,1>UD    0x042a0738
+                            urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g8<1>UD         g15<8,8,1>UD    0x042a0038
+                            urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g10<1>UD        g15<8,8,1>UD    0x042a0238
+                            urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g12<1>UD        g15<8,8,1>UD    0x042a0438
+                            urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g14<1>UD        g15<8,8,1>UD    0x042a0638
+                            urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g35<8,8,1>UD    0x02480228
+                            urb MsgDesc: 34 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g8<1>UD         g35<8,8,1>UD    0x02480428
+                            urb MsgDesc: 66 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g35<8,8,1>UD    0x02480628
+                            urb MsgDesc: 98 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0a0a8037
+                            urb MsgDesc: 3 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x0a0a8047
+                            urb MsgDesc: 4 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0a0a8057
+                            urb MsgDesc: 5 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x0a0a8067
+                            urb MsgDesc: 6 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x0a0a8077
+                            urb MsgDesc: 7 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x0a0a8087
+                            urb MsgDesc: 8 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0a0a8097
+                            urb MsgDesc: 9 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0a0a80a7
+                            urb MsgDesc: 10 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0a0a80b7
+                            urb MsgDesc: 11 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0a0a80c7
+                            urb MsgDesc: 12 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0a0a80d7
+                            urb MsgDesc: 13 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0a0a80e7
+                            urb MsgDesc: 14 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0a0a80f7
+                            urb MsgDesc: 15 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0a0a8107
+                            urb MsgDesc: 16 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0a0a8117
+                            urb MsgDesc: 17 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0a0a8127
+                            urb MsgDesc: 18 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0a0a8137
+                            urb MsgDesc: 19 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0a0a8147
+                            urb MsgDesc: 20 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0a0a8157
+                            urb MsgDesc: 21 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0a0a8167
+                            urb MsgDesc: 22 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0a0a8177
+                            urb MsgDesc: 23 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0a0a8187
+                            urb MsgDesc: 24 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0a0a8197
+                            urb MsgDesc: 25 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0a0a81a7
+                            urb MsgDesc: 26 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0a0a81b7
+                            urb MsgDesc: 27 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0a0a81c7
+                            urb MsgDesc: 28 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0a0a81d7
+                            urb MsgDesc: 29 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0a0a81e7
+                            urb MsgDesc: 30 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0a0a81f7
+                            urb MsgDesc: 31 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0a0a8207
+                            urb MsgDesc: 32 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g122<8,8,1>F    0x8c0a0027
+                            urb MsgDesc: 2 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x06424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x06229001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 2 { align1 1Q };
+send(16)        g120<1>UW       g12<8,8,1>UD    0x0c449001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1H };
+send(8)         g5<1>UW         g19<8,8,1>UD    0x0443a102
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(16)        g15<1>UW        g11<8,8,1>UD    0x0885a102
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g12<8,8,1>UD    0x0a43c000
+                            sampler MsgDesc: ld2dms_w SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g4<1>UW         g5<8,8,1>UD     0x04120001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q };
+send(16)        g4<1>UW         g7<8,8,1>UD     0x08240001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H };
+send(8)         null<1>F        g118<8,8,1>F    0x940a0027
+                            urb MsgDesc: 2 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT };
+send(8)         null<1>F        g2<8,8,1>F      0x12080067
+                            urb MsgDesc: 6 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080087
+                            urb MsgDesc: 8 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         g21<1>UD        g2<8,8,1>UD     0x02380068
+                            urb MsgDesc: 6 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         g35<1>UD        g2<8,8,1>UD     0x02380088
+                            urb MsgDesc: 8 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         null<1>F        g5<8,8,1>F      0x140a0067
+                            urb MsgDesc: 6 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g118<8,8,1>F    0x940a0067
+                            urb MsgDesc: 6 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT };
+send(8)         g2<1>UW         g8<8,8,1>UD     0x04220001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g14<8,8,1>UD    0x08440001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1H };
+send(8)         null<1>F        g123<8,8,1>F    0x8a0800d7
+                            urb MsgDesc: 13 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(8)         g22<1>UW        g14<8,8,1>UD    0x064a8405
+                            sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x084a8102
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g10<8,8,1>UD    0x084a8203
+                            sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g26<8,8,1>UD    0x0a4a8304
+                            sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 3 mlen 5 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g43<8,8,1>UD    0x0a8c8405
+                            sampler MsgDesc: gather4 SIMD16 Surface = 5 Sampler = 4 mlen 5 rlen 8 { align1 1H };
+send(16)        g43<1>UW        g7<8,8,1>UD     0x0e8c8102
+                            sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g51<8,8,1>UD    0x0e8c8203
+                            sampler MsgDesc: gather4 SIMD16 Surface = 3 Sampler = 2 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g26<8,8,1>UD    0x128c8304
+                            sampler MsgDesc: gather4 SIMD16 Surface = 4 Sampler = 3 mlen 9 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g15<8,8,1>UD    0x0e4a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(16)        null<1>UW       g2<8,8,1>UD     0x04008601
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, dec) mlen 2 rlen 0 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x08422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x10842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g7<8,8,1>UD     0x08126001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q };
+send(8)         g7<1>UW         g11<8,8,1>UD    0x08126102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q };
+send(16)        g10<1>UW        g12<8,8,1>UD    0x10246001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H };
+send(16)        g12<1>UW        g20<8,8,1>UD    0x10246102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 2 { align1 1H };
+send(8)         null<1>F        g18<8,8,1>UD    0x0e0a8047
+                            urb MsgDesc: 4 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q };
+send(8)         g9<1>UD         g34<8,8,1>UD    0x02480218
+                            urb MsgDesc: 33 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g17<1>UD        g34<8,8,1>UD    0x02480238
+                            urb MsgDesc: 35 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g2<1>UD         g6<8,8,1>UD     0x041a0128
+                            urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g22<1>UD        g8<8,8,1>UD     0x041a0028
+                            urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         null<1>F        g2<8,8,1>UD     0x06088027
+                            urb MsgDesc: 2 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x06088037
+                            urb MsgDesc: 3 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x06088047
+                            urb MsgDesc: 4 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x06088057
+                            urb MsgDesc: 5 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x06088067
+                            urb MsgDesc: 6 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x06088077
+                            urb MsgDesc: 7 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x06088087
+                            urb MsgDesc: 8 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x06088097
+                            urb MsgDesc: 9 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x060880a7
+                            urb MsgDesc: 10 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x060880b7
+                            urb MsgDesc: 11 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x060880c7
+                            urb MsgDesc: 12 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x060880d7
+                            urb MsgDesc: 13 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x060880e7
+                            urb MsgDesc: 14 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x060880f7
+                            urb MsgDesc: 15 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x06088107
+                            urb MsgDesc: 16 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x06088117
+                            urb MsgDesc: 17 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x06088127
+                            urb MsgDesc: 18 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x06088137
+                            urb MsgDesc: 19 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x06088147
+                            urb MsgDesc: 20 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x06088157
+                            urb MsgDesc: 21 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x06088167
+                            urb MsgDesc: 22 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x06088177
+                            urb MsgDesc: 23 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x06088187
+                            urb MsgDesc: 24 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x06088197
+                            urb MsgDesc: 25 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x060881a7
+                            urb MsgDesc: 26 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x060881b7
+                            urb MsgDesc: 27 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x060881c7
+                            urb MsgDesc: 28 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x060881d7
+                            urb MsgDesc: 29 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x060881e7
+                            urb MsgDesc: 30 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x060881f7
+                            urb MsgDesc: 31 SIMD8 write masked mlen 3 rlen 0 { align1 1Q };
+send(8)         g3<1>UW         g10<8,8,1>UD    0x0242a001
+                            sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g3<1>UW         g11<8,8,1>UD    0x0484a001
+                            sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x06320001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q };
+send(16)        g120<1>UW       g8<8,8,1>UD     0x0c640001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x02406000
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 1Q };
+send(8)         g127<1>UW       g6<8,8,1>UD     0x06120001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q };
+send(16)        g126<1>UW       g8<8,8,1>UD     0x0c240001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H };
+send(8)         g23<1>UW        g2<8,8,1>UD     0x04115e01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 2 rlen 1 { align1 1Q };
+send(8)         g39<1>UW        g45<8,8,1>UD    0x04116e01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 2 rlen 1 { align1 2Q };
+(+f1.0) send(8) null<1>UW       g2<8,8,1>UD     0x04018501
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, inc) mlen 2 rlen 0 { align1 1Q };
+(+f1.0) send(8) null<1>UW       g42<8,8,1>UD    0x04019501
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, inc) mlen 2 rlen 0 { align1 2Q };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x04423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g8<8,8,1>UD     0x04423102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x08843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x08843102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(8)         g6<1>UD         g22<8,8,1>UD    0x044a0318
+                            urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g10<1>UD        g22<8,8,1>UD    0x044a0518
+                            urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g14<1>UD        g22<8,8,1>UD    0x044a0718
+                            urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g18<1>UD        g22<8,8,1>UD    0x044a0918
+                            urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g13<1>UD        g29<8,8,1>UD    0x044a0218
+                            urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g17<1>UD        g29<8,8,1>UD    0x044a0418
+                            urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g21<1>UD        g29<8,8,1>UD    0x044a0618
+                            urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g25<1>UD        g29<8,8,1>UD    0x044a0818
+                            urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0c0a0217
+                            urb MsgDesc: 33 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0c0a0227
+                            urb MsgDesc: 34 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x0c0a0237
+                            urb MsgDesc: 35 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x0c0a0247
+                            urb MsgDesc: 36 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x0c0a0257
+                            urb MsgDesc: 37 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0c0a0267
+                            urb MsgDesc: 38 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0c0a0277
+                            urb MsgDesc: 39 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0c0a0287
+                            urb MsgDesc: 40 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0c0a0297
+                            urb MsgDesc: 41 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0c0a02a7
+                            urb MsgDesc: 42 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0c0a02b7
+                            urb MsgDesc: 43 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0c0a02c7
+                            urb MsgDesc: 44 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0c0a02d7
+                            urb MsgDesc: 45 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0c0a02e7
+                            urb MsgDesc: 46 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0c0a02f7
+                            urb MsgDesc: 47 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0c0a0307
+                            urb MsgDesc: 48 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0c0a0317
+                            urb MsgDesc: 49 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0c0a0327
+                            urb MsgDesc: 50 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0c0a0337
+                            urb MsgDesc: 51 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0c0a0347
+                            urb MsgDesc: 52 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0c0a0357
+                            urb MsgDesc: 53 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0c0a0367
+                            urb MsgDesc: 54 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0c0a0377
+                            urb MsgDesc: 55 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0c0a0387
+                            urb MsgDesc: 56 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0c0a0397
+                            urb MsgDesc: 57 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0c0a03a7
+                            urb MsgDesc: 58 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0c0a03b7
+                            urb MsgDesc: 59 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0c0a03c7
+                            urb MsgDesc: 60 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0c0a03d7
+                            urb MsgDesc: 61 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x0c0a03e7
+                            urb MsgDesc: 62 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g41<8,8,1>UD    0x0c0a03f7
+                            urb MsgDesc: 63 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0a080067
+                            urb MsgDesc: 6 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0a080077
+                            urb MsgDesc: 7 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0a080087
+                            urb MsgDesc: 8 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0a080097
+                            urb MsgDesc: 9 SIMD8 write mlen 5 rlen 0        { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0a0800a7
+                            urb MsgDesc: 10 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0a0800b7
+                            urb MsgDesc: 11 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0a0800c7
+                            urb MsgDesc: 12 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0a0800d7
+                            urb MsgDesc: 13 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0a0800e7
+                            urb MsgDesc: 14 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0a0800f7
+                            urb MsgDesc: 15 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0a080107
+                            urb MsgDesc: 16 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0a080117
+                            urb MsgDesc: 17 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0a080127
+                            urb MsgDesc: 18 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0a080137
+                            urb MsgDesc: 19 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0a080147
+                            urb MsgDesc: 20 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0a080157
+                            urb MsgDesc: 21 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0a080167
+                            urb MsgDesc: 22 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0a080177
+                            urb MsgDesc: 23 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0a080187
+                            urb MsgDesc: 24 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0a080197
+                            urb MsgDesc: 25 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0a0801a7
+                            urb MsgDesc: 26 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0a0801b7
+                            urb MsgDesc: 27 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0a0801c7
+                            urb MsgDesc: 28 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0a0801d7
+                            urb MsgDesc: 29 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x0a0801e7
+                            urb MsgDesc: 30 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         null<1>F        g41<8,8,1>UD    0x0a0801f7
+                            urb MsgDesc: 31 SIMD8 write mlen 5 rlen 0       { align1 1Q };
+send(8)         g13<1>UW        g2<8,8,1>UD     0x06123001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q };
+send(8)         g14<1>UW        g5<8,8,1>UD     0x06123102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 1 { align1 1Q };
+send(16)        g22<1>UW        g2<8,8,1>UD     0x0c243001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H };
+send(16)        g24<1>UW        g16<8,8,1>UD    0x0c243102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 2 { align1 1H };
+send(8)         g5<1>UW         g15<8,8,1>UD    0x04420203
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g27<8,8,1>UD    0x08840203
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 8 { align1 1H };
+send(16)        g4<1>UW         g17<8,8,1>UD    0x0420a503
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 3, SIMD16, inc) mlen 2 rlen 2 { align1 1H };
+send(16)        null<1>UW       g18<8,8,1>UD    0x04008504
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 4, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(16)        g11<1>UW        g19<8,8,1>UD    0x0420a602
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, dec) mlen 2 rlen 2 { align1 1H };
+send(16)        null<1>UW       g20<8,8,1>UD    0x04008505
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 5, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(16)        g16<1>UW        g21<8,8,1>UD    0x04205e01
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+send(16)        null<1>UW       g22<8,8,1>UD    0x04008506
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 6, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(8)         g26<1>UW        g26<8,8,1>UD    0x0242a203
+                            sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 1Q };
+send(8)         g30<1>UW        g30<8,8,1>UD    0x0242a304
+                            sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 4 { align1 1Q };
+send(8)         g34<1>UW        g34<8,8,1>UD    0x0242a405
+                            sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 4 { align1 1Q };
+send(8)         g38<1>UW        g38<8,8,1>UD    0x0242a506
+                            sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g25<8,8,1>UD    0x0242a102
+                            sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q };
+send(8)         g42<1>UW        g42<8,8,1>UD    0x0242a607
+                            sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 6 mlen 1 rlen 4 { align1 1Q };
+send(8)         g46<1>UW        g46<8,8,1>UD    0x0242a708
+                            sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 7 mlen 1 rlen 4 { align1 1Q };
+send(8)         g50<1>UW        g50<8,8,1>UD    0x0242a809
+                            sampler MsgDesc: resinfo SIMD8 Surface = 9 Sampler = 8 mlen 1 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g54<8,8,1>UD    0x0242a90a
+                            sampler MsgDesc: resinfo SIMD8 Surface = 10 Sampler = 9 mlen 1 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g55<8,8,1>UD    0x0242aa0b
+                            sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 10 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g56<8,8,1>UD    0x0242ab0c
+                            sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 11 mlen 1 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g57<8,8,1>UD    0x0242ac0d
+                            sampler MsgDesc: resinfo SIMD8 Surface = 13 Sampler = 12 mlen 1 rlen 4 { align1 1Q };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0484a102
+                            sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H };
+send(16)        g82<1>UW        g110<8,8,1>UD   0x0484aa0b
+                            sampler MsgDesc: resinfo SIMD16 Surface = 11 Sampler = 10 mlen 2 rlen 8 { align1 1H };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x0484a203
+                            sampler MsgDesc: resinfo SIMD16 Surface = 3 Sampler = 2 mlen 2 rlen 8 { align1 1H };
+send(16)        g90<1>UW        g112<8,8,1>UD   0x0484ab0c
+                            sampler MsgDesc: resinfo SIMD16 Surface = 12 Sampler = 11 mlen 2 rlen 8 { align1 1H };
+send(16)        g98<1>UW        g106<8,8,1>UD   0x0484ac0d
+                            sampler MsgDesc: resinfo SIMD16 Surface = 13 Sampler = 12 mlen 2 rlen 8 { align1 1H };
+send(16)        g26<1>UW        g34<8,8,1>UD    0x0484a304
+                            sampler MsgDesc: resinfo SIMD16 Surface = 4 Sampler = 3 mlen 2 rlen 8 { align1 1H };
+send(16)        g34<1>UW        g42<8,8,1>UD    0x0484a405
+                            sampler MsgDesc: resinfo SIMD16 Surface = 5 Sampler = 4 mlen 2 rlen 8 { align1 1H };
+send(16)        g42<1>UW        g50<8,8,1>UD    0x0484a506
+                            sampler MsgDesc: resinfo SIMD16 Surface = 6 Sampler = 5 mlen 2 rlen 8 { align1 1H };
+send(16)        g50<1>UW        g58<8,8,1>UD    0x0484a607
+                            sampler MsgDesc: resinfo SIMD16 Surface = 7 Sampler = 6 mlen 2 rlen 8 { align1 1H };
+send(16)        g58<1>UW        g66<8,8,1>UD    0x0484a708
+                            sampler MsgDesc: resinfo SIMD16 Surface = 8 Sampler = 7 mlen 2 rlen 8 { align1 1H };
+send(16)        g66<1>UW        g74<8,8,1>UD    0x0484a809
+                            sampler MsgDesc: resinfo SIMD16 Surface = 9 Sampler = 8 mlen 2 rlen 8 { align1 1H };
+send(16)        g74<1>UW        g108<8,8,1>UD   0x0484a90a
+                            sampler MsgDesc: resinfo SIMD16 Surface = 10 Sampler = 9 mlen 2 rlen 8 { align1 1H };
+send(16)        null<1>UW       g3<8,8,1>UD     0x040085fe
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(8)         null<1>F        g119<8,8,1>F    0x92080067
+                            urb MsgDesc: 6 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         g6<1>UW         g20<8,8,1>UD    0x12424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 4 { align1 1Q };
+send(8)         g17<1>UW        g2<8,8,1>UD     0x0413a001
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q };
+send(16)        g2<1>UW         g7<8,8,1>UD     0x0825a001
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H };
+send(8)         g9<1>UW         g17<8,8,1>UD    0x06422000
+                            sampler MsgDesc: sample_l SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        null<1>UW       g123<0,1,0>UD   0x060a03fd
+                            data MsgDesc: ( DC OWORD block write, 253, 3) mlen 3 rlen 0 { align1 1H };
+send(16)        g114<1>UW       g114<0,1,0>UD   0x022803fd
+                            data MsgDesc: ( DC OWORD block read, 253, 3) mlen 1 rlen 2 { align1 WE_all 1H };
+send(8)         null<1>F        g12<8,8,1>UD    0x0c0a0127
+                            urb MsgDesc: 18 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         g2<1>UW         g11<8,8,1>UD    0x04420405
+                            sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g12<8,8,1>UD    0x04420506
+                            sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x04420607
+                            sampler MsgDesc: sample SIMD8 Surface = 7 Sampler = 6 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g14<8,8,1>UD    0x04420708
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g15<8,8,1>UD    0x04420809
+                            sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 8 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g16<8,8,1>UD    0x0442090a
+                            sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 9 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g17<8,8,1>UD    0x04420a0b
+                            sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 10 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g18<8,8,1>UD    0x04420b0c
+                            sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 11 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g19<8,8,1>UD    0x04420c0d
+                            sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 12 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g20<8,8,1>UD    0x04420d0e
+                            sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 13 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g21<8,8,1>UD    0x04420e0f
+                            sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 14 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g22<8,8,1>UD    0x04420f10
+                            sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0011
+                            sampler MsgDesc: sample SIMD8 Surface = 17 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0112
+                            sampler MsgDesc: sample SIMD8 Surface = 18 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0213
+                            sampler MsgDesc: sample SIMD8 Surface = 19 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0314
+                            sampler MsgDesc: sample SIMD8 Surface = 20 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0415
+                            sampler MsgDesc: sample SIMD8 Surface = 21 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0516
+                            sampler MsgDesc: sample SIMD8 Surface = 22 Sampler = 5 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0617
+                            sampler MsgDesc: sample SIMD8 Surface = 23 Sampler = 6 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0718
+                            sampler MsgDesc: sample SIMD8 Surface = 24 Sampler = 7 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0819
+                            sampler MsgDesc: sample SIMD8 Surface = 25 Sampler = 8 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a091a
+                            sampler MsgDesc: sample SIMD8 Surface = 26 Sampler = 9 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0a1b
+                            sampler MsgDesc: sample SIMD8 Surface = 27 Sampler = 10 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0b1c
+                            sampler MsgDesc: sample SIMD8 Surface = 28 Sampler = 11 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0c1d
+                            sampler MsgDesc: sample SIMD8 Surface = 29 Sampler = 12 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0d1e
+                            sampler MsgDesc: sample SIMD8 Surface = 30 Sampler = 13 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g10<8,8,1>UD    0x064a0e1f
+                            sampler MsgDesc: sample SIMD8 Surface = 31 Sampler = 14 mlen 3 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x064a0f20
+                            sampler MsgDesc: sample SIMD8 Surface = 32 Sampler = 15 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g28<8,8,1>UD    0x08840405
+                            sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g29<8,8,1>UD    0x08840506
+                            sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g30<8,8,1>UD    0x08840607
+                            sampler MsgDesc: sample SIMD16 Surface = 7 Sampler = 6 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g31<8,8,1>UD    0x08840708
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g32<8,8,1>UD    0x08840809
+                            sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 8 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g33<8,8,1>UD    0x0884090a
+                            sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 9 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g34<8,8,1>UD    0x08840a0b
+                            sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 10 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g35<8,8,1>UD    0x08840b0c
+                            sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 11 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g36<8,8,1>UD    0x08840c0d
+                            sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 12 mlen 4 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g37<8,8,1>UD    0x08840d0e
+                            sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 13 mlen 4 rlen 8 { align1 1H };
+send(16)        g7<1>UW         g38<8,8,1>UD    0x08840e0f
+                            sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 14 mlen 4 rlen 8 { align1 1H };
+send(16)        g23<1>UW        g39<8,8,1>UD    0x08840f10
+                            sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 4 rlen 8 { align1 1H };
+send(16)        g17<1>UW        g2<8,8,1>UD     0x0a8c0011
+                            sampler MsgDesc: sample SIMD16 Surface = 17 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(16)        g29<1>UW        g7<8,8,1>UD     0x0a8c0112
+                            sampler MsgDesc: sample SIMD16 Surface = 18 Sampler = 1 mlen 5 rlen 8 { align1 1H };
+send(16)        g27<1>UW        g12<8,8,1>UD    0x0a8c0213
+                            sampler MsgDesc: sample SIMD16 Surface = 19 Sampler = 2 mlen 5 rlen 8 { align1 1H };
+send(16)        g32<1>UW        g17<8,8,1>UD    0x0a8c0314
+                            sampler MsgDesc: sample SIMD16 Surface = 20 Sampler = 3 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g22<8,8,1>UD    0x0a8c0415
+                            sampler MsgDesc: sample SIMD16 Surface = 21 Sampler = 4 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g27<8,8,1>UD    0x0a8c0516
+                            sampler MsgDesc: sample SIMD16 Surface = 22 Sampler = 5 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g32<8,8,1>UD    0x0a8c0617
+                            sampler MsgDesc: sample SIMD16 Surface = 23 Sampler = 6 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g37<8,8,1>UD    0x0a8c0718
+                            sampler MsgDesc: sample SIMD16 Surface = 24 Sampler = 7 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g42<8,8,1>UD    0x0a8c0819
+                            sampler MsgDesc: sample SIMD16 Surface = 25 Sampler = 8 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g47<8,8,1>UD    0x0a8c091a
+                            sampler MsgDesc: sample SIMD16 Surface = 26 Sampler = 9 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g52<8,8,1>UD    0x0a8c0a1b
+                            sampler MsgDesc: sample SIMD16 Surface = 27 Sampler = 10 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g57<8,8,1>UD    0x0a8c0b1c
+                            sampler MsgDesc: sample SIMD16 Surface = 28 Sampler = 11 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g62<8,8,1>UD    0x0a8c0c1d
+                            sampler MsgDesc: sample SIMD16 Surface = 29 Sampler = 12 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g67<8,8,1>UD    0x0a8c0d1e
+                            sampler MsgDesc: sample SIMD16 Surface = 30 Sampler = 13 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g72<8,8,1>UD    0x0a8c0e1f
+                            sampler MsgDesc: sample SIMD16 Surface = 31 Sampler = 14 mlen 5 rlen 8 { align1 1H };
+send(16)        g2<1>UW         g77<8,8,1>UD    0x0a8c0f20
+                            sampler MsgDesc: sample SIMD16 Surface = 32 Sampler = 15 mlen 5 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x02120102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 1 { align1 1Q };
+send(8)         g6<1>UW         g3<8,8,1>UD     0x02220102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 2 { align1 1Q };
+send(8)         g8<1>UW         g4<8,8,1>UD     0x02320102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 3 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x04240102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 2 { align1 1H };
+send(16)        g10<1>UW        g4<8,8,1>UD     0x04440102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1H };
+send(16)        g14<1>UW        g6<8,8,1>UD     0x04640102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 6 { align1 1H };
+send(8)         null<1>F        g8<8,8,1>UD     0x0c0a8027
+                            urb MsgDesc: 2 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>F     0x12080047
+                            urb MsgDesc: 4 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080087
+                            urb MsgDesc: 8 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         g5<1>UW         g10<8,8,1>UD    0x06420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g19<8,8,1>UD    0x0c840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(8)         g1<1>UW         g125<8,8,1>UD   0x02106e02
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(8)         g8<1>UW         g22<8,8,1>UD    0x02106efe
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 254, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080097
+                            urb MsgDesc: 9 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         g29<1>UW        g5<8,8,1>UD     0x0e4b2001
+                            sampler MsgDesc: gather4_po_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g68<1>UW        g72<8,8,1>UD    0x0212a102
+                            sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 1 { align1 1Q };
+send(8)         g67<1>UW        g5<8,8,1>UD     0x0a126001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q };
+send(8)         g69<1>UW        g10<8,8,1>UD    0x0a126102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q };
+send(16)        g36<1>UW        g40<8,8,1>UD    0x0424a102
+                            sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 2 { align1 1H };
+send(16)        g2<1>UW         g7<8,8,1>UD     0x14246001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 2 { align1 1H };
+send(16)        g37<1>UW        g17<8,8,1>UD    0x14246102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 2 { align1 1H };
+send(8)         g125<1>UW       g5<8,8,1>UD     0x04220102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 2 { align1 1Q };
+send(16)        g122<1>UW       g7<8,8,1>UD     0x08440102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1H };
+send(8)         null<1>F        g14<8,8,1>UD    0x0c0a8037
+                            urb MsgDesc: 3 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x0c0a8047
+                            urb MsgDesc: 4 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0c0a8057
+                            urb MsgDesc: 5 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         g6<1>UW         g7<8,8,1>UD     0x081a5001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q };
+send(8)         g7<1>UW         g11<8,8,1>UD    0x081a5102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q };
+send(16)        g10<1>UW        g12<8,8,1>UD    0x0e2c5001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 2 { align1 1H };
+send(16)        g12<1>UW        g19<8,8,1>UD    0x0e2c5102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 2 { align1 1H };
+send(8)         g5<1>UW         g6<8,8,1>UD     0x081a3001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q };
+send(8)         g6<1>UW         g10<8,8,1>UD    0x081a3102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q };
+send(16)        g9<1>UW         g11<8,8,1>UD    0x0e2c3001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 2 { align1 1H };
+send(16)        g11<1>UW        g18<8,8,1>UD    0x0e2c3102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 2 { align1 1H };
+send(8)         g5<1>UW         g7<8,8,1>UD     0x04320102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 3 { align1 1Q };
+send(16)        g8<1>UW         g14<8,8,1>UD    0x08640102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 6 { align1 1H };
+send(8)         g19<1>UW        g12<8,8,1>UD    0x04320003
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 3 { align1 1Q };
+send(16)        g34<1>UW        g41<8,8,1>UD    0x08640003
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 6 { align1 1H };
+send(8)         g11<1>UW        g2<8,8,1>UD     0x0443a008
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 8 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g15<1>UW        g2<8,8,1>UD     0x0443a109
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 9 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(8)         g19<1>UW        g2<8,8,1>UD     0x0443a20a
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 10 Sampler = 2 mlen 2 rlen 4 { align1 1Q };
+send(8)         g23<1>UW        g2<8,8,1>UD     0x0443a30b
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 11 Sampler = 3 mlen 2 rlen 4 { align1 1Q };
+send(8)         g27<1>UW        g2<8,8,1>UD     0x0443a40c
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 12 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
+send(8)         g31<1>UW        g2<8,8,1>UD     0x0443a50d
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 13 Sampler = 5 mlen 2 rlen 4 { align1 1Q };
+send(8)         g35<1>UW        g2<8,8,1>UD     0x0443a60e
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 14 Sampler = 6 mlen 2 rlen 4 { align1 1Q };
+send(8)         g39<1>UW        g2<8,8,1>UD     0x0443a70f
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 15 Sampler = 7 mlen 2 rlen 4 { align1 1Q };
+send(16)        g93<1>UW        g2<8,8,1>UD     0x0885a008
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 8 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g27<1>UW        g2<8,8,1>UD     0x0885a109
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 9 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(16)        g37<1>UW        g2<8,8,1>UD     0x0885a20a
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 10 Sampler = 2 mlen 4 rlen 8 { align1 1H };
+send(16)        g47<1>UW        g2<8,8,1>UD     0x0885a30b
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 11 Sampler = 3 mlen 4 rlen 8 { align1 1H };
+send(16)        g57<1>UW        g2<8,8,1>UD     0x0885a40c
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 12 Sampler = 4 mlen 4 rlen 8 { align1 1H };
+send(16)        g67<1>UW        g2<8,8,1>UD     0x0885a50d
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 13 Sampler = 5 mlen 4 rlen 8 { align1 1H };
+send(16)        g85<1>UW        g2<8,8,1>UD     0x0885a60e
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 14 Sampler = 6 mlen 4 rlen 8 { align1 1H };
+send(16)        g77<1>UW        g2<8,8,1>UD     0x0885a70f
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 15 Sampler = 7 mlen 4 rlen 8 { align1 1H };
+send(16)        g83<1>UW        g86<8,8,1>UD    0x04205e00
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+send(8)         null<1>F        g122<8,8,1>F    0x8c0a0047
+                            urb MsgDesc: 4 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g14<1>UW        g11<8,8,1>UD    0x084b0202
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x0a4b0101
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(8)         null<1>F        g3<8,8,1>F      0x12080087
+                            urb MsgDesc: 8 SIMD8 write mlen 9 rlen 0        { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a0800a7
+                            urb MsgDesc: 10 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(8)         g6<1>UW         g7<8,8,1>UD     0x081a6001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q };
+send(8)         g7<1>UW         g11<8,8,1>UD    0x081a6102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q };
+send(16)        g10<1>UW        g12<8,8,1>UD    0x0e2c6001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 2 { align1 1H };
+send(16)        g12<1>UW        g19<8,8,1>UD    0x0e2c6102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 2 { align1 1H };
+send(8)         g31<1>UD        g28<8,8,1>UD    0x02380238
+                            urb MsgDesc: 35 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g34<1>UD        g28<8,8,1>UD    0x02380438
+                            urb MsgDesc: 67 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g37<1>UD        g28<8,8,1>UD    0x02380638
+                            urb MsgDesc: 99 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g28<8,8,1>UD    0x02380248
+                            urb MsgDesc: 36 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g28<8,8,1>UD    0x02380448
+                            urb MsgDesc: 68 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g28<1>UD        g28<8,8,1>UD    0x02380648
+                            urb MsgDesc: 100 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g22<1>UD        g29<8,8,1>UD    0x02380258
+                            urb MsgDesc: 37 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g29<8,8,1>UD    0x02380458
+                            urb MsgDesc: 69 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g28<1>UD        g29<8,8,1>UD    0x02380658
+                            urb MsgDesc: 101 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g22<1>UD        g30<8,8,1>UD    0x02380268
+                            urb MsgDesc: 38 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g30<8,8,1>UD    0x02380468
+                            urb MsgDesc: 70 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g28<1>UD        g30<8,8,1>UD    0x02380668
+                            urb MsgDesc: 102 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g22<1>UD        g31<8,8,1>UD    0x02380278
+                            urb MsgDesc: 39 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g31<8,8,1>UD    0x02380478
+                            urb MsgDesc: 71 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g28<1>UD        g31<8,8,1>UD    0x02380678
+                            urb MsgDesc: 103 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g25<1>UD        g32<8,8,1>UD    0x02380488
+                            urb MsgDesc: 72 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g32<8,8,1>UD    0x02380288
+                            urb MsgDesc: 40 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g28<1>UD        g32<8,8,1>UD    0x02380688
+                            urb MsgDesc: 104 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g25<1>UD        g33<8,8,1>UD    0x02380498
+                            urb MsgDesc: 73 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g33<8,8,1>UD    0x02380298
+                            urb MsgDesc: 41 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g28<1>UD        g33<8,8,1>UD    0x02380698
+                            urb MsgDesc: 105 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g25<1>UD        g34<8,8,1>UD    0x023806a8
+                            urb MsgDesc: 106 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g34<8,8,1>UD    0x023802a8
+                            urb MsgDesc: 42 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g34<8,8,1>UD    0x023804a8
+                            urb MsgDesc: 74 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g8<1>UD         g35<8,8,1>UD    0x023802b8
+                            urb MsgDesc: 43 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g35<8,8,1>UD    0x023804b8
+                            urb MsgDesc: 75 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g35<8,8,1>UD    0x023806b8
+                            urb MsgDesc: 107 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g36<8,8,1>UD    0x023802c8
+                            urb MsgDesc: 44 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g36<8,8,1>UD    0x023804c8
+                            urb MsgDesc: 76 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g36<8,8,1>UD    0x023806c8
+                            urb MsgDesc: 108 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g37<8,8,1>UD    0x023802d8
+                            urb MsgDesc: 45 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g37<8,8,1>UD    0x023804d8
+                            urb MsgDesc: 77 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g37<8,8,1>UD    0x023806d8
+                            urb MsgDesc: 109 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g38<8,8,1>UD    0x023802e8
+                            urb MsgDesc: 46 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g38<8,8,1>UD    0x023804e8
+                            urb MsgDesc: 78 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g38<8,8,1>UD    0x023806e8
+                            urb MsgDesc: 110 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g39<8,8,1>UD    0x023802f8
+                            urb MsgDesc: 47 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g39<8,8,1>UD    0x023804f8
+                            urb MsgDesc: 79 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g25<1>UD        g39<8,8,1>UD    0x023806f8
+                            urb MsgDesc: 111 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g40<8,8,1>UD    0x02380308
+                            urb MsgDesc: 48 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g40<8,8,1>UD    0x02380508
+                            urb MsgDesc: 80 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g40<8,8,1>UD    0x02380708
+                            urb MsgDesc: 112 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g41<8,8,1>UD    0x02380318
+                            urb MsgDesc: 49 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g41<8,8,1>UD    0x02380518
+                            urb MsgDesc: 81 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g41<8,8,1>UD    0x02380718
+                            urb MsgDesc: 113 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g3<8,8,1>UD     0x02380328
+                            urb MsgDesc: 50 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g3<8,8,1>UD     0x02380528
+                            urb MsgDesc: 82 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g3<8,8,1>UD     0x02380728
+                            urb MsgDesc: 114 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g43<8,8,1>UD    0x02380338
+                            urb MsgDesc: 51 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g43<8,8,1>UD    0x02380538
+                            urb MsgDesc: 83 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g43<8,8,1>UD    0x02380738
+                            urb MsgDesc: 115 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g44<8,8,1>UD    0x02380348
+                            urb MsgDesc: 52 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g44<8,8,1>UD    0x02380548
+                            urb MsgDesc: 84 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g44<8,8,1>UD    0x02380748
+                            urb MsgDesc: 116 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g45<8,8,1>UD    0x02380358
+                            urb MsgDesc: 53 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g45<8,8,1>UD    0x02380558
+                            urb MsgDesc: 85 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g22<1>UD        g45<8,8,1>UD    0x02380758
+                            urb MsgDesc: 117 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g46<8,8,1>UD    0x02380368
+                            urb MsgDesc: 54 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g46<8,8,1>UD    0x02380568
+                            urb MsgDesc: 86 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g46<8,8,1>UD    0x02380768
+                            urb MsgDesc: 118 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g47<8,8,1>UD    0x02380378
+                            urb MsgDesc: 55 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g47<8,8,1>UD    0x02380578
+                            urb MsgDesc: 87 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g47<8,8,1>UD    0x02380778
+                            urb MsgDesc: 119 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g48<8,8,1>UD    0x02380388
+                            urb MsgDesc: 56 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g48<8,8,1>UD    0x02380588
+                            urb MsgDesc: 88 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g48<8,8,1>UD    0x02380788
+                            urb MsgDesc: 120 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g49<8,8,1>UD    0x02380398
+                            urb MsgDesc: 57 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g49<8,8,1>UD    0x02380598
+                            urb MsgDesc: 89 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g49<8,8,1>UD    0x02380798
+                            urb MsgDesc: 121 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g50<8,8,1>UD    0x023803a8
+                            urb MsgDesc: 58 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g50<8,8,1>UD    0x023805a8
+                            urb MsgDesc: 90 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g50<8,8,1>UD    0x023807a8
+                            urb MsgDesc: 122 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g54<8,8,1>UD    0x023803b8
+                            urb MsgDesc: 59 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g54<8,8,1>UD    0x023805b8
+                            urb MsgDesc: 91 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g54<8,8,1>UD    0x023807b8
+                            urb MsgDesc: 123 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g55<8,8,1>UD    0x023803c8
+                            urb MsgDesc: 60 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g55<8,8,1>UD    0x023805c8
+                            urb MsgDesc: 92 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g55<8,8,1>UD    0x023807c8
+                            urb MsgDesc: 124 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g56<8,8,1>UD    0x023803d8
+                            urb MsgDesc: 61 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g56<8,8,1>UD    0x023805d8
+                            urb MsgDesc: 93 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g56<8,8,1>UD    0x023807d8
+                            urb MsgDesc: 125 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g57<8,8,1>UD    0x023803e8
+                            urb MsgDesc: 62 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g57<8,8,1>UD    0x023805e8
+                            urb MsgDesc: 94 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g57<8,8,1>UD    0x023807e8
+                            urb MsgDesc: 126 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g58<8,8,1>UD    0x023803f8
+                            urb MsgDesc: 63 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g58<8,8,1>UD    0x023805f8
+                            urb MsgDesc: 95 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g58<8,8,1>UD    0x023807f8
+                            urb MsgDesc: 127 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g59<8,8,1>UD    0x02380208
+                            urb MsgDesc: 32 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g59<8,8,1>UD    0x02380408
+                            urb MsgDesc: 64 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g59<8,8,1>UD    0x02380608
+                            urb MsgDesc: 96 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g17<1>UD        g59<8,8,1>UD    0x02380808
+                            urb MsgDesc: 128 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         g8<1>UD         g60<8,8,1>UD    0x02380218
+                            urb MsgDesc: 33 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g60<8,8,1>UD    0x02380418
+                            urb MsgDesc: 65 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g14<1>UD        g60<8,8,1>UD    0x02380618
+                            urb MsgDesc: 97 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g17<1>UD        g60<8,8,1>UD    0x02380818
+                            urb MsgDesc: 129 SIMD8 read mlen 1 rlen 3       { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x0c0a8067
+                            urb MsgDesc: 6 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x0c0a8077
+                            urb MsgDesc: 7 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0c0a8087
+                            urb MsgDesc: 8 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0c0a8097
+                            urb MsgDesc: 9 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0c0a80a7
+                            urb MsgDesc: 10 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0c0a80b7
+                            urb MsgDesc: 11 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0c0a80c7
+                            urb MsgDesc: 12 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0c0a80d7
+                            urb MsgDesc: 13 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0c0a80e7
+                            urb MsgDesc: 14 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0c0a80f7
+                            urb MsgDesc: 15 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0c0a8107
+                            urb MsgDesc: 16 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0c0a8117
+                            urb MsgDesc: 17 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0c0a8127
+                            urb MsgDesc: 18 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0c0a8137
+                            urb MsgDesc: 19 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0c0a8147
+                            urb MsgDesc: 20 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0c0a8157
+                            urb MsgDesc: 21 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0c0a8167
+                            urb MsgDesc: 22 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0c0a8177
+                            urb MsgDesc: 23 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0c0a8187
+                            urb MsgDesc: 24 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0c0a8197
+                            urb MsgDesc: 25 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0c0a81a7
+                            urb MsgDesc: 26 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0c0a81b7
+                            urb MsgDesc: 27 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0c0a81c7
+                            urb MsgDesc: 28 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0c0a81d7
+                            urb MsgDesc: 29 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0c0a81e7
+                            urb MsgDesc: 30 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0c0a81f7
+                            urb MsgDesc: 31 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x0c0a8207
+                            urb MsgDesc: 32 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g41<8,8,1>UD    0x0c0a8217
+                            urb MsgDesc: 33 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x02106e01
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(16)        g11<1>UW        g19<8,8,1>UD    0x0420a601
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, dec) mlen 2 rlen 2 { align1 1H };
+send(16)        null<1>UW       g20<8,8,1>UD    0x04008503
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 3, SIMD16, inc) mlen 2 rlen 0 { align1 1H };
+send(8)         g17<1>UW        g11<8,8,1>UD    0x0813e001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q };
+send(16)        g22<1>UW        g2<8,8,1>UD     0x1025e001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H };
+send(8)         null<1>F        g122<8,8,1>UD   0x8c088007
+                            urb MsgDesc: 0 SIMD8 write masked mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x06423001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x06423102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g20<8,8,1>UD    0x0c843001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g26<8,8,1>UD    0x0c843102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         g14<1>UW        g14<8,8,1>UD    0x0a1a5001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q };
+send(8)         g15<1>UW        g19<8,8,1>UD    0x0a1a5102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q };
+send(16)        g39<1>UW        g7<8,8,1>UD     0x122c5001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 2 { align1 1H };
+send(16)        g41<1>UW        g16<8,8,1>UD    0x122c5102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x0c4b2001
+                            sampler MsgDesc: gather4_po_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(16)        g43<1>UW        g7<8,8,1>UD     0x168d2001
+                            sampler MsgDesc: gather4_po_c SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(8)         g54<1>UD        g7<8,8,1>UD     0x02280048
+                            urb MsgDesc: 4 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         g2<1>UW         g8<8,8,1>UD     0x02420001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g15<8,8,1>UD    0x04840001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(8)         g7<1>UW         g44<8,8,1>UD    0x02106e00
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(8)         null<1>UW       g44<8,8,1>UD    0x02009500
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, inc) mlen 1 rlen 0 { align1 1Q };
+send(8)         g7<1>UD         g37<8,8,1>UD    0x02480438
+                            urb MsgDesc: 67 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g11<1>UD        g37<8,8,1>UD    0x02480638
+                            urb MsgDesc: 99 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g13<1>UD        g14<8,8,1>UD    0x042a0148
+                            urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g14<8,8,1>UD    0x042a0048
+                            urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g124<1>UW       g13<8,8,1>UD    0x0c43c000
+                            sampler MsgDesc: ld2dms_w SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g14<8,8,1>UD    0x064a8404
+                            sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g10<8,8,1>UD    0x084a8202
+                            sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g26<8,8,1>UD    0x0a4a8303
+                            sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 3 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g14<8,8,1>UD    0x0e434102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 7 rlen 4 { align1 1Q };
+send(8)         g8<1>UW         g7<8,8,1>UD     0x121b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 1 { align1 1Q };
+send(8)         g9<1>UW         g16<8,8,1>UD    0x121b4102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 9 rlen 1 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x02380078
+                            urb MsgDesc: 7 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         g14<1>UW        g10<8,8,1>UD    0x064a8203
+                            sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(16)        g26<1>UW        g34<8,8,1>UD    0x0a8c8203
+                            sampler MsgDesc: gather4 SIMD16 Surface = 3 Sampler = 2 mlen 5 rlen 8 { align1 1H };
+send(8)         g50<1>UD        g51<8,8,1>UD    0x02180018
+                            urb MsgDesc: 1 SIMD8 read mlen 1 rlen 1         { align1 1Q };
+send(8)         g59<1>UW        g64<8,8,1>UD    0x02427002
+                            sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g64<8,8,1>UD    0x02427003
+                            sampler MsgDesc: ld SIMD8 Surface = 3 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g64<8,8,1>UD    0x02427004
+                            sampler MsgDesc: ld SIMD8 Surface = 4 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g64<8,8,1>UD    0x02427005
+                            sampler MsgDesc: ld SIMD8 Surface = 5 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g64<8,8,1>UD    0x02427006
+                            sampler MsgDesc: ld SIMD8 Surface = 6 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g64<8,8,1>UD    0x02427007
+                            sampler MsgDesc: ld SIMD8 Surface = 7 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g64<8,8,1>UD    0x02427008
+                            sampler MsgDesc: ld SIMD8 Surface = 8 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g64<8,8,1>UD    0x02427009
+                            sampler MsgDesc: ld SIMD8 Surface = 9 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g30<1>UW        g64<8,8,1>UD    0x0242700a
+                            sampler MsgDesc: ld SIMD8 Surface = 10 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g34<1>UW        g64<8,8,1>UD    0x0242700b
+                            sampler MsgDesc: ld SIMD8 Surface = 11 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g38<1>UW        g64<8,8,1>UD    0x0242700c
+                            sampler MsgDesc: ld SIMD8 Surface = 12 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g42<1>UW        g64<8,8,1>UD    0x0242700d
+                            sampler MsgDesc: ld SIMD8 Surface = 13 Sampler = 0 mlen 1 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x04438505
+                            sampler MsgDesc: sample_lz SIMD8 Surface = 5 Sampler = 5 mlen 2 rlen 4 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0a088067
+                            urb MsgDesc: 6 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0a088077
+                            urb MsgDesc: 7 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0a088087
+                            urb MsgDesc: 8 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0a088097
+                            urb MsgDesc: 9 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0a0880a7
+                            urb MsgDesc: 10 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0a0880b7
+                            urb MsgDesc: 11 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0a0880c7
+                            urb MsgDesc: 12 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0a0880d7
+                            urb MsgDesc: 13 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0a0880e7
+                            urb MsgDesc: 14 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0a0880f7
+                            urb MsgDesc: 15 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0a088107
+                            urb MsgDesc: 16 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0a088117
+                            urb MsgDesc: 17 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0a088127
+                            urb MsgDesc: 18 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0a088137
+                            urb MsgDesc: 19 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0a088147
+                            urb MsgDesc: 20 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0a088157
+                            urb MsgDesc: 21 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0a088167
+                            urb MsgDesc: 22 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0a088177
+                            urb MsgDesc: 23 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0a088187
+                            urb MsgDesc: 24 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0a088197
+                            urb MsgDesc: 25 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0a0881a7
+                            urb MsgDesc: 26 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0a0881b7
+                            urb MsgDesc: 27 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0a0881c7
+                            urb MsgDesc: 28 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0a0881d7
+                            urb MsgDesc: 29 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x0a0881e7
+                            urb MsgDesc: 30 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g41<8,8,1>UD    0x0a0881f7
+                            urb MsgDesc: 31 SIMD8 write masked mlen 5 rlen 0 { align1 1Q };
+send(8)         null<1>F        g4<8,8,1>UD     0x0e0a8027
+                            urb MsgDesc: 2 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q };
+send(8)         g5<1>UW         g6<8,8,1>UD     0x04123001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q };
+send(8)         g6<1>UW         g2<8,8,1>UD     0x04123102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 1 { align1 1Q };
+send(16)        g9<1>UW         g11<8,8,1>UD    0x08243001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H };
+send(16)        g11<1>UW        g2<8,8,1>UD     0x08243102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x0443d002
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g3<1>UW         g14<8,8,1>UD    0x0a43c102
+                            sampler MsgDesc: ld2dms_w SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g10<8,8,1>UD    0x0885d002
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g3<1>UW         g25<8,8,1>UD    0x1485c102
+                            sampler MsgDesc: ld2dms_w SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H };
+send(8)         g10<1>UW        g11<8,8,1>UD    0x0a123001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q };
+send(8)         g11<1>UW        g16<8,8,1>UD    0x0a123102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q };
+send(16)        g34<1>UW        g9<8,8,1>UD     0x14243001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 2 { align1 1H };
+send(16)        g36<1>UW        g19<8,8,1>UD    0x14243102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x08426001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x08426102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x10846001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g19<8,8,1>UD    0x10846102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+(+f1.0) send(8) g4<1>UW         g10<8,8,1>UD    0x0210b502
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, inc) mlen 1 rlen 1 { align1 1Q };
+(+f1.0) send(16) g5<1>UW        g13<8,8,1>UD    0x0420a502
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, inc) mlen 2 rlen 2 { align1 1H };
+send(8)         g8<1>UW         g9<8,8,1>UD     0x06321001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q };
+send(16)        g2<1>UW         g14<8,8,1>UD    0x0c641001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x04338000
+                            sampler MsgDesc: sample_lz SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 3 { align1 1Q };
+send(8)         g12<1>UD        g1<8,8,1>UD     0x02280058
+                            urb MsgDesc: 5 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0e0a8067
+                            urb MsgDesc: 6 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q };
+send(8)         g12<1>UD        g1<8,8,1>UD     0x02280078
+                            urb MsgDesc: 7 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0e0a8087
+                            urb MsgDesc: 8 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q };
+send(8)         g12<1>UD        g1<8,8,1>UD     0x02280098
+                            urb MsgDesc: 9 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0e0a80a7
+                            urb MsgDesc: 10 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q };
+send(16)        g9<1>UW         g17<8,8,1>UD    0x04847002
+                            sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 0 mlen 2 rlen 8 { align1 1H };
+send(16)        g23<1>UW        g32<8,8,1>UD    0x04205e02
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280068
+                            urb MsgDesc: 6 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280088
+                            urb MsgDesc: 8 SIMD8 read mlen 1 rlen 2         { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022800a8
+                            urb MsgDesc: 10 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022800b8
+                            urb MsgDesc: 11 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022800c8
+                            urb MsgDesc: 12 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022800d8
+                            urb MsgDesc: 13 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022800e8
+                            urb MsgDesc: 14 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022800f8
+                            urb MsgDesc: 15 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280108
+                            urb MsgDesc: 16 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280118
+                            urb MsgDesc: 17 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280128
+                            urb MsgDesc: 18 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280138
+                            urb MsgDesc: 19 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280148
+                            urb MsgDesc: 20 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280158
+                            urb MsgDesc: 21 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280168
+                            urb MsgDesc: 22 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280178
+                            urb MsgDesc: 23 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280188
+                            urb MsgDesc: 24 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280198
+                            urb MsgDesc: 25 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022801a8
+                            urb MsgDesc: 26 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022801b8
+                            urb MsgDesc: 27 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022801c8
+                            urb MsgDesc: 28 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022801d8
+                            urb MsgDesc: 29 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022801e8
+                            urb MsgDesc: 30 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x022801f8
+                            urb MsgDesc: 31 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g1<8,8,1>UD     0x02280208
+                            urb MsgDesc: 32 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g2<1>UW         g3<8,8,1>UD     0x04203000
+                            pixel interp MsgDesc: (persp, per_slot_offset, 0x00) mlen 2 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x08413000
+                            pixel interp MsgDesc: (persp, per_slot_offset, 0x00) mlen 4 rlen 4 { align1 1H };
+send(8)         g2<1>UW         g0<8,8,1>UD     0x02201010
+                            pixel interp MsgDesc: (persp, sample_position, 0x10) mlen 1 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g0<8,8,1>UD     0x02411010
+                            pixel interp MsgDesc: (persp, sample_position, 0x10) mlen 1 rlen 4 { align1 1H };
+send(8)         g2<1>UW         g0<8,8,1>UD     0x02201020
+                            pixel interp MsgDesc: (persp, sample_position, 0x20) mlen 1 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g0<8,8,1>UD     0x02411020
+                            pixel interp MsgDesc: (persp, sample_position, 0x20) mlen 1 rlen 4 { align1 1H };
+send(8)         g2<1>UW         g0<8,8,1>UD     0x02201030
+                            pixel interp MsgDesc: (persp, sample_position, 0x30) mlen 1 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g0<8,8,1>UD     0x02411030
+                            pixel interp MsgDesc: (persp, sample_position, 0x30) mlen 1 rlen 4 { align1 1H };
+send(8)         g20<1>UW        g15<8,8,1>UD    0x04320203
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 3 { align1 1Q };
+send(8)         g11<1>UW        g26<8,8,1>UD    0x04320405
+                            sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 3 { align1 1Q };
+send(8)         g8<1>UW         g24<8,8,1>UD    0x04320304
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 3 { align1 1Q };
+send(16)        g26<1>UW        g21<8,8,1>UD    0x08640203
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 6 { align1 1H };
+send(16)        g12<1>UW        g48<8,8,1>UD    0x08640405
+                            sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 6 { align1 1H };
+send(16)        g38<1>UW        g44<8,8,1>UD    0x08640304
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 6 { align1 1H };
+(+f1.0) send(8) null<1>UW       g94<8,8,1>UD    0x02009601
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, dec) mlen 1 rlen 0 { align1 1Q };
+(+f1.0) send(8) g47<1>UW        g94<8,8,1>UD    0x0210b601
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, dec) mlen 1 rlen 1 { align1 1Q };
+send(16)        g4<1>UW         g1<8,8,1>UD     0x04405c02
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD16, Mask = 0xc) mlen 2 rlen 4 { align1 1H };
+send(8)         null<1>UW       g100<8,8,1>UD   0x02009600
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, dec) mlen 1 rlen 0 { align1 1Q };
+send(8)         g51<1>UW        g100<8,8,1>UD   0x0210b600
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, dec) mlen 1 rlen 1 { align1 1Q };
+send(8)         g5<1>UW         g11<8,8,1>UD    0x064a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(16)        g7<1>UW         g19<8,8,1>UD    0x0a8c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080117
+                            urb MsgDesc: 17 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(8)         g3<1>UW         g3<8,8,1>UD     0x02415002
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD16, Mask = 0x0) mlen 1 rlen 4 { align1 1Q };
+send(8)         g5<1>UW         g4<8,8,1>UD     0x02416002
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 2Q };
+send(8)         g6<1>UW         g16<8,8,1>UD    0x0210b500
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, inc) mlen 1 rlen 1 { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080097
+                            urb MsgDesc: 9 SIMD8 write mlen 9 rlen 0        { align1 1Q EOT };
+send(8)         null<1>F        g4<8,8,1>F      0x120800c7
+                            urb MsgDesc: 12 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g5<8,8,1>F      0x120800e7
+                            urb MsgDesc: 14 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080107
+                            urb MsgDesc: 16 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x08434102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(8)         g67<1>UW        g36<8,8,1>UD    0x0823e000
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 2 { align1 1Q };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x0a23c000
+                            sampler MsgDesc: ld2dms_w SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 2 { align1 1Q };
+send(8)         g9<1>UW         g15<8,8,1>UD    0x021ab101
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 1 Sampler = 1 mlen 1 rlen 1 { align1 1Q };
+send(8)         g10<1>UW        g16<8,8,1>UD    0x021ab202
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 2 Sampler = 2 mlen 1 rlen 1 { align1 1Q };
+send(8)         g11<1>UW        g17<8,8,1>UD    0x021ab303
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 3 Sampler = 3 mlen 1 rlen 1 { align1 1Q };
+send(8)         g12<1>UW        g18<8,8,1>UD    0x021ab404
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 4 Sampler = 4 mlen 1 rlen 1 { align1 1Q };
+send(8)         g13<1>UW        g19<8,8,1>UD    0x021ab505
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 5 Sampler = 5 mlen 1 rlen 1 { align1 1Q };
+send(8)         g14<1>UW        g18<8,8,1>UD    0x08123102
+                            sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q };
+send(16)        g24<1>UW        g32<8,8,1>UD    0x10243102
+                            sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 2 { align1 1H };
+send(8)         g5<1>UW         g5<8,8,1>UD     0x04415000
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UD         g9<8,8,1>UD     0x043a0028
+                            urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x02380098
+                            urb MsgDesc: 9 SIMD8 read mlen 1 rlen 3         { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x023800a8
+                            urb MsgDesc: 10 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x023800b8
+                            urb MsgDesc: 11 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x023800d8
+                            urb MsgDesc: 13 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x023800e8
+                            urb MsgDesc: 14 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x023800f8
+                            urb MsgDesc: 15 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x02380108
+                            urb MsgDesc: 16 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g13<1>UD        g1<8,8,1>UD     0x02380118
+                            urb MsgDesc: 17 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         null<1>F        g60<8,8,1>F     0x120800a7
+                            urb MsgDesc: 10 SIMD8 write mlen 9 rlen 0       { align1 1Q };
+send(8)         null<1>F        g119<8,8,1>F    0x92080107
+                            urb MsgDesc: 16 SIMD8 write mlen 9 rlen 0       { align1 1Q EOT };
+send(8)         g3<1>UW         g7<8,8,1>UD     0x02115e01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(8)         g5<1>UW         g11<8,8,1>UD    0x02116e01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 2Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080067
+                            urb MsgDesc: 6 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         null<1>F        g80<8,8,1>F     0x140a00b7
+                            urb MsgDesc: 11 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a00d7
+                            urb MsgDesc: 13 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a00f7
+                            urb MsgDesc: 15 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a0117
+                            urb MsgDesc: 17 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a0137
+                            urb MsgDesc: 19 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g90<8,8,1>F     0x140a0157
+                            urb MsgDesc: 21 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g100<8,8,1>F    0x140a0177
+                            urb MsgDesc: 23 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g110<8,8,1>F    0x0c0a0197
+                            urb MsgDesc: 25 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g120<8,8,1>F    0x8c0a0197
+                            urb MsgDesc: 25 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         null<1>F        g123<8,8,1>F    0x8a0800b7
+                            urb MsgDesc: 11 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(8)         g22<1>UD        g53<8,8,1>UD    0x02180238
+                            urb MsgDesc: 35 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g54<1>UD        g53<8,8,1>UD    0x02180438
+                            urb MsgDesc: 67 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g67<1>UD        g53<8,8,1>UD    0x02180638
+                            urb MsgDesc: 99 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g61<1>UD        g53<8,8,1>UD    0x02180248
+                            urb MsgDesc: 36 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g66<1>UD        g53<8,8,1>UD    0x02180448
+                            urb MsgDesc: 68 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g63<1>UD        g53<8,8,1>UD    0x02180648
+                            urb MsgDesc: 100 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g68<1>UD        g65<8,8,1>UD    0x02180258
+                            urb MsgDesc: 37 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g69<1>UD        g65<8,8,1>UD    0x02180458
+                            urb MsgDesc: 69 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g70<1>UD        g65<8,8,1>UD    0x02180658
+                            urb MsgDesc: 101 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g75<1>UD        g24<8,8,1>UD    0x02180268
+                            urb MsgDesc: 38 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g76<1>UD        g24<8,8,1>UD    0x02180468
+                            urb MsgDesc: 70 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g77<1>UD        g24<8,8,1>UD    0x02180668
+                            urb MsgDesc: 102 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g82<1>UD        g25<8,8,1>UD    0x02180278
+                            urb MsgDesc: 39 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g83<1>UD        g25<8,8,1>UD    0x02180478
+                            urb MsgDesc: 71 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g84<1>UD        g25<8,8,1>UD    0x02180678
+                            urb MsgDesc: 103 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g89<1>UD        g26<8,8,1>UD    0x02180288
+                            urb MsgDesc: 40 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g90<1>UD        g26<8,8,1>UD    0x02180488
+                            urb MsgDesc: 72 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g91<1>UD        g26<8,8,1>UD    0x02180688
+                            urb MsgDesc: 104 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g96<1>UD        g27<8,8,1>UD    0x02180298
+                            urb MsgDesc: 41 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g97<1>UD        g27<8,8,1>UD    0x02180498
+                            urb MsgDesc: 73 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g98<1>UD        g27<8,8,1>UD    0x02180698
+                            urb MsgDesc: 105 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g103<1>UD       g28<8,8,1>UD    0x021802a8
+                            urb MsgDesc: 42 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g104<1>UD       g28<8,8,1>UD    0x021804a8
+                            urb MsgDesc: 74 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g105<1>UD       g28<8,8,1>UD    0x021806a8
+                            urb MsgDesc: 106 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g110<1>UD       g29<8,8,1>UD    0x021802b8
+                            urb MsgDesc: 43 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g111<1>UD       g29<8,8,1>UD    0x021804b8
+                            urb MsgDesc: 75 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g112<1>UD       g29<8,8,1>UD    0x021806b8
+                            urb MsgDesc: 107 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g117<1>UD       g30<8,8,1>UD    0x021802c8
+                            urb MsgDesc: 44 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g118<1>UD       g30<8,8,1>UD    0x021804c8
+                            urb MsgDesc: 76 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g119<1>UD       g30<8,8,1>UD    0x021806c8
+                            urb MsgDesc: 108 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g124<1>UD       g31<8,8,1>UD    0x021802d8
+                            urb MsgDesc: 45 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g125<1>UD       g31<8,8,1>UD    0x021804d8
+                            urb MsgDesc: 77 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g126<1>UD       g31<8,8,1>UD    0x021806d8
+                            urb MsgDesc: 109 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g10<1>UD        g32<8,8,1>UD    0x021802e8
+                            urb MsgDesc: 46 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g11<1>UD        g32<8,8,1>UD    0x021804e8
+                            urb MsgDesc: 78 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g12<1>UD        g32<8,8,1>UD    0x021806e8
+                            urb MsgDesc: 110 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g26<1>UD        g33<8,8,1>UD    0x021802f8
+                            urb MsgDesc: 47 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g27<1>UD        g33<8,8,1>UD    0x021804f8
+                            urb MsgDesc: 79 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g28<1>UD        g33<8,8,1>UD    0x021806f8
+                            urb MsgDesc: 111 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g33<1>UD        g35<8,8,1>UD    0x02180308
+                            urb MsgDesc: 48 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g34<1>UD        g35<8,8,1>UD    0x02180508
+                            urb MsgDesc: 80 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g35<1>UD        g35<8,8,1>UD    0x02180708
+                            urb MsgDesc: 112 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g64<1>UD        g36<8,8,1>UD    0x02180318
+                            urb MsgDesc: 49 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g41<1>UD        g36<8,8,1>UD    0x02180518
+                            urb MsgDesc: 81 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g42<1>UD        g36<8,8,1>UD    0x02180718
+                            urb MsgDesc: 113 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g6<1>UD         g37<8,8,1>UD    0x02180328
+                            urb MsgDesc: 50 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g48<1>UD        g37<8,8,1>UD    0x02180528
+                            urb MsgDesc: 82 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g49<1>UD        g37<8,8,1>UD    0x02180728
+                            urb MsgDesc: 114 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g67<1>UD        g38<8,8,1>UD    0x02180338
+                            urb MsgDesc: 51 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g56<1>UD        g38<8,8,1>UD    0x02180538
+                            urb MsgDesc: 83 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g57<1>UD        g38<8,8,1>UD    0x02180738
+                            urb MsgDesc: 115 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g66<1>UD        g39<8,8,1>UD    0x02180348
+                            urb MsgDesc: 52 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g63<1>UD        g39<8,8,1>UD    0x02180548
+                            urb MsgDesc: 84 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g40<1>UD        g39<8,8,1>UD    0x02180748
+                            urb MsgDesc: 116 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g69<1>UD        g64<8,8,1>UD    0x02180358
+                            urb MsgDesc: 53 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g70<1>UD        g64<8,8,1>UD    0x02180558
+                            urb MsgDesc: 85 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g71<1>UD        g64<8,8,1>UD    0x02180758
+                            urb MsgDesc: 117 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g76<1>UD        g41<8,8,1>UD    0x02180368
+                            urb MsgDesc: 54 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g77<1>UD        g41<8,8,1>UD    0x02180568
+                            urb MsgDesc: 86 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g78<1>UD        g41<8,8,1>UD    0x02180768
+                            urb MsgDesc: 118 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g83<1>UD        g42<8,8,1>UD    0x02180378
+                            urb MsgDesc: 55 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g84<1>UD        g42<8,8,1>UD    0x02180578
+                            urb MsgDesc: 87 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g85<1>UD        g42<8,8,1>UD    0x02180778
+                            urb MsgDesc: 119 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g90<1>UD        g43<8,8,1>UD    0x02180388
+                            urb MsgDesc: 56 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g91<1>UD        g43<8,8,1>UD    0x02180588
+                            urb MsgDesc: 88 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g92<1>UD        g43<8,8,1>UD    0x02180788
+                            urb MsgDesc: 120 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g97<1>UD        g44<8,8,1>UD    0x02180398
+                            urb MsgDesc: 57 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g98<1>UD        g44<8,8,1>UD    0x02180598
+                            urb MsgDesc: 89 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g99<1>UD        g44<8,8,1>UD    0x02180798
+                            urb MsgDesc: 121 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g104<1>UD       g45<8,8,1>UD    0x021803a8
+                            urb MsgDesc: 58 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g105<1>UD       g45<8,8,1>UD    0x021805a8
+                            urb MsgDesc: 90 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g106<1>UD       g45<8,8,1>UD    0x021807a8
+                            urb MsgDesc: 122 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g111<1>UD       g46<8,8,1>UD    0x021803b8
+                            urb MsgDesc: 59 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g112<1>UD       g46<8,8,1>UD    0x021805b8
+                            urb MsgDesc: 91 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g113<1>UD       g46<8,8,1>UD    0x021807b8
+                            urb MsgDesc: 123 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g118<1>UD       g6<8,8,1>UD     0x021803c8
+                            urb MsgDesc: 60 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g119<1>UD       g6<8,8,1>UD     0x021805c8
+                            urb MsgDesc: 92 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g120<1>UD       g6<8,8,1>UD     0x021807c8
+                            urb MsgDesc: 124 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g125<1>UD       g48<8,8,1>UD    0x021803d8
+                            urb MsgDesc: 61 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g126<1>UD       g48<8,8,1>UD    0x021805d8
+                            urb MsgDesc: 93 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g2<1>UD         g48<8,8,1>UD    0x021807d8
+                            urb MsgDesc: 125 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g12<1>UD        g49<8,8,1>UD    0x021803e8
+                            urb MsgDesc: 62 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g13<1>UD        g49<8,8,1>UD    0x021805e8
+                            urb MsgDesc: 94 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g14<1>UD        g49<8,8,1>UD    0x021807e8
+                            urb MsgDesc: 126 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g19<1>UD        g50<8,8,1>UD    0x021803f8
+                            urb MsgDesc: 63 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g20<1>UD        g50<8,8,1>UD    0x021805f8
+                            urb MsgDesc: 95 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g53<1>UD        g50<8,8,1>UD    0x021807f8
+                            urb MsgDesc: 127 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g28<1>UD        g51<8,8,1>UD    0x02180408
+                            urb MsgDesc: 64 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g29<1>UD        g51<8,8,1>UD    0x02180608
+                            urb MsgDesc: 96 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g30<1>UD        g51<8,8,1>UD    0x02180808
+                            urb MsgDesc: 128 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         g35<1>UD        g22<8,8,1>UD    0x02180218
+                            urb MsgDesc: 33 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g36<1>UD        g22<8,8,1>UD    0x02180418
+                            urb MsgDesc: 65 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g37<1>UD        g22<8,8,1>UD    0x02180618
+                            urb MsgDesc: 97 SIMD8 read mlen 1 rlen 1        { align1 1Q };
+send(8)         g38<1>UD        g22<8,8,1>UD    0x02180818
+                            urb MsgDesc: 129 SIMD8 read mlen 1 rlen 1       { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x080a8037
+                            urb MsgDesc: 3 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g10<8,8,1>UD    0x080a8047
+                            urb MsgDesc: 4 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x080a8057
+                            urb MsgDesc: 5 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x080a8067
+                            urb MsgDesc: 6 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x080a8077
+                            urb MsgDesc: 7 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x080a8087
+                            urb MsgDesc: 8 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x080a8097
+                            urb MsgDesc: 9 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x080a80a7
+                            urb MsgDesc: 10 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x080a80b7
+                            urb MsgDesc: 11 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x080a80c7
+                            urb MsgDesc: 12 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x080a80d7
+                            urb MsgDesc: 13 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x080a80e7
+                            urb MsgDesc: 14 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x080a80f7
+                            urb MsgDesc: 15 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x080a8107
+                            urb MsgDesc: 16 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x080a8117
+                            urb MsgDesc: 17 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x080a8127
+                            urb MsgDesc: 18 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x080a8137
+                            urb MsgDesc: 19 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x080a8147
+                            urb MsgDesc: 20 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x080a8157
+                            urb MsgDesc: 21 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x080a8167
+                            urb MsgDesc: 22 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x080a8177
+                            urb MsgDesc: 23 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x080a8187
+                            urb MsgDesc: 24 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x080a8197
+                            urb MsgDesc: 25 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x080a81a7
+                            urb MsgDesc: 26 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x080a81b7
+                            urb MsgDesc: 27 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x080a81c7
+                            urb MsgDesc: 28 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x080a81d7
+                            urb MsgDesc: 29 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x080a81e7
+                            urb MsgDesc: 30 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x080a81f7
+                            urb MsgDesc: 31 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x080a8207
+                            urb MsgDesc: 32 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x080a8217
+                            urb MsgDesc: 33 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         g18<1>UW        g19<8,8,1>UD    0x04115e00
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 2 rlen 1 { align1 1Q };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x0623d001
+                            sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g8<8,8,1>UD     0x0c45d001
+                            sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1H };
+send(8)         g101<1>UW       g10<8,8,1>UD    0x0c33c001
+                            sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 3 { align1 1Q };
+send(8)         g14<1>UW        g11<8,8,1>UD    0x084b0203
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 3 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x0a4b0102
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q };
+send(16)        g26<1>UW        g2<8,8,1>UD     0x0e8d0203
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 3 Sampler = 2 mlen 7 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g34<8,8,1>UD    0x128d0102
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g7<8,8,1>UD     0x0a1b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q };
+send(8)         g7<1>UW         g12<8,8,1>UD    0x0a1b4102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q };
+send(8)         g34<1>UD        g42<8,8,1>UD    0x02480248
+                            urb MsgDesc: 36 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g38<1>UD        g42<8,8,1>UD    0x02480448
+                            urb MsgDesc: 68 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g42<1>UD        g42<8,8,1>UD    0x02480648
+                            urb MsgDesc: 100 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g22<1>UD        g43<8,8,1>UD    0x02480258
+                            urb MsgDesc: 37 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g43<8,8,1>UD    0x02480458
+                            urb MsgDesc: 69 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g43<8,8,1>UD    0x02480658
+                            urb MsgDesc: 101 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g22<1>UD        g44<8,8,1>UD    0x02480268
+                            urb MsgDesc: 38 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g44<8,8,1>UD    0x02480468
+                            urb MsgDesc: 70 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g44<8,8,1>UD    0x02480668
+                            urb MsgDesc: 102 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g22<1>UD        g45<8,8,1>UD    0x02480278
+                            urb MsgDesc: 39 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g45<8,8,1>UD    0x02480478
+                            urb MsgDesc: 71 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g45<8,8,1>UD    0x02480678
+                            urb MsgDesc: 103 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g22<1>UD        g55<8,8,1>UD    0x02480288
+                            urb MsgDesc: 40 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g55<8,8,1>UD    0x02480488
+                            urb MsgDesc: 72 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g55<8,8,1>UD    0x02480688
+                            urb MsgDesc: 104 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g26<1>UD        g56<8,8,1>UD    0x02480498
+                            urb MsgDesc: 73 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g56<8,8,1>UD    0x02480298
+                            urb MsgDesc: 41 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g56<8,8,1>UD    0x02480698
+                            urb MsgDesc: 105 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g26<1>UD        g82<8,8,1>UD    0x024804a8
+                            urb MsgDesc: 74 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g82<8,8,1>UD    0x024802a8
+                            urb MsgDesc: 42 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g82<8,8,1>UD    0x024806a8
+                            urb MsgDesc: 106 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g26<1>UD        g83<8,8,1>UD    0x024804b8
+                            urb MsgDesc: 75 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g83<8,8,1>UD    0x024802b8
+                            urb MsgDesc: 43 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g30<1>UD        g83<8,8,1>UD    0x024806b8
+                            urb MsgDesc: 107 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g26<1>UD        g84<8,8,1>UD    0x024806c8
+                            urb MsgDesc: 108 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g84<8,8,1>UD    0x024802c8
+                            urb MsgDesc: 44 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g84<8,8,1>UD    0x024804c8
+                            urb MsgDesc: 76 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g8<1>UD         g85<8,8,1>UD    0x024802d8
+                            urb MsgDesc: 45 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g85<8,8,1>UD    0x024804d8
+                            urb MsgDesc: 77 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g85<8,8,1>UD    0x024806d8
+                            urb MsgDesc: 109 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g6<8,8,1>UD     0x024802e8
+                            urb MsgDesc: 46 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g6<8,8,1>UD     0x024804e8
+                            urb MsgDesc: 78 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g6<8,8,1>UD     0x024806e8
+                            urb MsgDesc: 110 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g3<8,8,1>UD     0x024802f8
+                            urb MsgDesc: 47 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g3<8,8,1>UD     0x024804f8
+                            urb MsgDesc: 79 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g3<8,8,1>UD     0x024806f8
+                            urb MsgDesc: 111 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g46<8,8,1>UD    0x02480308
+                            urb MsgDesc: 48 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g46<8,8,1>UD    0x02480508
+                            urb MsgDesc: 80 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g46<8,8,1>UD    0x02480708
+                            urb MsgDesc: 112 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g47<8,8,1>UD    0x02480318
+                            urb MsgDesc: 49 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g47<8,8,1>UD    0x02480518
+                            urb MsgDesc: 81 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g47<8,8,1>UD    0x02480718
+                            urb MsgDesc: 113 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g57<8,8,1>UD    0x02480328
+                            urb MsgDesc: 50 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g57<8,8,1>UD    0x02480528
+                            urb MsgDesc: 82 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g57<8,8,1>UD    0x02480728
+                            urb MsgDesc: 114 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g58<8,8,1>UD    0x02480338
+                            urb MsgDesc: 51 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g58<8,8,1>UD    0x02480538
+                            urb MsgDesc: 83 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g26<1>UD        g58<8,8,1>UD    0x02480738
+                            urb MsgDesc: 115 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g59<8,8,1>UD    0x02480348
+                            urb MsgDesc: 52 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g59<8,8,1>UD    0x02480548
+                            urb MsgDesc: 84 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g59<8,8,1>UD    0x02480748
+                            urb MsgDesc: 116 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g60<8,8,1>UD    0x02480358
+                            urb MsgDesc: 53 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g60<8,8,1>UD    0x02480558
+                            urb MsgDesc: 85 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g60<8,8,1>UD    0x02480758
+                            urb MsgDesc: 117 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g61<8,8,1>UD    0x02480368
+                            urb MsgDesc: 54 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g61<8,8,1>UD    0x02480568
+                            urb MsgDesc: 86 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g61<8,8,1>UD    0x02480768
+                            urb MsgDesc: 118 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g62<8,8,1>UD    0x02480378
+                            urb MsgDesc: 55 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g62<8,8,1>UD    0x02480578
+                            urb MsgDesc: 87 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g62<8,8,1>UD    0x02480778
+                            urb MsgDesc: 119 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g63<8,8,1>UD    0x02480388
+                            urb MsgDesc: 56 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g63<8,8,1>UD    0x02480588
+                            urb MsgDesc: 88 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g63<8,8,1>UD    0x02480788
+                            urb MsgDesc: 120 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g64<8,8,1>UD    0x02480398
+                            urb MsgDesc: 57 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g64<8,8,1>UD    0x02480598
+                            urb MsgDesc: 89 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g64<8,8,1>UD    0x02480798
+                            urb MsgDesc: 121 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g68<8,8,1>UD    0x024803a8
+                            urb MsgDesc: 58 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g68<8,8,1>UD    0x024805a8
+                            urb MsgDesc: 90 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g68<8,8,1>UD    0x024807a8
+                            urb MsgDesc: 122 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g69<8,8,1>UD    0x024803b8
+                            urb MsgDesc: 59 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g69<8,8,1>UD    0x024805b8
+                            urb MsgDesc: 91 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g22<1>UD        g69<8,8,1>UD    0x024807b8
+                            urb MsgDesc: 123 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g70<8,8,1>UD    0x024803c8
+                            urb MsgDesc: 60 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g70<8,8,1>UD    0x024805c8
+                            urb MsgDesc: 92 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g16<1>UD        g70<8,8,1>UD    0x024807c8
+                            urb MsgDesc: 124 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g71<8,8,1>UD    0x024803d8
+                            urb MsgDesc: 61 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g71<8,8,1>UD    0x024805d8
+                            urb MsgDesc: 93 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g16<1>UD        g71<8,8,1>UD    0x024807d8
+                            urb MsgDesc: 125 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g72<8,8,1>UD    0x024803e8
+                            urb MsgDesc: 62 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g72<8,8,1>UD    0x024805e8
+                            urb MsgDesc: 94 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g16<1>UD        g72<8,8,1>UD    0x024807e8
+                            urb MsgDesc: 126 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g8<1>UD         g73<8,8,1>UD    0x024803f8
+                            urb MsgDesc: 63 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g12<1>UD        g73<8,8,1>UD    0x024805f8
+                            urb MsgDesc: 95 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g16<1>UD        g73<8,8,1>UD    0x024807f8
+                            urb MsgDesc: 127 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         g12<1>UD        g75<8,8,1>UD    0x02480418
+                            urb MsgDesc: 65 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g16<1>UD        g75<8,8,1>UD    0x02480618
+                            urb MsgDesc: 97 SIMD8 read mlen 1 rlen 4        { align1 1Q };
+send(8)         g20<1>UD        g75<8,8,1>UD    0x02480818
+                            urb MsgDesc: 129 SIMD8 read mlen 1 rlen 4       { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0c0a00c7
+                            urb MsgDesc: 12 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0c0a00d7
+                            urb MsgDesc: 13 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0c0a00e7
+                            urb MsgDesc: 14 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0c0a00f7
+                            urb MsgDesc: 15 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0c0a0107
+                            urb MsgDesc: 16 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0c0a0117
+                            urb MsgDesc: 17 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0c0a0137
+                            urb MsgDesc: 19 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0c0a0147
+                            urb MsgDesc: 20 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0c0a0157
+                            urb MsgDesc: 21 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0c0a0167
+                            urb MsgDesc: 22 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0c0a0177
+                            urb MsgDesc: 23 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0c0a0187
+                            urb MsgDesc: 24 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0c0a01a7
+                            urb MsgDesc: 26 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0c0a01b7
+                            urb MsgDesc: 27 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0c0a01c7
+                            urb MsgDesc: 28 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0c0a01d7
+                            urb MsgDesc: 29 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0c0a01e7
+                            urb MsgDesc: 30 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0c0a01f7
+                            urb MsgDesc: 31 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q };
+send(16)        g46<1>UD        g12<0,1,0>UD    0x02280302
+                            const MsgDesc: (2, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g50<1>UD        g15<0,1,0>UD    0x02280304
+                            const MsgDesc: (4, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g34<1>UD        g20<0,1,0>UD    0x02280303
+                            const MsgDesc: (3, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(16)        g16<1>UD        g21<0,1,0>UD    0x02280306
+                            const MsgDesc: (6, 3, 0, 0) mlen 1 rlen 2       { align1 WE_all 1H };
+send(8)         g5<1>UW         g19<8,8,1>UD    0x02106e03
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(8)         g8<1>UW         g21<8,8,1>UD    0x02106e04
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(16)        g8<1>UW         g34<8,8,1>UD    0x04205e03
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+send(16)        g14<1>UW        g37<8,8,1>UD    0x04205e04
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H };
+send(8)         g15<1>UD        g12<8,8,1>UD    0x041a0038
+                            urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g2<1>UW         g54<8,8,1>UD    0x0242a707
+                            sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 7 mlen 1 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g55<8,8,1>UD    0x0242a808
+                            sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 8 mlen 1 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g56<8,8,1>UD    0x0242a909
+                            sampler MsgDesc: resinfo SIMD8 Surface = 9 Sampler = 9 mlen 1 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g57<8,8,1>UD    0x0242aa0a
+                            sampler MsgDesc: resinfo SIMD8 Surface = 10 Sampler = 10 mlen 1 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g58<8,8,1>UD    0x0242ab0b
+                            sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 11 mlen 1 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g59<8,8,1>UD    0x0242ac0c
+                            sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 12 mlen 1 rlen 4 { align1 1Q };
+send(8)         null<1>F        g9<8,8,1>UD     0x0c088027
+                            urb MsgDesc: 2 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g10<8,8,1>UD    0x0c088047
+                            urb MsgDesc: 4 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x0c088067
+                            urb MsgDesc: 6 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>UD     0x0c088037
+                            urb MsgDesc: 3 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g7<8,8,1>UD     0x0c088057
+                            urb MsgDesc: 5 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g8<8,8,1>UD     0x0c088077
+                            urb MsgDesc: 7 SIMD8 write masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a0197
+                            urb MsgDesc: 25 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a01b7
+                            urb MsgDesc: 27 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a01d7
+                            urb MsgDesc: 29 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g6<8,8,1>F      0x140a01f7
+                            urb MsgDesc: 31 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g120<8,8,1>F    0x8c0a0217
+                            urb MsgDesc: 33 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g8<1>UD         g6<8,8,1>UD     0x041a0318
+                            urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g9<1>UD         g6<8,8,1>UD     0x041a0518
+                            urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g10<1>UD        g6<8,8,1>UD     0x041a0718
+                            urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g11<1>UD        g6<8,8,1>UD     0x041a0918
+                            urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g7<1>UD         g11<8,8,1>UD    0x041a0218
+                            urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g8<1>UD         g11<8,8,1>UD    0x041a0418
+                            urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g9<1>UD         g11<8,8,1>UD    0x041a0618
+                            urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g10<1>UD        g11<8,8,1>UD    0x041a0818
+                            urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         null<1>F        g10<8,8,1>UD    0x080a8227
+                            urb MsgDesc: 34 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>UD    0x080a8237
+                            urb MsgDesc: 35 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x080a8247
+                            urb MsgDesc: 36 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x080a8257
+                            urb MsgDesc: 37 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x080a8267
+                            urb MsgDesc: 38 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x080a8277
+                            urb MsgDesc: 39 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x080a8287
+                            urb MsgDesc: 40 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x080a8297
+                            urb MsgDesc: 41 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x080a82a7
+                            urb MsgDesc: 42 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x080a82b7
+                            urb MsgDesc: 43 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x080a82c7
+                            urb MsgDesc: 44 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x080a82d7
+                            urb MsgDesc: 45 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x080a82e7
+                            urb MsgDesc: 46 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x080a82f7
+                            urb MsgDesc: 47 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x080a8307
+                            urb MsgDesc: 48 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x080a8317
+                            urb MsgDesc: 49 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x080a8327
+                            urb MsgDesc: 50 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x080a8337
+                            urb MsgDesc: 51 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x080a8347
+                            urb MsgDesc: 52 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x080a8357
+                            urb MsgDesc: 53 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x080a8367
+                            urb MsgDesc: 54 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x080a8377
+                            urb MsgDesc: 55 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x080a8387
+                            urb MsgDesc: 56 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x080a8397
+                            urb MsgDesc: 57 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x080a83a7
+                            urb MsgDesc: 58 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x080a83b7
+                            urb MsgDesc: 59 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x080a83c7
+                            urb MsgDesc: 60 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x080a83d7
+                            urb MsgDesc: 61 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x080a83e7
+                            urb MsgDesc: 62 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x080a83f7
+                            urb MsgDesc: 63 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q };
+send(8)         g8<1>UD         g9<8,8,1>UD     0x02480008
+                            urb MsgDesc: 0 SIMD8 read mlen 1 rlen 4         { align1 1Q };
+send(8)         null<1>F        g123<8,8,1>F    0x8a080007
+                            urb MsgDesc: 0 SIMD8 write mlen 5 rlen 0        { align1 1Q EOT };
+send(8)         g4<1>UW         g2<8,8,1>UD     0x04215c01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xc) mlen 2 rlen 2 { align1 1Q };
+send(8)         g40<1>UW        g38<8,8,1>UD    0x04216c01
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xc) mlen 2 rlen 2 { align1 2Q };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x104a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x04422001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x08842001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x06425001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g10<8,8,1>UD    0x06425102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x0c845001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0c845102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         null<1>F        g121<8,8,1>F    0x8a080197
+                            urb MsgDesc: 25 SIMD8 write mlen 5 rlen 0       { align1 1Q EOT };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x02415000
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0x0) mlen 1 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x06415000
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0x0) mlen 3 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x02215c00
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xc) mlen 1 rlen 2 { align1 1Q };
+send(8)         g17<1>UW        g27<8,8,1>UD    0x02115e00
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x02415001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 1 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g29<8,8,1>UD    0x02416001
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 2Q };
+send(8)         g9<1>UW         g19<8,8,1>UD    0x0843e102
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g23<1>UW        g7<8,8,1>UD     0x1085e102
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g5<8,8,1>UD     0x0c4b0001
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(16)        g120<1>UW       g7<8,8,1>UD     0x168d0001
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H };
+send(8)         g6<1>UW         g7<8,8,1>UD     0x0a134001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q };
+send(8)         g7<1>UW         g12<8,8,1>UD    0x0a134102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q };
+send(8)         g22<1>UD        g10<8,8,1>UD    0x041a0138
+                            urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g21<1>UD        g10<8,8,1>UD    0x041a0338
+                            urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g65<1>UD        g10<8,8,1>UD    0x041a0538
+                            urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g10<1>UD        g10<8,8,1>UD    0x041a0738
+                            urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g65<1>UD        g11<8,8,1>UD    0x041a0238
+                            urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g10<1>UD        g11<8,8,1>UD    0x041a0438
+                            urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g11<1>UD        g11<8,8,1>UD    0x041a0638
+                            urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g8<1>UD         g7<8,8,1>UD     0x041a0048
+                            urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g6<1>UW         g10<8,8,1>UD    0x0a4a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x06426001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g10<8,8,1>UD    0x06426102
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x0c846001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g18<8,8,1>UD    0x0c846102
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x08320001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 3 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x10640001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 6 { align1 1H };
+send(8)         g6<1>UW         g7<8,8,1>UD     0x0c1b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 1 { align1 1Q };
+send(8)         g7<1>UW         g13<8,8,1>UD    0x0c1b4102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 1 { align1 1Q };
+send(8)         g2<1>UW         g7<8,8,1>UD     0x08425001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g11<8,8,1>UD    0x08425102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
+send(16)        g2<1>UW         g11<8,8,1>UD    0x10845001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g19<8,8,1>UD    0x10845102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g2<8,8,1>UD     0x02306801
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0x8) mlen 1 rlen 3 { align1 1Q };
+send(16)        g120<1>UW       g2<8,8,1>UD     0x04605801
+                            dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0x8) mlen 2 rlen 6 { align1 1H };
+send(8)         g8<1>UD         g7<8,8,1>UD     0x043a0128
+                            urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g12<1>UW        g5<8,8,1>UD     0x0833e001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 3 { align1 1Q };
+send(8)         g15<1>UW        g17<8,8,1>UD    0x0823e001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1Q };
+send(16)        g7<1>UW         g13<8,8,1>UD    0x1065e001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 6 { align1 1H };
+send(16)        g33<1>UW        g21<8,8,1>UD    0x1045e001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1H };
+send(8)         g14<1>UW        g14<8,8,1>UD    0x101b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 1 { align1 1Q };
+send(8)         g15<1>UW        g22<8,8,1>UD    0x101b4102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 8 rlen 1 { align1 1Q };
+send(8)         g8<1>UD         g20<8,8,1>UD    0x044a0138
+                            urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g20<8,8,1>UD    0x044a0338
+                            urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g16<1>UD        g20<8,8,1>UD    0x044a0538
+                            urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g20<1>UD        g20<8,8,1>UD    0x044a0738
+                            urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g14<1>UD        g22<8,8,1>UD    0x044a0238
+                            urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g18<1>UD        g22<8,8,1>UD    0x044a0438
+                            urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g22<1>UD        g22<8,8,1>UD    0x044a0638
+                            urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g11<1>UW        g5<8,8,1>UD     0x04120003
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 1 { align1 1Q };
+send(8)         g12<1>UW        g5<8,8,1>UD     0x04120004
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 0 mlen 2 rlen 1 { align1 1Q };
+send(16)        g8<1>UW         g12<8,8,1>UD    0x08240003
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 2 { align1 1H };
+send(16)        g10<1>UW        g12<8,8,1>UD    0x08240004
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 0 mlen 4 rlen 2 { align1 1H };
+send(8)         g6<1>UW         g7<8,8,1>UD     0x08125001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q };
+send(8)         g7<1>UW         g11<8,8,1>UD    0x08125102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q };
+send(16)        g10<1>UW        g12<8,8,1>UD    0x10245001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H };
+send(16)        g12<1>UW        g20<8,8,1>UD    0x10245102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g13<8,8,1>UD    0x0623a001
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 2 { align1 1Q };
+send(16)        g6<1>UW         g23<8,8,1>UD    0x0c45a001
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1H };
+send(8)         g124<1>UW       g7<8,8,1>UD     0x0c4b2000
+                            sampler MsgDesc: gather4_po_c SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q };
+send(8)         g13<1>UD        g39<8,8,1>UD    0x041a0058
+                            urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g10<8,8,1>UD    0x041a0068
+                            urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g3<8,8,1>UD     0x041a0078
+                            urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g3<8,8,1>UD     0x041a0088
+                            urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g3<8,8,1>UD     0x041a0098
+                            urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g3<8,8,1>UD     0x041a00a8
+                            urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g3<8,8,1>UD     0x041a00b8
+                            urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g4<1>UD         g3<8,8,1>UD     0x041a00c8
+                            urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a00d8
+                            urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a00e8
+                            urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a00f8
+                            urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0108
+                            urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0118
+                            urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0148
+                            urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0158
+                            urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0168
+                            urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0178
+                            urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0188
+                            urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0198
+                            urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a01a8
+                            urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a01b8
+                            urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a01c8
+                            urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a01d8
+                            urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a01e8
+                            urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a01f8
+                            urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g3<1>UD         g2<8,8,1>UD     0x041a0208
+                            urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q };
+send(8)         g38<1>UW        g38<8,8,1>UD    0x084a8405
+                            sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 4 mlen 4 rlen 4 { align1 1Q };
+send(8)         g46<1>UW        g23<8,8,1>UD    0x064a8304
+                            sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(8)         g28<1>UW        g28<8,8,1>UD    0x064a8506
+                            sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 5 mlen 3 rlen 4 { align1 1Q };
+send(8)         g12<1>UW        g23<8,8,1>UD    0x064a8607
+                            sampler MsgDesc: gather4 SIMD8 Surface = 7 Sampler = 6 mlen 3 rlen 4 { align1 1Q };
+send(8)         g12<1>UW        g32<8,8,1>UD    0x084a8708
+                            sampler MsgDesc: gather4 SIMD8 Surface = 8 Sampler = 7 mlen 4 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g13<8,8,1>UD    0x064a8809
+                            sampler MsgDesc: gather4 SIMD8 Surface = 9 Sampler = 8 mlen 3 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g26<8,8,1>UD    0x084b090a
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 10 Sampler = 9 mlen 4 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x0a4b0a0b
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 11 Sampler = 10 mlen 5 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g6<8,8,1>UD     0x084b0b0c
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 12 Sampler = 11 mlen 4 rlen 4 { align1 1Q };
+send(16)        g30<1>UW        g73<8,8,1>UD    0x0a8c8304
+                            sampler MsgDesc: gather4 SIMD16 Surface = 4 Sampler = 3 mlen 5 rlen 8 { align1 1H };
+send(16)        g40<1>UW        g2<8,8,1>UD     0x0e8c8405
+                            sampler MsgDesc: gather4 SIMD16 Surface = 5 Sampler = 4 mlen 7 rlen 8 { align1 1H };
+send(16)        g5<1>UW         g33<8,8,1>UD    0x0a8c8506
+                            sampler MsgDesc: gather4 SIMD16 Surface = 6 Sampler = 5 mlen 5 rlen 8 { align1 1H };
+send(16)        g32<1>UW        g55<8,8,1>UD    0x0a8c8607
+                            sampler MsgDesc: gather4 SIMD16 Surface = 7 Sampler = 6 mlen 5 rlen 8 { align1 1H };
+send(16)        g30<1>UW        g23<8,8,1>UD    0x0e8c8708
+                            sampler MsgDesc: gather4 SIMD16 Surface = 8 Sampler = 7 mlen 7 rlen 8 { align1 1H };
+send(16)        g5<1>UW         g40<8,8,1>UD    0x0a8c8809
+                            sampler MsgDesc: gather4 SIMD16 Surface = 9 Sampler = 8 mlen 5 rlen 8 { align1 1H };
+send(16)        g38<1>UW        g67<8,8,1>UD    0x0e8d090a
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 10 Sampler = 9 mlen 7 rlen 8 { align1 1H };
+send(16)        g38<1>UW        g2<8,8,1>UD     0x128d0a0b
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 11 Sampler = 10 mlen 9 rlen 8 { align1 1H };
+send(16)        g10<1>UW        g39<8,8,1>UD    0x0e8d0b0c
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 12 Sampler = 11 mlen 7 rlen 8 { align1 1H };
+send(8)         g2<1>UW         g6<8,8,1>UD     0x0e4b2000
+                            sampler MsgDesc: gather4_po_c SIMD8 Surface = 0 Sampler = 0 mlen 7 rlen 4 { align1 1Q };
+send(8)         g11<1>UW        g7<8,8,1>UD     0x04120102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 1 { align1 1Q };
+send(8)         g12<1>UW        g7<8,8,1>UD     0x04120203
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 1 { align1 1Q };
+send(16)        g6<1>UW         g11<8,8,1>UD    0x08240102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 2 { align1 1H };
+send(16)        g8<1>UW         g11<8,8,1>UD    0x08240203
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 2 { align1 1H };
+send(8)         g5<1>UW         g6<8,8,1>UD     0x04220003
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 2 { align1 1Q };
+send(16)        g8<1>UW         g12<8,8,1>UD    0x08440003
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 4 { align1 1H };
+send(8)         g5<1>UW         g2<8,8,1>UD     0x04129001
+                            sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q };
+send(16)        g6<1>UW         g2<8,8,1>UD     0x08249001
+                            sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H };
+send(8)         g11<1>UW        g4<8,8,1>UD     0x04415002
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q };
+send(8)         g7<1>UW         g5<8,8,1>UD     0x04416002
+                            dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD8, Mask = 0x0) mlen 2 rlen 4 { align1 2Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0e0a8057
+                            urb MsgDesc: 5 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q };
+send(8)         g6<1>UD         g18<8,8,1>UD    0x043a0318
+                            urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g9<1>UD         g18<8,8,1>UD    0x043a0518
+                            urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g12<1>UD        g18<8,8,1>UD    0x043a0718
+                            urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g15<1>UD        g18<8,8,1>UD    0x043a0918
+                            urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g11<1>UD        g23<8,8,1>UD    0x043a0218
+                            urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g14<1>UD        g23<8,8,1>UD    0x043a0418
+                            urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g17<1>UD        g23<8,8,1>UD    0x043a0618
+                            urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g20<1>UD        g23<8,8,1>UD    0x043a0818
+                            urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         null<1>F        g12<8,8,1>UD    0x0c0a8227
+                            urb MsgDesc: 34 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g13<8,8,1>UD    0x0c0a8237
+                            urb MsgDesc: 35 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g14<8,8,1>UD    0x0c0a8247
+                            urb MsgDesc: 36 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g15<8,8,1>UD    0x0c0a8257
+                            urb MsgDesc: 37 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g16<8,8,1>UD    0x0c0a8267
+                            urb MsgDesc: 38 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g17<8,8,1>UD    0x0c0a8277
+                            urb MsgDesc: 39 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g18<8,8,1>UD    0x0c0a8287
+                            urb MsgDesc: 40 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g19<8,8,1>UD    0x0c0a8297
+                            urb MsgDesc: 41 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g20<8,8,1>UD    0x0c0a82a7
+                            urb MsgDesc: 42 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g21<8,8,1>UD    0x0c0a82b7
+                            urb MsgDesc: 43 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g22<8,8,1>UD    0x0c0a82c7
+                            urb MsgDesc: 44 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g23<8,8,1>UD    0x0c0a82d7
+                            urb MsgDesc: 45 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g24<8,8,1>UD    0x0c0a82e7
+                            urb MsgDesc: 46 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g25<8,8,1>UD    0x0c0a82f7
+                            urb MsgDesc: 47 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g26<8,8,1>UD    0x0c0a8307
+                            urb MsgDesc: 48 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g27<8,8,1>UD    0x0c0a8317
+                            urb MsgDesc: 49 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g28<8,8,1>UD    0x0c0a8327
+                            urb MsgDesc: 50 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g29<8,8,1>UD    0x0c0a8337
+                            urb MsgDesc: 51 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g30<8,8,1>UD    0x0c0a8347
+                            urb MsgDesc: 52 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>UD    0x0c0a8357
+                            urb MsgDesc: 53 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g32<8,8,1>UD    0x0c0a8367
+                            urb MsgDesc: 54 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g33<8,8,1>UD    0x0c0a8377
+                            urb MsgDesc: 55 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g34<8,8,1>UD    0x0c0a8387
+                            urb MsgDesc: 56 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g35<8,8,1>UD    0x0c0a8397
+                            urb MsgDesc: 57 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g36<8,8,1>UD    0x0c0a83a7
+                            urb MsgDesc: 58 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g37<8,8,1>UD    0x0c0a83b7
+                            urb MsgDesc: 59 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g38<8,8,1>UD    0x0c0a83c7
+                            urb MsgDesc: 60 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g39<8,8,1>UD    0x0c0a83d7
+                            urb MsgDesc: 61 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g40<8,8,1>UD    0x0c0a83e7
+                            urb MsgDesc: 62 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         null<1>F        g41<8,8,1>UD    0x0c0a83f7
+                            urb MsgDesc: 63 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q };
+send(8)         g8<1>UW         g7<8,8,1>UD     0x10134001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 1 { align1 1Q };
+send(8)         g9<1>UW         g15<8,8,1>UD    0x10134102
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 8 rlen 1 { align1 1Q };
+send(8)         g16<1>UD        g16<8,8,1>UD    0x044a0148
+                            urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g38<1>UW        g38<8,8,1>UD    0x084a8404
+                            sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 4 mlen 4 rlen 4 { align1 1Q };
+send(8)         g46<1>UW        g23<8,8,1>UD    0x064a8303
+                            sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
+send(8)         g28<1>UW        g28<8,8,1>UD    0x064a8505
+                            sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 5 mlen 3 rlen 4 { align1 1Q };
+send(8)         g12<1>UW        g23<8,8,1>UD    0x064a8606
+                            sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 6 mlen 3 rlen 4 { align1 1Q };
+send(8)         g12<1>UW        g32<8,8,1>UD    0x084a8707
+                            sampler MsgDesc: gather4 SIMD8 Surface = 7 Sampler = 7 mlen 4 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g13<8,8,1>UD    0x064a8808
+                            sampler MsgDesc: gather4 SIMD8 Surface = 8 Sampler = 8 mlen 3 rlen 4 { align1 1Q };
+send(8)         g26<1>UW        g26<8,8,1>UD    0x084b0909
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 9 Sampler = 9 mlen 4 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x0a4b0a0a
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 10 Sampler = 10 mlen 5 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g10<8,8,1>UD    0x084b0b0b
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 11 Sampler = 11 mlen 4 rlen 4 { align1 1Q };
+send(8)         g2<1>UD         g15<8,8,1>UD    0x043a0048
+                            urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g12<1>UD        g15<8,8,1>UD    0x043a0058
+                            urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0068
+                            urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0078
+                            urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0088
+                            urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0098
+                            urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a00a8
+                            urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a00b8
+                            urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a00c8
+                            urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a00d8
+                            urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a00e8
+                            urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a00f8
+                            urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0108
+                            urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0118
+                            urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0138
+                            urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0148
+                            urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0158
+                            urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0168
+                            urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0178
+                            urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0188
+                            urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0198
+                            urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a01a8
+                            urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a01b8
+                            urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a01c8
+                            urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a01d8
+                            urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a01e8
+                            urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a01f8
+                            urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g2<1>UD         g2<8,8,1>UD     0x043a0208
+                            urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         null<1>F        g11<8,8,1>F     0x140a0047
+                            urb MsgDesc: 4 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g31<8,8,1>F     0x140a0087
+                            urb MsgDesc: 8 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q };
+send(8)         null<1>F        g118<8,8,1>F    0x940a0087
+                            urb MsgDesc: 8 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT };
+send(8)         g14<1>UW        g11<8,8,1>UD    0x0a4b0202
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 2 mlen 5 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x0c4b0303
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 3 Sampler = 3 mlen 6 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g24<8,8,1>UD    0x084b0404
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 4 Sampler = 4 mlen 4 rlen 4 { align1 1Q };
+send(8)         g15<1>UW        g2<8,8,1>UD     0x06423203
+                            sampler MsgDesc: sample_c SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
+send(16)        g19<1>UW        g27<8,8,1>UD    0x0c843203
+                            sampler MsgDesc: sample_c SIMD16 Surface = 3 Sampler = 2 mlen 6 rlen 8 { align1 1H };
+send(8)         g7<1>UW         g9<8,8,1>UD     0x0a13c001
+                            sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q };
+send(16)        g20<1>UW        g7<8,8,1>UD     0x1425c001
+                            sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 2 { align1 1H };
+send(8)         g21<1>UW        g5<8,8,1>UD     0x0a33c001
+                            sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 3 { align1 1Q };
+send(8)         g18<1>UW        g24<8,8,1>UD    0x0a23c001
+                            sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 2 { align1 1Q };
+send(16)        g15<1>UW        g21<8,8,1>UD    0x1465c001
+                            sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 6 { align1 1H };
+send(16)        g7<1>UW         g31<8,8,1>UD    0x1445c001
+                            sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 1H };
+send(8)         g124<1>UW       g6<8,8,1>UD     0x04438303
+                            sampler MsgDesc: sample_lz SIMD8 Surface = 3 Sampler = 3 mlen 2 rlen 4 { align1 1Q };
+send(8)         g11<1>UD        g17<8,8,1>UD    0x043a0338
+                            urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g14<1>UD        g17<8,8,1>UD    0x043a0538
+                            urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g17<1>UD        g17<8,8,1>UD    0x043a0738
+                            urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g9<1>UD         g18<8,8,1>UD    0x043a0038
+                            urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g12<1>UD        g18<8,8,1>UD    0x043a0238
+                            urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g15<1>UD        g18<8,8,1>UD    0x043a0438
+                            urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g18<1>UD        g18<8,8,1>UD    0x043a0638
+                            urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q };
+send(8)         g6<1>UW         g10<8,8,1>UD    0x08424001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q };
+send(8)         g9<1>UW         g5<8,8,1>UD     0x04420002
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g13<1>UW        g7<8,8,1>UD     0x08840002
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+(+f1.0) send(8) g124<1>UW       g2<8,8,1>UD     0x0211a501
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, inc) mlen 1 rlen 1 { align1 1Q };
+(+f1.0) send(8) g121<1>UW       g3<8,8,1>UD     0x0211b501
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, inc) mlen 1 rlen 1 { align1 2Q };
+send(8)         g22<1>UD        g32<8,8,1>UD    0x02280238
+                            urb MsgDesc: 35 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g24<1>UD        g32<8,8,1>UD    0x02280438
+                            urb MsgDesc: 67 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g26<1>UD        g32<8,8,1>UD    0x02280638
+                            urb MsgDesc: 99 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g28<1>UD        g32<8,8,1>UD    0x02280248
+                            urb MsgDesc: 36 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g30<1>UD        g32<8,8,1>UD    0x02280448
+                            urb MsgDesc: 68 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g32<1>UD        g32<8,8,1>UD    0x02280648
+                            urb MsgDesc: 100 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g22<1>UD        g33<8,8,1>UD    0x02280258
+                            urb MsgDesc: 37 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g24<1>UD        g33<8,8,1>UD    0x02280458
+                            urb MsgDesc: 69 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g26<1>UD        g33<8,8,1>UD    0x02280658
+                            urb MsgDesc: 101 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g22<1>UD        g34<8,8,1>UD    0x02280268
+                            urb MsgDesc: 38 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g24<1>UD        g34<8,8,1>UD    0x02280468
+                            urb MsgDesc: 70 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g26<1>UD        g34<8,8,1>UD    0x02280668
+                            urb MsgDesc: 102 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g24<1>UD        g35<8,8,1>UD    0x02280478
+                            urb MsgDesc: 71 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g35<8,8,1>UD    0x02280278
+                            urb MsgDesc: 39 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g26<1>UD        g35<8,8,1>UD    0x02280678
+                            urb MsgDesc: 103 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g24<1>UD        g36<8,8,1>UD    0x02280688
+                            urb MsgDesc: 104 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g36<8,8,1>UD    0x02280288
+                            urb MsgDesc: 40 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g36<8,8,1>UD    0x02280488
+                            urb MsgDesc: 72 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g8<1>UD         g37<8,8,1>UD    0x02280298
+                            urb MsgDesc: 41 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g37<8,8,1>UD    0x02280498
+                            urb MsgDesc: 73 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g24<1>UD        g37<8,8,1>UD    0x02280698
+                            urb MsgDesc: 105 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g38<8,8,1>UD    0x022802a8
+                            urb MsgDesc: 42 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g38<8,8,1>UD    0x022804a8
+                            urb MsgDesc: 74 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g24<1>UD        g38<8,8,1>UD    0x022806a8
+                            urb MsgDesc: 106 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g39<8,8,1>UD    0x022802b8
+                            urb MsgDesc: 43 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g39<8,8,1>UD    0x022804b8
+                            urb MsgDesc: 75 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g24<1>UD        g39<8,8,1>UD    0x022806b8
+                            urb MsgDesc: 107 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g40<8,8,1>UD    0x022802c8
+                            urb MsgDesc: 44 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g40<8,8,1>UD    0x022804c8
+                            urb MsgDesc: 76 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g40<8,8,1>UD    0x022806c8
+                            urb MsgDesc: 108 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g41<8,8,1>UD    0x022802d8
+                            urb MsgDesc: 45 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g41<8,8,1>UD    0x022804d8
+                            urb MsgDesc: 77 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g41<8,8,1>UD    0x022806d8
+                            urb MsgDesc: 109 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g42<8,8,1>UD    0x022802e8
+                            urb MsgDesc: 46 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g42<8,8,1>UD    0x022804e8
+                            urb MsgDesc: 78 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g42<8,8,1>UD    0x022806e8
+                            urb MsgDesc: 110 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g43<8,8,1>UD    0x022802f8
+                            urb MsgDesc: 47 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g43<8,8,1>UD    0x022804f8
+                            urb MsgDesc: 79 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g22<1>UD        g43<8,8,1>UD    0x022806f8
+                            urb MsgDesc: 111 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g44<8,8,1>UD    0x02280308
+                            urb MsgDesc: 48 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g44<8,8,1>UD    0x02280508
+                            urb MsgDesc: 80 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g44<8,8,1>UD    0x02280708
+                            urb MsgDesc: 112 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g45<8,8,1>UD    0x02280318
+                            urb MsgDesc: 49 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g45<8,8,1>UD    0x02280518
+                            urb MsgDesc: 81 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g45<8,8,1>UD    0x02280718
+                            urb MsgDesc: 113 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g46<8,8,1>UD    0x02280328
+                            urb MsgDesc: 50 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g46<8,8,1>UD    0x02280528
+                            urb MsgDesc: 82 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g46<8,8,1>UD    0x02280728
+                            urb MsgDesc: 114 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g47<8,8,1>UD    0x02280338
+                            urb MsgDesc: 51 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g47<8,8,1>UD    0x02280538
+                            urb MsgDesc: 83 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g47<8,8,1>UD    0x02280738
+                            urb MsgDesc: 115 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g48<8,8,1>UD    0x02280348
+                            urb MsgDesc: 52 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g48<8,8,1>UD    0x02280548
+                            urb MsgDesc: 84 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g48<8,8,1>UD    0x02280748
+                            urb MsgDesc: 116 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g49<8,8,1>UD    0x02280358
+                            urb MsgDesc: 53 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g49<8,8,1>UD    0x02280558
+                            urb MsgDesc: 85 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g49<8,8,1>UD    0x02280758
+                            urb MsgDesc: 117 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g50<8,8,1>UD    0x02280368
+                            urb MsgDesc: 54 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g50<8,8,1>UD    0x02280568
+                            urb MsgDesc: 86 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g50<8,8,1>UD    0x02280768
+                            urb MsgDesc: 118 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g53<8,8,1>UD    0x02280378
+                            urb MsgDesc: 55 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g53<8,8,1>UD    0x02280578
+                            urb MsgDesc: 87 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g53<8,8,1>UD    0x02280778
+                            urb MsgDesc: 119 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g54<8,8,1>UD    0x02280388
+                            urb MsgDesc: 56 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g54<8,8,1>UD    0x02280588
+                            urb MsgDesc: 88 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g54<8,8,1>UD    0x02280788
+                            urb MsgDesc: 120 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g55<8,8,1>UD    0x02280398
+                            urb MsgDesc: 57 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g55<8,8,1>UD    0x02280598
+                            urb MsgDesc: 89 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g55<8,8,1>UD    0x02280798
+                            urb MsgDesc: 121 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g56<8,8,1>UD    0x022803a8
+                            urb MsgDesc: 58 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g56<8,8,1>UD    0x022805a8
+                            urb MsgDesc: 90 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g56<8,8,1>UD    0x022807a8
+                            urb MsgDesc: 122 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g57<8,8,1>UD    0x022803b8
+                            urb MsgDesc: 59 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g57<8,8,1>UD    0x022805b8
+                            urb MsgDesc: 91 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g57<8,8,1>UD    0x022807b8
+                            urb MsgDesc: 123 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g58<8,8,1>UD    0x022803c8
+                            urb MsgDesc: 60 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g58<8,8,1>UD    0x022805c8
+                            urb MsgDesc: 92 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g58<8,8,1>UD    0x022807c8
+                            urb MsgDesc: 124 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g59<8,8,1>UD    0x022803d8
+                            urb MsgDesc: 61 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g59<8,8,1>UD    0x022805d8
+                            urb MsgDesc: 93 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g59<8,8,1>UD    0x022807d8
+                            urb MsgDesc: 125 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g60<8,8,1>UD    0x022803e8
+                            urb MsgDesc: 62 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g60<8,8,1>UD    0x022805e8
+                            urb MsgDesc: 94 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g60<8,8,1>UD    0x022807e8
+                            urb MsgDesc: 126 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g61<8,8,1>UD    0x022803f8
+                            urb MsgDesc: 63 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g61<8,8,1>UD    0x022805f8
+                            urb MsgDesc: 95 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g61<8,8,1>UD    0x022807f8
+                            urb MsgDesc: 127 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g10<1>UD        g62<8,8,1>UD    0x02280408
+                            urb MsgDesc: 64 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g62<8,8,1>UD    0x02280608
+                            urb MsgDesc: 96 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g14<1>UD        g62<8,8,1>UD    0x02280808
+                            urb MsgDesc: 128 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g8<1>UD         g63<8,8,1>UD    0x02280218
+                            urb MsgDesc: 33 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g10<1>UD        g63<8,8,1>UD    0x02280418
+                            urb MsgDesc: 65 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g12<1>UD        g63<8,8,1>UD    0x02280618
+                            urb MsgDesc: 97 SIMD8 read mlen 1 rlen 2        { align1 1Q };
+send(8)         g14<1>UD        g63<8,8,1>UD    0x02280818
+                            urb MsgDesc: 129 SIMD8 read mlen 1 rlen 2       { align1 1Q };
+send(8)         g29<1>UW        g18<8,8,1>UD    0x04420008
+                            sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(8)         g35<1>UW        g18<8,8,1>UD    0x04420109
+                            sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(8)         g41<1>UW        g18<8,8,1>UD    0x0442020a
+                            sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 2 mlen 2 rlen 4 { align1 1Q };
+send(8)         g2<1>UW         g18<8,8,1>UD    0x0442030b
+                            sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 3 mlen 2 rlen 4 { align1 1Q };
+send(8)         g6<1>UW         g18<8,8,1>UD    0x0442040c
+                            sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
+send(8)         g10<1>UW        g18<8,8,1>UD    0x0442050d
+                            sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 5 mlen 2 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g18<8,8,1>UD    0x0442060e
+                            sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 6 mlen 2 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x0442070f
+                            sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 7 mlen 2 rlen 4 { align1 1Q };
+send(16)        g32<1>UW        g22<8,8,1>UD    0x08840008
+                            sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(16)        g42<1>UW        g22<8,8,1>UD    0x08840109
+                            sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 1 mlen 4 rlen 8 { align1 1H };
+send(16)        g60<1>UW        g22<8,8,1>UD    0x0884020a
+                            sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 2 mlen 4 rlen 8 { align1 1H };
+send(16)        g70<1>UW        g22<8,8,1>UD    0x0884030b
+                            sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 3 mlen 4 rlen 8 { align1 1H };
+send(16)        g78<1>UW        g22<8,8,1>UD    0x0884040c
+                            sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 4 mlen 4 rlen 8 { align1 1H };
+send(16)        g86<1>UW        g22<8,8,1>UD    0x0884050d
+                            sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 5 mlen 4 rlen 8 { align1 1H };
+send(16)        g94<1>UW        g22<8,8,1>UD    0x0884060e
+                            sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 6 mlen 4 rlen 8 { align1 1H };
+send(16)        g52<1>UW        g22<8,8,1>UD    0x0884070f
+                            sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 7 mlen 4 rlen 8 { align1 1H };
+send(8)         g16<1>UW        g42<8,8,1>UD    0x04438101
+                            sampler MsgDesc: sample_lz SIMD8 Surface = 1 Sampler = 1 mlen 2 rlen 4 { align1 1Q };
+send(8)         g20<1>UW        g42<8,8,1>UD    0x04438202
+                            sampler MsgDesc: sample_lz SIMD8 Surface = 2 Sampler = 2 mlen 2 rlen 4 { align1 1Q };
+send(8)         g29<1>UW        g42<8,8,1>UD    0x04438404
+                            sampler MsgDesc: sample_lz SIMD8 Surface = 4 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
+send(8)         g38<1>UW        g42<8,8,1>UD    0x04438606
+                            sampler MsgDesc: sample_lz SIMD8 Surface = 6 Sampler = 6 mlen 2 rlen 4 { align1 1Q };
+send(8)         g124<1>UW       g42<8,8,1>UD    0x04438707
+                            sampler MsgDesc: sample_lz SIMD8 Surface = 7 Sampler = 7 mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g16<8,8,1>UD    0x044a0058
+                            urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0068
+                            urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0078
+                            urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0088
+                            urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0098
+                            urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a00a8
+                            urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a00b8
+                            urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a00c8
+                            urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a00d8
+                            urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a00e8
+                            urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a00f8
+                            urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0108
+                            urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0118
+                            urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0158
+                            urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0168
+                            urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0178
+                            urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0188
+                            urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0198
+                            urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a01a8
+                            urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a01b8
+                            urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a01c8
+                            urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a01d8
+                            urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a01e8
+                            urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a01f8
+                            urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g12<1>UD        g2<8,8,1>UD     0x044a0208
+                            urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q };
+send(8)         g14<1>UW        g15<8,8,1>UD    0x0a125001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q };
+send(8)         g15<1>UW        g20<8,8,1>UD    0x0a125102
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q };
+send(16)        g41<1>UW        g7<8,8,1>UD     0x14245001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 2 { align1 1H };
+send(16)        g43<1>UW        g17<8,8,1>UD    0x14245102
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 2 { align1 1H };
+send(8)         g2<1>UW         g5<8,8,1>UD     0x06223001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 2 { align1 1Q };
+send(16)        g2<1>UW         g7<8,8,1>UD     0x0c443001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1H };
+send(8)         g2<1>UW         g2<8,8,1>UD     0x06323001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q };
+send(16)        g2<1>UW         g24<8,8,1>UD    0x0c643001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H };
+send(8)         null<1>F        g120<8,8,1>F    0x8c0a0117
+                            urb MsgDesc: 17 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380128
+                            urb MsgDesc: 18 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380138
+                            urb MsgDesc: 19 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380148
+                            urb MsgDesc: 20 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380158
+                            urb MsgDesc: 21 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380168
+                            urb MsgDesc: 22 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380178
+                            urb MsgDesc: 23 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380188
+                            urb MsgDesc: 24 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x02380198
+                            urb MsgDesc: 25 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x023801a8
+                            urb MsgDesc: 26 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x023801b8
+                            urb MsgDesc: 27 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x023801c8
+                            urb MsgDesc: 28 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x023801d8
+                            urb MsgDesc: 29 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x023801e8
+                            urb MsgDesc: 30 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g11<1>UD        g1<8,8,1>UD     0x023801f8
+                            urb MsgDesc: 31 SIMD8 read mlen 1 rlen 3        { align1 1Q };
+send(8)         g10<1>UW        g2<8,8,1>UD     0x04420004
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g2<8,8,1>UD     0x08840004
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g10<1>UW        g2<8,8,1>UD     0x04420003
+                            sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g2<8,8,1>UD     0x08840003
+                            sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 8 { align1 1H };
+send(8)         g11<1>UD        g13<8,8,1>UD    0x042a0058
+                            urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a0068
+                            urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a0078
+                            urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a0088
+                            urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a0098
+                            urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a00a8
+                            urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a00b8
+                            urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a00c8
+                            urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a00d8
+                            urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a00e8
+                            urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a00f8
+                            urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a0108
+                            urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g11<8,8,1>UD    0x042a0118
+                            urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a0158
+                            urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a0168
+                            urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a0178
+                            urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a0188
+                            urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a0198
+                            urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a01a8
+                            urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a01b8
+                            urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a01c8
+                            urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a01d8
+                            urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a01e8
+                            urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a01f8
+                            urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g2<1>UD         g3<8,8,1>UD     0x042a0208
+                            urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q };
+send(8)         g9<1>UW         g15<8,8,1>UD    0x021ab102
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 1 { align1 1Q };
+send(8)         g10<1>UW        g16<8,8,1>UD    0x021ab203
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 1 { align1 1Q };
+send(8)         g11<1>UW        g17<8,8,1>UD    0x021ab304
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 1 { align1 1Q };
+send(8)         g12<1>UW        g18<8,8,1>UD    0x021ab405
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 1 { align1 1Q };
+send(8)         g13<1>UW        g19<8,8,1>UD    0x021ab506
+                            sampler MsgDesc: sampleinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 1 { align1 1Q };
+send(16)        g14<1>UW        g16<8,8,1>UD    0x022cb102
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 2 Sampler = 1 mlen 1 rlen 2 { align1 1H };
+send(16)        g16<1>UW        g18<8,8,1>UD    0x022cb203
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 3 Sampler = 2 mlen 1 rlen 2 { align1 1H };
+send(16)        g18<1>UW        g20<8,8,1>UD    0x022cb304
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 4 Sampler = 3 mlen 1 rlen 2 { align1 1H };
+send(16)        g20<1>UW        g22<8,8,1>UD    0x022cb405
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 5 Sampler = 4 mlen 1 rlen 2 { align1 1H };
+send(16)        g22<1>UW        g24<8,8,1>UD    0x022cb506
+                            sampler MsgDesc: sampleinfo SIMD16 Surface = 6 Sampler = 5 mlen 1 rlen 2 { align1 1H };
+send(8)         g14<1>UW        g11<8,8,1>UD    0x0a4b0203
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 3 Sampler = 2 mlen 5 rlen 4 { align1 1Q };
+send(8)         g18<1>UW        g18<8,8,1>UD    0x0c4b0304
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 4 Sampler = 3 mlen 6 rlen 4 { align1 1Q };
+send(8)         g22<1>UW        g24<8,8,1>UD    0x084b0405
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 5 Sampler = 4 mlen 4 rlen 4 { align1 1Q };
+send(16)        g18<1>UW        g26<8,8,1>UD    0x128d0203
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 3 Sampler = 2 mlen 9 rlen 8 { align1 1H };
+send(16)        g26<1>UW        g35<8,8,1>UD    0x168d0304
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 4 Sampler = 3 mlen 11 rlen 8 { align1 1H };
+send(16)        g34<1>UW        g46<8,8,1>UD    0x0e8d0405
+                            sampler MsgDesc: gather4_c SIMD16 Surface = 5 Sampler = 4 mlen 7 rlen 8 { align1 1H };
+send(8)         g124<1>UW       g9<8,8,1>UD     0x0c4b0000
+                            sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q };

diff --git a/src/intel/tools/tests/gen9/send.expected b/src/intel/tools/tests/gen9/send.expected
new file mode 100644 (file)
index 0000000..9ed63c7
--- /dev/null
+++ b/src/intel/tools/tests/gen9/send.expected
@@ -0,0 +1,1803 @@
+31 00 60 06 e0 3a 00 20 60 0f 8d 06 17 00 08 8a
+31 00 60 06 e0 3a 00 20 a0 01 8d 06 07 00 08 12
+31 00 60 06 e0 3a 00 20 60 0f 8d 06 27 00 08 8a
+31 00 80 09 0c 02 20 21 40 00 00 06 00 03 28 02
+31 00 60 06 e0 3a 00 20 e0 0e 8d 06 17 00 08 92
+31 00 80 07 44 12 00 20 e0 0f 8d 06 10 00 00 82
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diff --git a/src/intel/tools/tests/gen9/sendc.asm b/src/intel/tools/tests/gen9/sendc.asm
new file mode 100644 (file)
index 0000000..c340cb5
--- /dev/null
+++ b/src/intel/tools/tests/gen9/sendc.asm
@@ -0,0 +1,264 @@
+sendc(8)        null<1>UW       g124<0,1,0>F    0x88031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g120<0,1,0>F    0x90031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       g114<0,1,0>F    0x82031100
+                            render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g124<8,8,1>UD   0x880ba001
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g121<8,8,1>UD   0x8e0da001
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g125<8,8,1>UD   0x860a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g123<8,8,1>UD   0x8a0c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT };
+(+f0.1) sendc(8) null<1>UW      g124<0,1,0>F    0x88031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g122<8,8,1>UD   0x8c0be001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g117<8,8,1>UD   0x960de001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g124<8,8,1>UD   0x880a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g121<8,8,1>UD   0x8e0c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g118<8,8,1>UD   0x940a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g125<8,8,1>UD   a0<0,1,0>UD     0x80000200
+                            sampler MsgDesc: indirect                       { align1 1Q EOT };
+sendc(8)        null<1>UW       g124<8,8,1>UD   0x880a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g121<8,8,1>UD   0x8e0bc001
+                            sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g121<8,8,1>UD   0x8e0a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g125<8,8,1>UD   0x860a2001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g123<8,8,1>UD   0x8a0c2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<0,1,0>F    0x8c0b1401
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<0,1,0>F    0x940b1001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g13<0,1,0>F     0x0e0b0401
+                            render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g121<0,1,0>F    0x8e0b1402
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g7<0,1,0>F      0x180b0001
+                            render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g116<0,1,0>F    0x980b1002
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g123<8,8,1>UD   0x8a0a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g119<8,8,1>UD   0x920c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT };
+sendc(1)        g2<1>UW         g2<0,1,0>UW     0x0209c000
+                            data MsgDesc: ( DC mfence, 0, 0) mlen 1 rlen 0  { align1 WE_all 1N };
+sendc(8)        null<1>UW       g120<8,8,1>UD   0x900b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g123<8,8,1>UD   0x8a0b4001
+                            sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(8)        g6<1>F          g2<0,1,0>UD     0x044b4100
+                            render MsgDesc: RT read MsgCtrl = 0x1 Surface = 0 mlen 2 rlen 4 { align1 1Q };
+sendc(16)       g9<1>F          g27<0,1,0>UD    0x048b4000
+                            render MsgDesc: RT read MsgCtrl = 0x0 Surface = 0 mlen 2 rlen 8 { align1 1H };
+sendc(8)        null<1>UW       g124<8,8,1>UD   0x880a3001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g121<8,8,1>UD   0x8e0c3001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g123<0,1,0>F    0x8a031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<0,1,0>F    0x94031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g5<0,1,0>F      0x0c0b0400
+                            render MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g5<0,1,0>F      0x0c0b0401
+                            render MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g5<0,1,0>F      0x0c0b0402
+                            render MsgDesc: RT write SIMD8 Surface = 2 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g5<0,1,0>F      0x0c0b0403
+                            render MsgDesc: RT write SIMD8 Surface = 3 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g5<0,1,0>F      0x0c0b0404
+                            render MsgDesc: RT write SIMD8 Surface = 4 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g122<0,1,0>F    0x8c0b1405
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 5 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g5<0,1,0>F      0x140b0000
+                            render MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g5<0,1,0>F      0x140b0001
+                            render MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g5<0,1,0>F      0x140b0002
+                            render MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g5<0,1,0>F      0x140b0003
+                            render MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g5<0,1,0>F      0x140b0004
+                            render MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g118<0,1,0>F    0x940b1005
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        g6<1>F          g6<0,1,0>UD     0x044b4101
+                            render MsgDesc: RT read MsgCtrl = 0x1 Surface = 1 mlen 2 rlen 4 { align1 1Q };
+sendc(8)        g10<1>F         g10<0,1,0>UD    0x044b4102
+                            render MsgDesc: RT read MsgCtrl = 0x1 Surface = 2 mlen 2 rlen 4 { align1 1Q };
+sendc(8)        g14<1>F         g14<0,1,0>UD    0x044b4103
+                            render MsgDesc: RT read MsgCtrl = 0x1 Surface = 3 mlen 2 rlen 4 { align1 1Q };
+sendc(8)        null<1>UW       g122<0,1,0>F    0x8c0b1403
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       g32<1>F         g14<0,1,0>UD    0x048b4001
+                            render MsgDesc: RT read MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 8 { align1 1H };
+sendc(16)       g40<1>F         g16<0,1,0>UD    0x048b4002
+                            render MsgDesc: RT read MsgCtrl = 0x0 Surface = 2 mlen 2 rlen 8 { align1 1H };
+sendc(16)       g48<1>F         g18<0,1,0>UD    0x048b4003
+                            render MsgDesc: RT read MsgCtrl = 0x0 Surface = 3 mlen 2 rlen 8 { align1 1H };
+sendc(16)       null<1>UW       g118<0,1,0>F    0x940b1003
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g124<8,8,1>UD   0x880a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g121<8,8,1>UD   0x8e0c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g125<8,8,1>UD   0x860ba001
+                            sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g123<8,8,1>UD   0x8a0da001
+                            sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g126<8,8,1>UD   0x840a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g125<8,8,1>UD   0x860c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g124<8,8,1>UD   0x880a2001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g121<8,8,1>UD   0x8e0c2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g123<8,8,1>UD   0x8a0be001
+                            sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g119<8,8,1>UD   0x920de001
+                            sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g120<8,8,1>UD   0x900a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g123<8,8,1>UD   0x8a0a2001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g119<8,8,1>UD   0x920c2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g125<8,8,1>UD   0x860a0304
+                            sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g123<8,8,1>UD   0x8a0c0304
+                            sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 5 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>UD   0x8c0a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g117<8,8,1>UD   0x960c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g125<8,8,1>UD   0x860a3001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g123<8,8,1>UD   0x8a0c3001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<0,1,0>F    0x8c0b1402
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<0,1,0>F    0x940b1002
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g124<8,8,1>UD   0x880a6001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g121<8,8,1>UD   0x8e0c6001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g123<8,8,1>UD   0x8a0a5001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g119<8,8,1>UD   0x920c5001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>UD   0x8c0a2001
+                            sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g117<8,8,1>UD   0x960c2001
+                            sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<8,8,1>UD   0x8c0bc001
+                            sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g117<8,8,1>UD   0x960dc001
+                            sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<0,1,0>F    0x8c0b1400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<0,1,0>F    0x940b1000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g124<8,8,1>UD   0x880a7001
+                            sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g121<8,8,1>UD   0x8e0c7001
+                            sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g118<0,1,0>F    0x940b1200
+                            render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g3<0,1,0>F      0x140b1200
+                            render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g118<0,1,0>F    0x940b1300
+                            render MsgDesc: RT write SIMD8/DualSrcHigh LastRT Surface = 0 mlen 10 rlen 0 { align1 2Q EOT };
+sendc(8)        null<1>UW       g123<8,8,1>UD   0x8a0a0001
+                            sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g119<8,8,1>UD   0x920c0001
+                            sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT };
+sendc(16)       g11<1>F         g37<0,1,0>UD    0x048b6000
+                            render MsgDesc: RT read MsgCtrl = 0x32 Surface = 0 mlen 2 rlen 8 { align1 1H };
+sendc(8)        null<1>UW       g23<0,1,0>F     0x0c0b0405
+                            render MsgDesc: RT write SIMD8 Surface = 5 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g29<0,1,0>F     0x0c0b0406
+                            render MsgDesc: RT write SIMD8 Surface = 6 mlen 6 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g122<0,1,0>F    0x8c0b1407
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 7 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g57<0,1,0>F     0x140b0005
+                            render MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g67<0,1,0>F     0x140b0006
+                            render MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g118<0,1,0>F    0x940b1007
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g125<8,8,1>UD   0x860a1001
+                            sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g123<8,8,1>UD   0x8a0c1001
+                            sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g10<0,1,0>F     0x0e0b0400
+                            render MsgDesc: RT write SIMD8 Surface = 0 mlen 7 rlen 0 { align1 1Q };
+sendc(8)        null<1>UW       g121<0,1,0>F    0x8e0b1401
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 7 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g2<0,1,0>F      0x160b0000
+                            render MsgDesc: RT write SIMD16 Surface = 0 mlen 11 rlen 0 { align1 1H };
+sendc(16)       null<1>UW       g117<0,1,0>F    0x960b1001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 11 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<0,1,0>F    0x8c0b1404
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 4 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<0,1,0>F    0x940b1004
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g122<0,1,0>F    0x8c0b1406
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 6 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g118<0,1,0>F    0x940b1006
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       g119<0,1,0>F    0x92031000
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 9 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       g116<0,1,0>F    0x980b1001
+                            render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 12 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g123<8,8,1>UD   0x8a0a6001
+                            sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g119<8,8,1>UD   0x920c6001
+                            sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g125<8,8,1>UD   0x860a0102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g123<8,8,1>UD   0x8a0c0102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 5 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g124<8,8,1>UD   0x880a5001
+                            sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g121<8,8,1>UD   0x8e0c5001
+                            sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g123<8,8,1>UD   0x8a0a4001
+                            sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g123<8,8,1>UD   0x8a0a3001
+                            sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g119<8,8,1>UD   0x920c3001
+                            sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g125<8,8,1>UD   0x860a0f10
+                            sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 3 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g123<8,8,1>UD   0x8a0c0f10
+                            sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 5 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g126<8,8,1>UD   0x840a0102
+                            sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g125<8,8,1>UD   0x860c0102
+                            sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 3 rlen 0 { align1 1H EOT };
+sendc(16)       null<1>UW       g11<0,1,0>F     0x180b0000
+                            render MsgDesc: RT write SIMD16 Surface = 0 mlen 12 rlen 0 { align1 1H };
+sendc(8)        null<1>UW       g122<0,1,0>F    0x8c031400
+                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT };
+sendc(8)        null<1>UW       g125<8,8,1>UD   0x860a0506
+                            sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 3 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g123<8,8,1>UD   0x8a0c0506
+                            sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 5 rlen 0 { align1 1H EOT };
+sendc(8)        null<1>UW       g125<8,8,1>UD   0x860b8001
+                            sampler MsgDesc: sample_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT };
+sendc(16)       null<1>UW       g123<8,8,1>UD   0x8a0d8001
+                            sampler MsgDesc: sample_lz SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT };

diff --git a/src/intel/tools/tests/gen9/sendc.expected b/src/intel/tools/tests/gen9/sendc.expected
new file mode 100644 (file)
index 0000000..b4c30df
--- /dev/null
+++ b/src/intel/tools/tests/gen9/sendc.expected
@@ -0,0 +1,132 @@
+32 00 60 05 40 3a 00 20 80 0f 00 06 00 14 03 88
+32 00 80 05 40 3a 00 20 00 0f 00 06 00 10 03 90
+32 00 80 05 40 3a 00 20 40 0e 00 06 00 11 03 82
+32 00 60 02 40 02 00 20 80 0f 8d 06 01 a0 0b 88
+32 00 80 02 40 02 00 20 20 0f 8d 06 01 a0 0d 8e
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+32 00 80 02 40 02 00 20 a0 0f 8d 06 02 01 0c 86
+32 00 80 05 40 3a 00 20 60 01 00 06 00 00 0b 18
+32 00 60 05 40 3a 00 20 40 0f 00 06 00 14 03 8c
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+32 00 80 02 40 02 00 20 60 0f 8d 06 01 80 0d 8a

diff --git a/src/intel/tools/tests/gen9/sends.asm b/src/intel/tools/tests/gen9/sends.asm
new file mode 100644 (file)
index 0000000..b803f4f
--- /dev/null
+++ b/src/intel/tools/tests/gen9/sends.asm
@@ -0,0 +1,268 @@
+sends(8)        nullUD          g34UD           g36UD           0x04035001                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q };
+sends(8)        nullUD          g1UD            g3UD            0x04036001                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 2Q };
+sends(8)        nullUD          g21UD           g23UD           0x04035001                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q };
+(+f1.0) sends(8) g9UD           g2UD            g3UD            0x0210b201                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+(+f1.0) sends(16) g11UD         g2UD            g6UD            0x0420a201                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+sends(16)       nullUD          g6UD            g8UD            0x04025efe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 254, SIMD16, Mask = 0xe) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+sends(16)       nullUD          g10UD           g12UD           0x040087fe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, add) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+(+f1.0) sends(8) nullUD         g11UD           g5UD            0x04035002                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g2UD            g11UD           0x04036002                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g3UD            g4UD            0x02026001                0x00000100
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
+(+f1.0) sends(16) nullUD        g3UD            g5UD            0x04025001                0x00000200
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 8 rlen 0 { align1 1H };
+sends(8)        nullUD          g2UD            g3UD            0x02009b00                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, imin) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g2UD            g4UD            0x04035e01                0x00000040
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g45UD           g41UD           0x04036e01                0x00000040
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g2UD            g4UD            0x04018c01                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, umax) mlen 2 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g45UD           g41UD           0x04019c01                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, umax) mlen 2 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g2UD            g4UD            0x04018401                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, mov) mlen 2 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g45UD           g41UD           0x04019401                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, mov) mlen 2 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g2UD            g4UD            0x04018e01                0x00000080
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, cmpwr) mlen 2 ex_mlen 2 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g11UD           g13UD           0x04019e01                0x00000080
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, cmpwr) mlen 2 ex_mlen 2 rlen 0 { align1 2Q };
+sends(16)       nullUD          g3UD            g1UD            0x04008dfe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, umin) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+sends(16)       nullUD          g5UD            g1UD            0x04008bfe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, imin) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+sends(16)       nullUD          g3UD            g1UD            0x04008cfe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, umax) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+sends(16)       nullUD          g5UD            g1UD            0x04008afe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, imax) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+sends(16)       nullUD          g3UD            g1UD            0x040081fe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, and) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+sends(16)       nullUD          g3UD            g1UD            0x040082fe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, or) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+sends(16)       nullUD          g3UD            g1UD            0x040083fe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, xor) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+sends(16)       nullUD          g3UD            g1UD            0x040084fe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, mov) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+sends(16)       nullUD          g3UD            g7UD            0x04008efe                0x00000100
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, cmpwr) mlen 2 ex_mlen 4 rlen 0 { align1 1H };
+sends(16)       g1UD            g19UD           g21UD           0x0420a4fe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, mov) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+sends(16)       g13UD           g23UD           g25UD           0x0420a2fe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, or) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+sends(8)        nullUD          g14UD           g10UD           0x02026000                0x00000100
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 0, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
+sends(8)        nullUD          g4UD            g2UD            0x02026efe                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 254, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+sends(8)        g7UD            g19UD           g20UD           0x0210bdfe                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD8, umin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+sends(8)        g11UD           g25UD           g26UD           0x0210b4fe                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD8, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+sends(16)       g1UD            g14UD           g16UD           0x0420a7fe                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, add) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+(+f1.0) sends(8) nullUD         g2UD            g13UD           g[a0]UD         0x00000100
+                            dp data 1 MsgDesc: indirect ex_mlen 4           { align1 1Q };
+(+f1.0) sends(8) nullUD         g5UD            g6UD            0x02026e01                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g5UD            g6UD            0x02026e02                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(16) nullUD        g6UD            g8UD            0x04025e01                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+(+f1.0) sends(16) nullUD        g6UD            g8UD            0x04025e02                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+(+f1.0) sends(8) g3UD           g8UD            g9UD            0x0210b702                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, add) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+(+f1.0) sends(16) g4UD          g11UD           g13UD           0x0420a702                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, add) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+(+f1.0) sends(8) nullUD         g5UD            g3UD            0x02026c01                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0xc) mlen 1 ex_mlen 2 rlen 0 { align1 1Q };
+(+f1.0) sends(16) nullUD        g19UD           g21UD           0x04025c01                0x00000100
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0xc) mlen 2 ex_mlen 4 rlen 0 { align1 1H };
+sends(8)        nullUD          g14UD           g15UD           0x02026e00                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 0, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+sends(8)        nullUD          g16UD           g9UD            0x02026c00                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 0, SIMD8, Mask = 0xc) mlen 1 ex_mlen 2 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g15UD           g18UD           0x06035001                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 3 ex_mlen 4 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g34UD           g11UD           0x06036001                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 3 ex_mlen 4 rlen 0 { align1 2Q };
+(+f1.0) sends(8) g13UD          g18UD           g19UD           0x0210bb02                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, imin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+(+f1.0) sends(8) g16UD          g25UD           g30UD           0x0210b402                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+(+f1.0) sends(16) g22UD         g27UD           g29UD           0x0420ab02                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, imin) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+(+f1.0) sends(16) g25UD         g37UD           g2UD            0x0420a402                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, mov) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+sends(16)       nullUD          g8UD            g10UD           0x04025c02                0x00000100
+                            dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xc) mlen 2 ex_mlen 4 rlen 0 { align1 1H };
+(+f1.0) sends(8) g127UD         g2UD            g9UD            0x0411a401                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, mov) mlen 2 ex_mlen 1 rlen 1 { align1 1Q };
+(+f1.0) sends(8) g127UD         g2UD            g4UD            0x0411b401                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, mov) mlen 2 ex_mlen 1 rlen 1 { align1 2Q };
+(+f1.0) sends(8) nullUD         g14UD           g15UD           0x02009201                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(16) nullUD        g24UD           g26UD           0x04008201                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+sends(8)        nullUD          g124UD          g11UD           0x04035000                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 0, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g5UD            g6UD            0x02035e02                0x00000040
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g7UD            g9UD            0x02036e02                0x00000040
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 2Q };
+sends(8)        nullUD          g11UD           g21UD           0x04035e00                0x00000040
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 0, SIMD16, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 1Q };
+sends(8)        nullUD          g15UD           g27UD           0x04035e02                0x00000040
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 1Q };
+sends(8)        nullUD          g16UD           g28UD           0x04036e02                0x00000040
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) g13UD          g19UD           g20UD           0x0210bd02                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, umin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+(+f1.0) sends(16) g22UD         g28UD           g30UD           0x0420ad02                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, umin) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+(+f1.0) sends(8) nullUD         g2UD            g4UD            0x04035c02                0x00000080
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xc) mlen 2 ex_mlen 2 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g38UD           g40UD           0x04036c02                0x00000080
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xc) mlen 2 ex_mlen 2 rlen 0 { align1 2Q };
+sends(8)        nullUD          g17UD           g6UD            0x02035000                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 0, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
+sends(8)        g124UD          g20UD           g21UD           0x0211a700                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, add) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+sends(8)        g124UD          g20UD           g21UD           0x0211ad00                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, umin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+sends(8)        g124UD          g20UD           g21UD           0x0211ac00                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, umax) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+sends(8)        g124UD          g20UD           g21UD           0x0211a100                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, and) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+sends(8)        g124UD          g20UD           g21UD           0x0211a200                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, or) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+sends(8)        g124UD          g20UD           g21UD           0x0211a300                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, xor) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+sends(8)        g124UD          g20UD           g21UD           0x0211a400                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+sends(8)        g124UD          g21UD           g6UD            0x0211ae00                0x00000080
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, cmpwr) mlen 1 ex_mlen 2 rlen 1 { align1 1Q };
+(+f1.0) sends(8) nullUD         g16UD           g2UD            0x02035001                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g29UD           g8UD            0x02036001                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g14UD           g18UD           0x02035e01                0x00000040
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g23UD           g7UD            0x02036e01                0x00000040
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g17UD           g2UD            0x02035002                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g28UD           g3UD            0x02036002                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g17UD           g2UD            0x02035003                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g23UD           g6UD            0x02036003                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g12UD           g13UD           0x02009701                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, add) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(16) nullUD        g20UD           g22UD           0x04008701                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, add) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+sends(8)        g7UD            g18UD           g19UD           0x0210bbfe                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD8, imin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+sends(8)        nullUD          g6UD            g1UD            0x04035003                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q };
+sends(8)        nullUD          g8UD            g10UD           0x04036003                0x00000100
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 2Q };
+(+f1.0) sends(8) g3UD           g21UD           g20UD           0x0210b701                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, add) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+(+f1.0) sends(8) g5UD           g21UD           g20UD           0x0210bd01                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+(+f1.0) sends(8) g6UD           g21UD           g20UD           0x0210bc01                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umax) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+(+f1.0) sends(8) g7UD           g21UD           g20UD           0x0210b101                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, and) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+(+f1.0) sends(8) g9UD           g21UD           g20UD           0x0210b301                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, xor) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+(+f1.0) sends(8) g10UD          g21UD           g20UD           0x0210b401                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q };
+(+f1.0) sends(8) g11UD          g21UD           g11UD           0x0210be01                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, cmpwr) mlen 1 ex_mlen 2 rlen 1 { align1 1Q };
+(+f1.0) sends(16) g3UD          g38UD           g36UD           0x0420a701                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, add) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+(+f1.0) sends(16) g7UD          g38UD           g36UD           0x0420ad01                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umin) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+(+f1.0) sends(16) g9UD          g38UD           g36UD           0x0420ac01                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umax) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+(+f1.0) sends(16) g11UD         g38UD           g36UD           0x0420a101                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, and) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+(+f1.0) sends(16) g15UD         g38UD           g36UD           0x0420a301                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, xor) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+(+f1.0) sends(16) g17UD         g38UD           g36UD           0x0420a401                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, mov) mlen 2 ex_mlen 2 rlen 2 { align1 1H };
+(+f1.0) sends(16) g19UD         g38UD           g21UD           0x0420ae01                0x00000100
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, cmpwr) mlen 2 ex_mlen 4 rlen 2 { align1 1H };
+sends(8)        nullUD          g4UD            g12UD           0x04035e09                0x00000040
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 9, SIMD16, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 1Q };
+sends(8)        nullUD          g5UD            g13UD           0x04036e09                0x00000040
+                            dp data 1 MsgDesc: ( DC typed surface write, Surface = 9, SIMD8, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g14UD           g18UD           0x02009d01                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umin) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g17UD           g19UD           0x02009c01                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umax) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g19UD           g20UD           0x02009101                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, and) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g27UD           g22UD           0x02009301                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, xor) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g29UD           g23UD           0x02009401                0x00000040
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, mov) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g32UD           g2UD            0x02009e01                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, cmpwr) mlen 1 ex_mlen 2 rlen 0 { align1 1Q };
+(+f1.0) sends(16) nullUD        g18UD           g32UD           0x04008d01                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umin) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+(+f1.0) sends(16) nullUD        g24UD           g33UD           0x04008c01                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umax) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+(+f1.0) sends(16) nullUD        g30UD           g34UD           0x04008101                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, and) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+(+f1.0) sends(16) nullUD        g46UD           g36UD           0x04008301                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, xor) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+(+f1.0) sends(16) nullUD        g49UD           g37UD           0x04008401                0x00000080
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, mov) mlen 2 ex_mlen 2 rlen 0 { align1 1H };
+(+f1.0) sends(16) nullUD        g56UD           g2UD            0x04008e01                0x00000100
+                            dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, cmpwr) mlen 2 ex_mlen 4 rlen 0 { align1 1H };
+(+f1.0) sends(8) nullUD         g20UD           g21UD           0x02018101                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, and) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g3UD            g38UD           0x02019101                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, and) mlen 1 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g19UD           g20UD           0x02018201                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, or) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g3UD            g36UD           0x02019201                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, or) mlen 1 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g19UD           g20UD           0x02018301                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, xor) mlen 1 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g3UD            g36UD           0x02019301                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, xor) mlen 1 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g2UD            g18UD           0x04018701                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, add) mlen 2 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g2UD            g4UD            0x04019701                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, add) mlen 2 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g2UD            g18UD           0x04018d01                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, umin) mlen 2 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g2UD            g4UD            0x04019d01                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, umin) mlen 2 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g2UD            g18UD           0x04018101                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, and) mlen 2 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g2UD            g4UD            0x04019101                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, and) mlen 2 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g2UD            g18UD           0x04018201                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, or) mlen 2 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g2UD            g4UD            0x04019201                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, or) mlen 2 ex_mlen 1 rlen 0 { align1 2Q };
+(+f1.0) sends(8) nullUD         g2UD            g18UD           0x04018301                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, xor) mlen 2 ex_mlen 1 rlen 0 { align1 1Q };
+(+f1.0) sends(8) nullUD         g2UD            g4UD            0x04019301                0x00000040
+                            dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, xor) mlen 2 ex_mlen 1 rlen 0 { align1 2Q };

diff --git a/src/intel/tools/tests/gen9/sends.expected b/src/intel/tools/tests/gen9/sends.expected
new file mode 100644 (file)
index 0000000..ff7a123
--- /dev/null
+++ b/src/intel/tools/tests/gen9/sends.expected
@@ -0,0 +1,134 @@
+33 00 60 0c 10 40 02 00 44 04 00 00 01 50 03 04
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+33 00 60 0c 18 50 81 0f 81 02 00 00 00 a4 11 02
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+33 00 61 0c 1a 40 a1 00 a1 02 00 00 01 bd 10 02
+33 00 61 0c 1a 40 c1 00 a1 02 00 00 01 bc 10 02
+33 00 61 0c 1a 40 e1 00 a1 02 00 00 01 b1 10 02
+33 00 61 0c 1a 40 21 01 a1 02 00 00 01 b3 10 02
+33 00 61 0c 1a 40 41 01 a1 02 00 00 01 b4 10 02
+33 00 61 0c 1a b0 60 01 a2 02 00 00 01 be 10 02
+33 00 81 0c 1a 40 62 00 c2 04 00 00 01 a7 20 04
+33 00 81 0c 1a 40 e2 00 c2 04 00 00 01 ad 20 04
+33 00 81 0c 1a 40 22 01 c2 04 00 00 01 ac 20 04
+33 00 81 0c 1a 40 62 01 c2 04 00 00 01 a1 20 04
+33 00 81 0c 1a 40 e2 01 c2 04 00 00 01 a3 20 04
+33 00 81 0c 1a 40 22 02 c2 04 00 00 01 a4 20 04
+33 00 81 0c 1a 50 61 02 c4 04 00 00 01 ae 20 04
+33 00 60 0c 10 c0 00 00 81 00 00 00 09 5e 03 04
+33 10 60 0c 10 d0 00 00 a1 00 00 00 09 6e 03 04
+33 00 61 0c 12 20 01 00 c1 01 00 00 01 9d 00 02
+33 00 61 0c 12 30 01 00 21 02 00 00 01 9c 00 02
+33 00 61 0c 12 40 01 00 61 02 00 00 01 91 00 02
+33 00 61 0c 12 60 01 00 61 03 00 00 01 93 00 02
+33 00 61 0c 12 70 01 00 a1 03 00 00 01 94 00 02
+33 00 61 0c 12 20 00 00 02 04 00 00 01 9e 00 02
+33 00 81 0c 12 00 02 00 42 02 00 00 01 8d 00 04
+33 00 81 0c 12 10 02 00 02 03 00 00 01 8c 00 04
+33 00 81 0c 12 20 02 00 c2 03 00 00 01 81 00 04
+33 00 81 0c 12 40 02 00 c2 05 00 00 01 83 00 04
+33 00 81 0c 12 50 02 00 22 06 00 00 01 84 00 04
+33 00 81 0c 12 20 00 00 04 07 00 00 01 8e 00 04
+33 00 61 0c 12 50 01 00 81 02 00 00 01 81 01 02
+33 10 61 0c 12 60 02 00 61 00 00 00 01 91 01 02
+33 00 61 0c 12 40 01 00 61 02 00 00 01 82 01 02
+33 10 61 0c 12 40 02 00 61 00 00 00 01 92 01 02
+33 00 61 0c 12 40 01 00 61 02 00 00 01 83 01 02
+33 10 61 0c 12 40 02 00 61 00 00 00 01 93 01 02
+33 00 61 0c 12 20 01 00 41 00 00 00 01 87 01 04
+33 10 61 0c 12 40 00 00 41 00 00 00 01 97 01 04
+33 00 61 0c 12 20 01 00 41 00 00 00 01 8d 01 04
+33 10 61 0c 12 40 00 00 41 00 00 00 01 9d 01 04
+33 00 61 0c 12 20 01 00 41 00 00 00 01 81 01 04
+33 10 61 0c 12 40 00 00 41 00 00 00 01 91 01 04
+33 00 61 0c 12 20 01 00 41 00 00 00 01 82 01 04
+33 10 61 0c 12 40 00 00 41 00 00 00 01 92 01 04
+33 00 61 0c 12 20 01 00 41 00 00 00 01 83 01 04
+33 10 61 0c 12 40 00 00 41 00 00 00 01 93 01 04

diff --git a/src/intel/tools/tests/gen9/shl.asm b/src/intel/tools/tests/gen9/shl.asm
new file mode 100644 (file)
index 0000000..03484a2
--- /dev/null
+++ b/src/intel/tools/tests/gen9/shl.asm
@@ -0,0 +1,13 @@
+shl(16)         g18<1>D         g20<8,8,1>D     0x00000002UD    { align1 1H };
+shl(8)          g18<1>D         g17<8,8,1>D     0x00000002UD    { align1 1Q };
+shl(1)          g8<1>UD         g5<0,1,0>UD     0x00000008UD    { align1 WE_all 1N };
+shl(8)          g4<1>UD         g6<8,8,1>UD     g3<8,8,1>UD     { align1 1Q };
+shl(1)          a0<1>UD         g43<0,1,0>UD    0x00000002UD    { align1 WE_all 1N };
+shl(16)         g116<1>D        g1<0,1,0>D      0x00000005UD    { align1 2H };
+shl(8)          g26<1>UD        g34<8,8,1>UW    0x00000002UD    { align1 1Q };
+shl(8)          g3<1>UD         g23<8,8,1>UD    g21<8,8,1>UD    { align1 WE_all 1Q };
+shl(16)         g10<1>UD        g10<8,8,1>UD    0x00000010UD    { align1 1H };
+shl(1)          g14<1>UD        g21<0,1,0>UD    0x00000008UD    { align1 WE_all 3N };
+shl(8)          g11<1>Q         g5<4,4,1>Q      g3<4,4,1>UD     { align1 1Q };
+shl(1)          a0<1>UD         g13<0,1,0>D     0x00000002UD    { align1 WE_all 1N };
+shl(8)          g22<1>Q         g8<4,4,1>Q      g4<4,4,1>UD     { align1 2Q };

diff --git a/src/intel/tools/tests/gen9/shl.expected b/src/intel/tools/tests/gen9/shl.expected
new file mode 100644 (file)
index 0000000..0b09a78
--- /dev/null
+++ b/src/intel/tools/tests/gen9/shl.expected
@@ -0,0 +1,13 @@
+09 00 80 00 28 0a 40 22 80 02 8d 06 02 00 00 00
+09 00 60 00 28 0a 40 22 20 02 8d 06 02 00 00 00
+09 00 00 00 0c 02 00 21 a0 00 00 06 08 00 00 00
+09 00 60 00 08 02 80 20 c0 00 8d 02 60 00 8d 00
+09 00 00 00 04 02 00 22 60 05 00 06 02 00 00 00
+09 20 80 00 28 0a 80 2e 20 00 00 06 05 00 00 00
+09 00 60 00 08 12 40 23 40 04 8d 06 02 00 00 00
+09 00 60 00 0c 02 60 20 e0 02 8d 02 a0 02 8d 00
+09 00 80 00 08 02 40 21 40 01 8d 06 10 00 00 00
+09 10 00 00 0c 02 c0 21 a0 02 00 06 08 00 00 00
+09 00 60 00 28 4b 60 21 a0 00 69 02 60 00 69 00
+09 00 00 00 04 0a 00 22 a0 01 00 06 02 00 00 00
+09 10 60 00 28 4b c0 22 00 01 69 02 80 00 69 00

diff --git a/src/intel/tools/tests/gen9/shr.asm b/src/intel/tools/tests/gen9/shr.asm
new file mode 100644 (file)
index 0000000..f64c617
--- /dev/null
+++ b/src/intel/tools/tests/gen9/shr.asm
@@ -0,0 +1,8 @@
+shr(8)          g20<1>UD        g19<8,8,1>UD    0x00000001UD    { align1 1Q };
+shr(16)         g43<1>UD        g41<8,8,1>UD    0x00000001UD    { align1 1H };
+shr.z.f0.0(8)   g3<1>UD         g1<8,8,1>UD     0x0000001bUD    { align1 1Q };
+shr(16)         g8<1>UW         g1<1,8,0>UB     0x44440000V     { align1 1H };
+shr.z.f0.0(8)   null<1>UD       g1<8,8,1>UD     0x0000001bUD    { align1 1Q };
+shr(8)          g3<1>UW         g1.28<1,8,0>UB  0x76543210V     { align1 1Q };
+shr(8)          g3<2>UW         g5<8,8,1>UD     g4<8,8,1>UW     { align1 1Q };
+shr(16)         g20<2>UW        g15<8,8,1>UD    g13<8,8,1>UW    { align1 1H };

diff --git a/src/intel/tools/tests/gen9/shr.expected b/src/intel/tools/tests/gen9/shr.expected
new file mode 100644 (file)
index 0000000..58830ed
--- /dev/null
+++ b/src/intel/tools/tests/gen9/shr.expected
@@ -0,0 +1,8 @@
+08 00 60 00 08 02 80 22 60 02 8d 06 01 00 00 00
+08 00 80 00 08 02 60 25 20 05 8d 06 01 00 00 00
+08 00 60 01 08 02 60 20 20 00 8d 06 1b 00 00 00
+08 00 80 00 48 22 00 21 20 00 2c 36 00 00 44 44
+08 00 60 01 00 02 00 20 20 00 8d 06 1b 00 00 00
+08 00 60 00 48 22 60 20 3c 00 2c 36 10 32 54 76
+08 00 60 00 48 02 60 40 a0 00 8d 12 80 00 8d 00
+08 00 80 00 48 02 80 42 e0 01 8d 12 a0 01 8d 00

diff --git a/src/intel/tools/tests/gen9/wait.asm b/src/intel/tools/tests/gen9/wait.asm
new file mode 100644 (file)
index 0000000..8cb494e
--- /dev/null
+++ b/src/intel/tools/tests/gen9/wait.asm
@@ -0,0 +1 @@
+wait(1)                         n0<0,1,0>UD                     { align1 WE_all 1N };

diff --git a/src/intel/tools/tests/gen9/wait.expected b/src/intel/tools/tests/gen9/wait.expected
new file mode 100644 (file)
index 0000000..81603b0
--- /dev/null
+++ b/src/intel/tools/tests/gen9/wait.expected
@@ -0,0 +1 @@
+30 00 00 00 04 00 00 32 00 12 00 38 00 00 8d 00

diff --git a/src/intel/tools/tests/gen9/while.asm b/src/intel/tools/tests/gen9/while.asm
new file mode 100644 (file)
index 0000000..00bd8e1
--- /dev/null
+++ b/src/intel/tools/tests/gen9/while.asm
@@ -0,0 +1,4 @@
+while(8)        JIP: -160                                       { align1 1Q };
+while(16)       JIP: -160                                       { align1 1H };
+(-f0.0) while(8) JIP: -384                                      { align1 1Q };
+(-f0.0) while(16) JIP: -384                                     { align1 1H };

diff --git a/src/intel/tools/tests/gen9/while.expected b/src/intel/tools/tests/gen9/while.expected
new file mode 100644 (file)
index 0000000..5b0fd85
--- /dev/null
+++ b/src/intel/tools/tests/gen9/while.expected
@@ -0,0 +1,4 @@
+27 00 60 00 20 0e 00 20 00 00 00 08 60 ff ff ff
+27 00 80 00 20 0e 00 20 00 00 00 08 60 ff ff ff
+27 00 71 00 20 0e 00 20 00 00 00 08 80 fe ff ff
+27 00 91 00 20 0e 00 20 00 00 00 08 80 fe ff ff

diff --git a/src/intel/tools/tests/gen9/xor.asm b/src/intel/tools/tests/gen9/xor.asm
new file mode 100644 (file)
index 0000000..bc4c054
--- /dev/null
+++ b/src/intel/tools/tests/gen9/xor.asm
@@ -0,0 +1,2 @@
+xor(16)         g3<1>UD         g1<0,1,0>UD     g1.1<0,1,0>UD   { align1 1H };
+xor(8)          g4<1>UD         g5.6<0,1,0>UD   ~g5.7<0,1,0>D   { align1 1Q };

diff --git a/src/intel/tools/tests/gen9/xor.expected b/src/intel/tools/tests/gen9/xor.expected
new file mode 100644 (file)
index 0000000..2e27e33
--- /dev/null
+++ b/src/intel/tools/tests/gen9/xor.expected
@@ -0,0 +1,2 @@
+07 00 80 00 08 02 60 20 20 00 00 02 24 00 00 00
+07 00 60 00 08 02 80 20 b8 00 00 0a bc 40 00 00

diff --git a/src/intel/tools/tests/run-test.sh b/src/intel/tools/tests/run-test.sh
new file mode 100644 (file)
index 0000000..803fe0f
--- /dev/null
+++ b/src/intel/tools/tests/run-test.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+SRCDIR="${srcdir}"
+I965_ASM="$1"
+
+test="TEST"
+
+if [ -n "$2" ] ; then
+   test="$2"
+fi
+
+if [ -n "$3" ] ; then
+   gen="$3"
+fi
+
+for file in ${SRCDIR}/${test}/*.asm; do
+   if [ -f "$file" ]; then
+      filename="${file%.*}"
+      "${I965_ASM}" -g ${gen} -o "${file}.out" "${file}"
+      if cmp "${file}.out" "${filename}.expected" 2> /dev/null; then
+         echo "${file} : PASS"
+      else
+         echo "Output comparison for ${file}"
+         diff -u "${filename}.expected" "${file}.out"
+      fi
+   fi
+done