gmicro.h (TARGET_SWITCHES): Add descriptions and mark them for translation.

2000-08-22  Philipp Thomas  <pthomas@suse.de>
            Masanobu Yuhara <yuhara@flab.fujitsu.co.jp>

	* gmicro.h (TARGET_SWITCHES): Add descriptions and mark them
	for translation.

Co-Authored-By: Masanobu Yuhara <yuhara@flab.fujitsu.co.jp>
From-SVN: r36078

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9f45f59af1cc3d20e01cea5c8459dcdde9f03bb3..a986ca2c993b7feaf18ccd1334acf00fb96d115a 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2000-08-22  Philipp Thomas  <pthomas@suse.de>
+            Masanobu Yuhara <yuhara@flab.fujitsu.co.jp>
+
+       * gmicro.h (TARGET_SWITCHES): Add descriptions and mark them
+       for translation.
+
 2000-08-30  Greg McGary  <greg@mcgary.org>
 
        * Makefile.in (fixinc.sh): Pass CC, CFLAGS and LDFLAGS to mkfixinc.sh

diff --git a/gcc/config/gmicro/gmicro.h b/gcc/config/gmicro/gmicro.h
index 377adf1b08ffe6e8ba4bbfee26d3718c6ec5053d..10d3d32d8045d45790fa25122342c481ddff98a1 100644 (file)
--- a/gcc/config/gmicro/gmicro.h
+++ b/gcc/config/gmicro/gmicro.h
@@ -86,25 +86,28 @@ extern int target_flags;
    An empty string NAME is used to identify the default VALUE.  */
 
 #define TARGET_SWITCHES  \
-  { { "g300", 1},                              \
-    { "g200", 2},                              \
-    { "g100", 4},                              \
-    { "fpu", 8},                               \
-    { "soft-float", -8},                       \
-    { "rtd", 0x10},                            \
-    { "no-rtd", -0x10},                                \
-    { "regparm", 0x20},                                \
-    { "no-regparm", -0x20},                    \
+  { { "g300", 1, _("Compile for Gmicro/300")},                 \
+    { "g200", 2, _("Compile for Gmicro/200")},                 \
+    { "g100", 4, _("Compile for Gmicro/100")},                 \
+    { "fpu", 8, _("Use floating point co-processor")},         \
+    { "soft-float", -8,                                                \
+      _("Do not use floating point co-processor")},            \
+    { "rtd", 0x10, _("Alternate calling convention")},         \
+    { "no-rtd", -0x10, _("Use normal calling convention")},    \
+    { "regparm", 0x20, NULL},                                  \
+    { "no-regparm", -0x20, NULL},                              \
 #if 0 /* Since we don't define PCC_BITFIELD_TYPE_MATTERS or use a large
         STRUCTURE_SIZE_BOUNDARY, we must have bitfield instructions.  */
-    { "bitfield", 0x40},                       \
-    { "no-bitfield", -0x40},                   \
+    { "bitfield", 0x40, _("Use bitfield instructions")},       \
+    { "no-bitfield", -0x40,                                    \
+      _("Do not use bitfield instructions")},                  \
 #endif
-    { "newreturn", 0x80},                      \
-    { "no-newreturn", -0x80},                  \
-    { "force-smov", 0x100},                    \
-    { "no-force-smov", -0x100},                        \
-    { "", TARGET_DEFAULT}}
+    { "newreturn", 0x80, _("Use alternative return sequence")},        \
+    { "no-newreturn", -0x80, _("Use normal return sequence")}, \
+    { "force-smov", 0x100, _("Always use string instruction")},        \
+    { "no-force-smov", -0x100,                                 \
+      _("Use string instruction when appropriate")},           \
+    { "", TARGET_DEFAULT, NULL}}
 
 
 /* Blow away G100 flag silently off TARGET_fpu (since we can't clear