x86: Use the new CondInst format for moves to/from control registers.

The condition is whether the control register index is valid.

Change-Id: I8a225fcfd4955032b5bbf7d3392ee5bcc7d6bc64
Reviewed-on: https://gem5-review.googlesource.com/4581
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 97c3dd6882633bf91991aecb58f24719b59de7a7..8b875682303f0d1e55eba33a6288abb1f292226e 100644 (file)
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -360,9 +360,11 @@
             0x04: decode LEGACY_DECODEVAL {
                 // no prefix
                 0x0: decode OPCODE_OP_BOTTOM3 {
-                    0x0: MOV(Rd,Cd);
+                    0x0: CondInst::MOV(
+                        {{isValidMiscReg(MISCREG_CR(MODRM_RM))}},Rd,Cd);
                     0x1: MOV(Rd,Dd);
-                    0x2: MOV(Cd,Rd);
+                    0x2: CondInst::MOV(
+                        {{isValidMiscReg(MISCREG_CR(MODRM_REG))}},Cd,Rd);
                     0x3: MOV(Dd,Rd);
                     default: UD2();
                 }