+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000088 # Number of seconds simulated
+sim_ticks 87707000 # Number of ticks simulated
+final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 163854 # Simulator instruction rate (inst/s)
+host_op_rate 163852 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 21217098 # Simulator tick rate (ticks/s)
+host_mem_usage 1151472 # Number of bytes of host memory used
+host_seconds 4.13 # Real time elapsed on the host
+sim_insts 677327 # Number of instructions simulated
+sim_ops 677327 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
+system.physmem.bytes_read::total 35776 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 559 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
+system.cpu0.workload.num_syscalls 89 # Number of system calls
+system.cpu0.numCycles 175415 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 175326 # Number of instructions committed
+system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu0.num_func_calls 390 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 120376 # number of integer instructions
+system.cpu0.num_fp_insts 0 # number of float instructions
+system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu0.num_mem_refs 82397 # number of memory refs
+system.cpu0.num_load_insts 54591 # Number of load instructions
+system.cpu0.num_store_insts 27806 # Number of store instructions
+system.cpu0.num_idle_cycles 0 # Number of idle cycles
+system.cpu0.num_busy_cycles 175415 # Number of busy cycles
+system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0 # Percentage of idle cycles
+system.cpu0.icache.replacements 215 # number of replacements
+system.cpu0.icache.tagsinuse 222.772698 # Cycle average of tags in use
+system.cpu0.icache.total_refs 174921 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 374.563169 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.435103 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits
+system.cpu0.icache.overall_hits::total 174921 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
+system.cpu0.icache.overall_misses::total 467 # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.dcache.replacements 2 # number of replacements
+system.cpu0.dcache.tagsinuse 150.745494 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 81883 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 490.317365 # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.294425 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits
+system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits
+system.cpu0.dcache.overall_hits::total 82008 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses
+system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses
+system.cpu0.dcache.overall_misses::total 328 # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses
+system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.dcache.fast_writes 0 # number of fast writes performed
+system.cpu0.dcache.cache_copies 0 # number of cache copies performed
+system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
+system.cpu0.dcache.writebacks::total 1 # number of writebacks
+system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.numCycles 173295 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 167398 # Number of instructions committed
+system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu1.num_func_calls 633 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 109926 # number of integer instructions
+system.cpu1.num_fp_insts 0 # number of float instructions
+system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu1.num_mem_refs 53394 # number of memory refs
+system.cpu1.num_load_insts 40652 # Number of load instructions
+system.cpu1.num_store_insts 12742 # Number of store instructions
+system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles
+system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles
+system.cpu1.icache.replacements 278 # number of replacements
+system.cpu1.icache.tagsinuse 76.751702 # Cycle average of tags in use
+system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.149906 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits
+system.cpu1.icache.overall_hits::total 167072 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses
+system.cpu1.icache.overall_misses::total 358 # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses
+system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.icache.fast_writes 0 # number of fast writes performed
+system.cpu1.icache.cache_copies 0 # number of cache copies performed
+system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.dcache.replacements 0 # number of replacements
+system.cpu1.dcache.tagsinuse 30.316999 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.059213 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits
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+system.cpu1.dcache.overall_hits::total 53033 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses
+system.cpu1.dcache.overall_misses::total 280 # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
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+system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
+system.l2c.Writeback_hits::total 1 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
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+system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits
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+system.l2c.overall_hits::cpu0.data 5 # number of overall hits
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+system.l2c.overall_hits::total 1220 # number of overall hits
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+system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses
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+system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
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+system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
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+system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
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+system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses
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+system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses)
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+system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses)
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+system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses)
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+system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses)
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+system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
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+system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses
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+system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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+system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses
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+system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses
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+system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff