freedom: bump submodules to their respective masters

diff --git a/common.mk b/common.mk
index db054830983f75d75ac16e9d71a01f60ad20a8ca..e23cbb7eaed1a1d9815b6db3eda48f4025452dfa 100644 (file)
--- a/common.mk
+++ b/common.mk
@@ -72,11 +72,26 @@ endif
 .PHONY: romgen
 romgen: $(romgen)
 
+f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F
+$(f):
+       echo $(VSRCS) > $@
+
+bit := $(BUILD_DIR)/obj/$(MODEL).bit
+$(bit): $(romgen) $(f)
+       cd $(BUILD_DIR); vivado \
+               -nojournal -mode batch \
+               -source $(fpga_common_script_dir)/vivado.tcl \
+               -tclargs \
+               -top-module "$(MODEL)" \
+               -F "$(f)" \
+               -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
+               -board "$(BOARD)"
+
+
 # Build .mcs
-mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs
-$(mcs): $(romgen)
-       VSRCS="$(VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
-       cp $(BUILD_DIR)/$(MODEL)/obj/system.mcs $@
+mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
+$(mcs): $(bit)
+       cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
 
 .PHONY: mcs
 mcs: $(mcs)

diff --git a/fpga-shells b/fpga-shells
index 2389e6e95717caca782e7444422da16fef687188..ba7beb676d55b73334bd4a85623e56c713a83773 160000 (submodule)
--- a/fpga-shells
+++ b/fpga-shells
@@ -1 +1 @@
-Subproject commit 2389e6e95717caca782e7444422da16fef687188
+Subproject commit ba7beb676d55b73334bd4a85623e56c713a83773

diff --git a/rocket-chip b/rocket-chip
index 82df766f4a5b1efb24b8659eb11c8b12c410a291..7e75d63ba6b4c1b50aaaf920e1c693ef6acf51d7 160000 (submodule)
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit 82df766f4a5b1efb24b8659eb11c8b12c410a291
+Subproject commit 7e75d63ba6b4c1b50aaaf920e1c693ef6acf51d7

diff --git a/sifive-blocks b/sifive-blocks
index f266b55da92e42350be5704b4fe7d2a934e986ae..d1d2f47f609638c43546d4a9d0a4018c73dee4bb 160000 (submodule)
--- a/sifive-blocks
+++ b/sifive-blocks
@@ -1 +1 @@
-Subproject commit f266b55da92e42350be5704b4fe7d2a934e986ae
+Subproject commit d1d2f47f609638c43546d4a9d0a4018c73dee4bb

diff --git a/src/main/scala/everywhere/e300artydevkit/Platform.scala b/src/main/scala/everywhere/e300artydevkit/Platform.scala
index a3253338a31e2b7cd94537c2c2d6bf20d9dc247c..be1789a1272f1f58fa81b869306cab05c306cc89 100644 (file)
--- a/src/main/scala/everywhere/e300artydevkit/Platform.scala
+++ b/src/main/scala/everywhere/e300artydevkit/Platform.scala
@@ -8,9 +8,9 @@ import freechips.rocketchip.coreplex._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.util.ResetCatchAndSync
 import freechips.rocketchip.system._
 
-import sifive.blocks.util.{ResetCatchAndSync}
 import sifive.blocks.devices.mockaon._
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.jtag._
@@ -82,10 +82,10 @@ class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
   val spi_pins  = sys.outer.spiParams.map  { c => Wire(new SPIPins(() => PinGen(), c))}
   val i2c_pins  = sys.outer.i2cParams.map  { c => Wire(new I2CPins(() => PinGen()))}
 
-  (uart_pins zip  sys_uart) map {case (p, r) => p.fromPort(r, clock = clock, reset = reset, syncStages = 0)}
-  (pwm_pins  zip  sys_pwm)  map {case (p, r) => p.fromPort(r)}
-  (spi_pins  zip  sys_spi)  map {case (p, r) => p.fromPort(r, clock = clock, reset = reset, syncStages = 0)}
-  (i2c_pins  zip  sys_i2c)  map {case (p, r) => p.fromPort(r, clock = clock, reset = reset, syncStages = 0)}
+  (uart_pins zip  sys_uart) map {case (p, r) => UARTPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
+  (pwm_pins  zip  sys_pwm)  map {case (p, r) => PWMPinsFromPort(p, r) }
+  (spi_pins  zip  sys_spi)  map {case (p, r) => SPIPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
+  (i2c_pins  zip  sys_i2c)  map {case (p, r) => I2CPinsFromPort(p, r, clock = clock, reset = reset, syncStages = 0)}
 
   //-----------------------------------------------------------------------
   // Default Pin connections before attaching pinmux
@@ -157,14 +157,14 @@ class E300ArtyDevKitPlatform(implicit val p: Parameters) extends Module {
   //-----------------------------------------------------------------------
 
   // Result of Pin Mux
-  io.pins.gpio.fromPort(sys.gpio(0))
+  GPIOPinsFromPort(io.pins.gpio, sys.gpio(0))
 
   // Dedicated SPI Pads
-  io.pins.qspi.fromPort(sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3)
+  SPIPinsFromPort(io.pins.qspi, sys.qspi(0), clock = sys.clock, reset = sys.reset, syncStages = 3)
 
   // JTAG Debug Interface
   val sjtag = sys.debug.systemjtag.get
-  io.pins.jtag.fromPort(sjtag.jtag)
+  JTAGPinsFromPort(io.pins.jtag, sjtag.jtag)
   sjtag.reset := io.jtag_reset
   sjtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
 

diff --git a/src/main/scala/unleashed/u500vc707devkit/Config.scala b/src/main/scala/unleashed/u500vc707devkit/Config.scala
index a899e9650612e6c18bc64a5fe1267ac61a536939..fd017bd805f56aa7bcfcba03f4422fa2f2775d52 100644 (file)
--- a/src/main/scala/unleashed/u500vc707devkit/Config.scala
+++ b/src/main/scala/unleashed/u500vc707devkit/Config.scala
@@ -13,6 +13,8 @@ import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.spi._
 import sifive.blocks.devices.uart._
 
+import sifive.fpgashells.devices.xilinx.xilinxvc707mig.{MemoryXilinxDDRKey,XilinxVC707MIGParams}
+
 // Default FreedomUVC707Config
 class FreedomUVC707Config extends Config(
   new WithJtagDTM            ++
@@ -40,7 +42,8 @@ class U500VC707DevKitConfig extends Config(
   new U500VC707DevKitPeripherals ++
   new FreedomUVC707Config().alter((site,here,up) => {
     case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
-    case PeripheryBusParams => up(PeripheryBusParams, site).copy(frequency = 50000000) // 50 MHz hperiphery
+    case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
+    case MemoryXilinxDDRKey => XilinxVC707MIGParams(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
     case DTSTimebase => BigInt(1000000)
     case ExtMem => up(ExtMem).copy(size = 0x40000000L)
     case JtagDTMKey => new JtagDTMConfig (

diff --git a/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala b/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala
index b281bb82d229c420498cd31ba393c90e15d03016..9ac76678e0e6a19879b455621468272eea5247b9 100644 (file)
--- a/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala
+++ b/src/main/scala/unleashed/u500vc707devkit/FPGAChip.scala
@@ -10,7 +10,7 @@ import freechips.rocketchip.diplomacy._
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.pinctrl.{BasePin}
 
-import sifive.fpgashells.shell.xilinx.vc707shell.{VC707Shell}
+import sifive.fpgashells.shell.xilinx.vc707shell._
 import sifive.fpgashells.ip.xilinx.{IOBUF}
 
 //-------------------------------------------------------------------------
@@ -27,7 +27,10 @@ object PinGen {
 // U500VC707DevKitFPGAChip
 //-------------------------------------------------------------------------
 
-class U500VC707DevKitFPGAChip(implicit override val p: Parameters) extends VC707Shell {
+class U500VC707DevKitFPGAChip(implicit override val p: Parameters)
+    extends VC707Shell
+    with HasPCIe
+    with HasDDR3 {
 
   //-----------------------------------------------------------------------
   // DUT
@@ -55,7 +58,7 @@ class U500VC707DevKitFPGAChip(implicit override val p: Parameters) extends VC707
     val gpioParams = p(PeripheryGPIOKey)
     val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0)))
 
-    gpio_pins.fromPort(dut.gpio(0))
+    GPIOPinsFromPort(gpio_pins, dut.gpio(0))
 
     gpio_pins.pins.foreach { _.i.ival := Bool(false) }
     gpio_pins.pins.zipWithIndex.foreach {