(no commit message)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index a333a4a516abfff60218ca256d1ded67414bf0f1..b04d05a3d0856ec3ff20585596f481c8d89a9042 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -120,6 +120,7 @@ widths as part of the actual operation, and the source and destination
 elwidth overrides, was particularly obtuse and hard to derive: some care
 and attention is advised, here, when reading the specification.
 
+
 **Non-vectorised**
 
 The concept of a Vectorised halt (`attn`) makes no sense. There are never
@@ -147,7 +148,10 @@ of a Scalar ISA and then adds additional instructions which only
 make sense in a Vector Context, such as Vector Shuffle, SVP64 goes to
 considerable lengths to keep strictly to augmentation and embedding
 of an entire Scalar ISA's instructions into an abstract Vectorisation
-Context.
+Context. That abstraction subdivides down into Categories appropriate
+for the type of operation (Branch, CRs, Memory, Arithmetic),
+and each Category has its own relevant but
+ultimately rational quirks.
 
 # CR weird instructions