ARM: Flesh out the 32 bit thumb store single instructions.

diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa
index 1dcbddec3c50b6d9518c640b33116901c11bee3e..5d191b6df0596beb648c2c15c4f909e99290c2b9 100644 (file)
--- a/src/arch/arm/isa/bitfields.isa
+++ b/src/arch/arm/isa/bitfields.isa
@@ -144,6 +144,7 @@ def bitfield HTOPCODE_8_7   htopcode8_7;
 def bitfield HTOPCODE_8_6   htopcode8_6;
 def bitfield HTOPCODE_8_5   htopcode8_5;
 def bitfield HTOPCODE_7     htopcode7;
+def bitfield HTOPCODE_7_5   htopcode7_5;
 def bitfield HTOPCODE_6_5   htopcode6_5;
 def bitfield HTOPCODE_5_4   htopcode5_4;
 def bitfield HTOPCODE_4     htopcode4;

diff --git a/src/arch/arm/isa/thumbdecode.isa b/src/arch/arm/isa/thumbdecode.isa
index 9bf596b886c5779010f5e9c16b5fa14192d8934a..84a4d826707bcd94dcd28623a4833933ffa493c1 100644 (file)
--- a/src/arch/arm/isa/thumbdecode.isa
+++ b/src/arch/arm/isa/thumbdecode.isa
@@ -388,7 +388,32 @@
         0x3: decode HTOPCODE_10_9 {
             0x0: decode HTOPCODE_4 {
                 0x0: decode HTOPCODE_8 {
-                    0x0: WarnUnimpl::Store_single_data_item();
+                    0x0: decode HTOPCODE_7_5 {
+                        0x0: decode LTOPCODE_11_8 {
+                            0x0: decode LTOPCODE_7_6 {
+                                0x0: WarnUnimpl::strb(); // register
+                            }
+                            0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::strb(); // immediate thumb
+                            0xe: WarnUnimpl::strbt();
+                        }
+                        0x1: decode LTOPCODE_11_8 {
+                            0x0: decode LTOPCODE_7_6 {
+                                0x0: WarnUnimpl::strh(); // register
+                            }
+                            0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::strh(); // immediate thumb
+                            0xe: WarnUnimpl::strht();
+                        }
+                        0x2: decode LTOPCODE_11_8 {
+                            0x0: decode LTOPCODE_7_6 {
+                                0x0: WarnUnimpl::str(); // register
+                            }
+                            0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::str(); // immediate thumb
+                            0xe: WarnUnimpl::strt();
+                        }
+                        0x4: WarnUnimpl::strb(); // immediate, thumb
+                        0x5: WarnUnimpl::strh(); // immediate, thumb
+                        0x6: WarnUnimpl::str(); // immediate, thumb
+                    }
                     0x1: WarnUnimpl::Advanced_SIMD_or_structure_load_store();
                 }
                 0x1: decode HTOPCODE_6_5 {

diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 23152d3cf1bacf51609dc2b63c03935514fe8fbe..9bdf69305d78a83d9d09153aa4c86e540aab0ac1 100644 (file)
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -156,6 +156,7 @@ namespace ArmISA
         Bitfield<24, 22> htopcode8_6;
         Bitfield<24, 21> htopcode8_5;
         Bitfield<23>     htopcode7;
+        Bitfield<23, 21> htopcode7_5;
         Bitfield<22, 21> htopcode6_5;
         Bitfield<21, 20> htopcode5_4;
         Bitfield<20>     htopcode4;