(no commit message)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 04d015f5b697073c0d5001214b711c7f2b04963f..02c620a45f4e4f83459c5bad8cff73db8d47e4a9 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -246,8 +246,8 @@ count and reducing assembler complexity are:
   of the predicates provides all of the other types of operations
   found in Vector ISAs (VEXTRACT, VINSERT etc) again with no need
   to actually provide explicit such instructions.
-* **Saturation**. **all** LD/ST and Arithmetic and Logical operations may
-  be saturated (without adding explicit saturated opcodes)
+* **Saturation**. applies to **all** LD/ST and Arithmetic and Logical 
+  operations (without adding explicit saturation ops)
 * **Reduction and Prefix-Sum** (Fibonnacci Series) Modes, including a
   "Reverse Gear" (running loops in reverse order).
 * **vec2/3/4 "Packing" and "Unpacking"** (similar to VSX `vpack` and `vpkss`)