aarch64: Prefer register ranges & support wrapping

Until now, binutils has supported register ranges such
as { v0.4s - v3.4s } as an unofficial shorthand for
{ v0.4s, v1.4s, v2.4s, v3.4s }.  The SME2 ISA embraces this form
and makes it the preferred disassembly.  It also embraces wrapped
lists such as { z31.s - z2.s }, which is something that binutils
didn't previously allow.

The range form was already binutils's preferred disassembly for 3- and
4-register lists.  This patch prefers it for 2-register lists too.
The patch also adds support for wrap-around.

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0acb36438432ffce51e35e5dc7126c6b3b56bd4c..2d4c6106506611d84562bb8e4f97403529bbdacd 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1358,7 +1358,6 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
   int val, val_range;
   int in_range;
   int ret_val;
-  int i;
   bool error = false;
   bool expect_index = false;
   unsigned int ptr_flags = PTR_IN_REGLIST;
@@ -1409,13 +1408,13 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
 
       if (in_range)
        {
-         if (val < val_range)
+         if (val == val_range)
            {
              set_first_syntax_error
                (_("invalid range in vector register list"));
              error = true;
            }
-         val_range++;
+         val_range = (val_range + 1) & 0x1f;
        }
       else
        {
@@ -1430,10 +1429,13 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
            }
        }
       if (! error)
-       for (i = val_range; i <= val; i++)
+       for (;;)
          {
-           ret_val |= i << (5 * nb_regs);
+           ret_val |= val_range << (5 * nb_regs);
            nb_regs++;
+           if (val_range == val)
+             break;
+           val_range = (val_range + 1) & 0x1f;
          }
       in_range = 0;
       ptr_flags |= PTR_GOOD_MATCH;

diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 48281fcc4cd19043f7482ec9710201465ababdc7..f07ef384f9467323e51285d4eb5c9988a56de90d 100644 (file)
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -242,12 +242,12 @@
 [^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `ext z0\.b,{z0\.b,z2\.b},#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.h,{z0\.b,z1\.b},#0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
-[^ :]+:[0-9]+: Info:           ext z0\.b, {z0\.b, z1\.b}, #0
+[^ :]+:[0-9]+: Info:           ext z0\.b, {z0\.b-z1\.b}, #0
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `ext z0\.b,{z0\.h,z1\.b},#0'
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `ext z0\.b,{z0\.b,z1\.h},#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.b,{z0\.h,z1\.h},#0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
-[^ :]+:[0-9]+: Info:           ext z0\.b, {z0\.b, z1\.b}, #0
+[^ :]+:[0-9]+: Info:           ext z0\.b, {z0\.b-z1\.b}, #0
 [^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
 [^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `ext z0\.b,{z0\.b},#0'
 [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ext z0\.b,z0\.b,#0'
@@ -1280,11 +1280,11 @@
 [^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 3 -- `splice z0\.b,p0,{z0\.b,z2\.b}'
 [^ :]+:[0-9]+: Error: operand mismatch -- `splice z0\.h,p0,{z0\.b,z1\.b}'
 [^ :]+:[0-9]+: Info:    did you mean this\?
-[^ :]+:[0-9]+: Info:           splice z0\.b, p0, {z0\.b, z1\.b}
+[^ :]+:[0-9]+: Info:           splice z0\.b, p0, {z0\.b-z1\.b}
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
-[^ :]+:[0-9]+: Info:           splice z0\.h, p0, {z0\.h, z1\.h}
-[^ :]+:[0-9]+: Info:           splice z0\.s, p0, {z0\.s, z1\.s}
-[^ :]+:[0-9]+: Info:           splice z0\.d, p0, {z0\.d, z1\.d}
+[^ :]+:[0-9]+: Info:           splice z0\.h, p0, {z0\.h-z1\.h}
+[^ :]+:[0-9]+: Info:           splice z0\.s, p0, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info:           splice z0\.d, p0, {z0\.d-z1\.d}
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.h,z1\.b}'
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.b,z1\.h}'
 [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `splice z32\.b,p0,{z0\.b,z1\.b}'
@@ -2336,21 +2336,21 @@
 [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `tbl z0\.b,{z0\.b,z1\.b},z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `tbl z0\.b,{z0\.b,z1\.b},z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
-[^ :]+:[0-9]+: Info:           tbl z0\.b, {z0\.b, z1\.b}, z0\.b
+[^ :]+:[0-9]+: Info:           tbl z0\.b, {z0\.b-z1\.b}, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
-[^ :]+:[0-9]+: Info:           tbl z0\.h, {z0\.h, z1\.h}, z0\.h
-[^ :]+:[0-9]+: Info:           tbl z0\.s, {z0\.s, z1\.s}, z0\.s
-[^ :]+:[0-9]+: Info:           tbl z0\.d, {z0\.d, z1\.d}, z0\.d
+[^ :]+:[0-9]+: Info:           tbl z0\.h, {z0\.h-z1\.h}, z0\.h
+[^ :]+:[0-9]+: Info:           tbl z0\.s, {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Info:           tbl z0\.d, {z0\.d-z1\.d}, z0\.d
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.b,z1\.h},z0\.b'
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.h,z0\.b},z0\.b'
 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.h,{z0\.b,z0\.b},z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `tbl z0\.h,{z0\.b,z1\.b},z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
-[^ :]+:[0-9]+: Info:           tbl z0\.b, {z0\.b, z1\.b}, z0\.b
+[^ :]+:[0-9]+: Info:           tbl z0\.b, {z0\.b-z1\.b}, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
-[^ :]+:[0-9]+: Info:           tbl z0\.h, {z0\.h, z1\.h}, z0\.h
-[^ :]+:[0-9]+: Info:           tbl z0\.s, {z0\.s, z1\.s}, z0\.s
-[^ :]+:[0-9]+: Info:           tbl z0\.d, {z0\.d, z1\.d}, z0\.d
+[^ :]+:[0-9]+: Info:           tbl z0\.h, {z0\.h-z1\.h}, z0\.h
+[^ :]+:[0-9]+: Info:           tbl z0\.s, {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Info:           tbl z0\.d, {z0\.d-z1\.d}, z0\.d
 [^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `tbx z32\.h,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `tbx z0\.h,z32\.b,z0\.b'
 [^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `tbx z0\.h,z0\.b,z32\.b'

diff --git a/gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d b/gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d
index 8e710562efc7f193214b524dc3007dbcfc8e8b64..5e41631b5ab6f66220183f164c6a3b20d34146a5 100644 (file)
--- a/gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d
+++ b/gas/testsuite/gas/aarch64/neon-vfp-reglist-post.d
@@ -6,161 +6,161 @@ Disassembly of section \.text:
 
 0+ <.*>:
    0:  0cdf7000        ld1     {v0.8b}, \[x0\], #8
-   4:  0cdfa000        ld1     {v0.8b, v1.8b}, \[x0\], #16
+   4:  0cdfa000        ld1     {v0.8b-v1.8b}, \[x0\], #16
    8:  0cdf6000        ld1     {v0.8b-v2.8b}, \[x0\], #24
    c:  0cdf2000        ld1     {v0.8b-v3.8b}, \[x0\], #32
   10:  0cdf7400        ld1     {v0.4h}, \[x0\], #8
-  14:  0cdfa400        ld1     {v0.4h, v1.4h}, \[x0\], #16
+  14:  0cdfa400        ld1     {v0.4h-v1.4h}, \[x0\], #16
   18:  0cdf6400        ld1     {v0.4h-v2.4h}, \[x0\], #24
   1c:  0cdf2400        ld1     {v0.4h-v3.4h}, \[x0\], #32
   20:  0cdf7800        ld1     {v0.2s}, \[x0\], #8
-  24:  0cdfa800        ld1     {v0.2s, v1.2s}, \[x0\], #16
+  24:  0cdfa800        ld1     {v0.2s-v1.2s}, \[x0\], #16
   28:  0cdf6800        ld1     {v0.2s-v2.2s}, \[x0\], #24
   2c:  0cdf2800        ld1     {v0.2s-v3.2s}, \[x0\], #32
   30:  0cdf7c00        ld1     {v0.1d}, \[x0\], #8
-  34:  0cdfac00        ld1     {v0.1d, v1.1d}, \[x0\], #16
+  34:  0cdfac00        ld1     {v0.1d-v1.1d}, \[x0\], #16
   38:  0cdf6c00        ld1     {v0.1d-v2.1d}, \[x0\], #24
   3c:  0cdf2c00        ld1     {v0.1d-v3.1d}, \[x0\], #32
   40:  0c9f7000        st1     {v0.8b}, \[x0\], #8
-  44:  0c9fa000        st1     {v0.8b, v1.8b}, \[x0\], #16
+  44:  0c9fa000        st1     {v0.8b-v1.8b}, \[x0\], #16
   48:  0c9f6000        st1     {v0.8b-v2.8b}, \[x0\], #24
   4c:  0c9f2000        st1     {v0.8b-v3.8b}, \[x0\], #32
   50:  0c9f7400        st1     {v0.4h}, \[x0\], #8
-  54:  0c9fa400        st1     {v0.4h, v1.4h}, \[x0\], #16
+  54:  0c9fa400        st1     {v0.4h-v1.4h}, \[x0\], #16
   58:  0c9f6400        st1     {v0.4h-v2.4h}, \[x0\], #24
   5c:  0c9f2400        st1     {v0.4h-v3.4h}, \[x0\], #32
   60:  0c9f7800        st1     {v0.2s}, \[x0\], #8
-  64:  0c9fa800        st1     {v0.2s, v1.2s}, \[x0\], #16
+  64:  0c9fa800        st1     {v0.2s-v1.2s}, \[x0\], #16
   68:  0c9f6800        st1     {v0.2s-v2.2s}, \[x0\], #24
   6c:  0c9f2800        st1     {v0.2s-v3.2s}, \[x0\], #32
   70:  0c9f7c00        st1     {v0.1d}, \[x0\], #8
-  74:  0c9fac00        st1     {v0.1d, v1.1d}, \[x0\], #16
+  74:  0c9fac00        st1     {v0.1d-v1.1d}, \[x0\], #16
   78:  0c9f6c00        st1     {v0.1d-v2.1d}, \[x0\], #24
   7c:  0c9f2c00        st1     {v0.1d-v3.1d}, \[x0\], #32
   80:  4cdf7000        ld1     {v0.16b}, \[x0\], #16
-  84:  4cdfa000        ld1     {v0.16b, v1.16b}, \[x0\], #32
+  84:  4cdfa000        ld1     {v0.16b-v1.16b}, \[x0\], #32
   88:  4cdf6000        ld1     {v0.16b-v2.16b}, \[x0\], #48
   8c:  4cdf2000        ld1     {v0.16b-v3.16b}, \[x0\], #64
   90:  4cdf7400        ld1     {v0.8h}, \[x0\], #16
-  94:  4cdfa400        ld1     {v0.8h, v1.8h}, \[x0\], #32
+  94:  4cdfa400        ld1     {v0.8h-v1.8h}, \[x0\], #32
   98:  4cdf6400        ld1     {v0.8h-v2.8h}, \[x0\], #48
   9c:  4cdf2400        ld1     {v0.8h-v3.8h}, \[x0\], #64
   a0:  4cdf7800        ld1     {v0.4s}, \[x0\], #16
-  a4:  4cdfa800        ld1     {v0.4s, v1.4s}, \[x0\], #32
+  a4:  4cdfa800        ld1     {v0.4s-v1.4s}, \[x0\], #32
   a8:  4cdf6800        ld1     {v0.4s-v2.4s}, \[x0\], #48
   ac:  4cdf2800        ld1     {v0.4s-v3.4s}, \[x0\], #64
   b0:  4cdf7c00        ld1     {v0.2d}, \[x0\], #16
-  b4:  4cdfac00        ld1     {v0.2d, v1.2d}, \[x0\], #32
+  b4:  4cdfac00        ld1     {v0.2d-v1.2d}, \[x0\], #32
   b8:  4cdf6c00        ld1     {v0.2d-v2.2d}, \[x0\], #48
   bc:  4cdf2c00        ld1     {v0.2d-v3.2d}, \[x0\], #64
   c0:  4c9f7000        st1     {v0.16b}, \[x0\], #16
-  c4:  4c9fa000        st1     {v0.16b, v1.16b}, \[x0\], #32
+  c4:  4c9fa000        st1     {v0.16b-v1.16b}, \[x0\], #32
   c8:  4c9f6000        st1     {v0.16b-v2.16b}, \[x0\], #48
   cc:  4c9f2000        st1     {v0.16b-v3.16b}, \[x0\], #64
   d0:  4c9f7400        st1     {v0.8h}, \[x0\], #16
-  d4:  4c9fa400        st1     {v0.8h, v1.8h}, \[x0\], #32
+  d4:  4c9fa400        st1     {v0.8h-v1.8h}, \[x0\], #32
   d8:  4c9f6400        st1     {v0.8h-v2.8h}, \[x0\], #48
   dc:  4c9f2400        st1     {v0.8h-v3.8h}, \[x0\], #64
   e0:  4c9f7800        st1     {v0.4s}, \[x0\], #16
-  e4:  4c9fa800        st1     {v0.4s, v1.4s}, \[x0\], #32
+  e4:  4c9fa800        st1     {v0.4s-v1.4s}, \[x0\], #32
   e8:  4c9f6800        st1     {v0.4s-v2.4s}, \[x0\], #48
   ec:  4c9f2800        st1     {v0.4s-v3.4s}, \[x0\], #64
   f0:  4c9f7c00        st1     {v0.2d}, \[x0\], #16
-  f4:  4c9fac00        st1     {v0.2d, v1.2d}, \[x0\], #32
+  f4:  4c9fac00        st1     {v0.2d-v1.2d}, \[x0\], #32
   f8:  4c9f6c00        st1     {v0.2d-v2.2d}, \[x0\], #48
   fc:  4c9f2c00        st1     {v0.2d-v3.2d}, \[x0\], #64
  100:  0cc77000        ld1     {v0.8b}, \[x0\], x7
- 104:  0cc7a000        ld1     {v0.8b, v1.8b}, \[x0\], x7
+ 104:  0cc7a000        ld1     {v0.8b-v1.8b}, \[x0\], x7
  108:  0cc76000        ld1     {v0.8b-v2.8b}, \[x0\], x7
  10c:  0cc72000        ld1     {v0.8b-v3.8b}, \[x0\], x7
  110:  0cc77400        ld1     {v0.4h}, \[x0\], x7
- 114:  0cc7a400        ld1     {v0.4h, v1.4h}, \[x0\], x7
+ 114:  0cc7a400        ld1     {v0.4h-v1.4h}, \[x0\], x7
  118:  0cc76400        ld1     {v0.4h-v2.4h}, \[x0\], x7
  11c:  0cc72400        ld1     {v0.4h-v3.4h}, \[x0\], x7
  120:  0cc77800        ld1     {v0.2s}, \[x0\], x7
- 124:  0cc7a800        ld1     {v0.2s, v1.2s}, \[x0\], x7
+ 124:  0cc7a800        ld1     {v0.2s-v1.2s}, \[x0\], x7
  128:  0cc76800        ld1     {v0.2s-v2.2s}, \[x0\], x7
  12c:  0cc72800        ld1     {v0.2s-v3.2s}, \[x0\], x7
  130:  0cc77c00        ld1     {v0.1d}, \[x0\], x7
- 134:  0cc7ac00        ld1     {v0.1d, v1.1d}, \[x0\], x7
+ 134:  0cc7ac00        ld1     {v0.1d-v1.1d}, \[x0\], x7
  138:  0cc76c00        ld1     {v0.1d-v2.1d}, \[x0\], x7
  13c:  0cc72c00        ld1     {v0.1d-v3.1d}, \[x0\], x7
  140:  4cc77000        ld1     {v0.16b}, \[x0\], x7
- 144:  4cc7a000        ld1     {v0.16b, v1.16b}, \[x0\], x7
+ 144:  4cc7a000        ld1     {v0.16b-v1.16b}, \[x0\], x7
  148:  4cc76000        ld1     {v0.16b-v2.16b}, \[x0\], x7
  14c:  4cc72000        ld1     {v0.16b-v3.16b}, \[x0\], x7
  150:  4cc77400        ld1     {v0.8h}, \[x0\], x7
- 154:  4cc7a400        ld1     {v0.8h, v1.8h}, \[x0\], x7
+ 154:  4cc7a400        ld1     {v0.8h-v1.8h}, \[x0\], x7
  158:  4cc76400        ld1     {v0.8h-v2.8h}, \[x0\], x7
  15c:  4cc72400        ld1     {v0.8h-v3.8h}, \[x0\], x7
  160:  4cc77800        ld1     {v0.4s}, \[x0\], x7
- 164:  4cc7a800        ld1     {v0.4s, v1.4s}, \[x0\], x7
+ 164:  4cc7a800        ld1     {v0.4s-v1.4s}, \[x0\], x7
  168:  4cc76800        ld1     {v0.4s-v2.4s}, \[x0\], x7
  16c:  4cc72800        ld1     {v0.4s-v3.4s}, \[x0\], x7
  170:  4cc77c00        ld1     {v0.2d}, \[x0\], x7
- 174:  4cc7ac00        ld1     {v0.2d, v1.2d}, \[x0\], x7
+ 174:  4cc7ac00        ld1     {v0.2d-v1.2d}, \[x0\], x7
  178:  4cc76c00        ld1     {v0.2d-v2.2d}, \[x0\], x7
  17c:  4cc72c00        ld1     {v0.2d-v3.2d}, \[x0\], x7
  180:  0c877000        st1     {v0.8b}, \[x0\], x7
- 184:  0c87a000        st1     {v0.8b, v1.8b}, \[x0\], x7
+ 184:  0c87a000        st1     {v0.8b-v1.8b}, \[x0\], x7
  188:  0c876000        st1     {v0.8b-v2.8b}, \[x0\], x7
  18c:  0c872000        st1     {v0.8b-v3.8b}, \[x0\], x7
  190:  0c877400        st1     {v0.4h}, \[x0\], x7
- 194:  0c87a400        st1     {v0.4h, v1.4h}, \[x0\], x7
+ 194:  0c87a400        st1     {v0.4h-v1.4h}, \[x0\], x7
  198:  0c876400        st1     {v0.4h-v2.4h}, \[x0\], x7
  19c:  0c872400        st1     {v0.4h-v3.4h}, \[x0\], x7
  1a0:  0c877800        st1     {v0.2s}, \[x0\], x7
- 1a4:  0c87a800        st1     {v0.2s, v1.2s}, \[x0\], x7
+ 1a4:  0c87a800        st1     {v0.2s-v1.2s}, \[x0\], x7
  1a8:  0c876800        st1     {v0.2s-v2.2s}, \[x0\], x7
  1ac:  0c872800        st1     {v0.2s-v3.2s}, \[x0\], x7
  1b0:  0c877c00        st1     {v0.1d}, \[x0\], x7
- 1b4:  0c87ac00        st1     {v0.1d, v1.1d}, \[x0\], x7
+ 1b4:  0c87ac00        st1     {v0.1d-v1.1d}, \[x0\], x7
  1b8:  0c876c00        st1     {v0.1d-v2.1d}, \[x0\], x7
  1bc:  0c872c00        st1     {v0.1d-v3.1d}, \[x0\], x7
  1c0:  4c877000        st1     {v0.16b}, \[x0\], x7
- 1c4:  4c87a000        st1     {v0.16b, v1.16b}, \[x0\], x7
+ 1c4:  4c87a000        st1     {v0.16b-v1.16b}, \[x0\], x7
  1c8:  4c876000        st1     {v0.16b-v2.16b}, \[x0\], x7
  1cc:  4c872000        st1     {v0.16b-v3.16b}, \[x0\], x7
  1d0:  4c877400        st1     {v0.8h}, \[x0\], x7
- 1d4:  4c87a400        st1     {v0.8h, v1.8h}, \[x0\], x7
+ 1d4:  4c87a400        st1     {v0.8h-v1.8h}, \[x0\], x7
  1d8:  4c876400        st1     {v0.8h-v2.8h}, \[x0\], x7
  1dc:  4c872400        st1     {v0.8h-v3.8h}, \[x0\], x7
  1e0:  4c877800        st1     {v0.4s}, \[x0\], x7
- 1e4:  4c87a800        st1     {v0.4s, v1.4s}, \[x0\], x7
+ 1e4:  4c87a800        st1     {v0.4s-v1.4s}, \[x0\], x7
  1e8:  4c876800        st1     {v0.4s-v2.4s}, \[x0\], x7
  1ec:  4c872800        st1     {v0.4s-v3.4s}, \[x0\], x7
  1f0:  4c877c00        st1     {v0.2d}, \[x0\], x7
- 1f4:  4c87ac00        st1     {v0.2d, v1.2d}, \[x0\], x7
+ 1f4:  4c87ac00        st1     {v0.2d-v1.2d}, \[x0\], x7
  1f8:  4c876c00        st1     {v0.2d-v2.2d}, \[x0\], x7
  1fc:  4c872c00        st1     {v0.2d-v3.2d}, \[x0\], x7
- 200:  0cdf8000        ld2     {v0.8b, v1.8b}, \[x0\], #16
- 204:  0cc78000        ld2     {v0.8b, v1.8b}, \[x0\], x7
- 208:  0cdf8400        ld2     {v0.4h, v1.4h}, \[x0\], #16
- 20c:  0cc78400        ld2     {v0.4h, v1.4h}, \[x0\], x7
- 210:  0cdf8800        ld2     {v0.2s, v1.2s}, \[x0\], #16
- 214:  0cc78800        ld2     {v0.2s, v1.2s}, \[x0\], x7
- 218:  0c9f8000        st2     {v0.8b, v1.8b}, \[x0\], #16
- 21c:  0c878000        st2     {v0.8b, v1.8b}, \[x0\], x7
- 220:  0c9f8400        st2     {v0.4h, v1.4h}, \[x0\], #16
- 224:  0c878400        st2     {v0.4h, v1.4h}, \[x0\], x7
- 228:  0c9f8800        st2     {v0.2s, v1.2s}, \[x0\], #16
- 22c:  0c878800        st2     {v0.2s, v1.2s}, \[x0\], x7
- 230:  4cdf8000        ld2     {v0.16b, v1.16b}, \[x0\], #32
- 234:  4cc78000        ld2     {v0.16b, v1.16b}, \[x0\], x7
- 238:  4cdf8400        ld2     {v0.8h, v1.8h}, \[x0\], #32
- 23c:  4cc78400        ld2     {v0.8h, v1.8h}, \[x0\], x7
- 240:  4cdf8800        ld2     {v0.4s, v1.4s}, \[x0\], #32
- 244:  4cc78800        ld2     {v0.4s, v1.4s}, \[x0\], x7
- 248:  4cdf8c00        ld2     {v0.2d, v1.2d}, \[x0\], #32
- 24c:  4cc78c00        ld2     {v0.2d, v1.2d}, \[x0\], x7
- 250:  4c9f8000        st2     {v0.16b, v1.16b}, \[x0\], #32
- 254:  4c878000        st2     {v0.16b, v1.16b}, \[x0\], x7
- 258:  4c9f8400        st2     {v0.8h, v1.8h}, \[x0\], #32
- 25c:  4c878400        st2     {v0.8h, v1.8h}, \[x0\], x7
- 260:  4c9f8800        st2     {v0.4s, v1.4s}, \[x0\], #32
- 264:  4c878800        st2     {v0.4s, v1.4s}, \[x0\], x7
- 268:  4c9f8c00        st2     {v0.2d, v1.2d}, \[x0\], #32
- 26c:  4c878c00        st2     {v0.2d, v1.2d}, \[x0\], x7
+ 200:  0cdf8000        ld2     {v0.8b-v1.8b}, \[x0\], #16
+ 204:  0cc78000        ld2     {v0.8b-v1.8b}, \[x0\], x7
+ 208:  0cdf8400        ld2     {v0.4h-v1.4h}, \[x0\], #16
+ 20c:  0cc78400        ld2     {v0.4h-v1.4h}, \[x0\], x7
+ 210:  0cdf8800        ld2     {v0.2s-v1.2s}, \[x0\], #16
+ 214:  0cc78800        ld2     {v0.2s-v1.2s}, \[x0\], x7
+ 218:  0c9f8000        st2     {v0.8b-v1.8b}, \[x0\], #16
+ 21c:  0c878000        st2     {v0.8b-v1.8b}, \[x0\], x7
+ 220:  0c9f8400        st2     {v0.4h-v1.4h}, \[x0\], #16
+ 224:  0c878400        st2     {v0.4h-v1.4h}, \[x0\], x7
+ 228:  0c9f8800        st2     {v0.2s-v1.2s}, \[x0\], #16
+ 22c:  0c878800        st2     {v0.2s-v1.2s}, \[x0\], x7
+ 230:  4cdf8000        ld2     {v0.16b-v1.16b}, \[x0\], #32
+ 234:  4cc78000        ld2     {v0.16b-v1.16b}, \[x0\], x7
+ 238:  4cdf8400        ld2     {v0.8h-v1.8h}, \[x0\], #32
+ 23c:  4cc78400        ld2     {v0.8h-v1.8h}, \[x0\], x7
+ 240:  4cdf8800        ld2     {v0.4s-v1.4s}, \[x0\], #32
+ 244:  4cc78800        ld2     {v0.4s-v1.4s}, \[x0\], x7
+ 248:  4cdf8c00        ld2     {v0.2d-v1.2d}, \[x0\], #32
+ 24c:  4cc78c00        ld2     {v0.2d-v1.2d}, \[x0\], x7
+ 250:  4c9f8000        st2     {v0.16b-v1.16b}, \[x0\], #32
+ 254:  4c878000        st2     {v0.16b-v1.16b}, \[x0\], x7
+ 258:  4c9f8400        st2     {v0.8h-v1.8h}, \[x0\], #32
+ 25c:  4c878400        st2     {v0.8h-v1.8h}, \[x0\], x7
+ 260:  4c9f8800        st2     {v0.4s-v1.4s}, \[x0\], #32
+ 264:  4c878800        st2     {v0.4s-v1.4s}, \[x0\], x7
+ 268:  4c9f8c00        st2     {v0.2d-v1.2d}, \[x0\], #32
+ 26c:  4c878c00        st2     {v0.2d-v1.2d}, \[x0\], x7
  270:  0cdf4000        ld3     {v0.8b-v2.8b}, \[x0\], #24
  274:  0cdf0000        ld4     {v0.8b-v3.8b}, \[x0\], #32
  278:  0cc74000        ld3     {v0.8b-v2.8b}, \[x0\], x7
@@ -218,130 +218,130 @@ Disassembly of section \.text:
  348:  4c874c00        st3     {v0.2d-v2.2d}, \[x0\], x7
  34c:  4c870c00        st4     {v0.2d-v3.2d}, \[x0\], x7
  350:  0ddf0400        ld1     {v0.b}\[1\], \[x0\], #1
- 354:  0dff0400        ld2     {v0.b, v1.b}\[1\], \[x0\], #2
+ 354:  0dff0400        ld2     {v0.b-v1.b}\[1\], \[x0\], #2
  358:  0ddf2400        ld3     {v0.b-v2.b}\[1\], \[x0\], #3
  35c:  0dff2400        ld4     {v0.b-v3.b}\[1\], \[x0\], #4
  360:  0ddfc000        ld1r    {v0.8b}, \[x0\], #1
- 364:  0dffc000        ld2r    {v0.8b, v1.8b}, \[x0\], #2
+ 364:  0dffc000        ld2r    {v0.8b-v1.8b}, \[x0\], #2
  368:  0ddfe000        ld3r    {v0.8b-v2.8b}, \[x0\], #3
  36c:  0dffe000        ld4r    {v0.8b-v3.8b}, \[x0\], #4
  370:  4ddfc000        ld1r    {v0.16b}, \[x0\], #1
- 374:  4dffc000        ld2r    {v0.16b, v1.16b}, \[x0\], #2
+ 374:  4dffc000        ld2r    {v0.16b-v1.16b}, \[x0\], #2
  378:  4ddfe000        ld3r    {v0.16b-v2.16b}, \[x0\], #3
  37c:  4dffe000        ld4r    {v0.16b-v3.16b}, \[x0\], #4
  380:  0d9f0400        st1     {v0.b}\[1\], \[x0\], #1
- 384:  0dbf0400        st2     {v0.b, v1.b}\[1\], \[x0\], #2
+ 384:  0dbf0400        st2     {v0.b-v1.b}\[1\], \[x0\], #2
  388:  0d9f2400        st3     {v0.b-v2.b}\[1\], \[x0\], #3
  38c:  0dbf2400        st4     {v0.b-v3.b}\[1\], \[x0\], #4
  390:  0ddf4800        ld1     {v0.h}\[1\], \[x0\], #2
- 394:  0dff4800        ld2     {v0.h, v1.h}\[1\], \[x0\], #4
+ 394:  0dff4800        ld2     {v0.h-v1.h}\[1\], \[x0\], #4
  398:  0ddf6800        ld3     {v0.h-v2.h}\[1\], \[x0\], #6
  39c:  0dff6800        ld4     {v0.h-v3.h}\[1\], \[x0\], #8
  3a0:  0ddfc400        ld1r    {v0.4h}, \[x0\], #2
- 3a4:  0dffc400        ld2r    {v0.4h, v1.4h}, \[x0\], #4
+ 3a4:  0dffc400        ld2r    {v0.4h-v1.4h}, \[x0\], #4
  3a8:  0ddfe400        ld3r    {v0.4h-v2.4h}, \[x0\], #6
  3ac:  0dffe400        ld4r    {v0.4h-v3.4h}, \[x0\], #8
  3b0:  4ddfc400        ld1r    {v0.8h}, \[x0\], #2
- 3b4:  4dffc400        ld2r    {v0.8h, v1.8h}, \[x0\], #4
+ 3b4:  4dffc400        ld2r    {v0.8h-v1.8h}, \[x0\], #4
  3b8:  4ddfe400        ld3r    {v0.8h-v2.8h}, \[x0\], #6
  3bc:  4dffe400        ld4r    {v0.8h-v3.8h}, \[x0\], #8
  3c0:  0d9f4800        st1     {v0.h}\[1\], \[x0\], #2
- 3c4:  0dbf4800        st2     {v0.h, v1.h}\[1\], \[x0\], #4
+ 3c4:  0dbf4800        st2     {v0.h-v1.h}\[1\], \[x0\], #4
  3c8:  0d9f6800        st3     {v0.h-v2.h}\[1\], \[x0\], #6
  3cc:  0dbf6800        st4     {v0.h-v3.h}\[1\], \[x0\], #8
  3d0:  0ddf9000        ld1     {v0.s}\[1\], \[x0\], #4
- 3d4:  0dff9000        ld2     {v0.s, v1.s}\[1\], \[x0\], #8
+ 3d4:  0dff9000        ld2     {v0.s-v1.s}\[1\], \[x0\], #8
  3d8:  0ddfb000        ld3     {v0.s-v2.s}\[1\], \[x0\], #12
  3dc:  0dffb000        ld4     {v0.s-v3.s}\[1\], \[x0\], #16
  3e0:  0ddfc800        ld1r    {v0.2s}, \[x0\], #4
- 3e4:  0dffc800        ld2r    {v0.2s, v1.2s}, \[x0\], #8
+ 3e4:  0dffc800        ld2r    {v0.2s-v1.2s}, \[x0\], #8
  3e8:  0ddfe800        ld3r    {v0.2s-v2.2s}, \[x0\], #12
  3ec:  0dffe800        ld4r    {v0.2s-v3.2s}, \[x0\], #16
  3f0:  4ddfc800        ld1r    {v0.4s}, \[x0\], #4
- 3f4:  4dffc800        ld2r    {v0.4s, v1.4s}, \[x0\], #8
+ 3f4:  4dffc800        ld2r    {v0.4s-v1.4s}, \[x0\], #8
  3f8:  4ddfe800        ld3r    {v0.4s-v2.4s}, \[x0\], #12
  3fc:  4dffe800        ld4r    {v0.4s-v3.4s}, \[x0\], #16
  400:  0d9f9000        st1     {v0.s}\[1\], \[x0\], #4
- 404:  0dbf9000        st2     {v0.s, v1.s}\[1\], \[x0\], #8
+ 404:  0dbf9000        st2     {v0.s-v1.s}\[1\], \[x0\], #8
  408:  0d9fb000        st3     {v0.s-v2.s}\[1\], \[x0\], #12
  40c:  0dbfb000        st4     {v0.s-v3.s}\[1\], \[x0\], #16
  410:  4ddf8400        ld1     {v0.d}\[1\], \[x0\], #8
- 414:  4dff8400        ld2     {v0.d, v1.d}\[1\], \[x0\], #16
+ 414:  4dff8400        ld2     {v0.d-v1.d}\[1\], \[x0\], #16
  418:  4ddfa400        ld3     {v0.d-v2.d}\[1\], \[x0\], #24
  41c:  4dffa400        ld4     {v0.d-v3.d}\[1\], \[x0\], #32
  420:  0ddfcc00        ld1r    {v0.1d}, \[x0\], #8
- 424:  0dffcc00        ld2r    {v0.1d, v1.1d}, \[x0\], #16
+ 424:  0dffcc00        ld2r    {v0.1d-v1.1d}, \[x0\], #16
  428:  0ddfec00        ld3r    {v0.1d-v2.1d}, \[x0\], #24
  42c:  0dffec00        ld4r    {v0.1d-v3.1d}, \[x0\], #32
  430:  4ddfcc00        ld1r    {v0.2d}, \[x0\], #8
- 434:  4dffcc00        ld2r    {v0.2d, v1.2d}, \[x0\], #16
+ 434:  4dffcc00        ld2r    {v0.2d-v1.2d}, \[x0\], #16
  438:  4ddfec00        ld3r    {v0.2d-v2.2d}, \[x0\], #24
  43c:  4dffec00        ld4r    {v0.2d-v3.2d}, \[x0\], #32
  440:  4d9f8400        st1     {v0.d}\[1\], \[x0\], #8
- 444:  4dbf8400        st2     {v0.d, v1.d}\[1\], \[x0\], #16
+ 444:  4dbf8400        st2     {v0.d-v1.d}\[1\], \[x0\], #16
  448:  4d9fa400        st3     {v0.d-v2.d}\[1\], \[x0\], #24
  44c:  4dbfa400        st4     {v0.d-v3.d}\[1\], \[x0\], #32
  450:  0dc70400        ld1     {v0.b}\[1\], \[x0\], x7
- 454:  0de70400        ld2     {v0.b, v1.b}\[1\], \[x0\], x7
+ 454:  0de70400        ld2     {v0.b-v1.b}\[1\], \[x0\], x7
  458:  0dc72400        ld3     {v0.b-v2.b}\[1\], \[x0\], x7
  45c:  0de72400        ld4     {v0.b-v3.b}\[1\], \[x0\], x7
  460:  0dc74800        ld1     {v0.h}\[1\], \[x0\], x7
- 464:  0de74800        ld2     {v0.h, v1.h}\[1\], \[x0\], x7
+ 464:  0de74800        ld2     {v0.h-v1.h}\[1\], \[x0\], x7
  468:  0dc76800        ld3     {v0.h-v2.h}\[1\], \[x0\], x7
  46c:  0de76800        ld4     {v0.h-v3.h}\[1\], \[x0\], x7
  470:  0dc79000        ld1     {v0.s}\[1\], \[x0\], x7
- 474:  0de79000        ld2     {v0.s, v1.s}\[1\], \[x0\], x7
+ 474:  0de79000        ld2     {v0.s-v1.s}\[1\], \[x0\], x7
  478:  0dc7b000        ld3     {v0.s-v2.s}\[1\], \[x0\], x7
  47c:  0de7b000        ld4     {v0.s-v3.s}\[1\], \[x0\], x7
  480:  4dc78400        ld1     {v0.d}\[1\], \[x0\], x7
- 484:  4de78400        ld2     {v0.d, v1.d}\[1\], \[x0\], x7
+ 484:  4de78400        ld2     {v0.d-v1.d}\[1\], \[x0\], x7
  488:  4dc7a400        ld3     {v0.d-v2.d}\[1\], \[x0\], x7
  48c:  4de7a400        ld4     {v0.d-v3.d}\[1\], \[x0\], x7
  490:  0dc7c000        ld1r    {v0.8b}, \[x0\], x7
- 494:  0de7c000        ld2r    {v0.8b, v1.8b}, \[x0\], x7
+ 494:  0de7c000        ld2r    {v0.8b-v1.8b}, \[x0\], x7
  498:  0dc7e000        ld3r    {v0.8b-v2.8b}, \[x0\], x7
  49c:  0de7e000        ld4r    {v0.8b-v3.8b}, \[x0\], x7
  4a0:  4dc7c000        ld1r    {v0.16b}, \[x0\], x7
- 4a4:  4de7c000        ld2r    {v0.16b, v1.16b}, \[x0\], x7
+ 4a4:  4de7c000        ld2r    {v0.16b-v1.16b}, \[x0\], x7
  4a8:  4dc7e000        ld3r    {v0.16b-v2.16b}, \[x0\], x7
  4ac:  4de7e000        ld4r    {v0.16b-v3.16b}, \[x0\], x7
  4b0:  0dc7c400        ld1r    {v0.4h}, \[x0\], x7
- 4b4:  0de7c400        ld2r    {v0.4h, v1.4h}, \[x0\], x7
+ 4b4:  0de7c400        ld2r    {v0.4h-v1.4h}, \[x0\], x7
  4b8:  0dc7e400        ld3r    {v0.4h-v2.4h}, \[x0\], x7
  4bc:  0de7e400        ld4r    {v0.4h-v3.4h}, \[x0\], x7
  4c0:  4dc7c400        ld1r    {v0.8h}, \[x0\], x7
- 4c4:  4de7c400        ld2r    {v0.8h, v1.8h}, \[x0\], x7
+ 4c4:  4de7c400        ld2r    {v0.8h-v1.8h}, \[x0\], x7
  4c8:  4dc7e400        ld3r    {v0.8h-v2.8h}, \[x0\], x7
  4cc:  4de7e400        ld4r    {v0.8h-v3.8h}, \[x0\], x7
  4d0:  0dc7c800        ld1r    {v0.2s}, \[x0\], x7
- 4d4:  0de7c800        ld2r    {v0.2s, v1.2s}, \[x0\], x7
+ 4d4:  0de7c800        ld2r    {v0.2s-v1.2s}, \[x0\], x7
  4d8:  0dc7e800        ld3r    {v0.2s-v2.2s}, \[x0\], x7
  4dc:  0de7e800        ld4r    {v0.2s-v3.2s}, \[x0\], x7
  4e0:  4dc7c800        ld1r    {v0.4s}, \[x0\], x7
- 4e4:  4de7c800        ld2r    {v0.4s, v1.4s}, \[x0\], x7
+ 4e4:  4de7c800        ld2r    {v0.4s-v1.4s}, \[x0\], x7
  4e8:  4dc7e800        ld3r    {v0.4s-v2.4s}, \[x0\], x7
  4ec:  4de7e800        ld4r    {v0.4s-v3.4s}, \[x0\], x7
  4f0:  0dc7cc00        ld1r    {v0.1d}, \[x0\], x7
- 4f4:  0de7cc00        ld2r    {v0.1d, v1.1d}, \[x0\], x7
+ 4f4:  0de7cc00        ld2r    {v0.1d-v1.1d}, \[x0\], x7
  4f8:  0dc7ec00        ld3r    {v0.1d-v2.1d}, \[x0\], x7
  4fc:  0de7ec00        ld4r    {v0.1d-v3.1d}, \[x0\], x7
  500:  4dc7cc00        ld1r    {v0.2d}, \[x0\], x7
- 504:  4de7cc00        ld2r    {v0.2d, v1.2d}, \[x0\], x7
+ 504:  4de7cc00        ld2r    {v0.2d-v1.2d}, \[x0\], x7
  508:  4dc7ec00        ld3r    {v0.2d-v2.2d}, \[x0\], x7
  50c:  4de7ec00        ld4r    {v0.2d-v3.2d}, \[x0\], x7
  510:  0d870400        st1     {v0.b}\[1\], \[x0\], x7
- 514:  0da70400        st2     {v0.b, v1.b}\[1\], \[x0\], x7
+ 514:  0da70400        st2     {v0.b-v1.b}\[1\], \[x0\], x7
  518:  0d872400        st3     {v0.b-v2.b}\[1\], \[x0\], x7
  51c:  0da72400        st4     {v0.b-v3.b}\[1\], \[x0\], x7
  520:  0d874800        st1     {v0.h}\[1\], \[x0\], x7
- 524:  0da74800        st2     {v0.h, v1.h}\[1\], \[x0\], x7
+ 524:  0da74800        st2     {v0.h-v1.h}\[1\], \[x0\], x7
  528:  0d876800        st3     {v0.h-v2.h}\[1\], \[x0\], x7
  52c:  0da76800        st4     {v0.h-v3.h}\[1\], \[x0\], x7
  530:  0d879000        st1     {v0.s}\[1\], \[x0\], x7
- 534:  0da79000        st2     {v0.s, v1.s}\[1\], \[x0\], x7
+ 534:  0da79000        st2     {v0.s-v1.s}\[1\], \[x0\], x7
  538:  0d87b000        st3     {v0.s-v2.s}\[1\], \[x0\], x7
  53c:  0da7b000        st4     {v0.s-v3.s}\[1\], \[x0\], x7
  540:  4d878400        st1     {v0.d}\[1\], \[x0\], x7
- 544:  4da78400        st2     {v0.d, v1.d}\[1\], \[x0\], x7
+ 544:  4da78400        st2     {v0.d-v1.d}\[1\], \[x0\], x7
  548:  4d87a400        st3     {v0.d-v2.d}\[1\], \[x0\], x7
  54c:  4da7a400        st4     {v0.d-v3.d}\[1\], \[x0\], x7

diff --git a/gas/testsuite/gas/aarch64/neon-vfp-reglist.d b/gas/testsuite/gas/aarch64/neon-vfp-reglist.d
index ad779685d4d616ebb36b1d604cec3f43afaf9aea..a8e7c2df7c2f9de92e564360eb362646324b45af 100644 (file)
--- a/gas/testsuite/gas/aarch64/neon-vfp-reglist.d
+++ b/gas/testsuite/gas/aarch64/neon-vfp-reglist.d
@@ -6,188 +6,188 @@ Disassembly of section \.text:
 
 0+ <.*>:
    0:  0c407000        ld1     {v0.8b}, \[x0\]
-   4:  0c40a000        ld1     {v0.8b, v1.8b}, \[x0\]
+   4:  0c40a000        ld1     {v0.8b-v1.8b}, \[x0\]
    8:  0c406000        ld1     {v0.8b-v2.8b}, \[x0\]
    c:  0c402000        ld1     {v0.8b-v3.8b}, \[x0\]
-  10:  0c408000        ld2     {v0.8b, v1.8b}, \[x0\]
+  10:  0c408000        ld2     {v0.8b-v1.8b}, \[x0\]
   14:  0c404000        ld3     {v0.8b-v2.8b}, \[x0\]
   18:  0c400000        ld4     {v0.8b-v3.8b}, \[x0\]
   1c:  0c007000        st1     {v0.8b}, \[x0\]
-  20:  0c00a000        st1     {v0.8b, v1.8b}, \[x0\]
+  20:  0c00a000        st1     {v0.8b-v1.8b}, \[x0\]
   24:  0c006000        st1     {v0.8b-v2.8b}, \[x0\]
   28:  0c002000        st1     {v0.8b-v3.8b}, \[x0\]
-  2c:  0c008000        st2     {v0.8b, v1.8b}, \[x0\]
+  2c:  0c008000        st2     {v0.8b-v1.8b}, \[x0\]
   30:  0c004000        st3     {v0.8b-v2.8b}, \[x0\]
   34:  0c000000        st4     {v0.8b-v3.8b}, \[x0\]
   38:  4c407000        ld1     {v0.16b}, \[x0\]
-  3c:  4c40a000        ld1     {v0.16b, v1.16b}, \[x0\]
+  3c:  4c40a000        ld1     {v0.16b-v1.16b}, \[x0\]
   40:  4c406000        ld1     {v0.16b-v2.16b}, \[x0\]
   44:  4c402000        ld1     {v0.16b-v3.16b}, \[x0\]
-  48:  4c408000        ld2     {v0.16b, v1.16b}, \[x0\]
+  48:  4c408000        ld2     {v0.16b-v1.16b}, \[x0\]
   4c:  4c404000        ld3     {v0.16b-v2.16b}, \[x0\]
   50:  4c400000        ld4     {v0.16b-v3.16b}, \[x0\]
   54:  4c007000        st1     {v0.16b}, \[x0\]
-  58:  4c00a000        st1     {v0.16b, v1.16b}, \[x0\]
+  58:  4c00a000        st1     {v0.16b-v1.16b}, \[x0\]
   5c:  4c006000        st1     {v0.16b-v2.16b}, \[x0\]
   60:  4c002000        st1     {v0.16b-v3.16b}, \[x0\]
-  64:  4c008000        st2     {v0.16b, v1.16b}, \[x0\]
+  64:  4c008000        st2     {v0.16b-v1.16b}, \[x0\]
   68:  4c004000        st3     {v0.16b-v2.16b}, \[x0\]
   6c:  4c000000        st4     {v0.16b-v3.16b}, \[x0\]
   70:  0c407400        ld1     {v0.4h}, \[x0\]
-  74:  0c40a400        ld1     {v0.4h, v1.4h}, \[x0\]
+  74:  0c40a400        ld1     {v0.4h-v1.4h}, \[x0\]
   78:  0c406400        ld1     {v0.4h-v2.4h}, \[x0\]
   7c:  0c402400        ld1     {v0.4h-v3.4h}, \[x0\]
-  80:  0c408400        ld2     {v0.4h, v1.4h}, \[x0\]
+  80:  0c408400        ld2     {v0.4h-v1.4h}, \[x0\]
   84:  0c404400        ld3     {v0.4h-v2.4h}, \[x0\]
   88:  0c400400        ld4     {v0.4h-v3.4h}, \[x0\]
   8c:  0c007400        st1     {v0.4h}, \[x0\]
-  90:  0c00a400        st1     {v0.4h, v1.4h}, \[x0\]
+  90:  0c00a400        st1     {v0.4h-v1.4h}, \[x0\]
   94:  0c006400        st1     {v0.4h-v2.4h}, \[x0\]
   98:  0c002400        st1     {v0.4h-v3.4h}, \[x0\]
-  9c:  0c008400        st2     {v0.4h, v1.4h}, \[x0\]
+  9c:  0c008400        st2     {v0.4h-v1.4h}, \[x0\]
   a0:  0c004400        st3     {v0.4h-v2.4h}, \[x0\]
   a4:  0c000400        st4     {v0.4h-v3.4h}, \[x0\]
   a8:  4c407400        ld1     {v0.8h}, \[x0\]
-  ac:  4c40a400        ld1     {v0.8h, v1.8h}, \[x0\]
+  ac:  4c40a400        ld1     {v0.8h-v1.8h}, \[x0\]
   b0:  4c406400        ld1     {v0.8h-v2.8h}, \[x0\]
   b4:  4c402400        ld1     {v0.8h-v3.8h}, \[x0\]
-  b8:  4c408400        ld2     {v0.8h, v1.8h}, \[x0\]
+  b8:  4c408400        ld2     {v0.8h-v1.8h}, \[x0\]
   bc:  4c404400        ld3     {v0.8h-v2.8h}, \[x0\]
   c0:  4c400400        ld4     {v0.8h-v3.8h}, \[x0\]
   c4:  4c007400        st1     {v0.8h}, \[x0\]
-  c8:  4c00a400        st1     {v0.8h, v1.8h}, \[x0\]
+  c8:  4c00a400        st1     {v0.8h-v1.8h}, \[x0\]
   cc:  4c006400        st1     {v0.8h-v2.8h}, \[x0\]
   d0:  4c002400        st1     {v0.8h-v3.8h}, \[x0\]
-  d4:  4c008400        st2     {v0.8h, v1.8h}, \[x0\]
+  d4:  4c008400        st2     {v0.8h-v1.8h}, \[x0\]
   d8:  4c004400        st3     {v0.8h-v2.8h}, \[x0\]
   dc:  4c000400        st4     {v0.8h-v3.8h}, \[x0\]
   e0:  0c407800        ld1     {v0.2s}, \[x0\]
-  e4:  0c40a800        ld1     {v0.2s, v1.2s}, \[x0\]
+  e4:  0c40a800        ld1     {v0.2s-v1.2s}, \[x0\]
   e8:  0c406800        ld1     {v0.2s-v2.2s}, \[x0\]
   ec:  0c402800        ld1     {v0.2s-v3.2s}, \[x0\]
-  f0:  0c408800        ld2     {v0.2s, v1.2s}, \[x0\]
+  f0:  0c408800        ld2     {v0.2s-v1.2s}, \[x0\]
   f4:  0c404800        ld3     {v0.2s-v2.2s}, \[x0\]
   f8:  0c400800        ld4     {v0.2s-v3.2s}, \[x0\]
   fc:  0c007800        st1     {v0.2s}, \[x0\]
- 100:  0c00a800        st1     {v0.2s, v1.2s}, \[x0\]
+ 100:  0c00a800        st1     {v0.2s-v1.2s}, \[x0\]
  104:  0c006800        st1     {v0.2s-v2.2s}, \[x0\]
  108:  0c002800        st1     {v0.2s-v3.2s}, \[x0\]
- 10c:  0c008800        st2     {v0.2s, v1.2s}, \[x0\]
+ 10c:  0c008800        st2     {v0.2s-v1.2s}, \[x0\]
  110:  0c004800        st3     {v0.2s-v2.2s}, \[x0\]
  114:  0c000800        st4     {v0.2s-v3.2s}, \[x0\]
  118:  4c407800        ld1     {v0.4s}, \[x0\]
- 11c:  4c40a800        ld1     {v0.4s, v1.4s}, \[x0\]
+ 11c:  4c40a800        ld1     {v0.4s-v1.4s}, \[x0\]
  120:  4c406800        ld1     {v0.4s-v2.4s}, \[x0\]
  124:  4c402800        ld1     {v0.4s-v3.4s}, \[x0\]
- 128:  4c408800        ld2     {v0.4s, v1.4s}, \[x0\]
+ 128:  4c408800        ld2     {v0.4s-v1.4s}, \[x0\]
  12c:  4c404800        ld3     {v0.4s-v2.4s}, \[x0\]
  130:  4c400800        ld4     {v0.4s-v3.4s}, \[x0\]
  134:  4c007800        st1     {v0.4s}, \[x0\]
- 138:  4c00a800        st1     {v0.4s, v1.4s}, \[x0\]
+ 138:  4c00a800        st1     {v0.4s-v1.4s}, \[x0\]
  13c:  4c006800        st1     {v0.4s-v2.4s}, \[x0\]
  140:  4c002800        st1     {v0.4s-v3.4s}, \[x0\]
- 144:  4c008800        st2     {v0.4s, v1.4s}, \[x0\]
+ 144:  4c008800        st2     {v0.4s-v1.4s}, \[x0\]
  148:  4c004800        st3     {v0.4s-v2.4s}, \[x0\]
  14c:  4c000800        st4     {v0.4s-v3.4s}, \[x0\]
  150:  4c407c00        ld1     {v0.2d}, \[x0\]
- 154:  4c40ac00        ld1     {v0.2d, v1.2d}, \[x0\]
+ 154:  4c40ac00        ld1     {v0.2d-v1.2d}, \[x0\]
  158:  4c406c00        ld1     {v0.2d-v2.2d}, \[x0\]
  15c:  4c402c00        ld1     {v0.2d-v3.2d}, \[x0\]
- 160:  4c408c00        ld2     {v0.2d, v1.2d}, \[x0\]
+ 160:  4c408c00        ld2     {v0.2d-v1.2d}, \[x0\]
  164:  4c404c00        ld3     {v0.2d-v2.2d}, \[x0\]
  168:  4c400c00        ld4     {v0.2d-v3.2d}, \[x0\]
  16c:  4c007c00        st1     {v0.2d}, \[x0\]
- 170:  4c00ac00        st1     {v0.2d, v1.2d}, \[x0\]
+ 170:  4c00ac00        st1     {v0.2d-v1.2d}, \[x0\]
  174:  4c006c00        st1     {v0.2d-v2.2d}, \[x0\]
  178:  4c002c00        st1     {v0.2d-v3.2d}, \[x0\]
- 17c:  4c008c00        st2     {v0.2d, v1.2d}, \[x0\]
+ 17c:  4c008c00        st2     {v0.2d-v1.2d}, \[x0\]
  180:  4c004c00        st3     {v0.2d-v2.2d}, \[x0\]
  184:  4c000c00        st4     {v0.2d-v3.2d}, \[x0\]
  188:  0d400400        ld1     {v0.b}\[1\], \[x0\]
- 18c:  0d600400        ld2     {v0.b, v1.b}\[1\], \[x0\]
+ 18c:  0d600400        ld2     {v0.b-v1.b}\[1\], \[x0\]
  190:  0d402400        ld3     {v0.b-v2.b}\[1\], \[x0\]
  194:  0d602400        ld4     {v0.b-v3.b}\[1\], \[x0\]
  198:  0d000400        st1     {v0.b}\[1\], \[x0\]
- 19c:  0d200400        st2     {v0.b, v1.b}\[1\], \[x0\]
+ 19c:  0d200400        st2     {v0.b-v1.b}\[1\], \[x0\]
  1a0:  0d002400        st3     {v0.b-v2.b}\[1\], \[x0\]
  1a4:  0d202400        st4     {v0.b-v3.b}\[1\], \[x0\]
  1a8:  0d400400        ld1     {v0.b}\[1\], \[x0\]
- 1ac:  0d600400        ld2     {v0.b, v1.b}\[1\], \[x0\]
+ 1ac:  0d600400        ld2     {v0.b-v1.b}\[1\], \[x0\]
  1b0:  0d402400        ld3     {v0.b-v2.b}\[1\], \[x0\]
  1b4:  0d602400        ld4     {v0.b-v3.b}\[1\], \[x0\]
  1b8:  0d000400        st1     {v0.b}\[1\], \[x0\]
- 1bc:  0d200400        st2     {v0.b, v1.b}\[1\], \[x0\]
+ 1bc:  0d200400        st2     {v0.b-v1.b}\[1\], \[x0\]
  1c0:  0d002400        st3     {v0.b-v2.b}\[1\], \[x0\]
  1c4:  0d202400        st4     {v0.b-v3.b}\[1\], \[x0\]
  1c8:  0d404800        ld1     {v0.h}\[1\], \[x0\]
- 1cc:  0d604800        ld2     {v0.h, v1.h}\[1\], \[x0\]
+ 1cc:  0d604800        ld2     {v0.h-v1.h}\[1\], \[x0\]
  1d0:  0d406800        ld3     {v0.h-v2.h}\[1\], \[x0\]
  1d4:  0d606800        ld4     {v0.h-v3.h}\[1\], \[x0\]
  1d8:  0d004800        st1     {v0.h}\[1\], \[x0\]
- 1dc:  0d204800        st2     {v0.h, v1.h}\[1\], \[x0\]
+ 1dc:  0d204800        st2     {v0.h-v1.h}\[1\], \[x0\]
  1e0:  0d006800        st3     {v0.h-v2.h}\[1\], \[x0\]
  1e4:  0d206800        st4     {v0.h-v3.h}\[1\], \[x0\]
  1e8:  0d404800        ld1     {v0.h}\[1\], \[x0\]
- 1ec:  0d604800        ld2     {v0.h, v1.h}\[1\], \[x0\]
+ 1ec:  0d604800        ld2     {v0.h-v1.h}\[1\], \[x0\]
  1f0:  0d406800        ld3     {v0.h-v2.h}\[1\], \[x0\]
  1f4:  0d606800        ld4     {v0.h-v3.h}\[1\], \[x0\]
  1f8:  0d004800        st1     {v0.h}\[1\], \[x0\]
- 1fc:  0d204800        st2     {v0.h, v1.h}\[1\], \[x0\]
+ 1fc:  0d204800        st2     {v0.h-v1.h}\[1\], \[x0\]
  200:  0d006800        st3     {v0.h-v2.h}\[1\], \[x0\]
  204:  0d206800        st4     {v0.h-v3.h}\[1\], \[x0\]
  208:  0d409000        ld1     {v0.s}\[1\], \[x0\]
- 20c:  0d609000        ld2     {v0.s, v1.s}\[1\], \[x0\]
+ 20c:  0d609000        ld2     {v0.s-v1.s}\[1\], \[x0\]
  210:  0d40b000        ld3     {v0.s-v2.s}\[1\], \[x0\]
  214:  0d60b000        ld4     {v0.s-v3.s}\[1\], \[x0\]
  218:  0d009000        st1     {v0.s}\[1\], \[x0\]
- 21c:  0d209000        st2     {v0.s, v1.s}\[1\], \[x0\]
+ 21c:  0d209000        st2     {v0.s-v1.s}\[1\], \[x0\]
  220:  0d00b000        st3     {v0.s-v2.s}\[1\], \[x0\]
  224:  0d20b000        st4     {v0.s-v3.s}\[1\], \[x0\]
  228:  0d409000        ld1     {v0.s}\[1\], \[x0\]
- 22c:  0d609000        ld2     {v0.s, v1.s}\[1\], \[x0\]
+ 22c:  0d609000        ld2     {v0.s-v1.s}\[1\], \[x0\]
  230:  0d40b000        ld3     {v0.s-v2.s}\[1\], \[x0\]
  234:  0d60b000        ld4     {v0.s-v3.s}\[1\], \[x0\]
  238:  0d009000        st1     {v0.s}\[1\], \[x0\]
- 23c:  0d209000        st2     {v0.s, v1.s}\[1\], \[x0\]
+ 23c:  0d209000        st2     {v0.s-v1.s}\[1\], \[x0\]
  240:  0d00b000        st3     {v0.s-v2.s}\[1\], \[x0\]
  244:  0d20b000        st4     {v0.s-v3.s}\[1\], \[x0\]
  248:  4d408400        ld1     {v0.d}\[1\], \[x0\]
- 24c:  4d608400        ld2     {v0.d, v1.d}\[1\], \[x0\]
+ 24c:  4d608400        ld2     {v0.d-v1.d}\[1\], \[x0\]
  250:  4d40a400        ld3     {v0.d-v2.d}\[1\], \[x0\]
  254:  4d60a400        ld4     {v0.d-v3.d}\[1\], \[x0\]
  258:  4d008400        st1     {v0.d}\[1\], \[x0\]
- 25c:  4d208400        st2     {v0.d, v1.d}\[1\], \[x0\]
+ 25c:  4d208400        st2     {v0.d-v1.d}\[1\], \[x0\]
  260:  4d00a400        st3     {v0.d-v2.d}\[1\], \[x0\]
  264:  4d20a400        st4     {v0.d-v3.d}\[1\], \[x0\]
  268:  0d40c000        ld1r    {v0.8b}, \[x0\]
- 26c:  0d60c000        ld2r    {v0.8b, v1.8b}, \[x0\]
+ 26c:  0d60c000        ld2r    {v0.8b-v1.8b}, \[x0\]
  270:  0d40e000        ld3r    {v0.8b-v2.8b}, \[x0\]
  274:  0d60e000        ld4r    {v0.8b-v3.8b}, \[x0\]
  278:  4d40c000        ld1r    {v0.16b}, \[x0\]
- 27c:  4d60c000        ld2r    {v0.16b, v1.16b}, \[x0\]
+ 27c:  4d60c000        ld2r    {v0.16b-v1.16b}, \[x0\]
  280:  4d40e000        ld3r    {v0.16b-v2.16b}, \[x0\]
  284:  4d60e000        ld4r    {v0.16b-v3.16b}, \[x0\]
  288:  0d40c400        ld1r    {v0.4h}, \[x0\]
- 28c:  0d60c400        ld2r    {v0.4h, v1.4h}, \[x0\]
+ 28c:  0d60c400        ld2r    {v0.4h-v1.4h}, \[x0\]
  290:  0d40e400        ld3r    {v0.4h-v2.4h}, \[x0\]
  294:  0d60e400        ld4r    {v0.4h-v3.4h}, \[x0\]
  298:  4d40c400        ld1r    {v0.8h}, \[x0\]
- 29c:  4d60c400        ld2r    {v0.8h, v1.8h}, \[x0\]
+ 29c:  4d60c400        ld2r    {v0.8h-v1.8h}, \[x0\]
  2a0:  4d40e400        ld3r    {v0.8h-v2.8h}, \[x0\]
  2a4:  4d60e400        ld4r    {v0.8h-v3.8h}, \[x0\]
  2a8:  0d40c800        ld1r    {v0.2s}, \[x0\]
- 2ac:  0d60c800        ld2r    {v0.2s, v1.2s}, \[x0\]
+ 2ac:  0d60c800        ld2r    {v0.2s-v1.2s}, \[x0\]
  2b0:  0d40e800        ld3r    {v0.2s-v2.2s}, \[x0\]
  2b4:  0d60e800        ld4r    {v0.2s-v3.2s}, \[x0\]
  2b8:  4d40c800        ld1r    {v0.4s}, \[x0\]
- 2bc:  4d60c800        ld2r    {v0.4s, v1.4s}, \[x0\]
+ 2bc:  4d60c800        ld2r    {v0.4s-v1.4s}, \[x0\]
  2c0:  4d40e800        ld3r    {v0.4s-v2.4s}, \[x0\]
  2c4:  4d60e800        ld4r    {v0.4s-v3.4s}, \[x0\]
  2c8:  0d40cc00        ld1r    {v0.1d}, \[x0\]
- 2cc:  0d60cc00        ld2r    {v0.1d, v1.1d}, \[x0\]
+ 2cc:  0d60cc00        ld2r    {v0.1d-v1.1d}, \[x0\]
  2d0:  0d40ec00        ld3r    {v0.1d-v2.1d}, \[x0\]
  2d4:  0d60ec00        ld4r    {v0.1d-v3.1d}, \[x0\]
  2d8:  4d40cc00        ld1r    {v0.2d}, \[x0\]
- 2dc:  4d60cc00        ld2r    {v0.2d, v1.2d}, \[x0\]
+ 2dc:  4d60cc00        ld2r    {v0.2d-v1.2d}, \[x0\]
  2e0:  4d40ec00        ld3r    {v0.2d-v2.2d}, \[x0\]
  2e4:  4d60ec00        ld4r    {v0.2d-v3.2d}, \[x0\]

diff --git a/gas/testsuite/gas/aarch64/reglist-1.d b/gas/testsuite/gas/aarch64/reglist-1.d
new file mode 100644 (file)
index 0000000..5ab8170
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reglist-1.d
@@ -0,0 +1,21 @@
+#as: -march=armv8-a+sve
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: 4c40ac1f        ld1     {v31\.2d-v0\.2d}, \[x0\]
+[^:]+: 4c40681f        ld1     {v31\.4s-v1\.4s}, \[x0\]
+[^:]+: 4c40241f        ld1     {v31\.8h-v2\.8h}, \[x0\]
+[^:]+: 4c40201e        ld1     {v30\.16b-v1\.16b}, \[x0\]
+[^:]+: 0c40601e        ld1     {v30\.8b-v0\.8b}, \[x0\]
+[^:]+: 0c40241d        ld1     {v29\.4h-v0\.4h}, \[x0\]
+[^:]+: a420e01f        ld2b    {z31\.b-z0\.b}, p0/z, \[x0\]
+[^:]+: a440e01e        ld3b    {z30\.b-z0\.b}, p0/z, \[x0\]
+[^:]+: a440e01f        ld3b    {z31\.b-z1\.b}, p0/z, \[x0\]
+[^:]+: a460e01d        ld4b    {z29\.b-z0\.b}, p0/z, \[x0\]
+[^:]+: a460e01e        ld4b    {z30\.b-z1\.b}, p0/z, \[x0\]
+[^:]+: a460e01f        ld4b    {z31\.b-z2\.b}, p0/z, \[x0\]

diff --git a/gas/testsuite/gas/aarch64/reglist-1.s b/gas/testsuite/gas/aarch64/reglist-1.s
new file mode 100644 (file)
index 0000000..631688f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reglist-1.s
@@ -0,0 +1,15 @@
+       ld1     { v31.2d - v0.2d }, [x0]
+       ld1     { v31.4s - v1.4s }, [x0]
+       ld1     { v31.8h - v2.8h }, [x0]
+       ld1     { v30.16b - v1.16b }, [x0]
+       ld1     { v30.8b - v0.8b }, [x0]
+       ld1     { v29.4h - v0.4h }, [x0]
+
+       ld2b    { z31.b - z0.b }, p0/z, [x0]
+
+       ld3b    { z30.b - z0.b }, p0/z, [x0]
+       ld3b    { z31.b - z1.b }, p0/z, [x0]
+
+       ld4b    { z29.b - z0.b }, p0/z, [x0]
+       ld4b    { z30.b - z1.b }, p0/z, [x0]
+       ld4b    { z31.b - z2.b }, p0/z, [x0]

diff --git a/gas/testsuite/gas/aarch64/reglist-2.d b/gas/testsuite/gas/aarch64/reglist-2.d
new file mode 100644 (file)
index 0000000..7bfc14b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reglist-2.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: reglist-2.s
+#error_output: reglist-2.l

diff --git a/gas/testsuite/gas/aarch64/reglist-2.l b/gas/testsuite/gas/aarch64/reglist-2.l
new file mode 100644 (file)
index 0000000..9d7dfbe
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reglist-2.l
@@ -0,0 +1,8 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v1\.2d-v0\.2d},\[x0\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v31\.2d-v3\.2d},\[x0\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v30\.2d-v2\.2d},\[x0\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v29\.2d-v1\.2d},\[x0\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `ld1 {v31\.2d-v30\.2d},\[x0\]'
+[^ :]+:[0-9]+: Error: invalid range in vector register list at operand 1 -- `ld1 {v0\.2d-v0\.2d},\[x0\]'
+[^ :]+:[0-9]+: Error: invalid range in vector register list at operand 1 -- `ld1 {v31\.2d-v31\.2d},\[x0\]'

diff --git a/gas/testsuite/gas/aarch64/reglist-2.s b/gas/testsuite/gas/aarch64/reglist-2.s
new file mode 100644 (file)
index 0000000..91a6cbf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/reglist-2.s
@@ -0,0 +1,7 @@
+       ld1     { v1.2d - v0.2d }, [x0]
+       ld1     { v31.2d - v3.2d }, [x0]
+       ld1     { v30.2d - v2.2d }, [x0]
+       ld1     { v29.2d - v1.2d }, [x0]
+       ld1     { v31.2d - v30.2d }, [x0]
+       ld1     { v0.2d - v0.2d }, [x0]
+       ld1     { v31.2d - v31.2d }, [x0]

diff --git a/gas/testsuite/gas/aarch64/sve.d b/gas/testsuite/gas/aarch64/sve.d
index ee5ba485f3cd8108cc3e78c9bc2a72357663dcc9..e3a6aab392c7469dcc75a7317b150c4df4740dad 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve.d
+++ b/gas/testsuite/gas/aarch64/sve.d
@@ -17486,359 +17486,359 @@ Disassembly of section .*:
 [^:]+: c531c000        ld1w    {z0.d}, p0/z, \[z0.d, #68\]
 [^:]+: c53fc000        ld1w    {z0.d}, p0/z, \[z0.d, #124\]
 [^:]+: c53fc000        ld1w    {z0.d}, p0/z, \[z0.d, #124\]
-[^:]+: a420c000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a420c000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a420c000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a420c000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a420c000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a420c001        ld2b    {z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a420c001        ld2b    {z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a420c001        ld2b    {z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a420c001        ld2b    {z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a420c001        ld2b    {z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a420c01f        ld2b    {z31.b, z0.b}, p0/z, \[x0, x0\]
-[^:]+: a420c01f        ld2b    {z31.b, z0.b}, p0/z, \[x0, x0\]
-[^:]+: a420c01f        ld2b    {z31.b, z0.b}, p0/z, \[x0, x0\]
-[^:]+: a420c800        ld2b    {z0.b, z1.b}, p2/z, \[x0, x0\]
-[^:]+: a420c800        ld2b    {z0.b, z1.b}, p2/z, \[x0, x0\]
-[^:]+: a420c800        ld2b    {z0.b, z1.b}, p2/z, \[x0, x0\]
-[^:]+: a420c800        ld2b    {z0.b, z1.b}, p2/z, \[x0, x0\]
-[^:]+: a420c800        ld2b    {z0.b, z1.b}, p2/z, \[x0, x0\]
-[^:]+: a420dc00        ld2b    {z0.b, z1.b}, p7/z, \[x0, x0\]
-[^:]+: a420dc00        ld2b    {z0.b, z1.b}, p7/z, \[x0, x0\]
-[^:]+: a420dc00        ld2b    {z0.b, z1.b}, p7/z, \[x0, x0\]
-[^:]+: a420dc00        ld2b    {z0.b, z1.b}, p7/z, \[x0, x0\]
-[^:]+: a420dc00        ld2b    {z0.b, z1.b}, p7/z, \[x0, x0\]
-[^:]+: a420c060        ld2b    {z0.b, z1.b}, p0/z, \[x3, x0\]
-[^:]+: a420c060        ld2b    {z0.b, z1.b}, p0/z, \[x3, x0\]
-[^:]+: a420c060        ld2b    {z0.b, z1.b}, p0/z, \[x3, x0\]
-[^:]+: a420c060        ld2b    {z0.b, z1.b}, p0/z, \[x3, x0\]
-[^:]+: a420c060        ld2b    {z0.b, z1.b}, p0/z, \[x3, x0\]
-[^:]+: a420c3e0        ld2b    {z0.b, z1.b}, p0/z, \[sp, x0\]
-[^:]+: a420c3e0        ld2b    {z0.b, z1.b}, p0/z, \[sp, x0\]
-[^:]+: a420c3e0        ld2b    {z0.b, z1.b}, p0/z, \[sp, x0\]
-[^:]+: a420c3e0        ld2b    {z0.b, z1.b}, p0/z, \[sp, x0\]
-[^:]+: a420c3e0        ld2b    {z0.b, z1.b}, p0/z, \[sp, x0\]
-[^:]+: a424c000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x4\]
-[^:]+: a424c000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x4\]
-[^:]+: a424c000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x4\]
-[^:]+: a424c000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x4\]
-[^:]+: a424c000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x4\]
-[^:]+: a43ec000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x30\]
-[^:]+: a43ec000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x30\]
-[^:]+: a43ec000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x30\]
-[^:]+: a43ec000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x30\]
-[^:]+: a43ec000        ld2b    {z0.b, z1.b}, p0/z, \[x0, x30\]
-[^:]+: a420e000        ld2b    {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e000        ld2b    {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e000        ld2b    {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e000        ld2b    {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e000        ld2b    {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e000        ld2b    {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e000        ld2b    {z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a420e001        ld2b    {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e001        ld2b    {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e001        ld2b    {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e001        ld2b    {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e001        ld2b    {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e001        ld2b    {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e001        ld2b    {z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a420e01f        ld2b    {z31.b, z0.b}, p0/z, \[x0\]
-[^:]+: a420e01f        ld2b    {z31.b, z0.b}, p0/z, \[x0\]
-[^:]+: a420e01f        ld2b    {z31.b, z0.b}, p0/z, \[x0\]
-[^:]+: a420e01f        ld2b    {z31.b, z0.b}, p0/z, \[x0\]
-[^:]+: a420e800        ld2b    {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420e800        ld2b    {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420e800        ld2b    {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420e800        ld2b    {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420e800        ld2b    {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420e800        ld2b    {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420e800        ld2b    {z0.b, z1.b}, p2/z, \[x0\]
-[^:]+: a420fc00        ld2b    {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420fc00        ld2b    {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420fc00        ld2b    {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420fc00        ld2b    {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420fc00        ld2b    {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420fc00        ld2b    {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420fc00        ld2b    {z0.b, z1.b}, p7/z, \[x0\]
-[^:]+: a420e060        ld2b    {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e060        ld2b    {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e060        ld2b    {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e060        ld2b    {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e060        ld2b    {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e060        ld2b    {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e060        ld2b    {z0.b, z1.b}, p0/z, \[x3\]
-[^:]+: a420e3e0        ld2b    {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a420e3e0        ld2b    {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a420e3e0        ld2b    {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a420e3e0        ld2b    {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a420e3e0        ld2b    {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a420e3e0        ld2b    {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a420e3e0        ld2b    {z0.b, z1.b}, p0/z, \[sp\]
-[^:]+: a427e000        ld2b    {z0.b, z1.b}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a427e000        ld2b    {z0.b, z1.b}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a427e000        ld2b    {z0.b, z1.b}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a428e000        ld2b    {z0.b, z1.b}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a428e000        ld2b    {z0.b, z1.b}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a428e000        ld2b    {z0.b, z1.b}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a429e000        ld2b    {z0.b, z1.b}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a429e000        ld2b    {z0.b, z1.b}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a429e000        ld2b    {z0.b, z1.b}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a42fe000        ld2b    {z0.b, z1.b}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a42fe000        ld2b    {z0.b, z1.b}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a42fe000        ld2b    {z0.b, z1.b}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a5a0c000        ld2d    {z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c000        ld2d    {z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c000        ld2d    {z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c001        ld2d    {z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c001        ld2d    {z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c001        ld2d    {z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c01f        ld2d    {z31.d, z0.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c01f        ld2d    {z31.d, z0.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c800        ld2d    {z0.d, z1.d}, p2/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c800        ld2d    {z0.d, z1.d}, p2/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c800        ld2d    {z0.d, z1.d}, p2/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0dc00        ld2d    {z0.d, z1.d}, p7/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0dc00        ld2d    {z0.d, z1.d}, p7/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0dc00        ld2d    {z0.d, z1.d}, p7/z, \[x0, x0, lsl #3\]
-[^:]+: a5a0c060        ld2d    {z0.d, z1.d}, p0/z, \[x3, x0, lsl #3\]
-[^:]+: a5a0c060        ld2d    {z0.d, z1.d}, p0/z, \[x3, x0, lsl #3\]
-[^:]+: a5a0c060        ld2d    {z0.d, z1.d}, p0/z, \[x3, x0, lsl #3\]
-[^:]+: a5a0c3e0        ld2d    {z0.d, z1.d}, p0/z, \[sp, x0, lsl #3\]
-[^:]+: a5a0c3e0        ld2d    {z0.d, z1.d}, p0/z, \[sp, x0, lsl #3\]
-[^:]+: a5a0c3e0        ld2d    {z0.d, z1.d}, p0/z, \[sp, x0, lsl #3\]
-[^:]+: a5a4c000        ld2d    {z0.d, z1.d}, p0/z, \[x0, x4, lsl #3\]
-[^:]+: a5a4c000        ld2d    {z0.d, z1.d}, p0/z, \[x0, x4, lsl #3\]
-[^:]+: a5a4c000        ld2d    {z0.d, z1.d}, p0/z, \[x0, x4, lsl #3\]
-[^:]+: a5bec000        ld2d    {z0.d, z1.d}, p0/z, \[x0, x30, lsl #3\]
-[^:]+: a5bec000        ld2d    {z0.d, z1.d}, p0/z, \[x0, x30, lsl #3\]
-[^:]+: a5bec000        ld2d    {z0.d, z1.d}, p0/z, \[x0, x30, lsl #3\]
-[^:]+: a5a0e000        ld2d    {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e000        ld2d    {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e000        ld2d    {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e000        ld2d    {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e000        ld2d    {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e000        ld2d    {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e000        ld2d    {z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5a0e001        ld2d    {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e001        ld2d    {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e001        ld2d    {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e001        ld2d    {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e001        ld2d    {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e001        ld2d    {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e001        ld2d    {z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5a0e01f        ld2d    {z31.d, z0.d}, p0/z, \[x0\]
-[^:]+: a5a0e01f        ld2d    {z31.d, z0.d}, p0/z, \[x0\]
-[^:]+: a5a0e01f        ld2d    {z31.d, z0.d}, p0/z, \[x0\]
-[^:]+: a5a0e01f        ld2d    {z31.d, z0.d}, p0/z, \[x0\]
-[^:]+: a5a0e800        ld2d    {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0e800        ld2d    {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0e800        ld2d    {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0e800        ld2d    {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0e800        ld2d    {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0e800        ld2d    {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0e800        ld2d    {z0.d, z1.d}, p2/z, \[x0\]
-[^:]+: a5a0fc00        ld2d    {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0fc00        ld2d    {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0fc00        ld2d    {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0fc00        ld2d    {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0fc00        ld2d    {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0fc00        ld2d    {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0fc00        ld2d    {z0.d, z1.d}, p7/z, \[x0\]
-[^:]+: a5a0e060        ld2d    {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e060        ld2d    {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e060        ld2d    {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e060        ld2d    {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e060        ld2d    {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e060        ld2d    {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e060        ld2d    {z0.d, z1.d}, p0/z, \[x3\]
-[^:]+: a5a0e3e0        ld2d    {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a0e3e0        ld2d    {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a0e3e0        ld2d    {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a0e3e0        ld2d    {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a0e3e0        ld2d    {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a0e3e0        ld2d    {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a0e3e0        ld2d    {z0.d, z1.d}, p0/z, \[sp\]
-[^:]+: a5a7e000        ld2d    {z0.d, z1.d}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a5a7e000        ld2d    {z0.d, z1.d}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a5a7e000        ld2d    {z0.d, z1.d}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a5a8e000        ld2d    {z0.d, z1.d}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a5a8e000        ld2d    {z0.d, z1.d}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a5a8e000        ld2d    {z0.d, z1.d}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a5a9e000        ld2d    {z0.d, z1.d}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a5a9e000        ld2d    {z0.d, z1.d}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a5a9e000        ld2d    {z0.d, z1.d}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a5afe000        ld2d    {z0.d, z1.d}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a5afe000        ld2d    {z0.d, z1.d}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a5afe000        ld2d    {z0.d, z1.d}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a4a0c000        ld2h    {z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c000        ld2h    {z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c000        ld2h    {z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c001        ld2h    {z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c001        ld2h    {z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c001        ld2h    {z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c01f        ld2h    {z31.h, z0.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c01f        ld2h    {z31.h, z0.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c800        ld2h    {z0.h, z1.h}, p2/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c800        ld2h    {z0.h, z1.h}, p2/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c800        ld2h    {z0.h, z1.h}, p2/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0dc00        ld2h    {z0.h, z1.h}, p7/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0dc00        ld2h    {z0.h, z1.h}, p7/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0dc00        ld2h    {z0.h, z1.h}, p7/z, \[x0, x0, lsl #1\]
-[^:]+: a4a0c060        ld2h    {z0.h, z1.h}, p0/z, \[x3, x0, lsl #1\]
-[^:]+: a4a0c060        ld2h    {z0.h, z1.h}, p0/z, \[x3, x0, lsl #1\]
-[^:]+: a4a0c060        ld2h    {z0.h, z1.h}, p0/z, \[x3, x0, lsl #1\]
-[^:]+: a4a0c3e0        ld2h    {z0.h, z1.h}, p0/z, \[sp, x0, lsl #1\]
-[^:]+: a4a0c3e0        ld2h    {z0.h, z1.h}, p0/z, \[sp, x0, lsl #1\]
-[^:]+: a4a0c3e0        ld2h    {z0.h, z1.h}, p0/z, \[sp, x0, lsl #1\]
-[^:]+: a4a4c000        ld2h    {z0.h, z1.h}, p0/z, \[x0, x4, lsl #1\]
-[^:]+: a4a4c000        ld2h    {z0.h, z1.h}, p0/z, \[x0, x4, lsl #1\]
-[^:]+: a4a4c000        ld2h    {z0.h, z1.h}, p0/z, \[x0, x4, lsl #1\]
-[^:]+: a4bec000        ld2h    {z0.h, z1.h}, p0/z, \[x0, x30, lsl #1\]
-[^:]+: a4bec000        ld2h    {z0.h, z1.h}, p0/z, \[x0, x30, lsl #1\]
-[^:]+: a4bec000        ld2h    {z0.h, z1.h}, p0/z, \[x0, x30, lsl #1\]
-[^:]+: a4a0e000        ld2h    {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e000        ld2h    {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e000        ld2h    {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e000        ld2h    {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e000        ld2h    {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e000        ld2h    {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e000        ld2h    {z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4a0e001        ld2h    {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e001        ld2h    {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e001        ld2h    {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e001        ld2h    {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e001        ld2h    {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e001        ld2h    {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e001        ld2h    {z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4a0e01f        ld2h    {z31.h, z0.h}, p0/z, \[x0\]
-[^:]+: a4a0e01f        ld2h    {z31.h, z0.h}, p0/z, \[x0\]
-[^:]+: a4a0e01f        ld2h    {z31.h, z0.h}, p0/z, \[x0\]
-[^:]+: a4a0e01f        ld2h    {z31.h, z0.h}, p0/z, \[x0\]
-[^:]+: a4a0e800        ld2h    {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0e800        ld2h    {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0e800        ld2h    {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0e800        ld2h    {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0e800        ld2h    {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0e800        ld2h    {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0e800        ld2h    {z0.h, z1.h}, p2/z, \[x0\]
-[^:]+: a4a0fc00        ld2h    {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0fc00        ld2h    {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0fc00        ld2h    {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0fc00        ld2h    {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0fc00        ld2h    {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0fc00        ld2h    {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0fc00        ld2h    {z0.h, z1.h}, p7/z, \[x0\]
-[^:]+: a4a0e060        ld2h    {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e060        ld2h    {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e060        ld2h    {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e060        ld2h    {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e060        ld2h    {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e060        ld2h    {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e060        ld2h    {z0.h, z1.h}, p0/z, \[x3\]
-[^:]+: a4a0e3e0        ld2h    {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a0e3e0        ld2h    {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a0e3e0        ld2h    {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a0e3e0        ld2h    {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a0e3e0        ld2h    {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a0e3e0        ld2h    {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a0e3e0        ld2h    {z0.h, z1.h}, p0/z, \[sp\]
-[^:]+: a4a7e000        ld2h    {z0.h, z1.h}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a4a7e000        ld2h    {z0.h, z1.h}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a4a7e000        ld2h    {z0.h, z1.h}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a4a8e000        ld2h    {z0.h, z1.h}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a4a8e000        ld2h    {z0.h, z1.h}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a4a8e000        ld2h    {z0.h, z1.h}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a4a9e000        ld2h    {z0.h, z1.h}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a4a9e000        ld2h    {z0.h, z1.h}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a4a9e000        ld2h    {z0.h, z1.h}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a4afe000        ld2h    {z0.h, z1.h}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a4afe000        ld2h    {z0.h, z1.h}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a4afe000        ld2h    {z0.h, z1.h}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a520c000        ld2w    {z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c000        ld2w    {z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c000        ld2w    {z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c001        ld2w    {z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c001        ld2w    {z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c001        ld2w    {z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c01f        ld2w    {z31.s, z0.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c01f        ld2w    {z31.s, z0.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a520c800        ld2w    {z0.s, z1.s}, p2/z, \[x0, x0, lsl #2\]
-[^:]+: a520c800        ld2w    {z0.s, z1.s}, p2/z, \[x0, x0, lsl #2\]
-[^:]+: a520c800        ld2w    {z0.s, z1.s}, p2/z, \[x0, x0, lsl #2\]
-[^:]+: a520dc00        ld2w    {z0.s, z1.s}, p7/z, \[x0, x0, lsl #2\]
-[^:]+: a520dc00        ld2w    {z0.s, z1.s}, p7/z, \[x0, x0, lsl #2\]
-[^:]+: a520dc00        ld2w    {z0.s, z1.s}, p7/z, \[x0, x0, lsl #2\]
-[^:]+: a520c060        ld2w    {z0.s, z1.s}, p0/z, \[x3, x0, lsl #2\]
-[^:]+: a520c060        ld2w    {z0.s, z1.s}, p0/z, \[x3, x0, lsl #2\]
-[^:]+: a520c060        ld2w    {z0.s, z1.s}, p0/z, \[x3, x0, lsl #2\]
-[^:]+: a520c3e0        ld2w    {z0.s, z1.s}, p0/z, \[sp, x0, lsl #2\]
-[^:]+: a520c3e0        ld2w    {z0.s, z1.s}, p0/z, \[sp, x0, lsl #2\]
-[^:]+: a520c3e0        ld2w    {z0.s, z1.s}, p0/z, \[sp, x0, lsl #2\]
-[^:]+: a524c000        ld2w    {z0.s, z1.s}, p0/z, \[x0, x4, lsl #2\]
-[^:]+: a524c000        ld2w    {z0.s, z1.s}, p0/z, \[x0, x4, lsl #2\]
-[^:]+: a524c000        ld2w    {z0.s, z1.s}, p0/z, \[x0, x4, lsl #2\]
-[^:]+: a53ec000        ld2w    {z0.s, z1.s}, p0/z, \[x0, x30, lsl #2\]
-[^:]+: a53ec000        ld2w    {z0.s, z1.s}, p0/z, \[x0, x30, lsl #2\]
-[^:]+: a53ec000        ld2w    {z0.s, z1.s}, p0/z, \[x0, x30, lsl #2\]
-[^:]+: a520e000        ld2w    {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e000        ld2w    {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e000        ld2w    {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e000        ld2w    {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e000        ld2w    {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e000        ld2w    {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e000        ld2w    {z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a520e001        ld2w    {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e001        ld2w    {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e001        ld2w    {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e001        ld2w    {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e001        ld2w    {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e001        ld2w    {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e001        ld2w    {z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a520e01f        ld2w    {z31.s, z0.s}, p0/z, \[x0\]
-[^:]+: a520e01f        ld2w    {z31.s, z0.s}, p0/z, \[x0\]
-[^:]+: a520e01f        ld2w    {z31.s, z0.s}, p0/z, \[x0\]
-[^:]+: a520e01f        ld2w    {z31.s, z0.s}, p0/z, \[x0\]
-[^:]+: a520e800        ld2w    {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520e800        ld2w    {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520e800        ld2w    {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520e800        ld2w    {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520e800        ld2w    {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520e800        ld2w    {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520e800        ld2w    {z0.s, z1.s}, p2/z, \[x0\]
-[^:]+: a520fc00        ld2w    {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520fc00        ld2w    {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520fc00        ld2w    {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520fc00        ld2w    {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520fc00        ld2w    {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520fc00        ld2w    {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520fc00        ld2w    {z0.s, z1.s}, p7/z, \[x0\]
-[^:]+: a520e060        ld2w    {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e060        ld2w    {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e060        ld2w    {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e060        ld2w    {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e060        ld2w    {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e060        ld2w    {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e060        ld2w    {z0.s, z1.s}, p0/z, \[x3\]
-[^:]+: a520e3e0        ld2w    {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a520e3e0        ld2w    {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a520e3e0        ld2w    {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a520e3e0        ld2w    {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a520e3e0        ld2w    {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a520e3e0        ld2w    {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a520e3e0        ld2w    {z0.s, z1.s}, p0/z, \[sp\]
-[^:]+: a527e000        ld2w    {z0.s, z1.s}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a527e000        ld2w    {z0.s, z1.s}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a527e000        ld2w    {z0.s, z1.s}, p0/z, \[x0, #14, mul vl\]
-[^:]+: a528e000        ld2w    {z0.s, z1.s}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a528e000        ld2w    {z0.s, z1.s}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a528e000        ld2w    {z0.s, z1.s}, p0/z, \[x0, #-16, mul vl\]
-[^:]+: a529e000        ld2w    {z0.s, z1.s}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a529e000        ld2w    {z0.s, z1.s}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a529e000        ld2w    {z0.s, z1.s}, p0/z, \[x0, #-14, mul vl\]
-[^:]+: a52fe000        ld2w    {z0.s, z1.s}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a52fe000        ld2w    {z0.s, z1.s}, p0/z, \[x0, #-2, mul vl\]
-[^:]+: a52fe000        ld2w    {z0.s, z1.s}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a420c000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a420c000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a420c000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a420c000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a420c000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a420c001        ld2b    {z1.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a420c001        ld2b    {z1.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a420c001        ld2b    {z1.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a420c001        ld2b    {z1.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a420c001        ld2b    {z1.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a420c01f        ld2b    {z31.b-z0.b}, p0/z, \[x0, x0\]
+[^:]+: a420c01f        ld2b    {z31.b-z0.b}, p0/z, \[x0, x0\]
+[^:]+: a420c01f        ld2b    {z31.b-z0.b}, p0/z, \[x0, x0\]
+[^:]+: a420c800        ld2b    {z0.b-z1.b}, p2/z, \[x0, x0\]
+[^:]+: a420c800        ld2b    {z0.b-z1.b}, p2/z, \[x0, x0\]
+[^:]+: a420c800        ld2b    {z0.b-z1.b}, p2/z, \[x0, x0\]
+[^:]+: a420c800        ld2b    {z0.b-z1.b}, p2/z, \[x0, x0\]
+[^:]+: a420c800        ld2b    {z0.b-z1.b}, p2/z, \[x0, x0\]
+[^:]+: a420dc00        ld2b    {z0.b-z1.b}, p7/z, \[x0, x0\]
+[^:]+: a420dc00        ld2b    {z0.b-z1.b}, p7/z, \[x0, x0\]
+[^:]+: a420dc00        ld2b    {z0.b-z1.b}, p7/z, \[x0, x0\]
+[^:]+: a420dc00        ld2b    {z0.b-z1.b}, p7/z, \[x0, x0\]
+[^:]+: a420dc00        ld2b    {z0.b-z1.b}, p7/z, \[x0, x0\]
+[^:]+: a420c060        ld2b    {z0.b-z1.b}, p0/z, \[x3, x0\]
+[^:]+: a420c060        ld2b    {z0.b-z1.b}, p0/z, \[x3, x0\]
+[^:]+: a420c060        ld2b    {z0.b-z1.b}, p0/z, \[x3, x0\]
+[^:]+: a420c060        ld2b    {z0.b-z1.b}, p0/z, \[x3, x0\]
+[^:]+: a420c060        ld2b    {z0.b-z1.b}, p0/z, \[x3, x0\]
+[^:]+: a420c3e0        ld2b    {z0.b-z1.b}, p0/z, \[sp, x0\]
+[^:]+: a420c3e0        ld2b    {z0.b-z1.b}, p0/z, \[sp, x0\]
+[^:]+: a420c3e0        ld2b    {z0.b-z1.b}, p0/z, \[sp, x0\]
+[^:]+: a420c3e0        ld2b    {z0.b-z1.b}, p0/z, \[sp, x0\]
+[^:]+: a420c3e0        ld2b    {z0.b-z1.b}, p0/z, \[sp, x0\]
+[^:]+: a424c000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x4\]
+[^:]+: a424c000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x4\]
+[^:]+: a424c000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x4\]
+[^:]+: a424c000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x4\]
+[^:]+: a424c000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x4\]
+[^:]+: a43ec000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x30\]
+[^:]+: a43ec000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x30\]
+[^:]+: a43ec000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x30\]
+[^:]+: a43ec000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x30\]
+[^:]+: a43ec000        ld2b    {z0.b-z1.b}, p0/z, \[x0, x30\]
+[^:]+: a420e000        ld2b    {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e000        ld2b    {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e000        ld2b    {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e000        ld2b    {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e000        ld2b    {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e000        ld2b    {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e000        ld2b    {z0.b-z1.b}, p0/z, \[x0\]
+[^:]+: a420e001        ld2b    {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e001        ld2b    {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e001        ld2b    {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e001        ld2b    {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e001        ld2b    {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e001        ld2b    {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e001        ld2b    {z1.b-z2.b}, p0/z, \[x0\]
+[^:]+: a420e01f        ld2b    {z31.b-z0.b}, p0/z, \[x0\]
+[^:]+: a420e01f        ld2b    {z31.b-z0.b}, p0/z, \[x0\]
+[^:]+: a420e01f        ld2b    {z31.b-z0.b}, p0/z, \[x0\]
+[^:]+: a420e01f        ld2b    {z31.b-z0.b}, p0/z, \[x0\]
+[^:]+: a420e800        ld2b    {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420e800        ld2b    {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420e800        ld2b    {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420e800        ld2b    {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420e800        ld2b    {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420e800        ld2b    {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420e800        ld2b    {z0.b-z1.b}, p2/z, \[x0\]
+[^:]+: a420fc00        ld2b    {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420fc00        ld2b    {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420fc00        ld2b    {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420fc00        ld2b    {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420fc00        ld2b    {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420fc00        ld2b    {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420fc00        ld2b    {z0.b-z1.b}, p7/z, \[x0\]
+[^:]+: a420e060        ld2b    {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e060        ld2b    {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e060        ld2b    {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e060        ld2b    {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e060        ld2b    {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e060        ld2b    {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e060        ld2b    {z0.b-z1.b}, p0/z, \[x3\]
+[^:]+: a420e3e0        ld2b    {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a420e3e0        ld2b    {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a420e3e0        ld2b    {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a420e3e0        ld2b    {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a420e3e0        ld2b    {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a420e3e0        ld2b    {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a420e3e0        ld2b    {z0.b-z1.b}, p0/z, \[sp\]
+[^:]+: a427e000        ld2b    {z0.b-z1.b}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a427e000        ld2b    {z0.b-z1.b}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a427e000        ld2b    {z0.b-z1.b}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a428e000        ld2b    {z0.b-z1.b}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a428e000        ld2b    {z0.b-z1.b}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a428e000        ld2b    {z0.b-z1.b}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a429e000        ld2b    {z0.b-z1.b}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a429e000        ld2b    {z0.b-z1.b}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a429e000        ld2b    {z0.b-z1.b}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a42fe000        ld2b    {z0.b-z1.b}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a42fe000        ld2b    {z0.b-z1.b}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a42fe000        ld2b    {z0.b-z1.b}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a5a0c000        ld2d    {z0.d-z1.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c000        ld2d    {z0.d-z1.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c000        ld2d    {z0.d-z1.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c001        ld2d    {z1.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c001        ld2d    {z1.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c001        ld2d    {z1.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c01f        ld2d    {z31.d-z0.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c01f        ld2d    {z31.d-z0.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c800        ld2d    {z0.d-z1.d}, p2/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c800        ld2d    {z0.d-z1.d}, p2/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c800        ld2d    {z0.d-z1.d}, p2/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0dc00        ld2d    {z0.d-z1.d}, p7/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0dc00        ld2d    {z0.d-z1.d}, p7/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0dc00        ld2d    {z0.d-z1.d}, p7/z, \[x0, x0, lsl #3\]
+[^:]+: a5a0c060        ld2d    {z0.d-z1.d}, p0/z, \[x3, x0, lsl #3\]
+[^:]+: a5a0c060        ld2d    {z0.d-z1.d}, p0/z, \[x3, x0, lsl #3\]
+[^:]+: a5a0c060        ld2d    {z0.d-z1.d}, p0/z, \[x3, x0, lsl #3\]
+[^:]+: a5a0c3e0        ld2d    {z0.d-z1.d}, p0/z, \[sp, x0, lsl #3\]
+[^:]+: a5a0c3e0        ld2d    {z0.d-z1.d}, p0/z, \[sp, x0, lsl #3\]
+[^:]+: a5a0c3e0        ld2d    {z0.d-z1.d}, p0/z, \[sp, x0, lsl #3\]
+[^:]+: a5a4c000        ld2d    {z0.d-z1.d}, p0/z, \[x0, x4, lsl #3\]
+[^:]+: a5a4c000        ld2d    {z0.d-z1.d}, p0/z, \[x0, x4, lsl #3\]
+[^:]+: a5a4c000        ld2d    {z0.d-z1.d}, p0/z, \[x0, x4, lsl #3\]
+[^:]+: a5bec000        ld2d    {z0.d-z1.d}, p0/z, \[x0, x30, lsl #3\]
+[^:]+: a5bec000        ld2d    {z0.d-z1.d}, p0/z, \[x0, x30, lsl #3\]
+[^:]+: a5bec000        ld2d    {z0.d-z1.d}, p0/z, \[x0, x30, lsl #3\]
+[^:]+: a5a0e000        ld2d    {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e000        ld2d    {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e000        ld2d    {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e000        ld2d    {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e000        ld2d    {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e000        ld2d    {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e000        ld2d    {z0.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5a0e001        ld2d    {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e001        ld2d    {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e001        ld2d    {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e001        ld2d    {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e001        ld2d    {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e001        ld2d    {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e001        ld2d    {z1.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5a0e01f        ld2d    {z31.d-z0.d}, p0/z, \[x0\]
+[^:]+: a5a0e01f        ld2d    {z31.d-z0.d}, p0/z, \[x0\]
+[^:]+: a5a0e01f        ld2d    {z31.d-z0.d}, p0/z, \[x0\]
+[^:]+: a5a0e01f        ld2d    {z31.d-z0.d}, p0/z, \[x0\]
+[^:]+: a5a0e800        ld2d    {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0e800        ld2d    {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0e800        ld2d    {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0e800        ld2d    {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0e800        ld2d    {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0e800        ld2d    {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0e800        ld2d    {z0.d-z1.d}, p2/z, \[x0\]
+[^:]+: a5a0fc00        ld2d    {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0fc00        ld2d    {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0fc00        ld2d    {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0fc00        ld2d    {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0fc00        ld2d    {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0fc00        ld2d    {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0fc00        ld2d    {z0.d-z1.d}, p7/z, \[x0\]
+[^:]+: a5a0e060        ld2d    {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e060        ld2d    {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e060        ld2d    {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e060        ld2d    {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e060        ld2d    {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e060        ld2d    {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e060        ld2d    {z0.d-z1.d}, p0/z, \[x3\]
+[^:]+: a5a0e3e0        ld2d    {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a0e3e0        ld2d    {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a0e3e0        ld2d    {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a0e3e0        ld2d    {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a0e3e0        ld2d    {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a0e3e0        ld2d    {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a0e3e0        ld2d    {z0.d-z1.d}, p0/z, \[sp\]
+[^:]+: a5a7e000        ld2d    {z0.d-z1.d}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a5a7e000        ld2d    {z0.d-z1.d}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a5a7e000        ld2d    {z0.d-z1.d}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a5a8e000        ld2d    {z0.d-z1.d}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a5a8e000        ld2d    {z0.d-z1.d}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a5a8e000        ld2d    {z0.d-z1.d}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a5a9e000        ld2d    {z0.d-z1.d}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a5a9e000        ld2d    {z0.d-z1.d}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a5a9e000        ld2d    {z0.d-z1.d}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a5afe000        ld2d    {z0.d-z1.d}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a5afe000        ld2d    {z0.d-z1.d}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a5afe000        ld2d    {z0.d-z1.d}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a4a0c000        ld2h    {z0.h-z1.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c000        ld2h    {z0.h-z1.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c000        ld2h    {z0.h-z1.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c001        ld2h    {z1.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c001        ld2h    {z1.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c001        ld2h    {z1.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c01f        ld2h    {z31.h-z0.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c01f        ld2h    {z31.h-z0.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c800        ld2h    {z0.h-z1.h}, p2/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c800        ld2h    {z0.h-z1.h}, p2/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c800        ld2h    {z0.h-z1.h}, p2/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0dc00        ld2h    {z0.h-z1.h}, p7/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0dc00        ld2h    {z0.h-z1.h}, p7/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0dc00        ld2h    {z0.h-z1.h}, p7/z, \[x0, x0, lsl #1\]
+[^:]+: a4a0c060        ld2h    {z0.h-z1.h}, p0/z, \[x3, x0, lsl #1\]
+[^:]+: a4a0c060        ld2h    {z0.h-z1.h}, p0/z, \[x3, x0, lsl #1\]
+[^:]+: a4a0c060        ld2h    {z0.h-z1.h}, p0/z, \[x3, x0, lsl #1\]
+[^:]+: a4a0c3e0        ld2h    {z0.h-z1.h}, p0/z, \[sp, x0, lsl #1\]
+[^:]+: a4a0c3e0        ld2h    {z0.h-z1.h}, p0/z, \[sp, x0, lsl #1\]
+[^:]+: a4a0c3e0        ld2h    {z0.h-z1.h}, p0/z, \[sp, x0, lsl #1\]
+[^:]+: a4a4c000        ld2h    {z0.h-z1.h}, p0/z, \[x0, x4, lsl #1\]
+[^:]+: a4a4c000        ld2h    {z0.h-z1.h}, p0/z, \[x0, x4, lsl #1\]
+[^:]+: a4a4c000        ld2h    {z0.h-z1.h}, p0/z, \[x0, x4, lsl #1\]
+[^:]+: a4bec000        ld2h    {z0.h-z1.h}, p0/z, \[x0, x30, lsl #1\]
+[^:]+: a4bec000        ld2h    {z0.h-z1.h}, p0/z, \[x0, x30, lsl #1\]
+[^:]+: a4bec000        ld2h    {z0.h-z1.h}, p0/z, \[x0, x30, lsl #1\]
+[^:]+: a4a0e000        ld2h    {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e000        ld2h    {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e000        ld2h    {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e000        ld2h    {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e000        ld2h    {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e000        ld2h    {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e000        ld2h    {z0.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4a0e001        ld2h    {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e001        ld2h    {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e001        ld2h    {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e001        ld2h    {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e001        ld2h    {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e001        ld2h    {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e001        ld2h    {z1.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4a0e01f        ld2h    {z31.h-z0.h}, p0/z, \[x0\]
+[^:]+: a4a0e01f        ld2h    {z31.h-z0.h}, p0/z, \[x0\]
+[^:]+: a4a0e01f        ld2h    {z31.h-z0.h}, p0/z, \[x0\]
+[^:]+: a4a0e01f        ld2h    {z31.h-z0.h}, p0/z, \[x0\]
+[^:]+: a4a0e800        ld2h    {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0e800        ld2h    {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0e800        ld2h    {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0e800        ld2h    {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0e800        ld2h    {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0e800        ld2h    {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0e800        ld2h    {z0.h-z1.h}, p2/z, \[x0\]
+[^:]+: a4a0fc00        ld2h    {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0fc00        ld2h    {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0fc00        ld2h    {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0fc00        ld2h    {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0fc00        ld2h    {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0fc00        ld2h    {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0fc00        ld2h    {z0.h-z1.h}, p7/z, \[x0\]
+[^:]+: a4a0e060        ld2h    {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e060        ld2h    {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e060        ld2h    {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e060        ld2h    {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e060        ld2h    {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e060        ld2h    {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e060        ld2h    {z0.h-z1.h}, p0/z, \[x3\]
+[^:]+: a4a0e3e0        ld2h    {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a0e3e0        ld2h    {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a0e3e0        ld2h    {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a0e3e0        ld2h    {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a0e3e0        ld2h    {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a0e3e0        ld2h    {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a0e3e0        ld2h    {z0.h-z1.h}, p0/z, \[sp\]
+[^:]+: a4a7e000        ld2h    {z0.h-z1.h}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a4a7e000        ld2h    {z0.h-z1.h}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a4a7e000        ld2h    {z0.h-z1.h}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a4a8e000        ld2h    {z0.h-z1.h}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a4a8e000        ld2h    {z0.h-z1.h}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a4a8e000        ld2h    {z0.h-z1.h}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a4a9e000        ld2h    {z0.h-z1.h}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a4a9e000        ld2h    {z0.h-z1.h}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a4a9e000        ld2h    {z0.h-z1.h}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a4afe000        ld2h    {z0.h-z1.h}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a4afe000        ld2h    {z0.h-z1.h}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a4afe000        ld2h    {z0.h-z1.h}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a520c000        ld2w    {z0.s-z1.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c000        ld2w    {z0.s-z1.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c000        ld2w    {z0.s-z1.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c001        ld2w    {z1.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c001        ld2w    {z1.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c001        ld2w    {z1.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c01f        ld2w    {z31.s-z0.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c01f        ld2w    {z31.s-z0.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a520c800        ld2w    {z0.s-z1.s}, p2/z, \[x0, x0, lsl #2\]
+[^:]+: a520c800        ld2w    {z0.s-z1.s}, p2/z, \[x0, x0, lsl #2\]
+[^:]+: a520c800        ld2w    {z0.s-z1.s}, p2/z, \[x0, x0, lsl #2\]
+[^:]+: a520dc00        ld2w    {z0.s-z1.s}, p7/z, \[x0, x0, lsl #2\]
+[^:]+: a520dc00        ld2w    {z0.s-z1.s}, p7/z, \[x0, x0, lsl #2\]
+[^:]+: a520dc00        ld2w    {z0.s-z1.s}, p7/z, \[x0, x0, lsl #2\]
+[^:]+: a520c060        ld2w    {z0.s-z1.s}, p0/z, \[x3, x0, lsl #2\]
+[^:]+: a520c060        ld2w    {z0.s-z1.s}, p0/z, \[x3, x0, lsl #2\]
+[^:]+: a520c060        ld2w    {z0.s-z1.s}, p0/z, \[x3, x0, lsl #2\]
+[^:]+: a520c3e0        ld2w    {z0.s-z1.s}, p0/z, \[sp, x0, lsl #2\]
+[^:]+: a520c3e0        ld2w    {z0.s-z1.s}, p0/z, \[sp, x0, lsl #2\]
+[^:]+: a520c3e0        ld2w    {z0.s-z1.s}, p0/z, \[sp, x0, lsl #2\]
+[^:]+: a524c000        ld2w    {z0.s-z1.s}, p0/z, \[x0, x4, lsl #2\]
+[^:]+: a524c000        ld2w    {z0.s-z1.s}, p0/z, \[x0, x4, lsl #2\]
+[^:]+: a524c000        ld2w    {z0.s-z1.s}, p0/z, \[x0, x4, lsl #2\]
+[^:]+: a53ec000        ld2w    {z0.s-z1.s}, p0/z, \[x0, x30, lsl #2\]
+[^:]+: a53ec000        ld2w    {z0.s-z1.s}, p0/z, \[x0, x30, lsl #2\]
+[^:]+: a53ec000        ld2w    {z0.s-z1.s}, p0/z, \[x0, x30, lsl #2\]
+[^:]+: a520e000        ld2w    {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e000        ld2w    {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e000        ld2w    {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e000        ld2w    {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e000        ld2w    {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e000        ld2w    {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e000        ld2w    {z0.s-z1.s}, p0/z, \[x0\]
+[^:]+: a520e001        ld2w    {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e001        ld2w    {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e001        ld2w    {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e001        ld2w    {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e001        ld2w    {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e001        ld2w    {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e001        ld2w    {z1.s-z2.s}, p0/z, \[x0\]
+[^:]+: a520e01f        ld2w    {z31.s-z0.s}, p0/z, \[x0\]
+[^:]+: a520e01f        ld2w    {z31.s-z0.s}, p0/z, \[x0\]
+[^:]+: a520e01f        ld2w    {z31.s-z0.s}, p0/z, \[x0\]
+[^:]+: a520e01f        ld2w    {z31.s-z0.s}, p0/z, \[x0\]
+[^:]+: a520e800        ld2w    {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520e800        ld2w    {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520e800        ld2w    {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520e800        ld2w    {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520e800        ld2w    {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520e800        ld2w    {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520e800        ld2w    {z0.s-z1.s}, p2/z, \[x0\]
+[^:]+: a520fc00        ld2w    {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520fc00        ld2w    {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520fc00        ld2w    {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520fc00        ld2w    {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520fc00        ld2w    {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520fc00        ld2w    {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520fc00        ld2w    {z0.s-z1.s}, p7/z, \[x0\]
+[^:]+: a520e060        ld2w    {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e060        ld2w    {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e060        ld2w    {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e060        ld2w    {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e060        ld2w    {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e060        ld2w    {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e060        ld2w    {z0.s-z1.s}, p0/z, \[x3\]
+[^:]+: a520e3e0        ld2w    {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a520e3e0        ld2w    {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a520e3e0        ld2w    {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a520e3e0        ld2w    {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a520e3e0        ld2w    {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a520e3e0        ld2w    {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a520e3e0        ld2w    {z0.s-z1.s}, p0/z, \[sp\]
+[^:]+: a527e000        ld2w    {z0.s-z1.s}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a527e000        ld2w    {z0.s-z1.s}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a527e000        ld2w    {z0.s-z1.s}, p0/z, \[x0, #14, mul vl\]
+[^:]+: a528e000        ld2w    {z0.s-z1.s}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a528e000        ld2w    {z0.s-z1.s}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a528e000        ld2w    {z0.s-z1.s}, p0/z, \[x0, #-16, mul vl\]
+[^:]+: a529e000        ld2w    {z0.s-z1.s}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a529e000        ld2w    {z0.s-z1.s}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a529e000        ld2w    {z0.s-z1.s}, p0/z, \[x0, #-14, mul vl\]
+[^:]+: a52fe000        ld2w    {z0.s-z1.s}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a52fe000        ld2w    {z0.s-z1.s}, p0/z, \[x0, #-2, mul vl\]
+[^:]+: a52fe000        ld2w    {z0.s-z1.s}, p0/z, \[x0, #-2, mul vl\]
 [^:]+: a440c000        ld3b    {z0.b-z2.b}, p0/z, \[x0, x0\]
 [^:]+: a440c000        ld3b    {z0.b-z2.b}, p0/z, \[x0, x0\]
 [^:]+: a440c000        ld3b    {z0.b-z2.b}, p0/z, \[x0, x0\]
@@ -17849,9 +17849,9 @@ Disassembly of section .*:
 [^:]+: a440c001        ld3b    {z1.b-z3.b}, p0/z, \[x0, x0\]
 [^:]+: a440c001        ld3b    {z1.b-z3.b}, p0/z, \[x0, x0\]
 [^:]+: a440c001        ld3b    {z1.b-z3.b}, p0/z, \[x0, x0\]
-[^:]+: a440c01f        ld3b    {z31.b, z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a440c01f        ld3b    {z31.b, z0.b, z1.b}, p0/z, \[x0, x0\]
-[^:]+: a440c01f        ld3b    {z31.b, z0.b, z1.b}, p0/z, \[x0, x0\]
+[^:]+: a440c01f        ld3b    {z31.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a440c01f        ld3b    {z31.b-z1.b}, p0/z, \[x0, x0\]
+[^:]+: a440c01f        ld3b    {z31.b-z1.b}, p0/z, \[x0, x0\]
 [^:]+: a440c800        ld3b    {z0.b-z2.b}, p2/z, \[x0, x0\]
 [^:]+: a440c800        ld3b    {z0.b-z2.b}, p2/z, \[x0, x0\]
 [^:]+: a440c800        ld3b    {z0.b-z2.b}, p2/z, \[x0, x0\]
@@ -17896,10 +17896,10 @@ Disassembly of section .*:
 [^:]+: a440e001        ld3b    {z1.b-z3.b}, p0/z, \[x0\]
 [^:]+: a440e001        ld3b    {z1.b-z3.b}, p0/z, \[x0\]
 [^:]+: a440e001        ld3b    {z1.b-z3.b}, p0/z, \[x0\]
-[^:]+: a440e01f        ld3b    {z31.b, z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a440e01f        ld3b    {z31.b, z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a440e01f        ld3b    {z31.b, z0.b, z1.b}, p0/z, \[x0\]
-[^:]+: a440e01f        ld3b    {z31.b, z0.b, z1.b}, p0/z, \[x0\]
+[^:]+: a440e01f        ld3b    {z31.b-z1.b}, p0/z, \[x0\]
+[^:]+: a440e01f        ld3b    {z31.b-z1.b}, p0/z, \[x0\]
+[^:]+: a440e01f        ld3b    {z31.b-z1.b}, p0/z, \[x0\]
+[^:]+: a440e01f        ld3b    {z31.b-z1.b}, p0/z, \[x0\]
 [^:]+: a440e800        ld3b    {z0.b-z2.b}, p2/z, \[x0\]
 [^:]+: a440e800        ld3b    {z0.b-z2.b}, p2/z, \[x0\]
 [^:]+: a440e800        ld3b    {z0.b-z2.b}, p2/z, \[x0\]
@@ -17946,8 +17946,8 @@ Disassembly of section .*:
 [^:]+: a5c0c001        ld3d    {z1.d-z3.d}, p0/z, \[x0, x0, lsl #3\]
 [^:]+: a5c0c001        ld3d    {z1.d-z3.d}, p0/z, \[x0, x0, lsl #3\]
 [^:]+: a5c0c001        ld3d    {z1.d-z3.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5c0c01f        ld3d    {z31.d, z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5c0c01f        ld3d    {z31.d, z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5c0c01f        ld3d    {z31.d-z1.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5c0c01f        ld3d    {z31.d-z1.d}, p0/z, \[x0, x0, lsl #3\]
 [^:]+: a5c0c800        ld3d    {z0.d-z2.d}, p2/z, \[x0, x0, lsl #3\]
 [^:]+: a5c0c800        ld3d    {z0.d-z2.d}, p2/z, \[x0, x0, lsl #3\]
 [^:]+: a5c0c800        ld3d    {z0.d-z2.d}, p2/z, \[x0, x0, lsl #3\]
@@ -17980,10 +17980,10 @@ Disassembly of section .*:
 [^:]+: a5c0e001        ld3d    {z1.d-z3.d}, p0/z, \[x0\]
 [^:]+: a5c0e001        ld3d    {z1.d-z3.d}, p0/z, \[x0\]
 [^:]+: a5c0e001        ld3d    {z1.d-z3.d}, p0/z, \[x0\]
-[^:]+: a5c0e01f        ld3d    {z31.d, z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5c0e01f        ld3d    {z31.d, z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5c0e01f        ld3d    {z31.d, z0.d, z1.d}, p0/z, \[x0\]
-[^:]+: a5c0e01f        ld3d    {z31.d, z0.d, z1.d}, p0/z, \[x0\]
+[^:]+: a5c0e01f        ld3d    {z31.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5c0e01f        ld3d    {z31.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5c0e01f        ld3d    {z31.d-z1.d}, p0/z, \[x0\]
+[^:]+: a5c0e01f        ld3d    {z31.d-z1.d}, p0/z, \[x0\]
 [^:]+: a5c0e800        ld3d    {z0.d-z2.d}, p2/z, \[x0\]
 [^:]+: a5c0e800        ld3d    {z0.d-z2.d}, p2/z, \[x0\]
 [^:]+: a5c0e800        ld3d    {z0.d-z2.d}, p2/z, \[x0\]
@@ -18030,8 +18030,8 @@ Disassembly of section .*:
 [^:]+: a4c0c001        ld3h    {z1.h-z3.h}, p0/z, \[x0, x0, lsl #1\]
 [^:]+: a4c0c001        ld3h    {z1.h-z3.h}, p0/z, \[x0, x0, lsl #1\]
 [^:]+: a4c0c001        ld3h    {z1.h-z3.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4c0c01f        ld3h    {z31.h, z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4c0c01f        ld3h    {z31.h, z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4c0c01f        ld3h    {z31.h-z1.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4c0c01f        ld3h    {z31.h-z1.h}, p0/z, \[x0, x0, lsl #1\]
 [^:]+: a4c0c800        ld3h    {z0.h-z2.h}, p2/z, \[x0, x0, lsl #1\]
 [^:]+: a4c0c800        ld3h    {z0.h-z2.h}, p2/z, \[x0, x0, lsl #1\]
 [^:]+: a4c0c800        ld3h    {z0.h-z2.h}, p2/z, \[x0, x0, lsl #1\]
@@ -18064,10 +18064,10 @@ Disassembly of section .*:
 [^:]+: a4c0e001        ld3h    {z1.h-z3.h}, p0/z, \[x0\]
 [^:]+: a4c0e001        ld3h    {z1.h-z3.h}, p0/z, \[x0\]
 [^:]+: a4c0e001        ld3h    {z1.h-z3.h}, p0/z, \[x0\]
-[^:]+: a4c0e01f        ld3h    {z31.h, z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4c0e01f        ld3h    {z31.h, z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4c0e01f        ld3h    {z31.h, z0.h, z1.h}, p0/z, \[x0\]
-[^:]+: a4c0e01f        ld3h    {z31.h, z0.h, z1.h}, p0/z, \[x0\]
+[^:]+: a4c0e01f        ld3h    {z31.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4c0e01f        ld3h    {z31.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4c0e01f        ld3h    {z31.h-z1.h}, p0/z, \[x0\]
+[^:]+: a4c0e01f        ld3h    {z31.h-z1.h}, p0/z, \[x0\]
 [^:]+: a4c0e800        ld3h    {z0.h-z2.h}, p2/z, \[x0\]
 [^:]+: a4c0e800        ld3h    {z0.h-z2.h}, p2/z, \[x0\]
 [^:]+: a4c0e800        ld3h    {z0.h-z2.h}, p2/z, \[x0\]
@@ -18114,8 +18114,8 @@ Disassembly of section .*:
 [^:]+: a540c001        ld3w    {z1.s-z3.s}, p0/z, \[x0, x0, lsl #2\]
 [^:]+: a540c001        ld3w    {z1.s-z3.s}, p0/z, \[x0, x0, lsl #2\]
 [^:]+: a540c001        ld3w    {z1.s-z3.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a540c01f        ld3w    {z31.s, z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a540c01f        ld3w    {z31.s, z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a540c01f        ld3w    {z31.s-z1.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a540c01f        ld3w    {z31.s-z1.s}, p0/z, \[x0, x0, lsl #2\]
 [^:]+: a540c800        ld3w    {z0.s-z2.s}, p2/z, \[x0, x0, lsl #2\]
 [^:]+: a540c800        ld3w    {z0.s-z2.s}, p2/z, \[x0, x0, lsl #2\]
 [^:]+: a540c800        ld3w    {z0.s-z2.s}, p2/z, \[x0, x0, lsl #2\]
@@ -18148,10 +18148,10 @@ Disassembly of section .*:
 [^:]+: a540e001        ld3w    {z1.s-z3.s}, p0/z, \[x0\]
 [^:]+: a540e001        ld3w    {z1.s-z3.s}, p0/z, \[x0\]
 [^:]+: a540e001        ld3w    {z1.s-z3.s}, p0/z, \[x0\]
-[^:]+: a540e01f        ld3w    {z31.s, z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a540e01f        ld3w    {z31.s, z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a540e01f        ld3w    {z31.s, z0.s, z1.s}, p0/z, \[x0\]
-[^:]+: a540e01f        ld3w    {z31.s, z0.s, z1.s}, p0/z, \[x0\]
+[^:]+: a540e01f        ld3w    {z31.s-z1.s}, p0/z, \[x0\]
+[^:]+: a540e01f        ld3w    {z31.s-z1.s}, p0/z, \[x0\]
+[^:]+: a540e01f        ld3w    {z31.s-z1.s}, p0/z, \[x0\]
+[^:]+: a540e01f        ld3w    {z31.s-z1.s}, p0/z, \[x0\]
 [^:]+: a540e800        ld3w    {z0.s-z2.s}, p2/z, \[x0\]
 [^:]+: a540e800        ld3w    {z0.s-z2.s}, p2/z, \[x0\]
 [^:]+: a540e800        ld3w    {z0.s-z2.s}, p2/z, \[x0\]
@@ -18202,9 +18202,9 @@ Disassembly of section .*:
 [^:]+: a460c001        ld4b    {z1.b-z4.b}, p0/z, \[x0, x0\]
 [^:]+: a460c001        ld4b    {z1.b-z4.b}, p0/z, \[x0, x0\]
 [^:]+: a460c001        ld4b    {z1.b-z4.b}, p0/z, \[x0, x0\]
-[^:]+: a460c01f        ld4b    {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a460c01f        ld4b    {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0, x0\]
-[^:]+: a460c01f        ld4b    {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0, x0\]
+[^:]+: a460c01f        ld4b    {z31.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a460c01f        ld4b    {z31.b-z2.b}, p0/z, \[x0, x0\]
+[^:]+: a460c01f        ld4b    {z31.b-z2.b}, p0/z, \[x0, x0\]
 [^:]+: a460c800        ld4b    {z0.b-z3.b}, p2/z, \[x0, x0\]
 [^:]+: a460c800        ld4b    {z0.b-z3.b}, p2/z, \[x0, x0\]
 [^:]+: a460c800        ld4b    {z0.b-z3.b}, p2/z, \[x0, x0\]
@@ -18249,10 +18249,10 @@ Disassembly of section .*:
 [^:]+: a460e001        ld4b    {z1.b-z4.b}, p0/z, \[x0\]
 [^:]+: a460e001        ld4b    {z1.b-z4.b}, p0/z, \[x0\]
 [^:]+: a460e001        ld4b    {z1.b-z4.b}, p0/z, \[x0\]
-[^:]+: a460e01f        ld4b    {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a460e01f        ld4b    {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a460e01f        ld4b    {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0\]
-[^:]+: a460e01f        ld4b    {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0\]
+[^:]+: a460e01f        ld4b    {z31.b-z2.b}, p0/z, \[x0\]
+[^:]+: a460e01f        ld4b    {z31.b-z2.b}, p0/z, \[x0\]
+[^:]+: a460e01f        ld4b    {z31.b-z2.b}, p0/z, \[x0\]
+[^:]+: a460e01f        ld4b    {z31.b-z2.b}, p0/z, \[x0\]
 [^:]+: a460e800        ld4b    {z0.b-z3.b}, p2/z, \[x0\]
 [^:]+: a460e800        ld4b    {z0.b-z3.b}, p2/z, \[x0\]
 [^:]+: a460e800        ld4b    {z0.b-z3.b}, p2/z, \[x0\]
@@ -18299,8 +18299,8 @@ Disassembly of section .*:
 [^:]+: a5e0c001        ld4d    {z1.d-z4.d}, p0/z, \[x0, x0, lsl #3\]
 [^:]+: a5e0c001        ld4d    {z1.d-z4.d}, p0/z, \[x0, x0, lsl #3\]
 [^:]+: a5e0c001        ld4d    {z1.d-z4.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5e0c01f        ld4d    {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-[^:]+: a5e0c01f        ld4d    {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5e0c01f        ld4d    {z31.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
+[^:]+: a5e0c01f        ld4d    {z31.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
 [^:]+: a5e0c800        ld4d    {z0.d-z3.d}, p2/z, \[x0, x0, lsl #3\]
 [^:]+: a5e0c800        ld4d    {z0.d-z3.d}, p2/z, \[x0, x0, lsl #3\]
 [^:]+: a5e0c800        ld4d    {z0.d-z3.d}, p2/z, \[x0, x0, lsl #3\]
@@ -18333,10 +18333,10 @@ Disassembly of section .*:
 [^:]+: a5e0e001        ld4d    {z1.d-z4.d}, p0/z, \[x0\]
 [^:]+: a5e0e001        ld4d    {z1.d-z4.d}, p0/z, \[x0\]
 [^:]+: a5e0e001        ld4d    {z1.d-z4.d}, p0/z, \[x0\]
-[^:]+: a5e0e01f        ld4d    {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5e0e01f        ld4d    {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5e0e01f        ld4d    {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0\]
-[^:]+: a5e0e01f        ld4d    {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0\]
+[^:]+: a5e0e01f        ld4d    {z31.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5e0e01f        ld4d    {z31.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5e0e01f        ld4d    {z31.d-z2.d}, p0/z, \[x0\]
+[^:]+: a5e0e01f        ld4d    {z31.d-z2.d}, p0/z, \[x0\]
 [^:]+: a5e0e800        ld4d    {z0.d-z3.d}, p2/z, \[x0\]
 [^:]+: a5e0e800        ld4d    {z0.d-z3.d}, p2/z, \[x0\]
 [^:]+: a5e0e800        ld4d    {z0.d-z3.d}, p2/z, \[x0\]
@@ -18383,8 +18383,8 @@ Disassembly of section .*:
 [^:]+: a4e0c001        ld4h    {z1.h-z4.h}, p0/z, \[x0, x0, lsl #1\]
 [^:]+: a4e0c001        ld4h    {z1.h-z4.h}, p0/z, \[x0, x0, lsl #1\]
 [^:]+: a4e0c001        ld4h    {z1.h-z4.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4e0c01f        ld4h    {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-[^:]+: a4e0c01f        ld4h    {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4e0c01f        ld4h    {z31.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
+[^:]+: a4e0c01f        ld4h    {z31.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
 [^:]+: a4e0c800        ld4h    {z0.h-z3.h}, p2/z, \[x0, x0, lsl #1\]
 [^:]+: a4e0c800        ld4h    {z0.h-z3.h}, p2/z, \[x0, x0, lsl #1\]
 [^:]+: a4e0c800        ld4h    {z0.h-z3.h}, p2/z, \[x0, x0, lsl #1\]
@@ -18417,10 +18417,10 @@ Disassembly of section .*:
 [^:]+: a4e0e001        ld4h    {z1.h-z4.h}, p0/z, \[x0\]
 [^:]+: a4e0e001        ld4h    {z1.h-z4.h}, p0/z, \[x0\]
 [^:]+: a4e0e001        ld4h    {z1.h-z4.h}, p0/z, \[x0\]
-[^:]+: a4e0e01f        ld4h    {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4e0e01f        ld4h    {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4e0e01f        ld4h    {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0\]
-[^:]+: a4e0e01f        ld4h    {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0\]
+[^:]+: a4e0e01f        ld4h    {z31.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4e0e01f        ld4h    {z31.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4e0e01f        ld4h    {z31.h-z2.h}, p0/z, \[x0\]
+[^:]+: a4e0e01f        ld4h    {z31.h-z2.h}, p0/z, \[x0\]
 [^:]+: a4e0e800        ld4h    {z0.h-z3.h}, p2/z, \[x0\]
 [^:]+: a4e0e800        ld4h    {z0.h-z3.h}, p2/z, \[x0\]
 [^:]+: a4e0e800        ld4h    {z0.h-z3.h}, p2/z, \[x0\]
@@ -18467,8 +18467,8 @@ Disassembly of section .*:
 [^:]+: a560c001        ld4w    {z1.s-z4.s}, p0/z, \[x0, x0, lsl #2\]
 [^:]+: a560c001        ld4w    {z1.s-z4.s}, p0/z, \[x0, x0, lsl #2\]
 [^:]+: a560c001        ld4w    {z1.s-z4.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a560c01f        ld4w    {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-[^:]+: a560c01f        ld4w    {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a560c01f        ld4w    {z31.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
+[^:]+: a560c01f        ld4w    {z31.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
 [^:]+: a560c800        ld4w    {z0.s-z3.s}, p2/z, \[x0, x0, lsl #2\]
 [^:]+: a560c800        ld4w    {z0.s-z3.s}, p2/z, \[x0, x0, lsl #2\]
 [^:]+: a560c800        ld4w    {z0.s-z3.s}, p2/z, \[x0, x0, lsl #2\]
@@ -18501,10 +18501,10 @@ Disassembly of section .*:
 [^:]+: a560e001        ld4w    {z1.s-z4.s}, p0/z, \[x0\]
 [^:]+: a560e001        ld4w    {z1.s-z4.s}, p0/z, \[x0\]
 [^:]+: a560e001        ld4w    {z1.s-z4.s}, p0/z, \[x0\]
-[^:]+: a560e01f        ld4w    {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a560e01f        ld4w    {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a560e01f        ld4w    {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0\]
-[^:]+: a560e01f        ld4w    {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0\]
+[^:]+: a560e01f        ld4w    {z31.s-z2.s}, p0/z, \[x0\]
+[^:]+: a560e01f        ld4w    {z31.s-z2.s}, p0/z, \[x0\]
+[^:]+: a560e01f        ld4w    {z31.s-z2.s}, p0/z, \[x0\]
+[^:]+: a560e01f        ld4w    {z31.s-z2.s}, p0/z, \[x0\]
 [^:]+: a560e800        ld4w    {z0.s-z3.s}, p2/z, \[x0\]
 [^:]+: a560e800        ld4w    {z0.s-z3.s}, p2/z, \[x0\]
 [^:]+: a560e800        ld4w    {z0.s-z3.s}, p2/z, \[x0\]
@@ -32604,359 +32604,359 @@ Disassembly of section .*:
 [^:]+: e569e000        st1w    {z0.d}, p0, \[x0, #-7, mul vl\]
 [^:]+: e56fe000        st1w    {z0.d}, p0, \[x0, #-1, mul vl\]
 [^:]+: e56fe000        st1w    {z0.d}, p0, \[x0, #-1, mul vl\]
-[^:]+: e4206000        st2b    {z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e4206000        st2b    {z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e4206000        st2b    {z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e4206000        st2b    {z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e4206000        st2b    {z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e4206001        st2b    {z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e4206001        st2b    {z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e4206001        st2b    {z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e4206001        st2b    {z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e4206001        st2b    {z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e420601f        st2b    {z31.b, z0.b}, p0, \[x0, x0\]
-[^:]+: e420601f        st2b    {z31.b, z0.b}, p0, \[x0, x0\]
-[^:]+: e420601f        st2b    {z31.b, z0.b}, p0, \[x0, x0\]
-[^:]+: e4206800        st2b    {z0.b, z1.b}, p2, \[x0, x0\]
-[^:]+: e4206800        st2b    {z0.b, z1.b}, p2, \[x0, x0\]
-[^:]+: e4206800        st2b    {z0.b, z1.b}, p2, \[x0, x0\]
-[^:]+: e4206800        st2b    {z0.b, z1.b}, p2, \[x0, x0\]
-[^:]+: e4206800        st2b    {z0.b, z1.b}, p2, \[x0, x0\]
-[^:]+: e4207c00        st2b    {z0.b, z1.b}, p7, \[x0, x0\]
-[^:]+: e4207c00        st2b    {z0.b, z1.b}, p7, \[x0, x0\]
-[^:]+: e4207c00        st2b    {z0.b, z1.b}, p7, \[x0, x0\]
-[^:]+: e4207c00        st2b    {z0.b, z1.b}, p7, \[x0, x0\]
-[^:]+: e4207c00        st2b    {z0.b, z1.b}, p7, \[x0, x0\]
-[^:]+: e4206060        st2b    {z0.b, z1.b}, p0, \[x3, x0\]
-[^:]+: e4206060        st2b    {z0.b, z1.b}, p0, \[x3, x0\]
-[^:]+: e4206060        st2b    {z0.b, z1.b}, p0, \[x3, x0\]
-[^:]+: e4206060        st2b    {z0.b, z1.b}, p0, \[x3, x0\]
-[^:]+: e4206060        st2b    {z0.b, z1.b}, p0, \[x3, x0\]
-[^:]+: e42063e0        st2b    {z0.b, z1.b}, p0, \[sp, x0\]
-[^:]+: e42063e0        st2b    {z0.b, z1.b}, p0, \[sp, x0\]
-[^:]+: e42063e0        st2b    {z0.b, z1.b}, p0, \[sp, x0\]
-[^:]+: e42063e0        st2b    {z0.b, z1.b}, p0, \[sp, x0\]
-[^:]+: e42063e0        st2b    {z0.b, z1.b}, p0, \[sp, x0\]
-[^:]+: e4246000        st2b    {z0.b, z1.b}, p0, \[x0, x4\]
-[^:]+: e4246000        st2b    {z0.b, z1.b}, p0, \[x0, x4\]
-[^:]+: e4246000        st2b    {z0.b, z1.b}, p0, \[x0, x4\]
-[^:]+: e4246000        st2b    {z0.b, z1.b}, p0, \[x0, x4\]
-[^:]+: e4246000        st2b    {z0.b, z1.b}, p0, \[x0, x4\]
-[^:]+: e43e6000        st2b    {z0.b, z1.b}, p0, \[x0, x30\]
-[^:]+: e43e6000        st2b    {z0.b, z1.b}, p0, \[x0, x30\]
-[^:]+: e43e6000        st2b    {z0.b, z1.b}, p0, \[x0, x30\]
-[^:]+: e43e6000        st2b    {z0.b, z1.b}, p0, \[x0, x30\]
-[^:]+: e43e6000        st2b    {z0.b, z1.b}, p0, \[x0, x30\]
-[^:]+: e430e000        st2b    {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e000        st2b    {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e000        st2b    {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e000        st2b    {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e000        st2b    {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e000        st2b    {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e000        st2b    {z0.b, z1.b}, p0, \[x0\]
-[^:]+: e430e001        st2b    {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e001        st2b    {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e001        st2b    {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e001        st2b    {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e001        st2b    {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e001        st2b    {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e001        st2b    {z1.b, z2.b}, p0, \[x0\]
-[^:]+: e430e01f        st2b    {z31.b, z0.b}, p0, \[x0\]
-[^:]+: e430e01f        st2b    {z31.b, z0.b}, p0, \[x0\]
-[^:]+: e430e01f        st2b    {z31.b, z0.b}, p0, \[x0\]
-[^:]+: e430e01f        st2b    {z31.b, z0.b}, p0, \[x0\]
-[^:]+: e430e800        st2b    {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430e800        st2b    {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430e800        st2b    {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430e800        st2b    {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430e800        st2b    {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430e800        st2b    {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430e800        st2b    {z0.b, z1.b}, p2, \[x0\]
-[^:]+: e430fc00        st2b    {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430fc00        st2b    {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430fc00        st2b    {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430fc00        st2b    {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430fc00        st2b    {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430fc00        st2b    {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430fc00        st2b    {z0.b, z1.b}, p7, \[x0\]
-[^:]+: e430e060        st2b    {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e060        st2b    {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e060        st2b    {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e060        st2b    {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e060        st2b    {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e060        st2b    {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e060        st2b    {z0.b, z1.b}, p0, \[x3\]
-[^:]+: e430e3e0        st2b    {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e430e3e0        st2b    {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e430e3e0        st2b    {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e430e3e0        st2b    {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e430e3e0        st2b    {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e430e3e0        st2b    {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e430e3e0        st2b    {z0.b, z1.b}, p0, \[sp\]
-[^:]+: e437e000        st2b    {z0.b, z1.b}, p0, \[x0, #14, mul vl\]
-[^:]+: e437e000        st2b    {z0.b, z1.b}, p0, \[x0, #14, mul vl\]
-[^:]+: e437e000        st2b    {z0.b, z1.b}, p0, \[x0, #14, mul vl\]
-[^:]+: e438e000        st2b    {z0.b, z1.b}, p0, \[x0, #-16, mul vl\]
-[^:]+: e438e000        st2b    {z0.b, z1.b}, p0, \[x0, #-16, mul vl\]
-[^:]+: e438e000        st2b    {z0.b, z1.b}, p0, \[x0, #-16, mul vl\]
-[^:]+: e439e000        st2b    {z0.b, z1.b}, p0, \[x0, #-14, mul vl\]
-[^:]+: e439e000        st2b    {z0.b, z1.b}, p0, \[x0, #-14, mul vl\]
-[^:]+: e439e000        st2b    {z0.b, z1.b}, p0, \[x0, #-14, mul vl\]
-[^:]+: e43fe000        st2b    {z0.b, z1.b}, p0, \[x0, #-2, mul vl\]
-[^:]+: e43fe000        st2b    {z0.b, z1.b}, p0, \[x0, #-2, mul vl\]
-[^:]+: e43fe000        st2b    {z0.b, z1.b}, p0, \[x0, #-2, mul vl\]
-[^:]+: e5a06000        st2d    {z0.d, z1.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a06000        st2d    {z0.d, z1.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a06000        st2d    {z0.d, z1.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a06001        st2d    {z1.d, z2.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a06001        st2d    {z1.d, z2.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a06001        st2d    {z1.d, z2.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a0601f        st2d    {z31.d, z0.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a0601f        st2d    {z31.d, z0.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5a06800        st2d    {z0.d, z1.d}, p2, \[x0, x0, lsl #3\]
-[^:]+: e5a06800        st2d    {z0.d, z1.d}, p2, \[x0, x0, lsl #3\]
-[^:]+: e5a06800        st2d    {z0.d, z1.d}, p2, \[x0, x0, lsl #3\]
-[^:]+: e5a07c00        st2d    {z0.d, z1.d}, p7, \[x0, x0, lsl #3\]
-[^:]+: e5a07c00        st2d    {z0.d, z1.d}, p7, \[x0, x0, lsl #3\]
-[^:]+: e5a07c00        st2d    {z0.d, z1.d}, p7, \[x0, x0, lsl #3\]
-[^:]+: e5a06060        st2d    {z0.d, z1.d}, p0, \[x3, x0, lsl #3\]
-[^:]+: e5a06060        st2d    {z0.d, z1.d}, p0, \[x3, x0, lsl #3\]
-[^:]+: e5a06060        st2d    {z0.d, z1.d}, p0, \[x3, x0, lsl #3\]
-[^:]+: e5a063e0        st2d    {z0.d, z1.d}, p0, \[sp, x0, lsl #3\]
-[^:]+: e5a063e0        st2d    {z0.d, z1.d}, p0, \[sp, x0, lsl #3\]
-[^:]+: e5a063e0        st2d    {z0.d, z1.d}, p0, \[sp, x0, lsl #3\]
-[^:]+: e5a46000        st2d    {z0.d, z1.d}, p0, \[x0, x4, lsl #3\]
-[^:]+: e5a46000        st2d    {z0.d, z1.d}, p0, \[x0, x4, lsl #3\]
-[^:]+: e5a46000        st2d    {z0.d, z1.d}, p0, \[x0, x4, lsl #3\]
-[^:]+: e5be6000        st2d    {z0.d, z1.d}, p0, \[x0, x30, lsl #3\]
-[^:]+: e5be6000        st2d    {z0.d, z1.d}, p0, \[x0, x30, lsl #3\]
-[^:]+: e5be6000        st2d    {z0.d, z1.d}, p0, \[x0, x30, lsl #3\]
-[^:]+: e5b0e000        st2d    {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e000        st2d    {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e000        st2d    {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e000        st2d    {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e000        st2d    {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e000        st2d    {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e000        st2d    {z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5b0e001        st2d    {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e001        st2d    {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e001        st2d    {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e001        st2d    {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e001        st2d    {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e001        st2d    {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e001        st2d    {z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5b0e01f        st2d    {z31.d, z0.d}, p0, \[x0\]
-[^:]+: e5b0e01f        st2d    {z31.d, z0.d}, p0, \[x0\]
-[^:]+: e5b0e01f        st2d    {z31.d, z0.d}, p0, \[x0\]
-[^:]+: e5b0e01f        st2d    {z31.d, z0.d}, p0, \[x0\]
-[^:]+: e5b0e800        st2d    {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0e800        st2d    {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0e800        st2d    {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0e800        st2d    {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0e800        st2d    {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0e800        st2d    {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0e800        st2d    {z0.d, z1.d}, p2, \[x0\]
-[^:]+: e5b0fc00        st2d    {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0fc00        st2d    {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0fc00        st2d    {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0fc00        st2d    {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0fc00        st2d    {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0fc00        st2d    {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0fc00        st2d    {z0.d, z1.d}, p7, \[x0\]
-[^:]+: e5b0e060        st2d    {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e060        st2d    {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e060        st2d    {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e060        st2d    {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e060        st2d    {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e060        st2d    {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e060        st2d    {z0.d, z1.d}, p0, \[x3\]
-[^:]+: e5b0e3e0        st2d    {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b0e3e0        st2d    {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b0e3e0        st2d    {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b0e3e0        st2d    {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b0e3e0        st2d    {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b0e3e0        st2d    {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b0e3e0        st2d    {z0.d, z1.d}, p0, \[sp\]
-[^:]+: e5b7e000        st2d    {z0.d, z1.d}, p0, \[x0, #14, mul vl\]
-[^:]+: e5b7e000        st2d    {z0.d, z1.d}, p0, \[x0, #14, mul vl\]
-[^:]+: e5b7e000        st2d    {z0.d, z1.d}, p0, \[x0, #14, mul vl\]
-[^:]+: e5b8e000        st2d    {z0.d, z1.d}, p0, \[x0, #-16, mul vl\]
-[^:]+: e5b8e000        st2d    {z0.d, z1.d}, p0, \[x0, #-16, mul vl\]
-[^:]+: e5b8e000        st2d    {z0.d, z1.d}, p0, \[x0, #-16, mul vl\]
-[^:]+: e5b9e000        st2d    {z0.d, z1.d}, p0, \[x0, #-14, mul vl\]
-[^:]+: e5b9e000        st2d    {z0.d, z1.d}, p0, \[x0, #-14, mul vl\]
-[^:]+: e5b9e000        st2d    {z0.d, z1.d}, p0, \[x0, #-14, mul vl\]
-[^:]+: e5bfe000        st2d    {z0.d, z1.d}, p0, \[x0, #-2, mul vl\]
-[^:]+: e5bfe000        st2d    {z0.d, z1.d}, p0, \[x0, #-2, mul vl\]
-[^:]+: e5bfe000        st2d    {z0.d, z1.d}, p0, \[x0, #-2, mul vl\]
-[^:]+: e4a06000        st2h    {z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a06000        st2h    {z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a06000        st2h    {z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a06001        st2h    {z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a06001        st2h    {z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a06001        st2h    {z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a0601f        st2h    {z31.h, z0.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a0601f        st2h    {z31.h, z0.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4a06800        st2h    {z0.h, z1.h}, p2, \[x0, x0, lsl #1\]
-[^:]+: e4a06800        st2h    {z0.h, z1.h}, p2, \[x0, x0, lsl #1\]
-[^:]+: e4a06800        st2h    {z0.h, z1.h}, p2, \[x0, x0, lsl #1\]
-[^:]+: e4a07c00        st2h    {z0.h, z1.h}, p7, \[x0, x0, lsl #1\]
-[^:]+: e4a07c00        st2h    {z0.h, z1.h}, p7, \[x0, x0, lsl #1\]
-[^:]+: e4a07c00        st2h    {z0.h, z1.h}, p7, \[x0, x0, lsl #1\]
-[^:]+: e4a06060        st2h    {z0.h, z1.h}, p0, \[x3, x0, lsl #1\]
-[^:]+: e4a06060        st2h    {z0.h, z1.h}, p0, \[x3, x0, lsl #1\]
-[^:]+: e4a06060        st2h    {z0.h, z1.h}, p0, \[x3, x0, lsl #1\]
-[^:]+: e4a063e0        st2h    {z0.h, z1.h}, p0, \[sp, x0, lsl #1\]
-[^:]+: e4a063e0        st2h    {z0.h, z1.h}, p0, \[sp, x0, lsl #1\]
-[^:]+: e4a063e0        st2h    {z0.h, z1.h}, p0, \[sp, x0, lsl #1\]
-[^:]+: e4a46000        st2h    {z0.h, z1.h}, p0, \[x0, x4, lsl #1\]
-[^:]+: e4a46000        st2h    {z0.h, z1.h}, p0, \[x0, x4, lsl #1\]
-[^:]+: e4a46000        st2h    {z0.h, z1.h}, p0, \[x0, x4, lsl #1\]
-[^:]+: e4be6000        st2h    {z0.h, z1.h}, p0, \[x0, x30, lsl #1\]
-[^:]+: e4be6000        st2h    {z0.h, z1.h}, p0, \[x0, x30, lsl #1\]
-[^:]+: e4be6000        st2h    {z0.h, z1.h}, p0, \[x0, x30, lsl #1\]
-[^:]+: e4b0e000        st2h    {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e000        st2h    {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e000        st2h    {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e000        st2h    {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e000        st2h    {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e000        st2h    {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e000        st2h    {z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4b0e001        st2h    {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e001        st2h    {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e001        st2h    {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e001        st2h    {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e001        st2h    {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e001        st2h    {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e001        st2h    {z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4b0e01f        st2h    {z31.h, z0.h}, p0, \[x0\]
-[^:]+: e4b0e01f        st2h    {z31.h, z0.h}, p0, \[x0\]
-[^:]+: e4b0e01f        st2h    {z31.h, z0.h}, p0, \[x0\]
-[^:]+: e4b0e01f        st2h    {z31.h, z0.h}, p0, \[x0\]
-[^:]+: e4b0e800        st2h    {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0e800        st2h    {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0e800        st2h    {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0e800        st2h    {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0e800        st2h    {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0e800        st2h    {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0e800        st2h    {z0.h, z1.h}, p2, \[x0\]
-[^:]+: e4b0fc00        st2h    {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0fc00        st2h    {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0fc00        st2h    {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0fc00        st2h    {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0fc00        st2h    {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0fc00        st2h    {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0fc00        st2h    {z0.h, z1.h}, p7, \[x0\]
-[^:]+: e4b0e060        st2h    {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e060        st2h    {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e060        st2h    {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e060        st2h    {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e060        st2h    {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e060        st2h    {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e060        st2h    {z0.h, z1.h}, p0, \[x3\]
-[^:]+: e4b0e3e0        st2h    {z0.h, z1.h}, p0, \[sp\]
-[^:]+: e4b0e3e0        st2h    {z0.h, z1.h}, p0, \[sp\]
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+[^:]+: e530e800        st2w    {z0.s-z1.s}, p2, \[x0\]
+[^:]+: e530fc00        st2w    {z0.s-z1.s}, p7, \[x0\]
+[^:]+: e530fc00        st2w    {z0.s-z1.s}, p7, \[x0\]
+[^:]+: e530fc00        st2w    {z0.s-z1.s}, p7, \[x0\]
+[^:]+: e530fc00        st2w    {z0.s-z1.s}, p7, \[x0\]
+[^:]+: e530fc00        st2w    {z0.s-z1.s}, p7, \[x0\]
+[^:]+: e530fc00        st2w    {z0.s-z1.s}, p7, \[x0\]
+[^:]+: e530fc00        st2w    {z0.s-z1.s}, p7, \[x0\]
+[^:]+: e530e060        st2w    {z0.s-z1.s}, p0, \[x3\]
+[^:]+: e530e060        st2w    {z0.s-z1.s}, p0, \[x3\]
+[^:]+: e530e060        st2w    {z0.s-z1.s}, p0, \[x3\]
+[^:]+: e530e060        st2w    {z0.s-z1.s}, p0, \[x3\]
+[^:]+: e530e060        st2w    {z0.s-z1.s}, p0, \[x3\]
+[^:]+: e530e060        st2w    {z0.s-z1.s}, p0, \[x3\]
+[^:]+: e530e060        st2w    {z0.s-z1.s}, p0, \[x3\]
+[^:]+: e530e3e0        st2w    {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e530e3e0        st2w    {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e530e3e0        st2w    {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e530e3e0        st2w    {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e530e3e0        st2w    {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e530e3e0        st2w    {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e530e3e0        st2w    {z0.s-z1.s}, p0, \[sp\]
+[^:]+: e537e000        st2w    {z0.s-z1.s}, p0, \[x0, #14, mul vl\]
+[^:]+: e537e000        st2w    {z0.s-z1.s}, p0, \[x0, #14, mul vl\]
+[^:]+: e537e000        st2w    {z0.s-z1.s}, p0, \[x0, #14, mul vl\]
+[^:]+: e538e000        st2w    {z0.s-z1.s}, p0, \[x0, #-16, mul vl\]
+[^:]+: e538e000        st2w    {z0.s-z1.s}, p0, \[x0, #-16, mul vl\]
+[^:]+: e538e000        st2w    {z0.s-z1.s}, p0, \[x0, #-16, mul vl\]
+[^:]+: e539e000        st2w    {z0.s-z1.s}, p0, \[x0, #-14, mul vl\]
+[^:]+: e539e000        st2w    {z0.s-z1.s}, p0, \[x0, #-14, mul vl\]
+[^:]+: e539e000        st2w    {z0.s-z1.s}, p0, \[x0, #-14, mul vl\]
+[^:]+: e53fe000        st2w    {z0.s-z1.s}, p0, \[x0, #-2, mul vl\]
+[^:]+: e53fe000        st2w    {z0.s-z1.s}, p0, \[x0, #-2, mul vl\]
+[^:]+: e53fe000        st2w    {z0.s-z1.s}, p0, \[x0, #-2, mul vl\]
 [^:]+: e4406000        st3b    {z0.b-z2.b}, p0, \[x0, x0\]
 [^:]+: e4406000        st3b    {z0.b-z2.b}, p0, \[x0, x0\]
 [^:]+: e4406000        st3b    {z0.b-z2.b}, p0, \[x0, x0\]
@@ -32967,9 +32967,9 @@ Disassembly of section .*:
 [^:]+: e4406001        st3b    {z1.b-z3.b}, p0, \[x0, x0\]
 [^:]+: e4406001        st3b    {z1.b-z3.b}, p0, \[x0, x0\]
 [^:]+: e4406001        st3b    {z1.b-z3.b}, p0, \[x0, x0\]
-[^:]+: e440601f        st3b    {z31.b, z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e440601f        st3b    {z31.b, z0.b, z1.b}, p0, \[x0, x0\]
-[^:]+: e440601f        st3b    {z31.b, z0.b, z1.b}, p0, \[x0, x0\]
+[^:]+: e440601f        st3b    {z31.b-z1.b}, p0, \[x0, x0\]
+[^:]+: e440601f        st3b    {z31.b-z1.b}, p0, \[x0, x0\]
+[^:]+: e440601f        st3b    {z31.b-z1.b}, p0, \[x0, x0\]
 [^:]+: e4406800        st3b    {z0.b-z2.b}, p2, \[x0, x0\]
 [^:]+: e4406800        st3b    {z0.b-z2.b}, p2, \[x0, x0\]
 [^:]+: e4406800        st3b    {z0.b-z2.b}, p2, \[x0, x0\]
@@ -33014,10 +33014,10 @@ Disassembly of section .*:
 [^:]+: e450e001        st3b    {z1.b-z3.b}, p0, \[x0\]
 [^:]+: e450e001        st3b    {z1.b-z3.b}, p0, \[x0\]
 [^:]+: e450e001        st3b    {z1.b-z3.b}, p0, \[x0\]
-[^:]+: e450e01f        st3b    {z31.b, z0.b, z1.b}, p0, \[x0\]
-[^:]+: e450e01f        st3b    {z31.b, z0.b, z1.b}, p0, \[x0\]
-[^:]+: e450e01f        st3b    {z31.b, z0.b, z1.b}, p0, \[x0\]
-[^:]+: e450e01f        st3b    {z31.b, z0.b, z1.b}, p0, \[x0\]
+[^:]+: e450e01f        st3b    {z31.b-z1.b}, p0, \[x0\]
+[^:]+: e450e01f        st3b    {z31.b-z1.b}, p0, \[x0\]
+[^:]+: e450e01f        st3b    {z31.b-z1.b}, p0, \[x0\]
+[^:]+: e450e01f        st3b    {z31.b-z1.b}, p0, \[x0\]
 [^:]+: e450e800        st3b    {z0.b-z2.b}, p2, \[x0\]
 [^:]+: e450e800        st3b    {z0.b-z2.b}, p2, \[x0\]
 [^:]+: e450e800        st3b    {z0.b-z2.b}, p2, \[x0\]
@@ -33064,8 +33064,8 @@ Disassembly of section .*:
 [^:]+: e5c06001        st3d    {z1.d-z3.d}, p0, \[x0, x0, lsl #3\]
 [^:]+: e5c06001        st3d    {z1.d-z3.d}, p0, \[x0, x0, lsl #3\]
 [^:]+: e5c06001        st3d    {z1.d-z3.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5c0601f        st3d    {z31.d, z0.d, z1.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5c0601f        st3d    {z31.d, z0.d, z1.d}, p0, \[x0, x0, lsl #3\]
+[^:]+: e5c0601f        st3d    {z31.d-z1.d}, p0, \[x0, x0, lsl #3\]
+[^:]+: e5c0601f        st3d    {z31.d-z1.d}, p0, \[x0, x0, lsl #3\]
 [^:]+: e5c06800        st3d    {z0.d-z2.d}, p2, \[x0, x0, lsl #3\]
 [^:]+: e5c06800        st3d    {z0.d-z2.d}, p2, \[x0, x0, lsl #3\]
 [^:]+: e5c06800        st3d    {z0.d-z2.d}, p2, \[x0, x0, lsl #3\]
@@ -33098,10 +33098,10 @@ Disassembly of section .*:
 [^:]+: e5d0e001        st3d    {z1.d-z3.d}, p0, \[x0\]
 [^:]+: e5d0e001        st3d    {z1.d-z3.d}, p0, \[x0\]
 [^:]+: e5d0e001        st3d    {z1.d-z3.d}, p0, \[x0\]
-[^:]+: e5d0e01f        st3d    {z31.d, z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5d0e01f        st3d    {z31.d, z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5d0e01f        st3d    {z31.d, z0.d, z1.d}, p0, \[x0\]
-[^:]+: e5d0e01f        st3d    {z31.d, z0.d, z1.d}, p0, \[x0\]
+[^:]+: e5d0e01f        st3d    {z31.d-z1.d}, p0, \[x0\]
+[^:]+: e5d0e01f        st3d    {z31.d-z1.d}, p0, \[x0\]
+[^:]+: e5d0e01f        st3d    {z31.d-z1.d}, p0, \[x0\]
+[^:]+: e5d0e01f        st3d    {z31.d-z1.d}, p0, \[x0\]
 [^:]+: e5d0e800        st3d    {z0.d-z2.d}, p2, \[x0\]
 [^:]+: e5d0e800        st3d    {z0.d-z2.d}, p2, \[x0\]
 [^:]+: e5d0e800        st3d    {z0.d-z2.d}, p2, \[x0\]
@@ -33148,8 +33148,8 @@ Disassembly of section .*:
 [^:]+: e4c06001        st3h    {z1.h-z3.h}, p0, \[x0, x0, lsl #1\]
 [^:]+: e4c06001        st3h    {z1.h-z3.h}, p0, \[x0, x0, lsl #1\]
 [^:]+: e4c06001        st3h    {z1.h-z3.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4c0601f        st3h    {z31.h, z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4c0601f        st3h    {z31.h, z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
+[^:]+: e4c0601f        st3h    {z31.h-z1.h}, p0, \[x0, x0, lsl #1\]
+[^:]+: e4c0601f        st3h    {z31.h-z1.h}, p0, \[x0, x0, lsl #1\]
 [^:]+: e4c06800        st3h    {z0.h-z2.h}, p2, \[x0, x0, lsl #1\]
 [^:]+: e4c06800        st3h    {z0.h-z2.h}, p2, \[x0, x0, lsl #1\]
 [^:]+: e4c06800        st3h    {z0.h-z2.h}, p2, \[x0, x0, lsl #1\]
@@ -33182,10 +33182,10 @@ Disassembly of section .*:
 [^:]+: e4d0e001        st3h    {z1.h-z3.h}, p0, \[x0\]
 [^:]+: e4d0e001        st3h    {z1.h-z3.h}, p0, \[x0\]
 [^:]+: e4d0e001        st3h    {z1.h-z3.h}, p0, \[x0\]
-[^:]+: e4d0e01f        st3h    {z31.h, z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4d0e01f        st3h    {z31.h, z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4d0e01f        st3h    {z31.h, z0.h, z1.h}, p0, \[x0\]
-[^:]+: e4d0e01f        st3h    {z31.h, z0.h, z1.h}, p0, \[x0\]
+[^:]+: e4d0e01f        st3h    {z31.h-z1.h}, p0, \[x0\]
+[^:]+: e4d0e01f        st3h    {z31.h-z1.h}, p0, \[x0\]
+[^:]+: e4d0e01f        st3h    {z31.h-z1.h}, p0, \[x0\]
+[^:]+: e4d0e01f        st3h    {z31.h-z1.h}, p0, \[x0\]
 [^:]+: e4d0e800        st3h    {z0.h-z2.h}, p2, \[x0\]
 [^:]+: e4d0e800        st3h    {z0.h-z2.h}, p2, \[x0\]
 [^:]+: e4d0e800        st3h    {z0.h-z2.h}, p2, \[x0\]
@@ -33232,8 +33232,8 @@ Disassembly of section .*:
 [^:]+: e5406001        st3w    {z1.s-z3.s}, p0, \[x0, x0, lsl #2\]
 [^:]+: e5406001        st3w    {z1.s-z3.s}, p0, \[x0, x0, lsl #2\]
 [^:]+: e5406001        st3w    {z1.s-z3.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e540601f        st3w    {z31.s, z0.s, z1.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e540601f        st3w    {z31.s, z0.s, z1.s}, p0, \[x0, x0, lsl #2\]
+[^:]+: e540601f        st3w    {z31.s-z1.s}, p0, \[x0, x0, lsl #2\]
+[^:]+: e540601f        st3w    {z31.s-z1.s}, p0, \[x0, x0, lsl #2\]
 [^:]+: e5406800        st3w    {z0.s-z2.s}, p2, \[x0, x0, lsl #2\]
 [^:]+: e5406800        st3w    {z0.s-z2.s}, p2, \[x0, x0, lsl #2\]
 [^:]+: e5406800        st3w    {z0.s-z2.s}, p2, \[x0, x0, lsl #2\]
@@ -33266,10 +33266,10 @@ Disassembly of section .*:
 [^:]+: e550e001        st3w    {z1.s-z3.s}, p0, \[x0\]
 [^:]+: e550e001        st3w    {z1.s-z3.s}, p0, \[x0\]
 [^:]+: e550e001        st3w    {z1.s-z3.s}, p0, \[x0\]
-[^:]+: e550e01f        st3w    {z31.s, z0.s, z1.s}, p0, \[x0\]
-[^:]+: e550e01f        st3w    {z31.s, z0.s, z1.s}, p0, \[x0\]
-[^:]+: e550e01f        st3w    {z31.s, z0.s, z1.s}, p0, \[x0\]
-[^:]+: e550e01f        st3w    {z31.s, z0.s, z1.s}, p0, \[x0\]
+[^:]+: e550e01f        st3w    {z31.s-z1.s}, p0, \[x0\]
+[^:]+: e550e01f        st3w    {z31.s-z1.s}, p0, \[x0\]
+[^:]+: e550e01f        st3w    {z31.s-z1.s}, p0, \[x0\]
+[^:]+: e550e01f        st3w    {z31.s-z1.s}, p0, \[x0\]
 [^:]+: e550e800        st3w    {z0.s-z2.s}, p2, \[x0\]
 [^:]+: e550e800        st3w    {z0.s-z2.s}, p2, \[x0\]
 [^:]+: e550e800        st3w    {z0.s-z2.s}, p2, \[x0\]
@@ -33320,9 +33320,9 @@ Disassembly of section .*:
 [^:]+: e4606001        st4b    {z1.b-z4.b}, p0, \[x0, x0\]
 [^:]+: e4606001        st4b    {z1.b-z4.b}, p0, \[x0, x0\]
 [^:]+: e4606001        st4b    {z1.b-z4.b}, p0, \[x0, x0\]
-[^:]+: e460601f        st4b    {z31.b, z0.b, z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e460601f        st4b    {z31.b, z0.b, z1.b, z2.b}, p0, \[x0, x0\]
-[^:]+: e460601f        st4b    {z31.b, z0.b, z1.b, z2.b}, p0, \[x0, x0\]
+[^:]+: e460601f        st4b    {z31.b-z2.b}, p0, \[x0, x0\]
+[^:]+: e460601f        st4b    {z31.b-z2.b}, p0, \[x0, x0\]
+[^:]+: e460601f        st4b    {z31.b-z2.b}, p0, \[x0, x0\]
 [^:]+: e4606800        st4b    {z0.b-z3.b}, p2, \[x0, x0\]
 [^:]+: e4606800        st4b    {z0.b-z3.b}, p2, \[x0, x0\]
 [^:]+: e4606800        st4b    {z0.b-z3.b}, p2, \[x0, x0\]
@@ -33367,10 +33367,10 @@ Disassembly of section .*:
 [^:]+: e470e001        st4b    {z1.b-z4.b}, p0, \[x0\]
 [^:]+: e470e001        st4b    {z1.b-z4.b}, p0, \[x0\]
 [^:]+: e470e001        st4b    {z1.b-z4.b}, p0, \[x0\]
-[^:]+: e470e01f        st4b    {z31.b, z0.b, z1.b, z2.b}, p0, \[x0\]
-[^:]+: e470e01f        st4b    {z31.b, z0.b, z1.b, z2.b}, p0, \[x0\]
-[^:]+: e470e01f        st4b    {z31.b, z0.b, z1.b, z2.b}, p0, \[x0\]
-[^:]+: e470e01f        st4b    {z31.b, z0.b, z1.b, z2.b}, p0, \[x0\]
+[^:]+: e470e01f        st4b    {z31.b-z2.b}, p0, \[x0\]
+[^:]+: e470e01f        st4b    {z31.b-z2.b}, p0, \[x0\]
+[^:]+: e470e01f        st4b    {z31.b-z2.b}, p0, \[x0\]
+[^:]+: e470e01f        st4b    {z31.b-z2.b}, p0, \[x0\]
 [^:]+: e470e800        st4b    {z0.b-z3.b}, p2, \[x0\]
 [^:]+: e470e800        st4b    {z0.b-z3.b}, p2, \[x0\]
 [^:]+: e470e800        st4b    {z0.b-z3.b}, p2, \[x0\]
@@ -33417,8 +33417,8 @@ Disassembly of section .*:
 [^:]+: e5e06001        st4d    {z1.d-z4.d}, p0, \[x0, x0, lsl #3\]
 [^:]+: e5e06001        st4d    {z1.d-z4.d}, p0, \[x0, x0, lsl #3\]
 [^:]+: e5e06001        st4d    {z1.d-z4.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5e0601f        st4d    {z31.d, z0.d, z1.d, z2.d}, p0, \[x0, x0, lsl #3\]
-[^:]+: e5e0601f        st4d    {z31.d, z0.d, z1.d, z2.d}, p0, \[x0, x0, lsl #3\]
+[^:]+: e5e0601f        st4d    {z31.d-z2.d}, p0, \[x0, x0, lsl #3\]
+[^:]+: e5e0601f        st4d    {z31.d-z2.d}, p0, \[x0, x0, lsl #3\]
 [^:]+: e5e06800        st4d    {z0.d-z3.d}, p2, \[x0, x0, lsl #3\]
 [^:]+: e5e06800        st4d    {z0.d-z3.d}, p2, \[x0, x0, lsl #3\]
 [^:]+: e5e06800        st4d    {z0.d-z3.d}, p2, \[x0, x0, lsl #3\]
@@ -33451,10 +33451,10 @@ Disassembly of section .*:
 [^:]+: e5f0e001        st4d    {z1.d-z4.d}, p0, \[x0\]
 [^:]+: e5f0e001        st4d    {z1.d-z4.d}, p0, \[x0\]
 [^:]+: e5f0e001        st4d    {z1.d-z4.d}, p0, \[x0\]
-[^:]+: e5f0e01f        st4d    {z31.d, z0.d, z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5f0e01f        st4d    {z31.d, z0.d, z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5f0e01f        st4d    {z31.d, z0.d, z1.d, z2.d}, p0, \[x0\]
-[^:]+: e5f0e01f        st4d    {z31.d, z0.d, z1.d, z2.d}, p0, \[x0\]
+[^:]+: e5f0e01f        st4d    {z31.d-z2.d}, p0, \[x0\]
+[^:]+: e5f0e01f        st4d    {z31.d-z2.d}, p0, \[x0\]
+[^:]+: e5f0e01f        st4d    {z31.d-z2.d}, p0, \[x0\]
+[^:]+: e5f0e01f        st4d    {z31.d-z2.d}, p0, \[x0\]
 [^:]+: e5f0e800        st4d    {z0.d-z3.d}, p2, \[x0\]
 [^:]+: e5f0e800        st4d    {z0.d-z3.d}, p2, \[x0\]
 [^:]+: e5f0e800        st4d    {z0.d-z3.d}, p2, \[x0\]
@@ -33501,8 +33501,8 @@ Disassembly of section .*:
 [^:]+: e4e06001        st4h    {z1.h-z4.h}, p0, \[x0, x0, lsl #1\]
 [^:]+: e4e06001        st4h    {z1.h-z4.h}, p0, \[x0, x0, lsl #1\]
 [^:]+: e4e06001        st4h    {z1.h-z4.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4e0601f        st4h    {z31.h, z0.h, z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
-[^:]+: e4e0601f        st4h    {z31.h, z0.h, z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
+[^:]+: e4e0601f        st4h    {z31.h-z2.h}, p0, \[x0, x0, lsl #1\]
+[^:]+: e4e0601f        st4h    {z31.h-z2.h}, p0, \[x0, x0, lsl #1\]
 [^:]+: e4e06800        st4h    {z0.h-z3.h}, p2, \[x0, x0, lsl #1\]
 [^:]+: e4e06800        st4h    {z0.h-z3.h}, p2, \[x0, x0, lsl #1\]
 [^:]+: e4e06800        st4h    {z0.h-z3.h}, p2, \[x0, x0, lsl #1\]
@@ -33535,10 +33535,10 @@ Disassembly of section .*:
 [^:]+: e4f0e001        st4h    {z1.h-z4.h}, p0, \[x0\]
 [^:]+: e4f0e001        st4h    {z1.h-z4.h}, p0, \[x0\]
 [^:]+: e4f0e001        st4h    {z1.h-z4.h}, p0, \[x0\]
-[^:]+: e4f0e01f        st4h    {z31.h, z0.h, z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4f0e01f        st4h    {z31.h, z0.h, z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4f0e01f        st4h    {z31.h, z0.h, z1.h, z2.h}, p0, \[x0\]
-[^:]+: e4f0e01f        st4h    {z31.h, z0.h, z1.h, z2.h}, p0, \[x0\]
+[^:]+: e4f0e01f        st4h    {z31.h-z2.h}, p0, \[x0\]
+[^:]+: e4f0e01f        st4h    {z31.h-z2.h}, p0, \[x0\]
+[^:]+: e4f0e01f        st4h    {z31.h-z2.h}, p0, \[x0\]
+[^:]+: e4f0e01f        st4h    {z31.h-z2.h}, p0, \[x0\]
 [^:]+: e4f0e800        st4h    {z0.h-z3.h}, p2, \[x0\]
 [^:]+: e4f0e800        st4h    {z0.h-z3.h}, p2, \[x0\]
 [^:]+: e4f0e800        st4h    {z0.h-z3.h}, p2, \[x0\]
@@ -33585,8 +33585,8 @@ Disassembly of section .*:
 [^:]+: e5606001        st4w    {z1.s-z4.s}, p0, \[x0, x0, lsl #2\]
 [^:]+: e5606001        st4w    {z1.s-z4.s}, p0, \[x0, x0, lsl #2\]
 [^:]+: e5606001        st4w    {z1.s-z4.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e560601f        st4w    {z31.s, z0.s, z1.s, z2.s}, p0, \[x0, x0, lsl #2\]
-[^:]+: e560601f        st4w    {z31.s, z0.s, z1.s, z2.s}, p0, \[x0, x0, lsl #2\]
+[^:]+: e560601f        st4w    {z31.s-z2.s}, p0, \[x0, x0, lsl #2\]
+[^:]+: e560601f        st4w    {z31.s-z2.s}, p0, \[x0, x0, lsl #2\]
 [^:]+: e5606800        st4w    {z0.s-z3.s}, p2, \[x0, x0, lsl #2\]
 [^:]+: e5606800        st4w    {z0.s-z3.s}, p2, \[x0, x0, lsl #2\]
 [^:]+: e5606800        st4w    {z0.s-z3.s}, p2, \[x0, x0, lsl #2\]
@@ -33619,10 +33619,10 @@ Disassembly of section .*:
 [^:]+: e570e001        st4w    {z1.s-z4.s}, p0, \[x0\]
 [^:]+: e570e001        st4w    {z1.s-z4.s}, p0, \[x0\]
 [^:]+: e570e001        st4w    {z1.s-z4.s}, p0, \[x0\]
-[^:]+: e570e01f        st4w    {z31.s, z0.s, z1.s, z2.s}, p0, \[x0\]
-[^:]+: e570e01f        st4w    {z31.s, z0.s, z1.s, z2.s}, p0, \[x0\]
-[^:]+: e570e01f        st4w    {z31.s, z0.s, z1.s, z2.s}, p0, \[x0\]
-[^:]+: e570e01f        st4w    {z31.s, z0.s, z1.s, z2.s}, p0, \[x0\]
+[^:]+: e570e01f        st4w    {z31.s-z2.s}, p0, \[x0\]
+[^:]+: e570e01f        st4w    {z31.s-z2.s}, p0, \[x0\]
+[^:]+: e570e01f        st4w    {z31.s-z2.s}, p0, \[x0\]
+[^:]+: e570e01f        st4w    {z31.s-z2.s}, p0, \[x0\]
 [^:]+: e570e800        st4w    {z0.s-z3.s}, p2, \[x0\]
 [^:]+: e570e800        st4w    {z0.s-z3.s}, p2, \[x0\]
 [^:]+: e570e800        st4w    {z0.s-z3.s}, p2, \[x0\]

diff --git a/gas/testsuite/gas/aarch64/sve2.d b/gas/testsuite/gas/aarch64/sve2.d
index beb76b5ffefd970b436517deb3d76d496433deab..6c0d94203cb72ff871312a11ce16459be4af95e8 100644 (file)
--- a/gas/testsuite/gas/aarch64/sve2.d
+++ b/gas/testsuite/gas/aarch64/sve2.d
@@ -113,9 +113,9 @@ Disassembly of section \.text:
  *[0-9a-f]+:   45409400        eortb   z0\.h, z0\.h, z0\.h
  *[0-9a-f]+:   45809400        eortb   z0\.s, z0\.s, z0\.s
  *[0-9a-f]+:   45c09400        eortb   z0\.d, z0\.d, z0\.d
- *[0-9a-f]+:   057b16b1        ext     z17\.b, {z21\.b, z22\.b}, #221
- *[0-9a-f]+:   05600000        ext     z0\.b, {z0\.b, z1\.b}, #0
- *[0-9a-f]+:   056003e0        ext     z0\.b, {z31\.b, z0\.b}, #0
+ *[0-9a-f]+:   057b16b1        ext     z17\.b, {z21\.b-z22\.b}, #221
+ *[0-9a-f]+:   05600000        ext     z0\.b, {z0\.b-z1\.b}, #0
+ *[0-9a-f]+:   056003e0        ext     z0\.b, {z31\.b-z0\.b}, #0
  *[0-9a-f]+:   645096b1        faddp   z17\.h, p5/m, z17\.h, z21\.h
  *[0-9a-f]+:   64508000        faddp   z0\.h, p0/m, z0\.h, z0\.h
  *[0-9a-f]+:   64908000        faddp   z0\.s, p0/m, z0\.s, z0\.s
@@ -480,12 +480,12 @@ Disassembly of section \.text:
  *[0-9a-f]+:   45407400        smullt  z0\.h, z0\.b, z0\.b
  *[0-9a-f]+:   45807400        smullt  z0\.s, z0\.h, z0\.h
  *[0-9a-f]+:   45c07400        smullt  z0\.d, z0\.s, z0\.s
- *[0-9a-f]+:   052d96b1        splice  z17\.b, p5, {z21\.b, z22\.b}
- *[0-9a-f]+:   052d8000        splice  z0\.b, p0, {z0\.b, z1\.b}
- *[0-9a-f]+:   056d8000        splice  z0\.h, p0, {z0\.h, z1\.h}
- *[0-9a-f]+:   05ad8000        splice  z0\.s, p0, {z0\.s, z1\.s}
- *[0-9a-f]+:   05ed8000        splice  z0\.d, p0, {z0\.d, z1\.d}
- *[0-9a-f]+:   052d83e0        splice  z0\.b, p0, {z31\.b, z0\.b}
+ *[0-9a-f]+:   052d96b1        splice  z17\.b, p5, {z21\.b-z22\.b}
+ *[0-9a-f]+:   052d8000        splice  z0\.b, p0, {z0\.b-z1\.b}
+ *[0-9a-f]+:   056d8000        splice  z0\.h, p0, {z0\.h-z1\.h}
+ *[0-9a-f]+:   05ad8000        splice  z0\.s, p0, {z0\.s-z1\.s}
+ *[0-9a-f]+:   05ed8000        splice  z0\.d, p0, {z0\.d-z1\.d}
+ *[0-9a-f]+:   052d83e0        splice  z0\.b, p0, {z31\.b-z0\.b}
  *[0-9a-f]+:   4408b6b1        sqabs   z17\.b, p5/m, z21\.b
  *[0-9a-f]+:   4408a000        sqabs   z0\.b, p0/m, z0\.b
  *[0-9a-f]+:   4448a000        sqabs   z0\.h, p0/m, z0\.h
@@ -915,12 +915,12 @@ Disassembly of section \.text:
  *[0-9a-f]+:   445c8000        suqadd  z0\.h, p0/m, z0\.h, z0\.h
  *[0-9a-f]+:   449c8000        suqadd  z0\.s, p0/m, z0\.s, z0\.s
  *[0-9a-f]+:   44dc8000        suqadd  z0\.d, p0/m, z0\.d, z0\.d
- *[0-9a-f]+:   053b2ab1        tbl     z17\.b, {z21\.b, z22\.b}, z27\.b
- *[0-9a-f]+:   05202800        tbl     z0\.b, {z0\.b, z1\.b}, z0\.b
- *[0-9a-f]+:   05602800        tbl     z0\.h, {z0\.h, z1\.h}, z0\.h
- *[0-9a-f]+:   05a02800        tbl     z0\.s, {z0\.s, z1\.s}, z0\.s
- *[0-9a-f]+:   05e02800        tbl     z0\.d, {z0\.d, z1\.d}, z0\.d
- *[0-9a-f]+:   05202be0        tbl     z0\.b, {z31\.b, z0\.b}, z0\.b
+ *[0-9a-f]+:   053b2ab1        tbl     z17\.b, {z21\.b-z22\.b}, z27\.b
+ *[0-9a-f]+:   05202800        tbl     z0\.b, {z0\.b-z1\.b}, z0\.b
+ *[0-9a-f]+:   05602800        tbl     z0\.h, {z0\.h-z1\.h}, z0\.h
+ *[0-9a-f]+:   05a02800        tbl     z0\.s, {z0\.s-z1\.s}, z0\.s
+ *[0-9a-f]+:   05e02800        tbl     z0\.d, {z0\.d-z1\.d}, z0\.d
+ *[0-9a-f]+:   05202be0        tbl     z0\.b, {z31\.b-z0\.b}, z0\.b
  *[0-9a-f]+:   053b2eb1        tbx     z17\.b, z21\.b, z27\.b
  *[0-9a-f]+:   05202c00        tbx     z0\.b, z0\.b, z0\.b
  *[0-9a-f]+:   05602c00        tbx     z0\.h, z0\.h, z0\.h

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 4e950cf70f8a00ea39f64d1672380eb4270e29fd..1a1e1bd22f3f6349dda404543e5df22349b010c7 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3246,7 +3246,7 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
   /* The hyphenated form is preferred for disassembly if there are
      more than two registers in the list, and the register numbers
      are monotonically increasing in increments of one.  */
-  if (stride == 1 && num_regs > 2 && last_reg > first_reg)
+  if (stride == 1 && num_regs > 1)
     snprintf (buf, size, "{%s-%s}%s",
              style_reg (styler, "%s%d.%s", prefix, first_reg, qlf_name),
              style_reg (styler, "%s%d.%s", prefix, last_reg, qlf_name), tb);