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abc9_ops: update comment
author
Eddie Hung
<eddie@fpgeh.com>
Fri, 22 May 2020 04:39:13 +0000
(21:39 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Fri, 22 May 2020 04:39:13 +0000
(21:39 -0700)
passes/techmap/abc9_ops.cc
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diff --git
a/passes/techmap/abc9_ops.cc
b/passes/techmap/abc9_ops.cc
index 10c980f733da8ff0d334b6adb1440b0f0726c690..8d55b18a08f5373820f5cee26489eb5ae538f6c8 100644
(file)
--- a/
passes/techmap/abc9_ops.cc
+++ b/
passes/techmap/abc9_ops.cc
@@
-547,7
+547,7
@@
void mark_scc(RTLIL::Module *module)
// For every unique SCC found, (arbitrarily) find the first
// cell in the component, and replace its output connections
// with a new wire driven by the old connection but with a
- // special (* abc9_
scc
*) attribute set (which is used by
+ // special (* abc9_
keep
*) attribute set (which is used by
// write_xaiger to break this wire into PI and POs)
pool<RTLIL::Const> ids_seen;
for (auto cell : module->cells()) {