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diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 2973944e1838cd7d631e90682b71f344248809a1..a481f5e2141d01f3c354b749f768d5744f98ccd4 100644 (file)
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -46,8 +46,8 @@ fashion that is hidden from the user, behind a consistent, stable ISA API.
 
 For the Opcode map (XO Field)
 see Power ISA v3.1, Book III, Appendix D, Table 13 (sheet 7 of 8), p1357.
-Proposed is the addition of `msubed` (**DRAFT, NOT APPROVED**) which is
-in `110110`.  A corresponding `madded` is proposed for `110010`
+Proposed is the addition of `madded` (**DRAFT, NOT APPROVED**) which is
+in `110010`.
 
 | 110000 | 110001  | 110010 | 110011 | 110100 | 110101 | 110110 | 110111 |
 | ------ | ------- | ------ | ------ | ------ | ------ | ------ | ------ |
@@ -62,7 +62,7 @@ used with the additional bit set for determining RS.
 | Rsrc1\_EXTRA2 | `12:13` | extends RA (R\*\_EXTRA2 Encoding)   |
 | Rsrc2\_EXTRA2 | `14:15` | extends RB (R\*\_EXTRA2 Encoding)   |
 | Rsrc3\_EXTRA2 | `16:17` | extends RC (R\*\_EXTRA2 Encoding)   |
-| EXTRA2_MODE   | `18`    | used by `msubed` and `madded` for RS   |
+| EXTRA2_MODE   | `18`    | used by `madded` for RS             |
 
 When `EXTRA2_MODE` is set to zero, the implicit RS register takes
 its Vector/Scalar setting from Rdest_EXTRA2, and takes
@@ -83,8 +83,8 @@ The pseudocode for `madded RT, RA, RB, RC` is:
     RT <- sum[64:127]
     RS <- sum[0:63] # RS is either RC or RT+VL
 
-Again RC is zero-extended (not shifted), the 128-bit product added
-to it; the lower half of the result stored in RT and the upper half
+RC is zero-extended (not shifted), the 128-bit product added
+to it; the lower half of that result stored in RT and the upper half
 in RS.
 
 The differences here to `maddhdu` are that `maddhdu` stores the upper